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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE --check-prefix=SSE23; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ssse3 | FileCheck %s --check-prefix=SSE --check-prefix=SSSE34; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE --check-prefix=SSE415; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX16; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX27 8; AVX128 tests:9 10define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {11; SSE2-LABEL: vsel_float:12; SSE2: # %bb.0: # %entry13; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]14; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]15; SSE2-NEXT: retq16;17; SSSE3-LABEL: vsel_float:18; SSSE3: # %bb.0: # %entry19; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]20; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]21; SSSE3-NEXT: retq22;23; SSE41-LABEL: vsel_float:24; SSE41: # %bb.0: # %entry25; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]26; SSE41-NEXT: retq27;28; AVX-LABEL: vsel_float:29; AVX: # %bb.0: # %entry30; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]31; AVX-NEXT: retq32entry:33 %vsel = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x float> %v1, <4 x float> %v234 ret <4 x float> %vsel35}36 37define <4 x float> @vsel_float2(<4 x float> %v1, <4 x float> %v2) {38; SSE2-LABEL: vsel_float2:39; SSE2: # %bb.0: # %entry40; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]41; SSE2-NEXT: movaps %xmm1, %xmm042; SSE2-NEXT: retq43;44; SSSE3-LABEL: vsel_float2:45; SSSE3: # %bb.0: # %entry46; SSSE3-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3]47; SSSE3-NEXT: movaps %xmm1, %xmm048; SSSE3-NEXT: retq49;50; SSE41-LABEL: vsel_float2:51; SSE41: # %bb.0: # %entry52; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]53; SSE41-NEXT: retq54;55; AVX-LABEL: vsel_float2:56; AVX: # %bb.0: # %entry57; AVX-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]58; AVX-NEXT: retq59entry:60 %vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %v1, <4 x float> %v261 ret <4 x float> %vsel62}63 64define <4 x i8> @vsel_4xi8(<4 x i8> %v1, <4 x i8> %v2) {65; SSE2-LABEL: vsel_4xi8:66; SSE2: # %bb.0: # %entry67; SSE2-NEXT: movaps {{.*#+}} xmm2 = [255,255,0,255,255,255,255,255,255,255,255,255,255,255,255,255]68; SSE2-NEXT: andps %xmm2, %xmm069; SSE2-NEXT: andnps %xmm1, %xmm270; SSE2-NEXT: orps %xmm2, %xmm071; SSE2-NEXT: retq72;73; SSSE3-LABEL: vsel_4xi8:74; SSSE3: # %bb.0: # %entry75; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]76; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,2,5,6,u,u,u,u,u,u,u,u,u,u,u,u]77; SSSE3-NEXT: retq78;79; SSE41-LABEL: vsel_4xi8:80; SSE41: # %bb.0: # %entry81; SSE41-NEXT: movdqa %xmm0, %xmm282; SSE41-NEXT: movss {{.*#+}} xmm0 = [255,255,0,255,0,0,0,0,0,0,0,0,0,0,0,0]83; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm184; SSE41-NEXT: movdqa %xmm1, %xmm085; SSE41-NEXT: retq86;87; AVX-LABEL: vsel_4xi8:88; AVX: # %bb.0: # %entry89; AVX-NEXT: vmovd {{.*#+}} xmm2 = [255,255,0,255,0,0,0,0,0,0,0,0,0,0,0,0]90; AVX-NEXT: vpblendvb %xmm2, %xmm0, %xmm1, %xmm091; AVX-NEXT: retq92entry:93 %vsel = select <4 x i1> <i1 true, i1 true, i1 false, i1 true>, <4 x i8> %v1, <4 x i8> %v294 ret <4 x i8> %vsel95}96 97define <4 x i16> @vsel_4xi16(<4 x i16> %v1, <4 x i16> %v2) {98; SSE2-LABEL: vsel_4xi16:99; SSE2: # %bb.0: # %entry100; SSE2-NEXT: movaps {{.*#+}} xmm2 = [65535,0,65535,65535,65535,65535,65535,65535]101; SSE2-NEXT: andps %xmm2, %xmm0102; SSE2-NEXT: andnps %xmm1, %xmm2103; SSE2-NEXT: orps %xmm2, %xmm0104; SSE2-NEXT: retq105;106; SSSE3-LABEL: vsel_4xi16:107; SSSE3: # %bb.0: # %entry108; SSSE3-NEXT: movaps {{.*#+}} xmm2 = [65535,0,65535,65535,65535,65535,65535,65535]109; SSSE3-NEXT: andps %xmm2, %xmm0110; SSSE3-NEXT: andnps %xmm1, %xmm2111; SSSE3-NEXT: orps %xmm2, %xmm0112; SSSE3-NEXT: retq113;114; SSE41-LABEL: vsel_4xi16:115; SSE41: # %bb.0: # %entry116; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3,4,5,6,7]117; SSE41-NEXT: retq118;119; AVX-LABEL: vsel_4xi16:120; AVX: # %bb.0: # %entry121; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3,4,5,6,7]122; AVX-NEXT: retq123entry:124 %vsel = select <4 x i1> <i1 true, i1 false, i1 true, i1 true>, <4 x i16> %v1, <4 x i16> %v2125 ret <4 x i16> %vsel126}127 128define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {129; SSE2-LABEL: vsel_i32:130; SSE2: # %bb.0: # %entry131; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]132; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]133; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]134; SSE2-NEXT: retq135;136; SSSE3-LABEL: vsel_i32:137; SSSE3: # %bb.0: # %entry138; SSSE3-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,3,2,3]139; SSSE3-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]140; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]141; SSSE3-NEXT: retq142;143; SSE41-LABEL: vsel_i32:144; SSE41: # %bb.0: # %entry145; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]146; SSE41-NEXT: retq147;148; AVX-LABEL: vsel_i32:149; AVX: # %bb.0: # %entry150; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]151; AVX-NEXT: retq152entry:153 %vsel = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x i32> %v1, <4 x i32> %v2154 ret <4 x i32> %vsel155}156 157define <2 x double> @vsel_double(<2 x double> %v1, <2 x double> %v2) {158; SSE2-LABEL: vsel_double:159; SSE2: # %bb.0: # %entry160; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]161; SSE2-NEXT: retq162;163; SSSE3-LABEL: vsel_double:164; SSSE3: # %bb.0: # %entry165; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]166; SSSE3-NEXT: retq167;168; SSE41-LABEL: vsel_double:169; SSE41: # %bb.0: # %entry170; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]171; SSE41-NEXT: retq172;173; AVX-LABEL: vsel_double:174; AVX: # %bb.0: # %entry175; AVX-NEXT: vmovsd {{.*#+}} xmm0 = xmm0[0],xmm1[1]176; AVX-NEXT: retq177entry:178 %vsel = select <2 x i1> <i1 true, i1 false>, <2 x double> %v1, <2 x double> %v2179 ret <2 x double> %vsel180}181 182define <2 x i64> @vsel_i64(<2 x i64> %v1, <2 x i64> %v2) {183; SSE2-LABEL: vsel_i64:184; SSE2: # %bb.0: # %entry185; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]186; SSE2-NEXT: retq187;188; SSSE3-LABEL: vsel_i64:189; SSSE3: # %bb.0: # %entry190; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]191; SSSE3-NEXT: retq192;193; SSE41-LABEL: vsel_i64:194; SSE41: # %bb.0: # %entry195; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]196; SSE41-NEXT: retq197;198; AVX-LABEL: vsel_i64:199; AVX: # %bb.0: # %entry200; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3]201; AVX-NEXT: retq202entry:203 %vsel = select <2 x i1> <i1 true, i1 false>, <2 x i64> %v1, <2 x i64> %v2204 ret <2 x i64> %vsel205}206 207define <8 x i16> @vsel_8xi16(<8 x i16> %v1, <8 x i16> %v2) {208; SSE2-LABEL: vsel_8xi16:209; SSE2: # %bb.0: # %entry210; SSE2-NEXT: movaps {{.*#+}} xmm2 = [0,65535,65535,65535,0,65535,65535,65535]211; SSE2-NEXT: andps %xmm2, %xmm1212; SSE2-NEXT: andnps %xmm0, %xmm2213; SSE2-NEXT: orps %xmm1, %xmm2214; SSE2-NEXT: movaps %xmm2, %xmm0215; SSE2-NEXT: retq216;217; SSSE3-LABEL: vsel_8xi16:218; SSSE3: # %bb.0: # %entry219; SSSE3-NEXT: movaps {{.*#+}} xmm2 = [0,65535,65535,65535,0,65535,65535,65535]220; SSSE3-NEXT: andps %xmm2, %xmm1221; SSSE3-NEXT: andnps %xmm0, %xmm2222; SSSE3-NEXT: orps %xmm1, %xmm2223; SSSE3-NEXT: movaps %xmm2, %xmm0224; SSSE3-NEXT: retq225;226; SSE41-LABEL: vsel_8xi16:227; SSE41: # %bb.0: # %entry228; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3],xmm0[4],xmm1[5,6,7]229; SSE41-NEXT: retq230;231; AVX-LABEL: vsel_8xi16:232; AVX: # %bb.0: # %entry233; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3],xmm0[4],xmm1[5,6,7]234; AVX-NEXT: retq235entry:236 %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x i16> %v1, <8 x i16> %v2237 ret <8 x i16> %vsel238}239 240define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {241; SSE2-LABEL: vsel_i8:242; SSE2: # %bb.0: # %entry243; SSE2-NEXT: movaps {{.*#+}} xmm2 = [0,255,255,255,0,255,255,255,0,255,255,255,0,255,255,255]244; SSE2-NEXT: andps %xmm2, %xmm1245; SSE2-NEXT: andnps %xmm0, %xmm2246; SSE2-NEXT: orps %xmm1, %xmm2247; SSE2-NEXT: movaps %xmm2, %xmm0248; SSE2-NEXT: retq249;250; SSSE3-LABEL: vsel_i8:251; SSSE3: # %bb.0: # %entry252; SSSE3-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[12],zero,zero,zero253; SSSE3-NEXT: pshufb {{.*#+}} xmm1 = zero,xmm1[1,2,3],zero,xmm1[5,6,7],zero,xmm1[9,10,11],zero,xmm1[13,14,15]254; SSSE3-NEXT: por %xmm1, %xmm0255; SSSE3-NEXT: retq256;257; SSE41-LABEL: vsel_i8:258; SSE41: # %bb.0: # %entry259; SSE41-NEXT: movdqa %xmm0, %xmm2260; SSE41-NEXT: movaps {{.*#+}} xmm0 = [0,255,255,255,0,255,255,255,0,255,255,255,0,255,255,255]261; SSE41-NEXT: pblendvb %xmm0, %xmm1, %xmm2262; SSE41-NEXT: movdqa %xmm2, %xmm0263; SSE41-NEXT: retq264;265; AVX1-LABEL: vsel_i8:266; AVX1: # %bb.0: # %entry267; AVX1-NEXT: vbroadcastss {{.*#+}} xmm2 = [0,255,255,255,0,255,255,255,0,255,255,255,0,255,255,255]268; AVX1-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0269; AVX1-NEXT: retq270;271; AVX2-LABEL: vsel_i8:272; AVX2: # %bb.0: # %entry273; AVX2-NEXT: vpbroadcastd {{.*#+}} xmm2 = [0,255,255,255,0,255,255,255,0,255,255,255,0,255,255,255]274; AVX2-NEXT: vpblendvb %xmm2, %xmm1, %xmm0, %xmm0275; AVX2-NEXT: retq276entry:277 %vsel = select <16 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <16 x i8> %v1, <16 x i8> %v2278 ret <16 x i8> %vsel279}280 281 282; AVX256 tests:283 284define <8 x float> @vsel_float8(<8 x float> %v1, <8 x float> %v2) {285; SSE2-LABEL: vsel_float8:286; SSE2: # %bb.0: # %entry287; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]288; SSE2-NEXT: movss {{.*#+}} xmm3 = xmm1[0],xmm3[1,2,3]289; SSE2-NEXT: movaps %xmm2, %xmm0290; SSE2-NEXT: movaps %xmm3, %xmm1291; SSE2-NEXT: retq292;293; SSSE3-LABEL: vsel_float8:294; SSSE3: # %bb.0: # %entry295; SSSE3-NEXT: movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]296; SSSE3-NEXT: movss {{.*#+}} xmm3 = xmm1[0],xmm3[1,2,3]297; SSSE3-NEXT: movaps %xmm2, %xmm0298; SSSE3-NEXT: movaps %xmm3, %xmm1299; SSSE3-NEXT: retq300;301; SSE41-LABEL: vsel_float8:302; SSE41: # %bb.0: # %entry303; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm2[1,2,3]304; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm1[0],xmm3[1,2,3]305; SSE41-NEXT: retq306;307; AVX-LABEL: vsel_float8:308; AVX: # %bb.0: # %entry309; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5,6,7]310; AVX-NEXT: retq311entry:312 %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x float> %v1, <8 x float> %v2313 ret <8 x float> %vsel314}315 316define <8 x i32> @vsel_i328(<8 x i32> %v1, <8 x i32> %v2) {317; SSE2-LABEL: vsel_i328:318; SSE2: # %bb.0: # %entry319; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]320; SSE2-NEXT: movss {{.*#+}} xmm3 = xmm1[0],xmm3[1,2,3]321; SSE2-NEXT: movaps %xmm2, %xmm0322; SSE2-NEXT: movaps %xmm3, %xmm1323; SSE2-NEXT: retq324;325; SSSE3-LABEL: vsel_i328:326; SSSE3: # %bb.0: # %entry327; SSSE3-NEXT: movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]328; SSSE3-NEXT: movss {{.*#+}} xmm3 = xmm1[0],xmm3[1,2,3]329; SSSE3-NEXT: movaps %xmm2, %xmm0330; SSSE3-NEXT: movaps %xmm3, %xmm1331; SSSE3-NEXT: retq332;333; SSE41-LABEL: vsel_i328:334; SSE41: # %bb.0: # %entry335; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm2[1,2,3]336; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm1[0],xmm3[1,2,3]337; SSE41-NEXT: retq338;339; AVX-LABEL: vsel_i328:340; AVX: # %bb.0: # %entry341; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3],ymm0[4],ymm1[5,6,7]342; AVX-NEXT: retq343entry:344 %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x i32> %v1, <8 x i32> %v2345 ret <8 x i32> %vsel346}347 348define <8 x double> @vsel_double8(<8 x double> %v1, <8 x double> %v2) {349; SSE2-LABEL: vsel_double8:350; SSE2: # %bb.0: # %entry351; SSE2-NEXT: movaps %xmm7, %xmm3352; SSE2-NEXT: movaps %xmm5, %xmm1353; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm4[2,3]354; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm6[2,3]355; SSE2-NEXT: retq356;357; SSSE3-LABEL: vsel_double8:358; SSSE3: # %bb.0: # %entry359; SSSE3-NEXT: movaps %xmm7, %xmm3360; SSSE3-NEXT: movaps %xmm5, %xmm1361; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm4[2,3]362; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm6[2,3]363; SSSE3-NEXT: retq364;365; SSE41-LABEL: vsel_double8:366; SSE41: # %bb.0: # %entry367; SSE41-NEXT: movaps %xmm7, %xmm3368; SSE41-NEXT: movaps %xmm5, %xmm1369; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm4[2,3]370; SSE41-NEXT: blendps {{.*#+}} xmm2 = xmm2[0,1],xmm6[2,3]371; SSE41-NEXT: retq372;373; AVX-LABEL: vsel_double8:374; AVX: # %bb.0: # %entry375; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm2[2,3,4,5,6,7]376; AVX-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1],ymm3[2,3,4,5,6,7]377; AVX-NEXT: retq378entry:379 %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x double> %v1, <8 x double> %v2380 ret <8 x double> %vsel381}382 383define <8 x i64> @vsel_i648(<8 x i64> %v1, <8 x i64> %v2) {384; SSE2-LABEL: vsel_i648:385; SSE2: # %bb.0: # %entry386; SSE2-NEXT: movaps %xmm7, %xmm3387; SSE2-NEXT: movaps %xmm5, %xmm1388; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm4[2,3]389; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm6[2,3]390; SSE2-NEXT: retq391;392; SSSE3-LABEL: vsel_i648:393; SSSE3: # %bb.0: # %entry394; SSSE3-NEXT: movaps %xmm7, %xmm3395; SSSE3-NEXT: movaps %xmm5, %xmm1396; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm4[2,3]397; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm6[2,3]398; SSSE3-NEXT: retq399;400; SSE41-LABEL: vsel_i648:401; SSE41: # %bb.0: # %entry402; SSE41-NEXT: movaps %xmm7, %xmm3403; SSE41-NEXT: movaps %xmm5, %xmm1404; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm4[2,3]405; SSE41-NEXT: blendps {{.*#+}} xmm2 = xmm2[0,1],xmm6[2,3]406; SSE41-NEXT: retq407;408; AVX-LABEL: vsel_i648:409; AVX: # %bb.0: # %entry410; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm2[2,3,4,5,6,7]411; AVX-NEXT: vblendps {{.*#+}} ymm1 = ymm1[0,1],ymm3[2,3,4,5,6,7]412; AVX-NEXT: retq413entry:414 %vsel = select <8 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <8 x i64> %v1, <8 x i64> %v2415 ret <8 x i64> %vsel416}417 418define <4 x double> @vsel_double4(<4 x double> %v1, <4 x double> %v2) {419; SSE2-LABEL: vsel_double4:420; SSE2: # %bb.0: # %entry421; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3]422; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3]423; SSE2-NEXT: retq424;425; SSSE3-LABEL: vsel_double4:426; SSSE3: # %bb.0: # %entry427; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3]428; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3]429; SSSE3-NEXT: retq430;431; SSE41-LABEL: vsel_double4:432; SSE41: # %bb.0: # %entry433; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3]434; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3]435; SSE41-NEXT: retq436;437; AVX-LABEL: vsel_double4:438; AVX: # %bb.0: # %entry439; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5],ymm1[6,7]440; AVX-NEXT: retq441entry:442 %vsel = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x double> %v1, <4 x double> %v2443 ret <4 x double> %vsel444}445 446define <2 x double> @testa(<2 x double> %x, <2 x double> %y) {447; SSE2-LABEL: testa:448; SSE2: # %bb.0: # %entry449; SSE2-NEXT: movapd %xmm1, %xmm2450; SSE2-NEXT: cmplepd %xmm0, %xmm2451; SSE2-NEXT: andpd %xmm2, %xmm0452; SSE2-NEXT: andnpd %xmm1, %xmm2453; SSE2-NEXT: orpd %xmm2, %xmm0454; SSE2-NEXT: retq455;456; SSSE3-LABEL: testa:457; SSSE3: # %bb.0: # %entry458; SSSE3-NEXT: movapd %xmm1, %xmm2459; SSSE3-NEXT: cmplepd %xmm0, %xmm2460; SSSE3-NEXT: andpd %xmm2, %xmm0461; SSSE3-NEXT: andnpd %xmm1, %xmm2462; SSSE3-NEXT: orpd %xmm2, %xmm0463; SSSE3-NEXT: retq464;465; SSE41-LABEL: testa:466; SSE41: # %bb.0: # %entry467; SSE41-NEXT: movapd %xmm0, %xmm2468; SSE41-NEXT: movapd %xmm1, %xmm0469; SSE41-NEXT: cmplepd %xmm2, %xmm0470; SSE41-NEXT: blendvpd %xmm0, %xmm2, %xmm1471; SSE41-NEXT: movapd %xmm1, %xmm0472; SSE41-NEXT: retq473;474; AVX-LABEL: testa:475; AVX: # %bb.0: # %entry476; AVX-NEXT: vcmplepd %xmm0, %xmm1, %xmm2477; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0478; AVX-NEXT: retq479entry:480 %max_is_x = fcmp oge <2 x double> %x, %y481 %max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y482 ret <2 x double> %max483}484 485define <2 x double> @testb(<2 x double> %x, <2 x double> %y) {486; SSE2-LABEL: testb:487; SSE2: # %bb.0: # %entry488; SSE2-NEXT: movapd %xmm1, %xmm2489; SSE2-NEXT: cmpnlepd %xmm0, %xmm2490; SSE2-NEXT: andpd %xmm2, %xmm0491; SSE2-NEXT: andnpd %xmm1, %xmm2492; SSE2-NEXT: orpd %xmm2, %xmm0493; SSE2-NEXT: retq494;495; SSSE3-LABEL: testb:496; SSSE3: # %bb.0: # %entry497; SSSE3-NEXT: movapd %xmm1, %xmm2498; SSSE3-NEXT: cmpnlepd %xmm0, %xmm2499; SSSE3-NEXT: andpd %xmm2, %xmm0500; SSSE3-NEXT: andnpd %xmm1, %xmm2501; SSSE3-NEXT: orpd %xmm2, %xmm0502; SSSE3-NEXT: retq503;504; SSE41-LABEL: testb:505; SSE41: # %bb.0: # %entry506; SSE41-NEXT: movapd %xmm0, %xmm2507; SSE41-NEXT: movapd %xmm1, %xmm0508; SSE41-NEXT: cmpnlepd %xmm2, %xmm0509; SSE41-NEXT: blendvpd %xmm0, %xmm2, %xmm1510; SSE41-NEXT: movapd %xmm1, %xmm0511; SSE41-NEXT: retq512;513; AVX-LABEL: testb:514; AVX: # %bb.0: # %entry515; AVX-NEXT: vcmpnlepd %xmm0, %xmm1, %xmm2516; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0517; AVX-NEXT: retq518entry:519 %min_is_x = fcmp ult <2 x double> %x, %y520 %min = select <2 x i1> %min_is_x, <2 x double> %x, <2 x double> %y521 ret <2 x double> %min522}523 524; If we can figure out a blend has a constant mask, we should emit the525; blend instruction with an immediate mask526define <4 x double> @constant_blendvpd_avx(<4 x double> %xy, <4 x double> %ab) {527; SSE2-LABEL: constant_blendvpd_avx:528; SSE2: # %bb.0: # %entry529; SSE2-NEXT: movaps %xmm2, %xmm0530; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3]531; SSE2-NEXT: retq532;533; SSSE3-LABEL: constant_blendvpd_avx:534; SSSE3: # %bb.0: # %entry535; SSSE3-NEXT: movaps %xmm2, %xmm0536; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3]537; SSSE3-NEXT: retq538;539; SSE41-LABEL: constant_blendvpd_avx:540; SSE41: # %bb.0: # %entry541; SSE41-NEXT: movaps %xmm2, %xmm0542; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm1[0,1],xmm3[2,3]543; SSE41-NEXT: retq544;545; AVX-LABEL: constant_blendvpd_avx:546; AVX: # %bb.0: # %entry547; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5],ymm1[6,7]548; AVX-NEXT: retq549entry:550 %select = select <4 x i1> <i1 false, i1 false, i1 true, i1 false>, <4 x double> %xy, <4 x double> %ab551 ret <4 x double> %select552}553 554define <8 x float> @constant_blendvps_avx(<8 x float> %xyzw, <8 x float> %abcd) {555; SSE2-LABEL: constant_blendvps_avx:556; SSE2: # %bb.0: # %entry557; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm2[2,0]558; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,0]559; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm3[2,0]560; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,1],xmm1[2,0]561; SSE2-NEXT: movaps %xmm2, %xmm0562; SSE2-NEXT: movaps %xmm3, %xmm1563; SSE2-NEXT: retq564;565; SSSE3-LABEL: constant_blendvps_avx:566; SSSE3: # %bb.0: # %entry567; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm2[2,0]568; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[2,0]569; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,0],xmm3[2,0]570; SSSE3-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,1],xmm1[2,0]571; SSSE3-NEXT: movaps %xmm2, %xmm0572; SSSE3-NEXT: movaps %xmm3, %xmm1573; SSSE3-NEXT: retq574;575; SSE41-LABEL: constant_blendvps_avx:576; SSE41: # %bb.0: # %entry577; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[3]578; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm3[0,1,2],xmm1[3]579; SSE41-NEXT: retq580;581; AVX-LABEL: constant_blendvps_avx:582; AVX: # %bb.0: # %entry583; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2],ymm0[3],ymm1[4,5,6],ymm0[7]584; AVX-NEXT: retq585entry:586 %select = select <8 x i1> <i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true>, <8 x float> %xyzw, <8 x float> %abcd587 ret <8 x float> %select588}589 590define <32 x i8> @constant_pblendvb_avx2(<32 x i8> %xyzw, <32 x i8> %abcd) {591; SSE2-LABEL: constant_pblendvb_avx2:592; SSE2: # %bb.0: # %entry593; SSE2-NEXT: movaps {{.*#+}} xmm4 = [255,255,0,255,0,0,0,255,255,255,0,255,0,0,0,255]594; SSE2-NEXT: movaps %xmm4, %xmm5595; SSE2-NEXT: andnps %xmm0, %xmm5596; SSE2-NEXT: andps %xmm4, %xmm2597; SSE2-NEXT: orps %xmm2, %xmm5598; SSE2-NEXT: andps %xmm4, %xmm3599; SSE2-NEXT: andnps %xmm1, %xmm4600; SSE2-NEXT: orps %xmm3, %xmm4601; SSE2-NEXT: movaps %xmm5, %xmm0602; SSE2-NEXT: movaps %xmm4, %xmm1603; SSE2-NEXT: retq604;605; SSSE3-LABEL: constant_pblendvb_avx2:606; SSSE3: # %bb.0: # %entry607; SSSE3-NEXT: movdqa {{.*#+}} xmm4 = [128,128,2,128,4,5,6,128,128,128,10,128,12,13,14,128]608; SSSE3-NEXT: pshufb %xmm4, %xmm0609; SSSE3-NEXT: movdqa {{.*#+}} xmm5 = [0,1,128,3,128,128,128,7,8,9,128,11,128,128,128,15]610; SSSE3-NEXT: pshufb %xmm5, %xmm2611; SSSE3-NEXT: por %xmm2, %xmm0612; SSSE3-NEXT: pshufb %xmm4, %xmm1613; SSSE3-NEXT: pshufb %xmm5, %xmm3614; SSSE3-NEXT: por %xmm3, %xmm1615; SSSE3-NEXT: retq616;617; SSE41-LABEL: constant_pblendvb_avx2:618; SSE41: # %bb.0: # %entry619; SSE41-NEXT: movdqa %xmm0, %xmm4620; SSE41-NEXT: movaps {{.*#+}} xmm0 = [255,255,0,255,0,0,0,255,255,255,0,255,0,0,0,255]621; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm4622; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm1623; SSE41-NEXT: movdqa %xmm4, %xmm0624; SSE41-NEXT: retq625;626; AVX1-LABEL: constant_pblendvb_avx2:627; AVX1: # %bb.0: # %entry628; AVX1-NEXT: vbroadcastsd {{.*#+}} ymm2 = [255,255,0,255,0,0,0,255,255,255,0,255,0,0,0,255,255,255,0,255,0,0,0,255,255,255,0,255,0,0,0,255]629; AVX1-NEXT: vandnps %ymm0, %ymm2, %ymm0630; AVX1-NEXT: vandps %ymm2, %ymm1, %ymm1631; AVX1-NEXT: vorps %ymm0, %ymm1, %ymm0632; AVX1-NEXT: retq633;634; AVX2-LABEL: constant_pblendvb_avx2:635; AVX2: # %bb.0: # %entry636; AVX2-NEXT: vpbroadcastq {{.*#+}} ymm2 = [255,255,0,255,0,0,0,255,255,255,0,255,0,0,0,255,255,255,0,255,0,0,0,255,255,255,0,255,0,0,0,255]637; AVX2-NEXT: vpblendvb %ymm2, %ymm1, %ymm0, %ymm0638; AVX2-NEXT: retq639entry:640 %select = select <32 x i1> <i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 true, i1 true, i1 true, i1 false>, <32 x i8> %xyzw, <32 x i8> %abcd641 ret <32 x i8> %select642}643 644declare <8 x float> @llvm.x86.avx.blendv.ps.256(<8 x float>, <8 x float>, <8 x float>)645declare <4 x double> @llvm.x86.avx.blendv.pd.256(<4 x double>, <4 x double>, <4 x double>)646 647;; 4 tests for shufflevectors that optimize to blend + immediate648define <4 x float> @blend_shufflevector_4xfloat(<4 x float> %a, <4 x float> %b) {649; SSE2-LABEL: blend_shufflevector_4xfloat:650; SSE2: # %bb.0: # %entry651; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]652; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]653; SSE2-NEXT: retq654;655; SSSE3-LABEL: blend_shufflevector_4xfloat:656; SSSE3: # %bb.0: # %entry657; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2],xmm1[1,3]658; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,2,1,3]659; SSSE3-NEXT: retq660;661; SSE41-LABEL: blend_shufflevector_4xfloat:662; SSE41: # %bb.0: # %entry663; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]664; SSE41-NEXT: retq665;666; AVX-LABEL: blend_shufflevector_4xfloat:667; AVX: # %bb.0: # %entry668; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3]669; AVX-NEXT: retq670entry:671 %select = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 7>672 ret <4 x float> %select673}674 675define <8 x float> @blend_shufflevector_8xfloat(<8 x float> %a, <8 x float> %b) {676; SSE2-LABEL: blend_shufflevector_8xfloat:677; SSE2: # %bb.0: # %entry678; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]679; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm3[3,0]680; SSE2-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,1],xmm1[0,2]681; SSE2-NEXT: movaps %xmm2, %xmm0682; SSE2-NEXT: movaps %xmm3, %xmm1683; SSE2-NEXT: retq684;685; SSSE3-LABEL: blend_shufflevector_8xfloat:686; SSSE3: # %bb.0: # %entry687; SSSE3-NEXT: movss {{.*#+}} xmm2 = xmm0[0],xmm2[1,2,3]688; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,0],xmm3[3,0]689; SSSE3-NEXT: shufps {{.*#+}} xmm3 = xmm3[0,1],xmm1[0,2]690; SSSE3-NEXT: movaps %xmm2, %xmm0691; SSSE3-NEXT: movaps %xmm3, %xmm1692; SSSE3-NEXT: retq693;694; SSE41-LABEL: blend_shufflevector_8xfloat:695; SSE41: # %bb.0: # %entry696; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm2[1,2,3]697; SSE41-NEXT: blendps {{.*#+}} xmm1 = xmm3[0,1],xmm1[2],xmm3[3]698; SSE41-NEXT: retq699;700; AVX-LABEL: blend_shufflevector_8xfloat:701; AVX: # %bb.0: # %entry702; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0],ymm1[1,2,3,4,5],ymm0[6],ymm1[7]703; AVX-NEXT: retq704entry:705 %select = shufflevector <8 x float> %a, <8 x float> %b, <8 x i32> <i32 0, i32 9, i32 10, i32 11, i32 12, i32 13, i32 6, i32 15>706 ret <8 x float> %select707}708 709define <4 x double> @blend_shufflevector_4xdouble(<4 x double> %a, <4 x double> %b) {710; SSE2-LABEL: blend_shufflevector_4xdouble:711; SSE2: # %bb.0: # %entry712; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3]713; SSE2-NEXT: retq714;715; SSSE3-LABEL: blend_shufflevector_4xdouble:716; SSSE3: # %bb.0: # %entry717; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3]718; SSSE3-NEXT: retq719;720; SSE41-LABEL: blend_shufflevector_4xdouble:721; SSE41: # %bb.0: # %entry722; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3]723; SSE41-NEXT: retq724;725; AVX-LABEL: blend_shufflevector_4xdouble:726; AVX: # %bb.0: # %entry727; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm0[0,1],ymm1[2,3],ymm0[4,5,6,7]728; AVX-NEXT: retq729entry:730 %select = shufflevector <4 x double> %a, <4 x double> %b, <4 x i32> <i32 0, i32 5, i32 2, i32 3>731 ret <4 x double> %select732}733 734define <4 x i64> @blend_shufflevector_4xi64(<4 x i64> %a, <4 x i64> %b) {735; SSE-LABEL: blend_shufflevector_4xi64:736; SSE: # %bb.0: # %entry737; SSE-NEXT: movaps %xmm3, %xmm1738; SSE-NEXT: movsd {{.*#+}} xmm0 = xmm2[0],xmm0[1]739; SSE-NEXT: retq740;741; AVX-LABEL: blend_shufflevector_4xi64:742; AVX: # %bb.0: # %entry743; AVX-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3],ymm1[4,5,6,7]744; AVX-NEXT: retq745entry:746 %select = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 4, i32 1, i32 6, i32 7>747 ret <4 x i64> %select748}749 750define <4 x i32> @blend_logic_v4i32(<4 x i32> %b, <4 x i32> %a, <4 x i32> %c) {751; SSE2-LABEL: blend_logic_v4i32:752; SSE2: # %bb.0: # %entry753; SSE2-NEXT: psrad $31, %xmm0754; SSE2-NEXT: pand %xmm0, %xmm1755; SSE2-NEXT: pandn %xmm2, %xmm0756; SSE2-NEXT: por %xmm1, %xmm0757; SSE2-NEXT: retq758;759; SSSE3-LABEL: blend_logic_v4i32:760; SSSE3: # %bb.0: # %entry761; SSSE3-NEXT: psrad $31, %xmm0762; SSSE3-NEXT: pand %xmm0, %xmm1763; SSSE3-NEXT: pandn %xmm2, %xmm0764; SSSE3-NEXT: por %xmm1, %xmm0765; SSSE3-NEXT: retq766;767; SSE41-LABEL: blend_logic_v4i32:768; SSE41: # %bb.0: # %entry769; SSE41-NEXT: psrad $31, %xmm0770; SSE41-NEXT: pblendvb %xmm0, %xmm1, %xmm2771; SSE41-NEXT: movdqa %xmm2, %xmm0772; SSE41-NEXT: retq773;774; AVX-LABEL: blend_logic_v4i32:775; AVX: # %bb.0: # %entry776; AVX-NEXT: vpsrad $31, %xmm0, %xmm0777; AVX-NEXT: vpblendvb %xmm0, %xmm1, %xmm2, %xmm0778; AVX-NEXT: retq779entry:780 %b.lobit = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>781 %sub = sub nsw <4 x i32> zeroinitializer, %a782 %0 = xor <4 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1>783 %1 = and <4 x i32> %c, %0784 %2 = and <4 x i32> %a, %b.lobit785 %cond = or <4 x i32> %1, %2786 ret <4 x i32> %cond787}788 789define <8 x i32> @blend_logic_v8i32(<8 x i32> %b, <8 x i32> %a, <8 x i32> %c) {790; SSE2-LABEL: blend_logic_v8i32:791; SSE2: # %bb.0: # %entry792; SSE2-NEXT: psrad $31, %xmm0793; SSE2-NEXT: psrad $31, %xmm1794; SSE2-NEXT: pand %xmm1, %xmm3795; SSE2-NEXT: pandn %xmm5, %xmm1796; SSE2-NEXT: por %xmm3, %xmm1797; SSE2-NEXT: pand %xmm0, %xmm2798; SSE2-NEXT: pandn %xmm4, %xmm0799; SSE2-NEXT: por %xmm2, %xmm0800; SSE2-NEXT: retq801;802; SSSE3-LABEL: blend_logic_v8i32:803; SSSE3: # %bb.0: # %entry804; SSSE3-NEXT: psrad $31, %xmm0805; SSSE3-NEXT: psrad $31, %xmm1806; SSSE3-NEXT: pand %xmm1, %xmm3807; SSSE3-NEXT: pandn %xmm5, %xmm1808; SSSE3-NEXT: por %xmm3, %xmm1809; SSSE3-NEXT: pand %xmm0, %xmm2810; SSSE3-NEXT: pandn %xmm4, %xmm0811; SSSE3-NEXT: por %xmm2, %xmm0812; SSSE3-NEXT: retq813;814; SSE41-LABEL: blend_logic_v8i32:815; SSE41: # %bb.0: # %entry816; SSE41-NEXT: psrad $31, %xmm1817; SSE41-NEXT: psrad $31, %xmm0818; SSE41-NEXT: pblendvb %xmm0, %xmm2, %xmm4819; SSE41-NEXT: movdqa %xmm1, %xmm0820; SSE41-NEXT: pblendvb %xmm0, %xmm3, %xmm5821; SSE41-NEXT: movdqa %xmm4, %xmm0822; SSE41-NEXT: movdqa %xmm5, %xmm1823; SSE41-NEXT: retq824;825; AVX1-LABEL: blend_logic_v8i32:826; AVX1: # %bb.0: # %entry827; AVX1-NEXT: vpsrad $31, %xmm0, %xmm3828; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0829; AVX1-NEXT: vpsrad $31, %xmm0, %xmm0830; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm3, %ymm0831; AVX1-NEXT: vandnps %ymm2, %ymm0, %ymm2832; AVX1-NEXT: vandps %ymm0, %ymm1, %ymm0833; AVX1-NEXT: vorps %ymm0, %ymm2, %ymm0834; AVX1-NEXT: retq835;836; AVX2-LABEL: blend_logic_v8i32:837; AVX2: # %bb.0: # %entry838; AVX2-NEXT: vpsrad $31, %ymm0, %ymm0839; AVX2-NEXT: vpblendvb %ymm0, %ymm1, %ymm2, %ymm0840; AVX2-NEXT: retq841entry:842 %b.lobit = ashr <8 x i32> %b, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>843 %sub = sub nsw <8 x i32> zeroinitializer, %a844 %0 = xor <8 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>845 %1 = and <8 x i32> %c, %0846 %2 = and <8 x i32> %a, %b.lobit847 %cond = or <8 x i32> %1, %2848 ret <8 x i32> %cond849}850 851define <4 x i32> @blend_neg_logic_v4i32(<4 x i32> %a, <4 x i32> %b) {852; SSE-LABEL: blend_neg_logic_v4i32:853; SSE: # %bb.0: # %entry854; SSE-NEXT: psrad $31, %xmm1855; SSE-NEXT: pxor %xmm1, %xmm0856; SSE-NEXT: psubd %xmm1, %xmm0857; SSE-NEXT: retq858;859; AVX-LABEL: blend_neg_logic_v4i32:860; AVX: # %bb.0: # %entry861; AVX-NEXT: vpsrad $31, %xmm1, %xmm1862; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0863; AVX-NEXT: vpsubd %xmm1, %xmm0, %xmm0864; AVX-NEXT: retq865entry:866 %b.lobit = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>867 %sub = sub nsw <4 x i32> zeroinitializer, %a868 %0 = xor <4 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1>869 %1 = and <4 x i32> %a, %0870 %2 = and <4 x i32> %b.lobit, %sub871 %cond = or <4 x i32> %1, %2872 ret <4 x i32> %cond873}874 875define <8 x i32> @blend_neg_logic_v8i32(<8 x i32> %a, <8 x i32> %b) {876; SSE-LABEL: blend_neg_logic_v8i32:877; SSE: # %bb.0: # %entry878; SSE-NEXT: psrad $31, %xmm3879; SSE-NEXT: psrad $31, %xmm2880; SSE-NEXT: pxor %xmm2, %xmm0881; SSE-NEXT: psubd %xmm2, %xmm0882; SSE-NEXT: pxor %xmm3, %xmm1883; SSE-NEXT: psubd %xmm3, %xmm1884; SSE-NEXT: retq885;886; AVX1-LABEL: blend_neg_logic_v8i32:887; AVX1: # %bb.0: # %entry888; AVX1-NEXT: vpsrad $31, %xmm1, %xmm2889; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm1890; AVX1-NEXT: vpsrad $31, %xmm1, %xmm1891; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1892; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2893; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3894; AVX1-NEXT: vpsubd %xmm2, %xmm3, %xmm2895; AVX1-NEXT: vpsubd %xmm0, %xmm3, %xmm3896; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm3, %ymm2897; AVX1-NEXT: vandnps %ymm0, %ymm1, %ymm0898; AVX1-NEXT: vandps %ymm2, %ymm1, %ymm1899; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0900; AVX1-NEXT: retq901;902; AVX2-LABEL: blend_neg_logic_v8i32:903; AVX2: # %bb.0: # %entry904; AVX2-NEXT: vpsrad $31, %ymm1, %ymm1905; AVX2-NEXT: vpxor %ymm1, %ymm0, %ymm0906; AVX2-NEXT: vpsubd %ymm1, %ymm0, %ymm0907; AVX2-NEXT: retq908entry:909 %b.lobit = ashr <8 x i32> %b, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>910 %sub = sub nsw <8 x i32> zeroinitializer, %a911 %0 = xor <8 x i32> %b.lobit, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>912 %1 = and <8 x i32> %a, %0913 %2 = and <8 x i32> %b.lobit, %sub914 %cond = or <8 x i32> %1, %2915 ret <8 x i32> %cond916}917 918define <4 x i32> @blend_neg_logic_v4i32_2(<4 x i32> %v, <4 x i32> %c) {919; SSE-LABEL: blend_neg_logic_v4i32_2:920; SSE: # %bb.0: # %entry921; SSE-NEXT: psrad $31, %xmm1922; SSE-NEXT: pxor %xmm1, %xmm0923; SSE-NEXT: psubd %xmm0, %xmm1924; SSE-NEXT: movdqa %xmm1, %xmm0925; SSE-NEXT: retq926;927; AVX-LABEL: blend_neg_logic_v4i32_2:928; AVX: # %bb.0: # %entry929; AVX-NEXT: vpsrad $31, %xmm1, %xmm1930; AVX-NEXT: vpxor %xmm1, %xmm0, %xmm0931; AVX-NEXT: vpsubd %xmm0, %xmm1, %xmm0932; AVX-NEXT: retq933entry:934 %0 = ashr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>935 %1 = trunc <4 x i32> %0 to <4 x i1>936 %2 = sub nsw <4 x i32> zeroinitializer, %v937 %3 = select <4 x i1> %1, <4 x i32> %v, <4 x i32> %2938 ret <4 x i32> %3939}940