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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s --check-prefix=SSE23; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s --check-prefix=AVX24 5define <8 x i32> @zext_and_v8i32(<8 x i16> %x, <8 x i16> %y) {6; SSE2-LABEL: zext_and_v8i32:7; SSE2: # %bb.0:8; SSE2-NEXT: pand %xmm0, %xmm19; SSE2-NEXT: pxor %xmm2, %xmm210; SSE2-NEXT: movdqa %xmm1, %xmm011; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]12; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]13; SSE2-NEXT: retq14;15; AVX2-LABEL: zext_and_v8i32:16; AVX2: # %bb.0:17; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm018; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero19; AVX2-NEXT: retq20 %xz = zext <8 x i16> %x to <8 x i32>21 %yz = zext <8 x i16> %y to <8 x i32>22 %r = and <8 x i32> %xz, %yz23 ret <8 x i32> %r24}25 26define <8 x i32> @zext_or_v8i32(<8 x i16> %x, <8 x i16> %y) {27; SSE2-LABEL: zext_or_v8i32:28; SSE2: # %bb.0:29; SSE2-NEXT: por %xmm0, %xmm130; SSE2-NEXT: pxor %xmm2, %xmm231; SSE2-NEXT: movdqa %xmm1, %xmm032; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]33; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]34; SSE2-NEXT: retq35;36; AVX2-LABEL: zext_or_v8i32:37; AVX2: # %bb.0:38; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm039; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero40; AVX2-NEXT: retq41 %xz = zext <8 x i16> %x to <8 x i32>42 %yz = zext <8 x i16> %y to <8 x i32>43 %r = or <8 x i32> %xz, %yz44 ret <8 x i32> %r45}46 47define <8 x i32> @zext_xor_v8i32(<8 x i16> %x, <8 x i16> %y) {48; SSE2-LABEL: zext_xor_v8i32:49; SSE2: # %bb.0:50; SSE2-NEXT: pxor %xmm0, %xmm151; SSE2-NEXT: pxor %xmm2, %xmm252; SSE2-NEXT: movdqa %xmm1, %xmm053; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]54; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]55; SSE2-NEXT: retq56;57; AVX2-LABEL: zext_xor_v8i32:58; AVX2: # %bb.0:59; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm060; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero61; AVX2-NEXT: retq62 %xz = zext <8 x i16> %x to <8 x i32>63 %yz = zext <8 x i16> %y to <8 x i32>64 %r = xor <8 x i32> %xz, %yz65 ret <8 x i32> %r66}67 68define <8 x i32> @sext_and_v8i32(<8 x i16> %x, <8 x i16> %y) {69; SSE2-LABEL: sext_and_v8i32:70; SSE2: # %bb.0:71; SSE2-NEXT: pand %xmm1, %xmm072; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]73; SSE2-NEXT: psrad $16, %xmm274; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]75; SSE2-NEXT: psrad $16, %xmm176; SSE2-NEXT: movdqa %xmm2, %xmm077; SSE2-NEXT: retq78;79; AVX2-LABEL: sext_and_v8i32:80; AVX2: # %bb.0:81; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm082; AVX2-NEXT: vpmovsxwd %xmm0, %ymm083; AVX2-NEXT: retq84 %xs = sext <8 x i16> %x to <8 x i32>85 %ys = sext <8 x i16> %y to <8 x i32>86 %r = and <8 x i32> %xs, %ys87 ret <8 x i32> %r88}89 90define <8 x i32> @sext_or_v8i32(<8 x i16> %x, <8 x i16> %y) {91; SSE2-LABEL: sext_or_v8i32:92; SSE2: # %bb.0:93; SSE2-NEXT: por %xmm1, %xmm094; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]95; SSE2-NEXT: psrad $16, %xmm296; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]97; SSE2-NEXT: psrad $16, %xmm198; SSE2-NEXT: movdqa %xmm2, %xmm099; SSE2-NEXT: retq100;101; AVX2-LABEL: sext_or_v8i32:102; AVX2: # %bb.0:103; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0104; AVX2-NEXT: vpmovsxwd %xmm0, %ymm0105; AVX2-NEXT: retq106 %xs = sext <8 x i16> %x to <8 x i32>107 %ys = sext <8 x i16> %y to <8 x i32>108 %r = or <8 x i32> %xs, %ys109 ret <8 x i32> %r110}111 112define <8 x i32> @sext_xor_v8i32(<8 x i16> %x, <8 x i16> %y) {113; SSE2-LABEL: sext_xor_v8i32:114; SSE2: # %bb.0:115; SSE2-NEXT: pxor %xmm1, %xmm0116; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3]117; SSE2-NEXT: psrad $16, %xmm2118; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm0[4],xmm1[5],xmm0[5],xmm1[6],xmm0[6],xmm1[7],xmm0[7]119; SSE2-NEXT: psrad $16, %xmm1120; SSE2-NEXT: movdqa %xmm2, %xmm0121; SSE2-NEXT: retq122;123; AVX2-LABEL: sext_xor_v8i32:124; AVX2: # %bb.0:125; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0126; AVX2-NEXT: vpmovsxwd %xmm0, %ymm0127; AVX2-NEXT: retq128 %xs = sext <8 x i16> %x to <8 x i32>129 %ys = sext <8 x i16> %y to <8 x i32>130 %r = xor <8 x i32> %xs, %ys131 ret <8 x i32> %r132}133 134define <8 x i16> @zext_and_v8i16(<8 x i8> %x, <8 x i8> %y) {135; SSE2-LABEL: zext_and_v8i16:136; SSE2: # %bb.0:137; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]138; SSE2-NEXT: pxor %xmm2, %xmm2139; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]140; SSE2-NEXT: pand %xmm1, %xmm0141; SSE2-NEXT: retq142;143; AVX2-LABEL: zext_and_v8i16:144; AVX2: # %bb.0:145; AVX2-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero146; AVX2-NEXT: vpmovzxbw {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero147; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0148; AVX2-NEXT: retq149 %xz = zext <8 x i8> %x to <8 x i16>150 %yz = zext <8 x i8> %y to <8 x i16>151 %r = and <8 x i16> %xz, %yz152 ret <8 x i16> %r153}154 155define <8 x i16> @zext_or_v8i16(<8 x i8> %x, <8 x i8> %y) {156; SSE2-LABEL: zext_or_v8i16:157; SSE2: # %bb.0:158; SSE2-NEXT: por %xmm1, %xmm0159; SSE2-NEXT: pxor %xmm1, %xmm1160; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]161; SSE2-NEXT: retq162;163; AVX2-LABEL: zext_or_v8i16:164; AVX2: # %bb.0:165; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0166; AVX2-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero167; AVX2-NEXT: retq168 %xz = zext <8 x i8> %x to <8 x i16>169 %yz = zext <8 x i8> %y to <8 x i16>170 %r = or <8 x i16> %xz, %yz171 ret <8 x i16> %r172}173 174define <8 x i16> @zext_xor_v8i16(<8 x i8> %x, <8 x i8> %y) {175; SSE2-LABEL: zext_xor_v8i16:176; SSE2: # %bb.0:177; SSE2-NEXT: pxor %xmm1, %xmm0178; SSE2-NEXT: pxor %xmm1, %xmm1179; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7]180; SSE2-NEXT: retq181;182; AVX2-LABEL: zext_xor_v8i16:183; AVX2: # %bb.0:184; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0185; AVX2-NEXT: vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero186; AVX2-NEXT: retq187 %xz = zext <8 x i8> %x to <8 x i16>188 %yz = zext <8 x i8> %y to <8 x i16>189 %r = xor <8 x i16> %xz, %yz190 ret <8 x i16> %r191}192 193define <8 x i16> @sext_and_v8i16(<8 x i8> %x, <8 x i8> %y) {194; SSE2-LABEL: sext_and_v8i16:195; SSE2: # %bb.0:196; SSE2-NEXT: pand %xmm1, %xmm0197; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]198; SSE2-NEXT: psraw $8, %xmm0199; SSE2-NEXT: retq200;201; AVX2-LABEL: sext_and_v8i16:202; AVX2: # %bb.0:203; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0204; AVX2-NEXT: vpmovsxbw %xmm0, %xmm0205; AVX2-NEXT: retq206 %xs = sext <8 x i8> %x to <8 x i16>207 %ys = sext <8 x i8> %y to <8 x i16>208 %r = and <8 x i16> %xs, %ys209 ret <8 x i16> %r210}211 212define <8 x i16> @sext_or_v8i16(<8 x i8> %x, <8 x i8> %y) {213; SSE2-LABEL: sext_or_v8i16:214; SSE2: # %bb.0:215; SSE2-NEXT: por %xmm1, %xmm0216; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]217; SSE2-NEXT: psraw $8, %xmm0218; SSE2-NEXT: retq219;220; AVX2-LABEL: sext_or_v8i16:221; AVX2: # %bb.0:222; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0223; AVX2-NEXT: vpmovsxbw %xmm0, %xmm0224; AVX2-NEXT: retq225 %xs = sext <8 x i8> %x to <8 x i16>226 %ys = sext <8 x i8> %y to <8 x i16>227 %r = or <8 x i16> %xs, %ys228 ret <8 x i16> %r229}230 231define <8 x i16> @sext_xor_v8i16(<8 x i8> %x, <8 x i8> %y) {232; SSE2-LABEL: sext_xor_v8i16:233; SSE2: # %bb.0:234; SSE2-NEXT: pxor %xmm1, %xmm0235; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]236; SSE2-NEXT: psraw $8, %xmm0237; SSE2-NEXT: retq238;239; AVX2-LABEL: sext_xor_v8i16:240; AVX2: # %bb.0:241; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0242; AVX2-NEXT: vpmovsxbw %xmm0, %xmm0243; AVX2-NEXT: retq244 %xs = sext <8 x i8> %x to <8 x i16>245 %ys = sext <8 x i8> %y to <8 x i16>246 %r = xor <8 x i16> %xs, %ys247 ret <8 x i16> %r248}249 250define <8 x i32> @bool_zext_and(<8 x i1> %x, <8 x i1> %y) {251; SSE2-LABEL: bool_zext_and:252; SSE2: # %bb.0:253; SSE2-NEXT: movdqa %xmm0, %xmm3254; SSE2-NEXT: punpckhwd {{.*#+}} xmm3 = xmm3[4,4,5,5,6,6,7,7]255; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]256; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1257; SSE2-NEXT: pxor %xmm4, %xmm4258; SSE2-NEXT: movdqa %xmm1, %xmm2259; SSE2-NEXT: punpckhwd {{.*#+}} xmm2 = xmm2[4],xmm4[4],xmm2[5],xmm4[5],xmm2[6],xmm4[6],xmm2[7],xmm4[7]260; SSE2-NEXT: pand %xmm3, %xmm2261; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3]262; SSE2-NEXT: pand %xmm1, %xmm0263; SSE2-NEXT: movdqa %xmm2, %xmm1264; SSE2-NEXT: retq265;266; AVX2-LABEL: bool_zext_and:267; AVX2: # %bb.0:268; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero269; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1270; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero271; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0272; AVX2-NEXT: retq273 %xz = zext <8 x i1> %x to <8 x i32>274 %yz = zext <8 x i1> %y to <8 x i32>275 %r = and <8 x i32> %xz, %yz276 ret <8 x i32> %r277}278 279define <8 x i32> @bool_zext_or(<8 x i1> %x, <8 x i1> %y) {280; SSE2-LABEL: bool_zext_or:281; SSE2: # %bb.0:282; SSE2-NEXT: por %xmm0, %xmm1283; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1284; SSE2-NEXT: pxor %xmm2, %xmm2285; SSE2-NEXT: movdqa %xmm1, %xmm0286; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]287; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]288; SSE2-NEXT: retq289;290; AVX2-LABEL: bool_zext_or:291; AVX2: # %bb.0:292; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0293; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0294; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero295; AVX2-NEXT: retq296 %xz = zext <8 x i1> %x to <8 x i32>297 %yz = zext <8 x i1> %y to <8 x i32>298 %r = or <8 x i32> %xz, %yz299 ret <8 x i32> %r300}301 302define <8 x i32> @bool_zext_xor(<8 x i1> %x, <8 x i1> %y) {303; SSE2-LABEL: bool_zext_xor:304; SSE2: # %bb.0:305; SSE2-NEXT: pxor %xmm0, %xmm1306; SSE2-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1307; SSE2-NEXT: pxor %xmm2, %xmm2308; SSE2-NEXT: movdqa %xmm1, %xmm0309; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]310; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]311; SSE2-NEXT: retq312;313; AVX2-LABEL: bool_zext_xor:314; AVX2: # %bb.0:315; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0316; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0317; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero318; AVX2-NEXT: retq319 %xz = zext <8 x i1> %x to <8 x i32>320 %yz = zext <8 x i1> %y to <8 x i32>321 %r = xor <8 x i32> %xz, %yz322 ret <8 x i32> %r323}324 325define <8 x i32> @bool_sext_and(<8 x i1> %x, <8 x i1> %y) {326; SSE2-LABEL: bool_sext_and:327; SSE2: # %bb.0:328; SSE2-NEXT: pand %xmm0, %xmm1329; SSE2-NEXT: movdqa %xmm1, %xmm0330; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]331; SSE2-NEXT: pslld $31, %xmm0332; SSE2-NEXT: psrad $31, %xmm0333; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]334; SSE2-NEXT: pslld $31, %xmm1335; SSE2-NEXT: psrad $31, %xmm1336; SSE2-NEXT: retq337;338; AVX2-LABEL: bool_sext_and:339; AVX2: # %bb.0:340; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0341; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero342; AVX2-NEXT: vpslld $31, %ymm0, %ymm0343; AVX2-NEXT: vpsrad $31, %ymm0, %ymm0344; AVX2-NEXT: retq345 %xs = sext <8 x i1> %x to <8 x i32>346 %ys = sext <8 x i1> %y to <8 x i32>347 %r = and <8 x i32> %xs, %ys348 ret <8 x i32> %r349}350 351define <8 x i32> @bool_sext_or(<8 x i1> %x, <8 x i1> %y) {352; SSE2-LABEL: bool_sext_or:353; SSE2: # %bb.0:354; SSE2-NEXT: por %xmm0, %xmm1355; SSE2-NEXT: movdqa %xmm1, %xmm0356; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]357; SSE2-NEXT: pslld $31, %xmm0358; SSE2-NEXT: psrad $31, %xmm0359; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]360; SSE2-NEXT: pslld $31, %xmm1361; SSE2-NEXT: psrad $31, %xmm1362; SSE2-NEXT: retq363;364; AVX2-LABEL: bool_sext_or:365; AVX2: # %bb.0:366; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0367; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero368; AVX2-NEXT: vpslld $31, %ymm0, %ymm0369; AVX2-NEXT: vpsrad $31, %ymm0, %ymm0370; AVX2-NEXT: retq371 %xs = sext <8 x i1> %x to <8 x i32>372 %ys = sext <8 x i1> %y to <8 x i32>373 %r = or <8 x i32> %xs, %ys374 ret <8 x i32> %r375}376 377define <8 x i32> @bool_sext_xor(<8 x i1> %x, <8 x i1> %y) {378; SSE2-LABEL: bool_sext_xor:379; SSE2: # %bb.0:380; SSE2-NEXT: pxor %xmm0, %xmm1381; SSE2-NEXT: movdqa %xmm1, %xmm0382; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]383; SSE2-NEXT: pslld $31, %xmm0384; SSE2-NEXT: psrad $31, %xmm0385; SSE2-NEXT: punpckhwd {{.*#+}} xmm1 = xmm1[4,4,5,5,6,6,7,7]386; SSE2-NEXT: pslld $31, %xmm1387; SSE2-NEXT: psrad $31, %xmm1388; SSE2-NEXT: retq389;390; AVX2-LABEL: bool_sext_xor:391; AVX2: # %bb.0:392; AVX2-NEXT: vpxor %xmm1, %xmm0, %xmm0393; AVX2-NEXT: vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero394; AVX2-NEXT: vpslld $31, %ymm0, %ymm0395; AVX2-NEXT: vpsrad $31, %ymm0, %ymm0396; AVX2-NEXT: retq397 %xs = sext <8 x i1> %x to <8 x i32>398 %ys = sext <8 x i1> %y to <8 x i32>399 %r = xor <8 x i32> %xs, %ys400 ret <8 x i32> %r401}402 403