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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s --check-prefix=SSE3; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s --check-prefix=AVX4 5; xor undef, undef --> 0 because it's not worth fighting to make that return undef?6 7define <4 x i64> @xor_insert_insert(<2 x i64> %x, <2 x i64> %y) {8; SSE-LABEL: xor_insert_insert:9; SSE: # %bb.0:10; SSE-NEXT: xorps %xmm1, %xmm011; SSE-NEXT: xorps %xmm1, %xmm112; SSE-NEXT: retq13;14; AVX-LABEL: xor_insert_insert:15; AVX: # %bb.0:16; AVX-NEXT: vxorps %xmm1, %xmm0, %xmm017; AVX-NEXT: retq18 %xw = shufflevector <2 x i64> %x, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>19 %yw = shufflevector <2 x i64> %y, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>20 %r = xor <4 x i64> %xw, %yw21 ret <4 x i64> %r22}23 24define <4 x i64> @xor_insert_insert_high_half(<2 x i64> %x, <2 x i64> %y) {25; SSE-LABEL: xor_insert_insert_high_half:26; SSE: # %bb.0:27; SSE-NEXT: xorps %xmm0, %xmm128; SSE-NEXT: xorps %xmm0, %xmm029; SSE-NEXT: retq30;31; AVX-LABEL: xor_insert_insert_high_half:32; AVX: # %bb.0:33; AVX-NEXT: vxorps %xmm1, %xmm0, %xmm034; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm135; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm036; AVX-NEXT: retq37 %xw = shufflevector <2 x i64> %x, <2 x i64> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>38 %yw = shufflevector <2 x i64> %y, <2 x i64> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>39 %r = xor <4 x i64> %xw, %yw40 ret <4 x i64> %r41}42 43; All elements of the add are undefined:44; x[0] , x[1] , x[2] , x[3], u , u , u , u45; + u , u , u , u , 42 , 43 , 44 , 4546 47define <8 x i32> @add_undef_elts(<4 x i32> %x) {48; SSE-LABEL: add_undef_elts:49; SSE: # %bb.0:50; SSE-NEXT: retq51;52; AVX-LABEL: add_undef_elts:53; AVX: # %bb.0:54; AVX-NEXT: retq55 %extend = shufflevector <4 x i32> %x, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>56 %bogus_bo = add <8 x i32> %extend, <i32 undef, i32 undef, i32 undef, i32 undef, i32 42, i32 43, i32 44, i32 12>57 %arbitrary_shuf = shufflevector <8 x i32> %bogus_bo, <8 x i32> undef, <8 x i32> <i32 6, i32 0, i32 5, i32 4, i32 3, i32 2, i32 1, i32 7>58 ret <8 x i32> %arbitrary_shuf59}60 61; Verify that constant operand 0 for a sub works too.62 63define <8 x i32> @sub_undef_elts(<4 x i32> %x) {64; SSE-LABEL: sub_undef_elts:65; SSE: # %bb.0:66; SSE-NEXT: retq67;68; AVX-LABEL: sub_undef_elts:69; AVX: # %bb.0:70; AVX-NEXT: retq71 %extend = shufflevector <4 x i32> %x, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>72 %bogus_bo = sub <8 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 42, i32 43, i32 44, i32 12>, %extend73 %arbitrary_shuf = shufflevector <8 x i32> %bogus_bo, <8 x i32> undef, <8 x i32> <i32 1, i32 0, i32 5, i32 4, i32 3, i32 2, i32 6, i32 7>74 ret <8 x i32> %arbitrary_shuf75}76 77; and undef, C --> 0, so this tests that we are tracking known zero lanes.78 79define <4 x i64> @and_undef_elts(<2 x i64> %x) {80; SSE-LABEL: and_undef_elts:81; SSE: # %bb.0:82; SSE-NEXT: xorps %xmm0, %xmm083; SSE-NEXT: xorps %xmm1, %xmm184; SSE-NEXT: retq85;86; AVX-LABEL: and_undef_elts:87; AVX: # %bb.0:88; AVX-NEXT: vxorps %xmm0, %xmm0, %xmm089; AVX-NEXT: retq90 %extend = shufflevector <2 x i64> %x, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>91 %bogus_bo = and <4 x i64> %extend, <i64 undef, i64 undef, i64 42, i64 43>92 %arbitrary_shuf = shufflevector <4 x i64> %bogus_bo, <4 x i64> undef, <4 x i32> <i32 3, i32 0, i32 1, i32 2>93 ret <4 x i64> %arbitrary_shuf94}95 96; or undef, C --> -1, so this tests that we are tracking known all-ones lanes.97 98define <4 x i64> @or_undef_elts(<2 x i64> %x) {99; SSE-LABEL: or_undef_elts:100; SSE: # %bb.0:101; SSE-NEXT: pcmpeqd %xmm0, %xmm0102; SSE-NEXT: pcmpeqd %xmm1, %xmm1103; SSE-NEXT: retq104;105; AVX-LABEL: or_undef_elts:106; AVX: # %bb.0:107; AVX-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0108; AVX-NEXT: vpermpd {{.*#+}} ymm0 = ymm0[3,0,1,2]109; AVX-NEXT: vorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0110; AVX-NEXT: retq111 %extend = shufflevector <2 x i64> %x, <2 x i64> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>112 %bogus_bo = or <4 x i64> %extend, <i64 undef, i64 undef, i64 42, i64 43>113 %arbitrary_shuf = shufflevector <4 x i64> %bogus_bo, <4 x i64> undef, <4 x i32> <i32 3, i32 0, i32 1, i32 2>114 ret <4 x i64> %arbitrary_shuf115}116 117; Verify that this isn't limited to high/low halves.118 119define <8 x i32> @xor_undef_elts(<4 x i32> %x) {120; SSE-LABEL: xor_undef_elts:121; SSE: # %bb.0:122; SSE-NEXT: retq123;124; AVX-LABEL: xor_undef_elts:125; AVX: # %bb.0:126; AVX-NEXT: retq127 %extend = shufflevector <4 x i32> %x, <4 x i32> undef, <8 x i32> <i32 undef, i32 undef, i32 1, i32 3, i32 0, i32 2, i32 undef, i32 undef>128 %bogus_bo = xor <8 x i32> %extend, <i32 42, i32 43, i32 undef, i32 undef, i32 undef, i32 undef, i32 44, i32 12>129 %arbitrary_shuf = shufflevector <8 x i32> %bogus_bo, <8 x i32> undef, <8 x i32> <i32 6, i32 1, i32 5, i32 4, i32 3, i32 2, i32 0, i32 7>130 ret <8 x i32> %arbitrary_shuf131}132 133; Verify that this isn't limited to high/low halves134; Special case: the undef-ness of the 1st shuffle may be lost if we turn that into vector concat.135 136define <8 x i32> @xor_undef_elts_alt(<4 x i32> %x) {137; SSE-LABEL: xor_undef_elts_alt:138; SSE: # %bb.0:139; SSE-NEXT: movaps %xmm0, %xmm1140; SSE-NEXT: movaps {{.*#+}} xmm2 = [u,u,44,12]141; SSE-NEXT: xorps %xmm0, %xmm2142; SSE-NEXT: xorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1143; SSE-NEXT: movaps %xmm1, %xmm0144; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0],xmm2[2,0]145; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm2[1,0]146; SSE-NEXT: shufps {{.*#+}} xmm2 = xmm2[3,0],xmm1[0,0]147; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[3,2],xmm2[2,0]148; SSE-NEXT: retq149;150; AVX-LABEL: xor_undef_elts_alt:151; AVX: # %bb.0:152; AVX-NEXT: # kill: def $xmm0 killed $xmm0 def $ymm0153; AVX-NEXT: vmovaps {{.*#+}} ymm1 = [2,1,1,0,3,2,0,3]154; AVX-NEXT: vpermps %ymm0, %ymm1, %ymm0155; AVX-NEXT: vxorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0156; AVX-NEXT: retq157 %extend = shufflevector <4 x i32> %x, <4 x i32> undef, <8 x i32> <i32 undef, i32 undef, i32 2, i32 3, i32 0, i32 1, i32 undef, i32 undef>158 %bogus_bo = xor <8 x i32> %extend, <i32 42, i32 43, i32 undef, i32 undef, i32 undef, i32 undef, i32 44, i32 12>159 %arbitrary_shuf = shufflevector <8 x i32> %bogus_bo, <8 x i32> undef, <8 x i32> <i32 6, i32 1, i32 5, i32 4, i32 3, i32 2, i32 0, i32 7>160 ret <8 x i32> %arbitrary_shuf161}162 163