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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=ALL,SSE,SSE23; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=ALL,SSE,SSE414; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=ALL,AVX5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=ALL,AVX6; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=ALL,AVX512,AVX512F7; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefixes=ALL,AVX512,AVX512VL8; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512fp16,+avx512vl | FileCheck %s --check-prefixes=ALL,AVX512,AVX512FP169 10;11; vXf3212;13 14define float @test_v1f32(<1 x float> %a0) {15; ALL-LABEL: test_v1f32:16; ALL: # %bb.0:17; ALL-NEXT: retq18 %1 = call nnan float @llvm.vector.reduce.fmax.v1f32(<1 x float> %a0)19 ret float %120}21 22define float @test_v2f32(<2 x float> %a0) {23; SSE2-LABEL: test_v2f32:24; SSE2: # %bb.0:25; SSE2-NEXT: movaps %xmm0, %xmm126; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]27; SSE2-NEXT: maxss %xmm1, %xmm028; SSE2-NEXT: retq29;30; SSE41-LABEL: test_v2f32:31; SSE41: # %bb.0:32; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]33; SSE41-NEXT: maxss %xmm1, %xmm034; SSE41-NEXT: retq35;36; AVX-LABEL: test_v2f32:37; AVX: # %bb.0:38; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]39; AVX-NEXT: vmaxss %xmm1, %xmm0, %xmm040; AVX-NEXT: retq41;42; AVX512-LABEL: test_v2f32:43; AVX512: # %bb.0:44; AVX512-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]45; AVX512-NEXT: vmaxss %xmm1, %xmm0, %xmm046; AVX512-NEXT: retq47 %1 = call nnan float @llvm.vector.reduce.fmax.v2f32(<2 x float> %a0)48 ret float %149}50 51define float @test_v4f32(<4 x float> %a0) {52; SSE2-LABEL: test_v4f32:53; SSE2: # %bb.0:54; SSE2-NEXT: movaps %xmm0, %xmm155; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]56; SSE2-NEXT: maxps %xmm1, %xmm057; SSE2-NEXT: movaps %xmm0, %xmm158; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]59; SSE2-NEXT: maxss %xmm1, %xmm060; SSE2-NEXT: retq61;62; SSE41-LABEL: test_v4f32:63; SSE41: # %bb.0:64; SSE41-NEXT: movaps %xmm0, %xmm165; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]66; SSE41-NEXT: maxps %xmm1, %xmm067; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]68; SSE41-NEXT: maxss %xmm1, %xmm069; SSE41-NEXT: retq70;71; AVX-LABEL: test_v4f32:72; AVX: # %bb.0:73; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]74; AVX-NEXT: vmaxps %xmm1, %xmm0, %xmm075; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]76; AVX-NEXT: vmaxss %xmm1, %xmm0, %xmm077; AVX-NEXT: retq78;79; AVX512-LABEL: test_v4f32:80; AVX512: # %bb.0:81; AVX512-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]82; AVX512-NEXT: vmaxps %xmm1, %xmm0, %xmm083; AVX512-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]84; AVX512-NEXT: vmaxss %xmm1, %xmm0, %xmm085; AVX512-NEXT: retq86 %1 = call nnan float @llvm.vector.reduce.fmax.v4f32(<4 x float> %a0)87 ret float %188}89 90define float @test_v8f32(<8 x float> %a0) {91; SSE2-LABEL: test_v8f32:92; SSE2: # %bb.0:93; SSE2-NEXT: maxps %xmm1, %xmm094; SSE2-NEXT: movaps %xmm0, %xmm195; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]96; SSE2-NEXT: maxps %xmm1, %xmm097; SSE2-NEXT: movaps %xmm0, %xmm198; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]99; SSE2-NEXT: maxss %xmm1, %xmm0100; SSE2-NEXT: retq101;102; SSE41-LABEL: test_v8f32:103; SSE41: # %bb.0:104; SSE41-NEXT: maxps %xmm1, %xmm0105; SSE41-NEXT: movaps %xmm0, %xmm1106; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]107; SSE41-NEXT: maxps %xmm1, %xmm0108; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]109; SSE41-NEXT: maxss %xmm1, %xmm0110; SSE41-NEXT: retq111;112; AVX-LABEL: test_v8f32:113; AVX: # %bb.0:114; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1115; AVX-NEXT: vmaxps %xmm1, %xmm0, %xmm0116; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]117; AVX-NEXT: vmaxps %xmm1, %xmm0, %xmm0118; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]119; AVX-NEXT: vmaxss %xmm1, %xmm0, %xmm0120; AVX-NEXT: vzeroupper121; AVX-NEXT: retq122;123; AVX512-LABEL: test_v8f32:124; AVX512: # %bb.0:125; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm1126; AVX512-NEXT: vmaxps %xmm1, %xmm0, %xmm0127; AVX512-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]128; AVX512-NEXT: vmaxps %xmm1, %xmm0, %xmm0129; AVX512-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]130; AVX512-NEXT: vmaxss %xmm1, %xmm0, %xmm0131; AVX512-NEXT: vzeroupper132; AVX512-NEXT: retq133 %1 = call nnan float @llvm.vector.reduce.fmax.v8f32(<8 x float> %a0)134 ret float %1135}136 137define float @test_v16f32(<16 x float> %a0) {138; SSE2-LABEL: test_v16f32:139; SSE2: # %bb.0:140; SSE2-NEXT: maxps %xmm3, %xmm1141; SSE2-NEXT: maxps %xmm2, %xmm0142; SSE2-NEXT: maxps %xmm1, %xmm0143; SSE2-NEXT: movaps %xmm0, %xmm1144; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]145; SSE2-NEXT: maxps %xmm1, %xmm0146; SSE2-NEXT: movaps %xmm0, %xmm1147; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]148; SSE2-NEXT: maxss %xmm1, %xmm0149; SSE2-NEXT: retq150;151; SSE41-LABEL: test_v16f32:152; SSE41: # %bb.0:153; SSE41-NEXT: maxps %xmm3, %xmm1154; SSE41-NEXT: maxps %xmm2, %xmm0155; SSE41-NEXT: maxps %xmm1, %xmm0156; SSE41-NEXT: movaps %xmm0, %xmm1157; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]158; SSE41-NEXT: maxps %xmm1, %xmm0159; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]160; SSE41-NEXT: maxss %xmm1, %xmm0161; SSE41-NEXT: retq162;163; AVX-LABEL: test_v16f32:164; AVX: # %bb.0:165; AVX-NEXT: vmaxps %ymm1, %ymm0, %ymm0166; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1167; AVX-NEXT: vmaxps %xmm1, %xmm0, %xmm0168; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]169; AVX-NEXT: vmaxps %xmm1, %xmm0, %xmm0170; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]171; AVX-NEXT: vmaxss %xmm1, %xmm0, %xmm0172; AVX-NEXT: vzeroupper173; AVX-NEXT: retq174;175; AVX512-LABEL: test_v16f32:176; AVX512: # %bb.0:177; AVX512-NEXT: vextractf64x4 $1, %zmm0, %ymm1178; AVX512-NEXT: vmaxps %ymm1, %ymm0, %ymm0179; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm1180; AVX512-NEXT: vmaxps %xmm1, %xmm0, %xmm0181; AVX512-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]182; AVX512-NEXT: vmaxps %xmm1, %xmm0, %xmm0183; AVX512-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]184; AVX512-NEXT: vmaxss %xmm1, %xmm0, %xmm0185; AVX512-NEXT: vzeroupper186; AVX512-NEXT: retq187 %1 = call nnan float @llvm.vector.reduce.fmax.v16f32(<16 x float> %a0)188 ret float %1189}190 191;192; vXf64193;194 195define double @test_v2f64(<2 x double> %a0) {196; SSE-LABEL: test_v2f64:197; SSE: # %bb.0:198; SSE-NEXT: movapd %xmm0, %xmm1199; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]200; SSE-NEXT: maxsd %xmm1, %xmm0201; SSE-NEXT: retq202;203; AVX-LABEL: test_v2f64:204; AVX: # %bb.0:205; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]206; AVX-NEXT: vmaxsd %xmm1, %xmm0, %xmm0207; AVX-NEXT: retq208;209; AVX512-LABEL: test_v2f64:210; AVX512: # %bb.0:211; AVX512-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]212; AVX512-NEXT: vmaxsd %xmm1, %xmm0, %xmm0213; AVX512-NEXT: retq214 %1 = call nnan double @llvm.vector.reduce.fmax.v2f64(<2 x double> %a0)215 ret double %1216}217 218define double @test_v3f64(<3 x double> %a0) {219; SSE2-LABEL: test_v3f64:220; SSE2: # %bb.0:221; SSE2-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]222; SSE2-NEXT: shufpd {{.*#+}} xmm2 = xmm2[0],mem[1]223; SSE2-NEXT: maxpd %xmm2, %xmm0224; SSE2-NEXT: movapd %xmm0, %xmm1225; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]226; SSE2-NEXT: maxsd %xmm1, %xmm0227; SSE2-NEXT: retq228;229; SSE41-LABEL: test_v3f64:230; SSE41: # %bb.0:231; SSE41-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0]232; SSE41-NEXT: blendpd {{.*#+}} xmm2 = xmm2[0],mem[1]233; SSE41-NEXT: maxpd %xmm2, %xmm0234; SSE41-NEXT: movapd %xmm0, %xmm1235; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]236; SSE41-NEXT: maxsd %xmm1, %xmm0237; SSE41-NEXT: retq238;239; AVX-LABEL: test_v3f64:240; AVX: # %bb.0:241; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]242; AVX-NEXT: vmaxsd %xmm1, %xmm0, %xmm1243; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0244; AVX-NEXT: vmaxsd %xmm0, %xmm1, %xmm0245; AVX-NEXT: vzeroupper246; AVX-NEXT: retq247;248; AVX512-LABEL: test_v3f64:249; AVX512: # %bb.0:250; AVX512-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]251; AVX512-NEXT: vmaxsd %xmm1, %xmm0, %xmm1252; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm0253; AVX512-NEXT: vmaxsd %xmm0, %xmm1, %xmm0254; AVX512-NEXT: vzeroupper255; AVX512-NEXT: retq256 %1 = call nnan double @llvm.vector.reduce.fmax.v3f64(<3 x double> %a0)257 ret double %1258}259 260define double @test_v4f64(<4 x double> %a0) {261; SSE-LABEL: test_v4f64:262; SSE: # %bb.0:263; SSE-NEXT: maxpd %xmm1, %xmm0264; SSE-NEXT: movapd %xmm0, %xmm1265; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]266; SSE-NEXT: maxsd %xmm1, %xmm0267; SSE-NEXT: retq268;269; AVX-LABEL: test_v4f64:270; AVX: # %bb.0:271; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1272; AVX-NEXT: vmaxpd %xmm1, %xmm0, %xmm0273; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]274; AVX-NEXT: vmaxsd %xmm1, %xmm0, %xmm0275; AVX-NEXT: vzeroupper276; AVX-NEXT: retq277;278; AVX512-LABEL: test_v4f64:279; AVX512: # %bb.0:280; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm1281; AVX512-NEXT: vmaxpd %xmm1, %xmm0, %xmm0282; AVX512-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]283; AVX512-NEXT: vmaxsd %xmm1, %xmm0, %xmm0284; AVX512-NEXT: vzeroupper285; AVX512-NEXT: retq286 %1 = call nnan double @llvm.vector.reduce.fmax.v4f64(<4 x double> %a0)287 ret double %1288}289 290define double @test_v8f64(<8 x double> %a0) {291; SSE-LABEL: test_v8f64:292; SSE: # %bb.0:293; SSE-NEXT: maxpd %xmm3, %xmm1294; SSE-NEXT: maxpd %xmm2, %xmm0295; SSE-NEXT: maxpd %xmm1, %xmm0296; SSE-NEXT: movapd %xmm0, %xmm1297; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]298; SSE-NEXT: maxsd %xmm1, %xmm0299; SSE-NEXT: retq300;301; AVX-LABEL: test_v8f64:302; AVX: # %bb.0:303; AVX-NEXT: vmaxpd %ymm1, %ymm0, %ymm0304; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1305; AVX-NEXT: vmaxpd %xmm1, %xmm0, %xmm0306; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]307; AVX-NEXT: vmaxsd %xmm1, %xmm0, %xmm0308; AVX-NEXT: vzeroupper309; AVX-NEXT: retq310;311; AVX512-LABEL: test_v8f64:312; AVX512: # %bb.0:313; AVX512-NEXT: vextractf64x4 $1, %zmm0, %ymm1314; AVX512-NEXT: vmaxpd %ymm1, %ymm0, %ymm0315; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm1316; AVX512-NEXT: vmaxpd %xmm1, %xmm0, %xmm0317; AVX512-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]318; AVX512-NEXT: vmaxsd %xmm1, %xmm0, %xmm0319; AVX512-NEXT: vzeroupper320; AVX512-NEXT: retq321 %1 = call nnan double @llvm.vector.reduce.fmax.v8f64(<8 x double> %a0)322 ret double %1323}324 325define double @test_v16f64(<16 x double> %a0) {326; SSE-LABEL: test_v16f64:327; SSE: # %bb.0:328; SSE-NEXT: maxpd %xmm6, %xmm2329; SSE-NEXT: maxpd %xmm4, %xmm0330; SSE-NEXT: maxpd %xmm2, %xmm0331; SSE-NEXT: maxpd %xmm7, %xmm3332; SSE-NEXT: maxpd %xmm5, %xmm1333; SSE-NEXT: maxpd %xmm3, %xmm1334; SSE-NEXT: maxpd %xmm1, %xmm0335; SSE-NEXT: movapd %xmm0, %xmm1336; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]337; SSE-NEXT: maxsd %xmm1, %xmm0338; SSE-NEXT: retq339;340; AVX-LABEL: test_v16f64:341; AVX: # %bb.0:342; AVX-NEXT: vmaxpd %ymm3, %ymm1, %ymm1343; AVX-NEXT: vmaxpd %ymm2, %ymm0, %ymm0344; AVX-NEXT: vmaxpd %ymm1, %ymm0, %ymm0345; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1346; AVX-NEXT: vmaxpd %xmm1, %xmm0, %xmm0347; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]348; AVX-NEXT: vmaxsd %xmm1, %xmm0, %xmm0349; AVX-NEXT: vzeroupper350; AVX-NEXT: retq351;352; AVX512-LABEL: test_v16f64:353; AVX512: # %bb.0:354; AVX512-NEXT: vmaxpd %zmm1, %zmm0, %zmm0355; AVX512-NEXT: vextractf64x4 $1, %zmm0, %ymm1356; AVX512-NEXT: vmaxpd %ymm1, %ymm0, %ymm0357; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm1358; AVX512-NEXT: vmaxpd %xmm1, %xmm0, %xmm0359; AVX512-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]360; AVX512-NEXT: vmaxsd %xmm1, %xmm0, %xmm0361; AVX512-NEXT: vzeroupper362; AVX512-NEXT: retq363 %1 = call nnan double @llvm.vector.reduce.fmax.v16f64(<16 x double> %a0)364 ret double %1365}366 367define half @test_v2f16(<2 x half> %a0) nounwind {368; SSE-LABEL: test_v2f16:369; SSE: # %bb.0:370; SSE-NEXT: pushq %rbp371; SSE-NEXT: pushq %rbx372; SSE-NEXT: subq $40, %rsp373; SSE-NEXT: movdqa %xmm0, %xmm1374; SSE-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill375; SSE-NEXT: psrld $16, %xmm0376; SSE-NEXT: pextrw $0, %xmm0, %ebx377; SSE-NEXT: pextrw $0, %xmm1, %ebp378; SSE-NEXT: callq __extendhfsf2@PLT379; SSE-NEXT: movd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Folded Spill380; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload381; SSE-NEXT: callq __extendhfsf2@PLT382; SSE-NEXT: ucomiss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 4-byte Folded Reload383; SSE-NEXT: cmoval %ebp, %ebx384; SSE-NEXT: pinsrw $0, %ebx, %xmm0385; SSE-NEXT: addq $40, %rsp386; SSE-NEXT: popq %rbx387; SSE-NEXT: popq %rbp388; SSE-NEXT: retq389;390; AVX-LABEL: test_v2f16:391; AVX: # %bb.0:392; AVX-NEXT: pushq %rbp393; AVX-NEXT: pushq %rbx394; AVX-NEXT: subq $40, %rsp395; AVX-NEXT: vmovdqa %xmm0, %xmm1396; AVX-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill397; AVX-NEXT: vpsrld $16, %xmm0, %xmm0398; AVX-NEXT: vpextrw $0, %xmm0, %ebx399; AVX-NEXT: vpextrw $0, %xmm1, %ebp400; AVX-NEXT: callq __extendhfsf2@PLT401; AVX-NEXT: vmovd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Folded Spill402; AVX-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload403; AVX-NEXT: callq __extendhfsf2@PLT404; AVX-NEXT: vucomiss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 4-byte Folded Reload405; AVX-NEXT: cmoval %ebp, %ebx406; AVX-NEXT: vpinsrw $0, %ebx, %xmm0, %xmm0407; AVX-NEXT: addq $40, %rsp408; AVX-NEXT: popq %rbx409; AVX-NEXT: popq %rbp410; AVX-NEXT: retq411;412; AVX512F-LABEL: test_v2f16:413; AVX512F: # %bb.0:414; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0415; AVX512F-NEXT: vpsrld $16, %xmm0, %xmm1416; AVX512F-NEXT: vcvtph2ps %xmm0, %xmm2417; AVX512F-NEXT: vcvtph2ps %xmm1, %xmm3418; AVX512F-NEXT: vucomiss %xmm3, %xmm2419; AVX512F-NEXT: seta %al420; AVX512F-NEXT: kmovd %eax, %k1421; AVX512F-NEXT: vmovdqu16 %zmm0, %zmm1 {%k1}422; AVX512F-NEXT: vmovdqa %xmm1, %xmm0423; AVX512F-NEXT: vzeroupper424; AVX512F-NEXT: retq425;426; AVX512VL-LABEL: test_v2f16:427; AVX512VL: # %bb.0:428; AVX512VL-NEXT: vpsrld $16, %xmm0, %xmm1429; AVX512VL-NEXT: vcvtph2ps %xmm0, %xmm2430; AVX512VL-NEXT: vcvtph2ps %xmm1, %xmm3431; AVX512VL-NEXT: vcmpltss %xmm2, %xmm3, %k1432; AVX512VL-NEXT: vmovdqu16 %xmm0, %xmm1 {%k1}433; AVX512VL-NEXT: vmovdqa %xmm1, %xmm0434; AVX512VL-NEXT: retq435;436; AVX512FP16-LABEL: test_v2f16:437; AVX512FP16: # %bb.0:438; AVX512FP16-NEXT: vpsrld $16, %xmm0, %xmm1439; AVX512FP16-NEXT: vcmpltsh %xmm0, %xmm1, %k1440; AVX512FP16-NEXT: vmovsh %xmm0, %xmm0, %xmm1 {%k1}441; AVX512FP16-NEXT: vmovaps %xmm1, %xmm0442; AVX512FP16-NEXT: retq443 %1 = call nnan half @llvm.vector.reduce.fmax.v2f16(<2 x half> %a0)444 ret half %1445}446declare float @llvm.vector.reduce.fmax.v1f32(<1 x float>)447declare float @llvm.vector.reduce.fmax.v2f32(<2 x float>)448declare float @llvm.vector.reduce.fmax.v4f32(<4 x float>)449declare float @llvm.vector.reduce.fmax.v8f32(<8 x float>)450declare float @llvm.vector.reduce.fmax.v16f32(<16 x float>)451 452declare double @llvm.vector.reduce.fmax.v2f64(<2 x double>)453declare double @llvm.vector.reduce.fmax.v3f64(<3 x double>)454declare double @llvm.vector.reduce.fmax.v4f64(<4 x double>)455declare double @llvm.vector.reduce.fmax.v8f64(<8 x double>)456declare double @llvm.vector.reduce.fmax.v16f64(<16 x double>)457 458declare half @llvm.vector.reduce.fmax.v2f16(<2 x half>)459