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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=ALL,SSE,SSE23; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefixes=ALL,SSE,SSE414; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=ALL,AVX5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=ALL,AVX6; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw | FileCheck %s --check-prefixes=ALL,AVX512,AVX512F7; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512bw,+avx512vl | FileCheck %s --check-prefixes=ALL,AVX512,AVX512VL8; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512fp16,+avx512vl | FileCheck %s --check-prefixes=ALL,AVX512,AVX512FP169 10;11; vXf3212;13 14define float @test_v1f32(<1 x float> %a0) {15; ALL-LABEL: test_v1f32:16; ALL: # %bb.0:17; ALL-NEXT: retq18 %1 = call nnan float @llvm.vector.reduce.fmin.v1f32(<1 x float> %a0)19 ret float %120}21 22define float @test_v2f32(<2 x float> %a0) {23; SSE2-LABEL: test_v2f32:24; SSE2: # %bb.0:25; SSE2-NEXT: movaps %xmm0, %xmm126; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]27; SSE2-NEXT: minss %xmm1, %xmm028; SSE2-NEXT: retq29;30; SSE41-LABEL: test_v2f32:31; SSE41: # %bb.0:32; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]33; SSE41-NEXT: minss %xmm1, %xmm034; SSE41-NEXT: retq35;36; AVX-LABEL: test_v2f32:37; AVX: # %bb.0:38; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]39; AVX-NEXT: vminss %xmm1, %xmm0, %xmm040; AVX-NEXT: retq41;42; AVX512-LABEL: test_v2f32:43; AVX512: # %bb.0:44; AVX512-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]45; AVX512-NEXT: vminss %xmm1, %xmm0, %xmm046; AVX512-NEXT: retq47 %1 = call nnan float @llvm.vector.reduce.fmin.v2f32(<2 x float> %a0)48 ret float %149}50 51define float @test_v3f32(<3 x float> %a0) {52; SSE2-LABEL: test_v3f32:53; SSE2: # %bb.0:54; SSE2-NEXT: movaps %xmm0, %xmm255; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[1,1],xmm0[1,1]56; SSE2-NEXT: movaps %xmm0, %xmm157; SSE2-NEXT: minss %xmm2, %xmm158; SSE2-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]59; SSE2-NEXT: minss %xmm0, %xmm160; SSE2-NEXT: movaps %xmm1, %xmm061; SSE2-NEXT: retq62;63; SSE41-LABEL: test_v3f32:64; SSE41: # %bb.0:65; SSE41-NEXT: movshdup {{.*#+}} xmm2 = xmm0[1,1,3,3]66; SSE41-NEXT: movaps %xmm0, %xmm167; SSE41-NEXT: minss %xmm2, %xmm168; SSE41-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]69; SSE41-NEXT: minss %xmm0, %xmm170; SSE41-NEXT: movaps %xmm1, %xmm071; SSE41-NEXT: retq72;73; AVX-LABEL: test_v3f32:74; AVX: # %bb.0:75; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]76; AVX-NEXT: vminss %xmm1, %xmm0, %xmm177; AVX-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]78; AVX-NEXT: vminss %xmm0, %xmm1, %xmm079; AVX-NEXT: retq80;81; AVX512-LABEL: test_v3f32:82; AVX512: # %bb.0:83; AVX512-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]84; AVX512-NEXT: vminss %xmm1, %xmm0, %xmm185; AVX512-NEXT: vshufpd {{.*#+}} xmm0 = xmm0[1,0]86; AVX512-NEXT: vminss %xmm0, %xmm1, %xmm087; AVX512-NEXT: retq88 %1 = call nnan float @llvm.vector.reduce.fmin.v3f32(<3 x float> %a0)89 ret float %190}91 92define float @test_v4f32(<4 x float> %a0) {93; SSE2-LABEL: test_v4f32:94; SSE2: # %bb.0:95; SSE2-NEXT: movaps %xmm0, %xmm196; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]97; SSE2-NEXT: minps %xmm1, %xmm098; SSE2-NEXT: movaps %xmm0, %xmm199; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]100; SSE2-NEXT: minss %xmm1, %xmm0101; SSE2-NEXT: retq102;103; SSE41-LABEL: test_v4f32:104; SSE41: # %bb.0:105; SSE41-NEXT: movaps %xmm0, %xmm1106; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]107; SSE41-NEXT: minps %xmm1, %xmm0108; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]109; SSE41-NEXT: minss %xmm1, %xmm0110; SSE41-NEXT: retq111;112; AVX-LABEL: test_v4f32:113; AVX: # %bb.0:114; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]115; AVX-NEXT: vminps %xmm1, %xmm0, %xmm0116; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]117; AVX-NEXT: vminss %xmm1, %xmm0, %xmm0118; AVX-NEXT: retq119;120; AVX512-LABEL: test_v4f32:121; AVX512: # %bb.0:122; AVX512-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]123; AVX512-NEXT: vminps %xmm1, %xmm0, %xmm0124; AVX512-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]125; AVX512-NEXT: vminss %xmm1, %xmm0, %xmm0126; AVX512-NEXT: retq127 %1 = call nnan float @llvm.vector.reduce.fmin.v4f32(<4 x float> %a0)128 ret float %1129}130 131define float @test_v8f32(<8 x float> %a0) {132; SSE2-LABEL: test_v8f32:133; SSE2: # %bb.0:134; SSE2-NEXT: minps %xmm1, %xmm0135; SSE2-NEXT: movaps %xmm0, %xmm1136; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]137; SSE2-NEXT: minps %xmm1, %xmm0138; SSE2-NEXT: movaps %xmm0, %xmm1139; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]140; SSE2-NEXT: minss %xmm1, %xmm0141; SSE2-NEXT: retq142;143; SSE41-LABEL: test_v8f32:144; SSE41: # %bb.0:145; SSE41-NEXT: minps %xmm1, %xmm0146; SSE41-NEXT: movaps %xmm0, %xmm1147; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]148; SSE41-NEXT: minps %xmm1, %xmm0149; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]150; SSE41-NEXT: minss %xmm1, %xmm0151; SSE41-NEXT: retq152;153; AVX-LABEL: test_v8f32:154; AVX: # %bb.0:155; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1156; AVX-NEXT: vminps %xmm1, %xmm0, %xmm0157; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]158; AVX-NEXT: vminps %xmm1, %xmm0, %xmm0159; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]160; AVX-NEXT: vminss %xmm1, %xmm0, %xmm0161; AVX-NEXT: vzeroupper162; AVX-NEXT: retq163;164; AVX512-LABEL: test_v8f32:165; AVX512: # %bb.0:166; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm1167; AVX512-NEXT: vminps %xmm1, %xmm0, %xmm0168; AVX512-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]169; AVX512-NEXT: vminps %xmm1, %xmm0, %xmm0170; AVX512-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]171; AVX512-NEXT: vminss %xmm1, %xmm0, %xmm0172; AVX512-NEXT: vzeroupper173; AVX512-NEXT: retq174 %1 = call nnan float @llvm.vector.reduce.fmin.v8f32(<8 x float> %a0)175 ret float %1176}177 178define float @test_v16f32(<16 x float> %a0) {179; SSE2-LABEL: test_v16f32:180; SSE2: # %bb.0:181; SSE2-NEXT: minps %xmm3, %xmm1182; SSE2-NEXT: minps %xmm2, %xmm0183; SSE2-NEXT: minps %xmm1, %xmm0184; SSE2-NEXT: movaps %xmm0, %xmm1185; SSE2-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]186; SSE2-NEXT: minps %xmm1, %xmm0187; SSE2-NEXT: movaps %xmm0, %xmm1188; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[1,1],xmm0[1,1]189; SSE2-NEXT: minss %xmm1, %xmm0190; SSE2-NEXT: retq191;192; SSE41-LABEL: test_v16f32:193; SSE41: # %bb.0:194; SSE41-NEXT: minps %xmm3, %xmm1195; SSE41-NEXT: minps %xmm2, %xmm0196; SSE41-NEXT: minps %xmm1, %xmm0197; SSE41-NEXT: movaps %xmm0, %xmm1198; SSE41-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]199; SSE41-NEXT: minps %xmm1, %xmm0200; SSE41-NEXT: movshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]201; SSE41-NEXT: minss %xmm1, %xmm0202; SSE41-NEXT: retq203;204; AVX-LABEL: test_v16f32:205; AVX: # %bb.0:206; AVX-NEXT: vminps %ymm1, %ymm0, %ymm0207; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1208; AVX-NEXT: vminps %xmm1, %xmm0, %xmm0209; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]210; AVX-NEXT: vminps %xmm1, %xmm0, %xmm0211; AVX-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]212; AVX-NEXT: vminss %xmm1, %xmm0, %xmm0213; AVX-NEXT: vzeroupper214; AVX-NEXT: retq215;216; AVX512-LABEL: test_v16f32:217; AVX512: # %bb.0:218; AVX512-NEXT: vextractf64x4 $1, %zmm0, %ymm1219; AVX512-NEXT: vminps %ymm1, %ymm0, %ymm0220; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm1221; AVX512-NEXT: vminps %xmm1, %xmm0, %xmm0222; AVX512-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]223; AVX512-NEXT: vminps %xmm1, %xmm0, %xmm0224; AVX512-NEXT: vmovshdup {{.*#+}} xmm1 = xmm0[1,1,3,3]225; AVX512-NEXT: vminss %xmm1, %xmm0, %xmm0226; AVX512-NEXT: vzeroupper227; AVX512-NEXT: retq228 %1 = call nnan float @llvm.vector.reduce.fmin.v16f32(<16 x float> %a0)229 ret float %1230}231 232;233; vXf64234;235 236define double @test_v2f64(<2 x double> %a0) {237; SSE-LABEL: test_v2f64:238; SSE: # %bb.0:239; SSE-NEXT: movapd %xmm0, %xmm1240; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]241; SSE-NEXT: minsd %xmm1, %xmm0242; SSE-NEXT: retq243;244; AVX-LABEL: test_v2f64:245; AVX: # %bb.0:246; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]247; AVX-NEXT: vminsd %xmm1, %xmm0, %xmm0248; AVX-NEXT: retq249;250; AVX512-LABEL: test_v2f64:251; AVX512: # %bb.0:252; AVX512-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]253; AVX512-NEXT: vminsd %xmm1, %xmm0, %xmm0254; AVX512-NEXT: retq255 %1 = call nnan double @llvm.vector.reduce.fmin.v2f64(<2 x double> %a0)256 ret double %1257}258 259define double @test_v4f64(<4 x double> %a0) {260; SSE-LABEL: test_v4f64:261; SSE: # %bb.0:262; SSE-NEXT: minpd %xmm1, %xmm0263; SSE-NEXT: movapd %xmm0, %xmm1264; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]265; SSE-NEXT: minsd %xmm1, %xmm0266; SSE-NEXT: retq267;268; AVX-LABEL: test_v4f64:269; AVX: # %bb.0:270; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1271; AVX-NEXT: vminpd %xmm1, %xmm0, %xmm0272; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]273; AVX-NEXT: vminsd %xmm1, %xmm0, %xmm0274; AVX-NEXT: vzeroupper275; AVX-NEXT: retq276;277; AVX512-LABEL: test_v4f64:278; AVX512: # %bb.0:279; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm1280; AVX512-NEXT: vminpd %xmm1, %xmm0, %xmm0281; AVX512-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]282; AVX512-NEXT: vminsd %xmm1, %xmm0, %xmm0283; AVX512-NEXT: vzeroupper284; AVX512-NEXT: retq285 %1 = call nnan double @llvm.vector.reduce.fmin.v4f64(<4 x double> %a0)286 ret double %1287}288 289define double @test_v8f64(<8 x double> %a0) {290; SSE-LABEL: test_v8f64:291; SSE: # %bb.0:292; SSE-NEXT: minpd %xmm3, %xmm1293; SSE-NEXT: minpd %xmm2, %xmm0294; SSE-NEXT: minpd %xmm1, %xmm0295; SSE-NEXT: movapd %xmm0, %xmm1296; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]297; SSE-NEXT: minsd %xmm1, %xmm0298; SSE-NEXT: retq299;300; AVX-LABEL: test_v8f64:301; AVX: # %bb.0:302; AVX-NEXT: vminpd %ymm1, %ymm0, %ymm0303; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1304; AVX-NEXT: vminpd %xmm1, %xmm0, %xmm0305; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]306; AVX-NEXT: vminsd %xmm1, %xmm0, %xmm0307; AVX-NEXT: vzeroupper308; AVX-NEXT: retq309;310; AVX512-LABEL: test_v8f64:311; AVX512: # %bb.0:312; AVX512-NEXT: vextractf64x4 $1, %zmm0, %ymm1313; AVX512-NEXT: vminpd %ymm1, %ymm0, %ymm0314; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm1315; AVX512-NEXT: vminpd %xmm1, %xmm0, %xmm0316; AVX512-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]317; AVX512-NEXT: vminsd %xmm1, %xmm0, %xmm0318; AVX512-NEXT: vzeroupper319; AVX512-NEXT: retq320 %1 = call nnan double @llvm.vector.reduce.fmin.v8f64(<8 x double> %a0)321 ret double %1322}323 324define double @test_v16f64(<16 x double> %a0) {325; SSE-LABEL: test_v16f64:326; SSE: # %bb.0:327; SSE-NEXT: minpd %xmm6, %xmm2328; SSE-NEXT: minpd %xmm4, %xmm0329; SSE-NEXT: minpd %xmm2, %xmm0330; SSE-NEXT: minpd %xmm7, %xmm3331; SSE-NEXT: minpd %xmm5, %xmm1332; SSE-NEXT: minpd %xmm3, %xmm1333; SSE-NEXT: minpd %xmm1, %xmm0334; SSE-NEXT: movapd %xmm0, %xmm1335; SSE-NEXT: unpckhpd {{.*#+}} xmm1 = xmm1[1],xmm0[1]336; SSE-NEXT: minsd %xmm1, %xmm0337; SSE-NEXT: retq338;339; AVX-LABEL: test_v16f64:340; AVX: # %bb.0:341; AVX-NEXT: vminpd %ymm3, %ymm1, %ymm1342; AVX-NEXT: vminpd %ymm2, %ymm0, %ymm0343; AVX-NEXT: vminpd %ymm1, %ymm0, %ymm0344; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1345; AVX-NEXT: vminpd %xmm1, %xmm0, %xmm0346; AVX-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]347; AVX-NEXT: vminsd %xmm1, %xmm0, %xmm0348; AVX-NEXT: vzeroupper349; AVX-NEXT: retq350;351; AVX512-LABEL: test_v16f64:352; AVX512: # %bb.0:353; AVX512-NEXT: vminpd %zmm1, %zmm0, %zmm0354; AVX512-NEXT: vextractf64x4 $1, %zmm0, %ymm1355; AVX512-NEXT: vminpd %ymm1, %ymm0, %ymm0356; AVX512-NEXT: vextractf128 $1, %ymm0, %xmm1357; AVX512-NEXT: vminpd %xmm1, %xmm0, %xmm0358; AVX512-NEXT: vshufpd {{.*#+}} xmm1 = xmm0[1,0]359; AVX512-NEXT: vminsd %xmm1, %xmm0, %xmm0360; AVX512-NEXT: vzeroupper361; AVX512-NEXT: retq362 %1 = call nnan double @llvm.vector.reduce.fmin.v16f64(<16 x double> %a0)363 ret double %1364}365 366define half @test_v2f16(<2 x half> %a0) nounwind {367; SSE-LABEL: test_v2f16:368; SSE: # %bb.0:369; SSE-NEXT: pushq %rbp370; SSE-NEXT: pushq %rbx371; SSE-NEXT: subq $40, %rsp372; SSE-NEXT: movdqa %xmm0, %xmm1373; SSE-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill374; SSE-NEXT: psrld $16, %xmm0375; SSE-NEXT: pextrw $0, %xmm0, %ebx376; SSE-NEXT: pextrw $0, %xmm1, %ebp377; SSE-NEXT: callq __extendhfsf2@PLT378; SSE-NEXT: movd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Folded Spill379; SSE-NEXT: movaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload380; SSE-NEXT: callq __extendhfsf2@PLT381; SSE-NEXT: ucomiss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 4-byte Folded Reload382; SSE-NEXT: cmovbl %ebp, %ebx383; SSE-NEXT: pinsrw $0, %ebx, %xmm0384; SSE-NEXT: addq $40, %rsp385; SSE-NEXT: popq %rbx386; SSE-NEXT: popq %rbp387; SSE-NEXT: retq388;389; AVX-LABEL: test_v2f16:390; AVX: # %bb.0:391; AVX-NEXT: pushq %rbp392; AVX-NEXT: pushq %rbx393; AVX-NEXT: subq $40, %rsp394; AVX-NEXT: vmovdqa %xmm0, %xmm1395; AVX-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill396; AVX-NEXT: vpsrld $16, %xmm0, %xmm0397; AVX-NEXT: vpextrw $0, %xmm0, %ebx398; AVX-NEXT: vpextrw $0, %xmm1, %ebp399; AVX-NEXT: callq __extendhfsf2@PLT400; AVX-NEXT: vmovd %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Folded Spill401; AVX-NEXT: vmovaps {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload402; AVX-NEXT: callq __extendhfsf2@PLT403; AVX-NEXT: vucomiss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 4-byte Folded Reload404; AVX-NEXT: cmovbl %ebp, %ebx405; AVX-NEXT: vpinsrw $0, %ebx, %xmm0, %xmm0406; AVX-NEXT: addq $40, %rsp407; AVX-NEXT: popq %rbx408; AVX-NEXT: popq %rbp409; AVX-NEXT: retq410;411; AVX512F-LABEL: test_v2f16:412; AVX512F: # %bb.0:413; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 def $zmm0414; AVX512F-NEXT: vpsrld $16, %xmm0, %xmm1415; AVX512F-NEXT: vcvtph2ps %xmm0, %xmm2416; AVX512F-NEXT: vcvtph2ps %xmm1, %xmm3417; AVX512F-NEXT: xorl %eax, %eax418; AVX512F-NEXT: vucomiss %xmm3, %xmm2419; AVX512F-NEXT: sbbl %eax, %eax420; AVX512F-NEXT: kmovd %eax, %k1421; AVX512F-NEXT: vmovdqu16 %zmm0, %zmm1 {%k1}422; AVX512F-NEXT: vmovdqa %xmm1, %xmm0423; AVX512F-NEXT: vzeroupper424; AVX512F-NEXT: retq425;426; AVX512VL-LABEL: test_v2f16:427; AVX512VL: # %bb.0:428; AVX512VL-NEXT: vpsrld $16, %xmm0, %xmm1429; AVX512VL-NEXT: vcvtph2ps %xmm0, %xmm2430; AVX512VL-NEXT: vcvtph2ps %xmm1, %xmm3431; AVX512VL-NEXT: vcmpltss %xmm3, %xmm2, %k1432; AVX512VL-NEXT: vmovdqu16 %xmm0, %xmm1 {%k1}433; AVX512VL-NEXT: vmovdqa %xmm1, %xmm0434; AVX512VL-NEXT: retq435;436; AVX512FP16-LABEL: test_v2f16:437; AVX512FP16: # %bb.0:438; AVX512FP16-NEXT: vpsrld $16, %xmm0, %xmm1439; AVX512FP16-NEXT: vcmpltsh %xmm1, %xmm0, %k1440; AVX512FP16-NEXT: vmovsh %xmm0, %xmm0, %xmm1 {%k1}441; AVX512FP16-NEXT: vmovaps %xmm1, %xmm0442; AVX512FP16-NEXT: retq443 %1 = call nnan half @llvm.vector.reduce.fmin.v2f16(<2 x half> %a0)444 ret half %1445}446 447declare float @llvm.vector.reduce.fmin.v1f32(<1 x float>)448declare float @llvm.vector.reduce.fmin.v2f32(<2 x float>)449declare float @llvm.vector.reduce.fmin.v3f32(<3 x float>)450declare float @llvm.vector.reduce.fmin.v4f32(<4 x float>)451declare float @llvm.vector.reduce.fmin.v8f32(<8 x float>)452declare float @llvm.vector.reduce.fmin.v16f32(<16 x float>)453 454declare double @llvm.vector.reduce.fmin.v2f64(<2 x double>)455declare double @llvm.vector.reduce.fmin.v4f64(<4 x double>)456declare double @llvm.vector.reduce.fmin.v8f64(<8 x double>)457declare double @llvm.vector.reduce.fmin.v16f64(<16 x double>)458 459declare half @llvm.vector.reduce.fmin.v2f16(<2 x half>)460