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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq | FileCheck %s --check-prefixes=ALL,AVX512DQ3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefixes=ALL,AVX512BW4 5;6; Variable Shifts7;8 9define <8 x i64> @var_shift_v8i64(<8 x i64> %a, <8 x i64> %b) nounwind {10; ALL-LABEL: var_shift_v8i64:11; ALL: # %bb.0:12; ALL-NEXT: vpsravq %zmm1, %zmm0, %zmm013; ALL-NEXT: retq14 %shift = ashr <8 x i64> %a, %b15 ret <8 x i64> %shift16}17 18define <16 x i32> @var_shift_v16i32(<16 x i32> %a, <16 x i32> %b) nounwind {19; ALL-LABEL: var_shift_v16i32:20; ALL: # %bb.0:21; ALL-NEXT: vpsravd %zmm1, %zmm0, %zmm022; ALL-NEXT: retq23 %shift = ashr <16 x i32> %a, %b24 ret <16 x i32> %shift25}26 27define <32 x i16> @var_shift_v32i16(<32 x i16> %a, <32 x i16> %b) nounwind {28; AVX512DQ-LABEL: var_shift_v32i16:29; AVX512DQ: # %bb.0:30; AVX512DQ-NEXT: vpmovzxwd {{.*#+}} zmm2 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero31; AVX512DQ-NEXT: vpmovsxwd %ymm0, %zmm332; AVX512DQ-NEXT: vpsravd %zmm2, %zmm3, %zmm233; AVX512DQ-NEXT: vpmovdw %zmm2, %ymm234; AVX512DQ-NEXT: vextracti64x4 $1, %zmm1, %ymm135; AVX512DQ-NEXT: vpmovzxwd {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero36; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm037; AVX512DQ-NEXT: vpmovsxwd %ymm0, %zmm038; AVX512DQ-NEXT: vpsravd %zmm1, %zmm0, %zmm039; AVX512DQ-NEXT: vpmovdw %zmm0, %ymm040; AVX512DQ-NEXT: vinserti64x4 $1, %ymm0, %zmm2, %zmm041; AVX512DQ-NEXT: retq42;43; AVX512BW-LABEL: var_shift_v32i16:44; AVX512BW: # %bb.0:45; AVX512BW-NEXT: vpsravw %zmm1, %zmm0, %zmm046; AVX512BW-NEXT: retq47 %shift = ashr <32 x i16> %a, %b48 ret <32 x i16> %shift49}50 51define <64 x i8> @var_shift_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {52; AVX512DQ-LABEL: var_shift_v64i8:53; AVX512DQ: # %bb.0:54; AVX512DQ-NEXT: vextracti64x4 $1, %zmm1, %ymm255; AVX512DQ-NEXT: vpsllw $5, %ymm2, %ymm256; AVX512DQ-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm2[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]57; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm458; AVX512DQ-NEXT: vpunpckhbw {{.*#+}} ymm5 = ymm4[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]59; AVX512DQ-NEXT: vpsraw $4, %ymm5, %ymm660; AVX512DQ-NEXT: vpblendvb %ymm3, %ymm6, %ymm5, %ymm561; AVX512DQ-NEXT: vpsraw $2, %ymm5, %ymm662; AVX512DQ-NEXT: vpaddw %ymm3, %ymm3, %ymm763; AVX512DQ-NEXT: vpblendvb %ymm7, %ymm6, %ymm5, %ymm564; AVX512DQ-NEXT: vpsraw $1, %ymm5, %ymm665; AVX512DQ-NEXT: vpsllw $2, %ymm3, %ymm366; AVX512DQ-NEXT: vpblendvb %ymm3, %ymm6, %ymm5, %ymm367; AVX512DQ-NEXT: vpsrlw $8, %ymm3, %ymm368; AVX512DQ-NEXT: vpunpcklbw {{.*#+}} ymm2 = ymm2[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]69; AVX512DQ-NEXT: vpunpcklbw {{.*#+}} ymm4 = ymm4[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]70; AVX512DQ-NEXT: vpsraw $4, %ymm4, %ymm571; AVX512DQ-NEXT: vpblendvb %ymm2, %ymm5, %ymm4, %ymm472; AVX512DQ-NEXT: vpsraw $2, %ymm4, %ymm573; AVX512DQ-NEXT: vpaddw %ymm2, %ymm2, %ymm674; AVX512DQ-NEXT: vpblendvb %ymm6, %ymm5, %ymm4, %ymm475; AVX512DQ-NEXT: vpsraw $1, %ymm4, %ymm576; AVX512DQ-NEXT: vpsllw $2, %ymm2, %ymm277; AVX512DQ-NEXT: vpblendvb %ymm2, %ymm5, %ymm4, %ymm278; AVX512DQ-NEXT: vpsrlw $8, %ymm2, %ymm279; AVX512DQ-NEXT: vpackuswb %ymm3, %ymm2, %ymm280; AVX512DQ-NEXT: vpsllw $5, %ymm1, %ymm181; AVX512DQ-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]82; AVX512DQ-NEXT: vpunpckhbw {{.*#+}} ymm4 = ymm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]83; AVX512DQ-NEXT: vpsraw $4, %ymm4, %ymm584; AVX512DQ-NEXT: vpblendvb %ymm3, %ymm5, %ymm4, %ymm485; AVX512DQ-NEXT: vpsraw $2, %ymm4, %ymm586; AVX512DQ-NEXT: vpaddw %ymm3, %ymm3, %ymm687; AVX512DQ-NEXT: vpblendvb %ymm6, %ymm5, %ymm4, %ymm488; AVX512DQ-NEXT: vpsraw $1, %ymm4, %ymm589; AVX512DQ-NEXT: vpsllw $2, %ymm3, %ymm390; AVX512DQ-NEXT: vpblendvb %ymm3, %ymm5, %ymm4, %ymm391; AVX512DQ-NEXT: vpsrlw $8, %ymm3, %ymm392; AVX512DQ-NEXT: vpunpcklbw {{.*#+}} ymm1 = ymm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]93; AVX512DQ-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]94; AVX512DQ-NEXT: vpsraw $4, %ymm0, %ymm495; AVX512DQ-NEXT: vpblendvb %ymm1, %ymm4, %ymm0, %ymm096; AVX512DQ-NEXT: vpsraw $2, %ymm0, %ymm497; AVX512DQ-NEXT: vpaddw %ymm1, %ymm1, %ymm598; AVX512DQ-NEXT: vpblendvb %ymm5, %ymm4, %ymm0, %ymm099; AVX512DQ-NEXT: vpsraw $1, %ymm0, %ymm4100; AVX512DQ-NEXT: vpsllw $2, %ymm1, %ymm1101; AVX512DQ-NEXT: vpblendvb %ymm1, %ymm4, %ymm0, %ymm0102; AVX512DQ-NEXT: vpsrlw $8, %ymm0, %ymm0103; AVX512DQ-NEXT: vpackuswb %ymm3, %ymm0, %ymm0104; AVX512DQ-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0105; AVX512DQ-NEXT: retq106;107; AVX512BW-LABEL: var_shift_v64i8:108; AVX512BW: # %bb.0:109; AVX512BW-NEXT: vpsrlw $8, %zmm1, %zmm2110; AVX512BW-NEXT: vpsravw %zmm2, %zmm0, %zmm2111; AVX512BW-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %zmm1112; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm0113; AVX512BW-NEXT: vpsraw $8, %zmm0, %zmm0114; AVX512BW-NEXT: vpsravw %zmm1, %zmm0, %zmm0115; AVX512BW-NEXT: movabsq $6148914691236517205, %rax # imm = 0x5555555555555555116; AVX512BW-NEXT: kmovq %rax, %k1117; AVX512BW-NEXT: vmovdqu8 %zmm0, %zmm2 {%k1}118; AVX512BW-NEXT: vmovdqa64 %zmm2, %zmm0119; AVX512BW-NEXT: retq120 %shift = ashr <64 x i8> %a, %b121 ret <64 x i8> %shift122}123 124;125; Uniform Variable Shifts126;127 128define <8 x i64> @splatvar_shift_v8i64(<8 x i64> %a, <8 x i64> %b) nounwind {129; ALL-LABEL: splatvar_shift_v8i64:130; ALL: # %bb.0:131; ALL-NEXT: vpsraq %xmm1, %zmm0, %zmm0132; ALL-NEXT: retq133 %splat = shufflevector <8 x i64> %b, <8 x i64> poison, <8 x i32> zeroinitializer134 %shift = ashr <8 x i64> %a, %splat135 ret <8 x i64> %shift136}137 138define <16 x i32> @splatvar_shift_v16i32(<16 x i32> %a, <16 x i32> %b) nounwind {139; ALL-LABEL: splatvar_shift_v16i32:140; ALL: # %bb.0:141; ALL-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero142; ALL-NEXT: vpsrad %xmm1, %zmm0, %zmm0143; ALL-NEXT: retq144 %splat = shufflevector <16 x i32> %b, <16 x i32> poison, <16 x i32> zeroinitializer145 %shift = ashr <16 x i32> %a, %splat146 ret <16 x i32> %shift147}148 149define <32 x i16> @splatvar_shift_v32i16(<32 x i16> %a, <32 x i16> %b) nounwind {150; AVX512DQ-LABEL: splatvar_shift_v32i16:151; AVX512DQ: # %bb.0:152; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm2153; AVX512DQ-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero154; AVX512DQ-NEXT: vpsraw %xmm1, %ymm2, %ymm2155; AVX512DQ-NEXT: vpsraw %xmm1, %ymm0, %ymm0156; AVX512DQ-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0157; AVX512DQ-NEXT: retq158;159; AVX512BW-LABEL: splatvar_shift_v32i16:160; AVX512BW: # %bb.0:161; AVX512BW-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero162; AVX512BW-NEXT: vpsraw %xmm1, %zmm0, %zmm0163; AVX512BW-NEXT: retq164 %splat = shufflevector <32 x i16> %b, <32 x i16> poison, <32 x i32> zeroinitializer165 %shift = ashr <32 x i16> %a, %splat166 ret <32 x i16> %shift167}168 169define <64 x i8> @splatvar_shift_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {170; AVX512DQ-LABEL: splatvar_shift_v64i8:171; AVX512DQ: # %bb.0:172; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm2173; AVX512DQ-NEXT: vpmovzxbq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[1],zero,zero,zero,zero,zero,zero,zero174; AVX512DQ-NEXT: vpsrlw %xmm1, %ymm2, %ymm2175; AVX512DQ-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3176; AVX512DQ-NEXT: vpsrlw %xmm1, %xmm3, %xmm3177; AVX512DQ-NEXT: vpsrlw $8, %xmm3, %xmm3178; AVX512DQ-NEXT: vpbroadcastb %xmm3, %ymm3179; AVX512DQ-NEXT: vpand %ymm3, %ymm2, %ymm2180; AVX512DQ-NEXT: vpbroadcastb {{.*#+}} ymm4 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]181; AVX512DQ-NEXT: vpsrlw %xmm1, %ymm4, %ymm4182; AVX512DQ-NEXT: vpxor %ymm4, %ymm2, %ymm2183; AVX512DQ-NEXT: vpsubb %ymm4, %ymm2, %ymm2184; AVX512DQ-NEXT: vpsrlw %xmm1, %ymm0, %ymm0185; AVX512DQ-NEXT: vpand %ymm3, %ymm0, %ymm0186; AVX512DQ-NEXT: vpxor %ymm4, %ymm0, %ymm0187; AVX512DQ-NEXT: vpsubb %ymm4, %ymm0, %ymm0188; AVX512DQ-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0189; AVX512DQ-NEXT: retq190;191; AVX512BW-LABEL: splatvar_shift_v64i8:192; AVX512BW: # %bb.0:193; AVX512BW-NEXT: vpmovzxbq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[1],zero,zero,zero,zero,zero,zero,zero194; AVX512BW-NEXT: vpsrlw %xmm1, %zmm0, %zmm0195; AVX512BW-NEXT: vpbroadcastb {{.*#+}} zmm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]196; AVX512BW-NEXT: vpsrlw %xmm1, %zmm2, %zmm2197; AVX512BW-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3198; AVX512BW-NEXT: vpsrlw %xmm1, %xmm3, %xmm1199; AVX512BW-NEXT: vpsrlw $8, %xmm1, %xmm1200; AVX512BW-NEXT: vpbroadcastb %xmm1, %zmm1201; AVX512BW-NEXT: vpternlogq {{.*#+}} zmm1 = zmm2 ^ (zmm1 & zmm0)202; AVX512BW-NEXT: vpsubb %zmm2, %zmm1, %zmm0203; AVX512BW-NEXT: retq204 %splat = shufflevector <64 x i8> %b, <64 x i8> poison, <64 x i32> zeroinitializer205 %shift = ashr <64 x i8> %a, %splat206 ret <64 x i8> %shift207}208 209;210; Uniform Variable Modulo Shifts211;212 213define <8 x i64> @splatvar_modulo_shift_v8i64(<8 x i64> %a, <8 x i64> %b) nounwind {214; ALL-LABEL: splatvar_modulo_shift_v8i64:215; ALL: # %bb.0:216; ALL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1217; ALL-NEXT: vpsraq %xmm1, %zmm0, %zmm0218; ALL-NEXT: retq219 %mod = and <8 x i64> %b, <i64 63, i64 63, i64 63, i64 63, i64 63, i64 63, i64 63, i64 63>220 %splat = shufflevector <8 x i64> %mod, <8 x i64> poison, <8 x i32> zeroinitializer221 %shift = ashr <8 x i64> %a, %splat222 ret <8 x i64> %shift223}224 225define <16 x i32> @splatvar_modulo_shift_v16i32(<16 x i32> %a, <16 x i32> %b) nounwind {226; ALL-LABEL: splatvar_modulo_shift_v16i32:227; ALL: # %bb.0:228; ALL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1229; ALL-NEXT: vpsrad %xmm1, %zmm0, %zmm0230; ALL-NEXT: retq231 %mod = and <16 x i32> %b, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>232 %splat = shufflevector <16 x i32> %mod, <16 x i32> poison, <16 x i32> zeroinitializer233 %shift = ashr <16 x i32> %a, %splat234 ret <16 x i32> %shift235}236 237define <32 x i16> @splatvar_modulo_shift_v32i16(<32 x i16> %a, <32 x i16> %b) nounwind {238; AVX512DQ-LABEL: splatvar_modulo_shift_v32i16:239; AVX512DQ: # %bb.0:240; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm2241; AVX512DQ-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1242; AVX512DQ-NEXT: vpsraw %xmm1, %ymm2, %ymm2243; AVX512DQ-NEXT: vpsraw %xmm1, %ymm0, %ymm0244; AVX512DQ-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0245; AVX512DQ-NEXT: retq246;247; AVX512BW-LABEL: splatvar_modulo_shift_v32i16:248; AVX512BW: # %bb.0:249; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1250; AVX512BW-NEXT: vpsraw %xmm1, %zmm0, %zmm0251; AVX512BW-NEXT: retq252 %mod = and <32 x i16> %b, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>253 %splat = shufflevector <32 x i16> %mod, <32 x i16> poison, <32 x i32> zeroinitializer254 %shift = ashr <32 x i16> %a, %splat255 ret <32 x i16> %shift256}257 258define <64 x i8> @splatvar_modulo_shift_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {259; AVX512DQ-LABEL: splatvar_modulo_shift_v64i8:260; AVX512DQ: # %bb.0:261; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm2262; AVX512DQ-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1263; AVX512DQ-NEXT: vpsrlw %xmm1, %ymm2, %ymm2264; AVX512DQ-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3265; AVX512DQ-NEXT: vpsrlw %xmm1, %xmm3, %xmm3266; AVX512DQ-NEXT: vpsrlw $8, %xmm3, %xmm3267; AVX512DQ-NEXT: vpbroadcastb %xmm3, %ymm3268; AVX512DQ-NEXT: vpand %ymm3, %ymm2, %ymm2269; AVX512DQ-NEXT: vpbroadcastb {{.*#+}} ymm4 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]270; AVX512DQ-NEXT: vpsrlw %xmm1, %ymm4, %ymm4271; AVX512DQ-NEXT: vpxor %ymm4, %ymm2, %ymm2272; AVX512DQ-NEXT: vpsubb %ymm4, %ymm2, %ymm2273; AVX512DQ-NEXT: vpsrlw %xmm1, %ymm0, %ymm0274; AVX512DQ-NEXT: vpand %ymm3, %ymm0, %ymm0275; AVX512DQ-NEXT: vpxor %ymm4, %ymm0, %ymm0276; AVX512DQ-NEXT: vpsubb %ymm4, %ymm0, %ymm0277; AVX512DQ-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0278; AVX512DQ-NEXT: retq279;280; AVX512BW-LABEL: splatvar_modulo_shift_v64i8:281; AVX512BW: # %bb.0:282; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1283; AVX512BW-NEXT: vpsrlw %xmm1, %zmm0, %zmm0284; AVX512BW-NEXT: vpbroadcastb {{.*#+}} zmm2 = [128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128]285; AVX512BW-NEXT: vpsrlw %xmm1, %zmm2, %zmm2286; AVX512BW-NEXT: vpcmpeqd %xmm3, %xmm3, %xmm3287; AVX512BW-NEXT: vpsrlw %xmm1, %xmm3, %xmm1288; AVX512BW-NEXT: vpsrlw $8, %xmm1, %xmm1289; AVX512BW-NEXT: vpbroadcastb %xmm1, %zmm1290; AVX512BW-NEXT: vpternlogq {{.*#+}} zmm1 = zmm2 ^ (zmm1 & zmm0)291; AVX512BW-NEXT: vpsubb %zmm2, %zmm1, %zmm0292; AVX512BW-NEXT: retq293 %mod = and <64 x i8> %b, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>294 %splat = shufflevector <64 x i8> %mod, <64 x i8> poison, <64 x i32> zeroinitializer295 %shift = ashr <64 x i8> %a, %splat296 ret <64 x i8> %shift297}298 299;300; Constant Shifts301;302 303define <8 x i64> @constant_shift_v8i64(<8 x i64> %a) nounwind {304; ALL-LABEL: constant_shift_v8i64:305; ALL: # %bb.0:306; ALL-NEXT: vpsravq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0307; ALL-NEXT: retq308 %shift = ashr <8 x i64> %a, <i64 1, i64 7, i64 31, i64 62, i64 1, i64 7, i64 31, i64 62>309 ret <8 x i64> %shift310}311 312define <16 x i32> @constant_shift_v16i32(<16 x i32> %a) nounwind {313; ALL-LABEL: constant_shift_v16i32:314; ALL: # %bb.0:315; ALL-NEXT: vpsravd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0316; ALL-NEXT: retq317 %shift = ashr <16 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 8, i32 7, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 8, i32 7>318 ret <16 x i32> %shift319}320 321define <32 x i16> @constant_shift_v32i16(<32 x i16> %a) nounwind {322; AVX512DQ-LABEL: constant_shift_v32i16:323; AVX512DQ: # %bb.0:324; AVX512DQ-NEXT: vpmovsxwd %ymm0, %zmm1325; AVX512DQ-NEXT: vpmovsxbd {{.*#+}} zmm2 = [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15]326; AVX512DQ-NEXT: vpsravd %zmm2, %zmm1, %zmm1327; AVX512DQ-NEXT: vpmovdw %zmm1, %ymm1328; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm0329; AVX512DQ-NEXT: vpmovsxwd %ymm0, %zmm0330; AVX512DQ-NEXT: vpsravd %zmm2, %zmm0, %zmm0331; AVX512DQ-NEXT: vpmovdw %zmm0, %ymm0332; AVX512DQ-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0333; AVX512DQ-NEXT: retq334;335; AVX512BW-LABEL: constant_shift_v32i16:336; AVX512BW: # %bb.0:337; AVX512BW-NEXT: vpsravw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0338; AVX512BW-NEXT: retq339 %shift = ashr <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>340 ret <32 x i16> %shift341}342 343define <32 x i16> @constant_shift_v32i16_pairs(<32 x i16> %a) nounwind {344; AVX512DQ-LABEL: constant_shift_v32i16_pairs:345; AVX512DQ: # %bb.0:346; AVX512DQ-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0347; AVX512DQ-NEXT: vmovdqa64 {{.*#+}} zmm1 = [128,128,128,128,64,64,64,64,32,32,32,32,16,16,16,16,8,8,8,8,4,4,4,4,2,2,2,2,1,1,1,1]348; AVX512DQ-NEXT: vpternlogq {{.*#+}} zmm0 = zmm1 ^ (zmm0 & mem)349; AVX512DQ-NEXT: vpsubw %ymm1, %ymm0, %ymm1350; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm0351; AVX512DQ-NEXT: vpsubw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0352; AVX512DQ-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0353; AVX512DQ-NEXT: retq354;355; AVX512BW-LABEL: constant_shift_v32i16_pairs:356; AVX512BW: # %bb.0:357; AVX512BW-NEXT: vpsravw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0358; AVX512BW-NEXT: retq359 %shift = ashr <32 x i16> %a, <i16 8, i16 8, i16 8, i16 8, i16 9, i16 9, i16 9, i16 9, i16 10, i16 10, i16 10, i16 10, i16 11, i16 11, i16 11, i16 11, i16 12, i16 12, i16 12, i16 12, i16 13, i16 13, i16 13, i16 13, i16 14, i16 14, i16 14, i16 14, i16 15, i16 15, i16 15, i16 15>360 ret <32 x i16> %shift361}362 363define <64 x i8> @constant_shift_v64i8(<64 x i8> %a) nounwind {364; AVX512DQ-LABEL: constant_shift_v64i8:365; AVX512DQ: # %bb.0:366; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm1367; AVX512DQ-NEXT: vpunpckhbw {{.*#+}} ymm2 = ymm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]368; AVX512DQ-NEXT: vpsraw $8, %ymm2, %ymm2369; AVX512DQ-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [2,4,8,16,32,64,128,256,2,4,8,16,32,64,128,256]370; AVX512DQ-NEXT: # ymm3 = mem[0,1,0,1]371; AVX512DQ-NEXT: vpmullw %ymm3, %ymm2, %ymm2372; AVX512DQ-NEXT: vpsrlw $8, %ymm2, %ymm2373; AVX512DQ-NEXT: vpunpcklbw {{.*#+}} ymm1 = ymm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]374; AVX512DQ-NEXT: vpsraw $8, %ymm1, %ymm1375; AVX512DQ-NEXT: vbroadcasti128 {{.*#+}} ymm4 = [256,128,64,32,16,8,4,2,256,128,64,32,16,8,4,2]376; AVX512DQ-NEXT: # ymm4 = mem[0,1,0,1]377; AVX512DQ-NEXT: vpmullw %ymm4, %ymm1, %ymm1378; AVX512DQ-NEXT: vpsrlw $8, %ymm1, %ymm1379; AVX512DQ-NEXT: vpackuswb %ymm2, %ymm1, %ymm1380; AVX512DQ-NEXT: vpunpckhbw {{.*#+}} ymm2 = ymm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31]381; AVX512DQ-NEXT: vpsraw $8, %ymm2, %ymm2382; AVX512DQ-NEXT: vpmullw %ymm3, %ymm2, %ymm2383; AVX512DQ-NEXT: vpsrlw $8, %ymm2, %ymm2384; AVX512DQ-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23]385; AVX512DQ-NEXT: vpsraw $8, %ymm0, %ymm0386; AVX512DQ-NEXT: vpmullw %ymm4, %ymm0, %ymm0387; AVX512DQ-NEXT: vpsrlw $8, %ymm0, %ymm0388; AVX512DQ-NEXT: vpackuswb %ymm2, %ymm0, %ymm0389; AVX512DQ-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0390; AVX512DQ-NEXT: retq391;392; AVX512BW-LABEL: constant_shift_v64i8:393; AVX512BW: # %bb.0:394; AVX512BW-NEXT: vpunpckhbw {{.*#+}} zmm1 = zmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31,40,40,41,41,42,42,43,43,44,44,45,45,46,46,47,47,56,56,57,57,58,58,59,59,60,60,61,61,62,62,63,63]395; AVX512BW-NEXT: vpsraw $8, %zmm1, %zmm1396; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1397; AVX512BW-NEXT: vpsrlw $8, %zmm1, %zmm1398; AVX512BW-NEXT: vpunpcklbw {{.*#+}} zmm0 = zmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23,32,32,33,33,34,34,35,35,36,36,37,37,38,38,39,39,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55]399; AVX512BW-NEXT: vpsraw $8, %zmm0, %zmm0400; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0401; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0402; AVX512BW-NEXT: vpackuswb %zmm1, %zmm0, %zmm0403; AVX512BW-NEXT: retq404 %shift = ashr <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>405 ret <64 x i8> %shift406}407 408define <64 x i8> @constant_shift_v64i8_pairs(<64 x i8> %a) nounwind {409; AVX512DQ-LABEL: constant_shift_v64i8_pairs:410; AVX512DQ: # %bb.0:411; AVX512DQ-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1 # [1024,1024,16384,16384,1024,4096,4096,2048,1024,32768,8192,16384,4096,512,2048,u]412; AVX512DQ-NEXT: vpblendw {{.*#+}} ymm2 = ymm1[0,1,2,3,4,5,6],ymm0[7],ymm1[8,9,10,11,12,13,14],ymm0[15]413; AVX512DQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm2[4,5,6,7]414; AVX512DQ-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1415; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm2 = [2,2,2,2,32,32,32,32,2,2,8,8,8,8,4,4,2,2,64,64,16,16,32,32,8,8,1,1,4,4,128,128]416; AVX512DQ-NEXT: vpxor %ymm2, %ymm1, %ymm1417; AVX512DQ-NEXT: vpsubb %ymm2, %ymm1, %ymm1418; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm0419; AVX512DQ-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm2 # [512,32768,u,512,4096,u,32768,8192,32768,4096,4096,8192,1024,1024,2048,1024]420; AVX512DQ-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1],xmm0[2],xmm2[3,4],xmm0[5],xmm2[6,7]421; AVX512DQ-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm2[4,5,6,7]422; AVX512DQ-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0423; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm2 = [1,1,64,64,128,128,1,1,8,8,128,128,64,64,16,16,64,64,8,8,8,8,16,16,2,2,2,2,4,4,2,2]424; AVX512DQ-NEXT: vpxor %ymm2, %ymm0, %ymm0425; AVX512DQ-NEXT: vpsubb %ymm2, %ymm0, %ymm0426; AVX512DQ-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0427; AVX512DQ-NEXT: retq428;429; AVX512BW-LABEL: constant_shift_v64i8_pairs:430; AVX512BW: # %bb.0:431; AVX512BW-NEXT: vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0432; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm1 = [2,2,2,2,32,32,32,32,2,2,8,8,8,8,4,4,2,2,64,64,16,16,32,32,8,8,1,1,4,4,128,128,1,1,64,64,128,128,1,1,8,8,128,128,64,64,16,16,64,64,8,8,8,8,16,16,2,2,2,2,4,4,2,2]433; AVX512BW-NEXT: vpternlogq {{.*#+}} zmm0 = zmm1 ^ (zmm0 & mem)434; AVX512BW-NEXT: vpsubb %zmm1, %zmm0, %zmm0435; AVX512BW-NEXT: retq436 %shift = ashr <64 x i8> %a, <i8 6, i8 6, i8 6, i8 6, i8 2, i8 2, i8 2, i8 2, i8 6, i8 6, i8 4, i8 4, i8 4, i8 4, i8 5, i8 5, i8 6, i8 6, i8 1, i8 1, i8 3, i8 3, i8 2, i8 2, i8 4, i8 4, i8 7, i8 7, i8 5, i8 5, i8 0, i8 0, i8 7, i8 7, i8 1, i8 1, i8 0, i8 0, i8 7, i8 7, i8 4, i8 4, i8 0, i8 0, i8 1, i8 1, i8 3, i8 3, i8 1, i8 1, i8 4, i8 4, i8 4, i8 4, i8 3, i8 3, i8 6, i8 6, i8 6, i8 6, i8 5, i8 5, i8 6, i8 6>437 ret <64 x i8> %shift438}439 440define <64 x i8> @constant_shift_v64i8_quads(<64 x i8> %a) nounwind {441; AVX512DQ-LABEL: constant_shift_v64i8_quads:442; AVX512DQ: # %bb.0:443; AVX512DQ-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0444; AVX512DQ-NEXT: vmovdqa64 {{.*#+}} zmm1 = [16,16,16,16,4,4,4,4,32,32,32,32,1,1,1,1,1,1,1,1,4,4,4,4,1,1,1,1,4,4,4,4,8,8,8,8,16,16,16,16,16,16,16,16,2,2,2,2,64,64,64,64,4,4,4,4,32,32,32,32,128,128,128,128]445; AVX512DQ-NEXT: vpternlogq {{.*#+}} zmm0 = zmm1 ^ (zmm0 & mem)446; AVX512DQ-NEXT: vpsubb %ymm1, %ymm0, %ymm1447; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm0448; AVX512DQ-NEXT: vpsubb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0449; AVX512DQ-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0450; AVX512DQ-NEXT: retq451;452; AVX512BW-LABEL: constant_shift_v64i8_quads:453; AVX512BW: # %bb.0:454; AVX512BW-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0455; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm1 = [16,16,16,16,4,4,4,4,32,32,32,32,1,1,1,1,1,1,1,1,4,4,4,4,1,1,1,1,4,4,4,4,8,8,8,8,16,16,16,16,16,16,16,16,2,2,2,2,64,64,64,64,4,4,4,4,32,32,32,32,128,128,128,128]456; AVX512BW-NEXT: vpternlogq {{.*#+}} zmm0 = zmm1 ^ (zmm0 & mem)457; AVX512BW-NEXT: vpsubb %zmm1, %zmm0, %zmm0458; AVX512BW-NEXT: retq459 %shift = ashr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 5, i8 5, i8 5, i8 5, i8 2, i8 2, i8 2, i8 2, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 5, i8 5, i8 5, i8 5, i8 7, i8 7, i8 7, i8 7, i8 5, i8 5, i8 5, i8 5, i8 4, i8 4, i8 4, i8 4, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 6, i8 6, i8 6, i8 6, i8 1, i8 1, i8 1, i8 1, i8 5, i8 5, i8 5, i8 5, i8 2, i8 2, i8 2, i8 2, i8 0, i8 0, i8 0, i8 0>460 ret <64 x i8> %shift461}462 463;464; Uniform Constant Shifts465;466 467define <8 x i64> @splatconstant_shift_v8i64(<8 x i64> %a) nounwind {468; ALL-LABEL: splatconstant_shift_v8i64:469; ALL: # %bb.0:470; ALL-NEXT: vpsraq $7, %zmm0, %zmm0471; ALL-NEXT: retq472 %shift = ashr <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>473 ret <8 x i64> %shift474}475 476define <16 x i32> @splatconstant_shift_v16i32(<16 x i32> %a) nounwind {477; ALL-LABEL: splatconstant_shift_v16i32:478; ALL: # %bb.0:479; ALL-NEXT: vpsrad $5, %zmm0, %zmm0480; ALL-NEXT: retq481 %shift = ashr <16 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>482 ret <16 x i32> %shift483}484 485define <32 x i16> @splatconstant_shift_v32i16(<32 x i16> %a) nounwind {486; AVX512DQ-LABEL: splatconstant_shift_v32i16:487; AVX512DQ: # %bb.0:488; AVX512DQ-NEXT: vpsraw $3, %ymm0, %ymm1489; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm0490; AVX512DQ-NEXT: vpsraw $3, %ymm0, %ymm0491; AVX512DQ-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0492; AVX512DQ-NEXT: retq493;494; AVX512BW-LABEL: splatconstant_shift_v32i16:495; AVX512BW: # %bb.0:496; AVX512BW-NEXT: vpsraw $3, %zmm0, %zmm0497; AVX512BW-NEXT: retq498 %shift = ashr <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>499 ret <32 x i16> %shift500}501 502define <64 x i8> @splatconstant_shift_v64i8(<64 x i8> %a) nounwind {503; AVX512DQ-LABEL: splatconstant_shift_v64i8:504; AVX512DQ: # %bb.0:505; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm1506; AVX512DQ-NEXT: vpsrlw $3, %ymm1, %ymm1507; AVX512DQ-NEXT: vpbroadcastb {{.*#+}} ymm2 = [31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31,31]508; AVX512DQ-NEXT: vpand %ymm2, %ymm1, %ymm1509; AVX512DQ-NEXT: vpbroadcastb {{.*#+}} ymm3 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]510; AVX512DQ-NEXT: vpxor %ymm3, %ymm1, %ymm1511; AVX512DQ-NEXT: vpsubb %ymm3, %ymm1, %ymm1512; AVX512DQ-NEXT: vpsrlw $3, %ymm0, %ymm0513; AVX512DQ-NEXT: vpand %ymm2, %ymm0, %ymm0514; AVX512DQ-NEXT: vpxor %ymm3, %ymm0, %ymm0515; AVX512DQ-NEXT: vpsubb %ymm3, %ymm0, %ymm0516; AVX512DQ-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0517; AVX512DQ-NEXT: retq518;519; AVX512BW-LABEL: splatconstant_shift_v64i8:520; AVX512BW: # %bb.0:521; AVX512BW-NEXT: vpsrlw $3, %zmm0, %zmm0522; AVX512BW-NEXT: vpbroadcastb {{.*#+}} zmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]523; AVX512BW-NEXT: vpternlogd {{.*#+}} zmm0 = zmm1 ^ (zmm0 & m32bcst)524; AVX512BW-NEXT: vpsubb %zmm1, %zmm0, %zmm0525; AVX512BW-NEXT: retq526 %shift = ashr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>527 ret <64 x i8> %shift528}529 530define <64 x i8> @ashr_const7_v64i8(<64 x i8> %a) {531; AVX512DQ-LABEL: ashr_const7_v64i8:532; AVX512DQ: # %bb.0:533; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm1534; AVX512DQ-NEXT: vpxor %xmm2, %xmm2, %xmm2535; AVX512DQ-NEXT: vpcmpgtb %ymm1, %ymm2, %ymm1536; AVX512DQ-NEXT: vpcmpgtb %ymm0, %ymm2, %ymm0537; AVX512DQ-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0538; AVX512DQ-NEXT: retq539;540; AVX512BW-LABEL: ashr_const7_v64i8:541; AVX512BW: # %bb.0:542; AVX512BW-NEXT: vpmovb2m %zmm0, %k0543; AVX512BW-NEXT: vpmovm2b %k0, %zmm0544; AVX512BW-NEXT: retq545 %res = ashr <64 x i8> %a, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>546 ret <64 x i8> %res547}548 549define <8 x i64> @PR52719(<8 x i64> %a0, i32 %a1) {550; ALL-LABEL: PR52719:551; ALL: # %bb.0:552; ALL-NEXT: vmovd %edi, %xmm1553; ALL-NEXT: vpsraq %xmm1, %zmm0, %zmm0554; ALL-NEXT: retq555 %vec = insertelement <8 x i32> poison, i32 %a1, i64 0556 %splat = shufflevector <8 x i32> %vec, <8 x i32> poison, <8 x i32> zeroinitializer557 %zext = zext <8 x i32> %splat to <8 x i64>558 %ashr = ashr <8 x i64> %a0, %zext559 ret <8 x i64> %ashr560}561