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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq | FileCheck %s --check-prefixes=ALL,AVX512DQ3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefixes=ALL,AVX512BW4 5;6; Variable Shifts7;8 9define <8 x i64> @var_shift_v8i64(<8 x i64> %a, <8 x i64> %b) nounwind {10; ALL-LABEL: var_shift_v8i64:11; ALL: # %bb.0:12; ALL-NEXT: vpsrlvq %zmm1, %zmm0, %zmm013; ALL-NEXT: retq14 %shift = lshr <8 x i64> %a, %b15 ret <8 x i64> %shift16}17 18define <16 x i32> @var_shift_v16i32(<16 x i32> %a, <16 x i32> %b) nounwind {19; ALL-LABEL: var_shift_v16i32:20; ALL: # %bb.0:21; ALL-NEXT: vpsrlvd %zmm1, %zmm0, %zmm022; ALL-NEXT: retq23 %shift = lshr <16 x i32> %a, %b24 ret <16 x i32> %shift25}26 27define <32 x i16> @var_shift_v32i16(<32 x i16> %a, <32 x i16> %b) nounwind {28; AVX512DQ-LABEL: var_shift_v32i16:29; AVX512DQ: # %bb.0:30; AVX512DQ-NEXT: vpmovzxwd {{.*#+}} zmm2 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero31; AVX512DQ-NEXT: vpmovzxwd {{.*#+}} zmm3 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero32; AVX512DQ-NEXT: vpsrlvd %zmm2, %zmm3, %zmm233; AVX512DQ-NEXT: vpmovdw %zmm2, %ymm234; AVX512DQ-NEXT: vextracti64x4 $1, %zmm1, %ymm135; AVX512DQ-NEXT: vpmovzxwd {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero36; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm037; AVX512DQ-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero38; AVX512DQ-NEXT: vpsrlvd %zmm1, %zmm0, %zmm039; AVX512DQ-NEXT: vpmovdw %zmm0, %ymm040; AVX512DQ-NEXT: vinserti64x4 $1, %ymm0, %zmm2, %zmm041; AVX512DQ-NEXT: retq42;43; AVX512BW-LABEL: var_shift_v32i16:44; AVX512BW: # %bb.0:45; AVX512BW-NEXT: vpsrlvw %zmm1, %zmm0, %zmm046; AVX512BW-NEXT: retq47 %shift = lshr <32 x i16> %a, %b48 ret <32 x i16> %shift49}50 51define <64 x i8> @var_shift_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {52; AVX512DQ-LABEL: var_shift_v64i8:53; AVX512DQ: # %bb.0:54; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm255; AVX512DQ-NEXT: vpsrlw $4, %ymm2, %ymm356; AVX512DQ-NEXT: vpbroadcastb {{.*#+}} ymm4 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]57; AVX512DQ-NEXT: vpand %ymm4, %ymm3, %ymm358; AVX512DQ-NEXT: vextracti64x4 $1, %zmm1, %ymm559; AVX512DQ-NEXT: vpsllw $5, %ymm5, %ymm560; AVX512DQ-NEXT: vpblendvb %ymm5, %ymm3, %ymm2, %ymm261; AVX512DQ-NEXT: vpsrlw $2, %ymm2, %ymm362; AVX512DQ-NEXT: vpbroadcastb {{.*#+}} ymm6 = [63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63,63]63; AVX512DQ-NEXT: vpand %ymm6, %ymm3, %ymm364; AVX512DQ-NEXT: vpaddb %ymm5, %ymm5, %ymm565; AVX512DQ-NEXT: vpblendvb %ymm5, %ymm3, %ymm2, %ymm266; AVX512DQ-NEXT: vpsrlw $1, %ymm2, %ymm367; AVX512DQ-NEXT: vpbroadcastb {{.*#+}} ymm7 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127]68; AVX512DQ-NEXT: vpand %ymm7, %ymm3, %ymm369; AVX512DQ-NEXT: vpaddb %ymm5, %ymm5, %ymm570; AVX512DQ-NEXT: vpblendvb %ymm5, %ymm3, %ymm2, %ymm271; AVX512DQ-NEXT: vpsrlw $4, %ymm0, %ymm372; AVX512DQ-NEXT: vpand %ymm4, %ymm3, %ymm373; AVX512DQ-NEXT: vpsllw $5, %ymm1, %ymm174; AVX512DQ-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm075; AVX512DQ-NEXT: vpsrlw $2, %ymm0, %ymm376; AVX512DQ-NEXT: vpand %ymm6, %ymm3, %ymm377; AVX512DQ-NEXT: vpaddb %ymm1, %ymm1, %ymm178; AVX512DQ-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm079; AVX512DQ-NEXT: vpsrlw $1, %ymm0, %ymm380; AVX512DQ-NEXT: vpand %ymm7, %ymm3, %ymm381; AVX512DQ-NEXT: vpaddb %ymm1, %ymm1, %ymm182; AVX512DQ-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm083; AVX512DQ-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm084; AVX512DQ-NEXT: retq85;86; AVX512BW-LABEL: var_shift_v64i8:87; AVX512BW: # %bb.0:88; AVX512BW-NEXT: vpbroadcastw {{.*#+}} zmm2 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]89; AVX512BW-NEXT: vpandq %zmm2, %zmm1, %zmm390; AVX512BW-NEXT: vpandq %zmm2, %zmm0, %zmm291; AVX512BW-NEXT: vpsrlvw %zmm3, %zmm2, %zmm292; AVX512BW-NEXT: vpsrlw $8, %zmm1, %zmm193; AVX512BW-NEXT: vpsrlvw %zmm1, %zmm0, %zmm094; AVX512BW-NEXT: movabsq $6148914691236517205, %rax # imm = 0x555555555555555595; AVX512BW-NEXT: kmovq %rax, %k196; AVX512BW-NEXT: vmovdqu8 %zmm2, %zmm0 {%k1}97; AVX512BW-NEXT: retq98 %shift = lshr <64 x i8> %a, %b99 ret <64 x i8> %shift100}101 102;103; Uniform Variable Shifts104;105 106define <8 x i64> @splatvar_shift_v8i64(<8 x i64> %a, <8 x i64> %b) nounwind {107; ALL-LABEL: splatvar_shift_v8i64:108; ALL: # %bb.0:109; ALL-NEXT: vpsrlq %xmm1, %zmm0, %zmm0110; ALL-NEXT: retq111 %splat = shufflevector <8 x i64> %b, <8 x i64> poison, <8 x i32> zeroinitializer112 %shift = lshr <8 x i64> %a, %splat113 ret <8 x i64> %shift114}115 116define <16 x i32> @splatvar_shift_v16i32(<16 x i32> %a, <16 x i32> %b) nounwind {117; ALL-LABEL: splatvar_shift_v16i32:118; ALL: # %bb.0:119; ALL-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero120; ALL-NEXT: vpsrld %xmm1, %zmm0, %zmm0121; ALL-NEXT: retq122 %splat = shufflevector <16 x i32> %b, <16 x i32> poison, <16 x i32> zeroinitializer123 %shift = lshr <16 x i32> %a, %splat124 ret <16 x i32> %shift125}126 127define <32 x i16> @splatvar_shift_v32i16(<32 x i16> %a, <32 x i16> %b) nounwind {128; AVX512DQ-LABEL: splatvar_shift_v32i16:129; AVX512DQ: # %bb.0:130; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm2131; AVX512DQ-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero132; AVX512DQ-NEXT: vpsrlw %xmm1, %ymm2, %ymm2133; AVX512DQ-NEXT: vpsrlw %xmm1, %ymm0, %ymm0134; AVX512DQ-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0135; AVX512DQ-NEXT: retq136;137; AVX512BW-LABEL: splatvar_shift_v32i16:138; AVX512BW: # %bb.0:139; AVX512BW-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero140; AVX512BW-NEXT: vpsrlw %xmm1, %zmm0, %zmm0141; AVX512BW-NEXT: retq142 %splat = shufflevector <32 x i16> %b, <32 x i16> poison, <32 x i32> zeroinitializer143 %shift = lshr <32 x i16> %a, %splat144 ret <32 x i16> %shift145}146 147define <64 x i8> @splatvar_shift_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {148; AVX512DQ-LABEL: splatvar_shift_v64i8:149; AVX512DQ: # %bb.0:150; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm2151; AVX512DQ-NEXT: vpmovzxbq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[1],zero,zero,zero,zero,zero,zero,zero152; AVX512DQ-NEXT: vpsrlw %xmm1, %ymm2, %ymm2153; AVX512DQ-NEXT: vpsrlw %xmm1, %ymm0, %ymm0154; AVX512DQ-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0155; AVX512DQ-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2156; AVX512DQ-NEXT: vpsrlw %xmm1, %xmm2, %xmm1157; AVX512DQ-NEXT: vpsrlw $8, %xmm1, %xmm1158; AVX512DQ-NEXT: vpbroadcastb %xmm1, %ymm1159; AVX512DQ-NEXT: vinserti64x4 $1, %ymm1, %zmm1, %zmm1160; AVX512DQ-NEXT: vpandq %zmm1, %zmm0, %zmm0161; AVX512DQ-NEXT: retq162;163; AVX512BW-LABEL: splatvar_shift_v64i8:164; AVX512BW: # %bb.0:165; AVX512BW-NEXT: vpmovzxbq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[1],zero,zero,zero,zero,zero,zero,zero166; AVX512BW-NEXT: vpsrlw %xmm1, %zmm0, %zmm0167; AVX512BW-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2168; AVX512BW-NEXT: vpsrlw %xmm1, %xmm2, %xmm1169; AVX512BW-NEXT: vpsrlw $8, %xmm1, %xmm1170; AVX512BW-NEXT: vpbroadcastb %xmm1, %zmm1171; AVX512BW-NEXT: vpandq %zmm1, %zmm0, %zmm0172; AVX512BW-NEXT: retq173 %splat = shufflevector <64 x i8> %b, <64 x i8> poison, <64 x i32> zeroinitializer174 %shift = lshr <64 x i8> %a, %splat175 ret <64 x i8> %shift176}177 178;179; Uniform Variable Modulo Shifts180;181 182define <8 x i64> @splatvar_modulo_shift_v8i64(<8 x i64> %a, <8 x i64> %b) nounwind {183; ALL-LABEL: splatvar_modulo_shift_v8i64:184; ALL: # %bb.0:185; ALL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1186; ALL-NEXT: vpsrlq %xmm1, %zmm0, %zmm0187; ALL-NEXT: retq188 %mod = and <8 x i64> %b, <i64 63, i64 63, i64 63, i64 63, i64 63, i64 63, i64 63, i64 63>189 %splat = shufflevector <8 x i64> %mod, <8 x i64> poison, <8 x i32> zeroinitializer190 %shift = lshr <8 x i64> %a, %splat191 ret <8 x i64> %shift192}193 194define <16 x i32> @splatvar_modulo_shift_v16i32(<16 x i32> %a, <16 x i32> %b) nounwind {195; ALL-LABEL: splatvar_modulo_shift_v16i32:196; ALL: # %bb.0:197; ALL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1198; ALL-NEXT: vpsrld %xmm1, %zmm0, %zmm0199; ALL-NEXT: retq200 %mod = and <16 x i32> %b, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>201 %splat = shufflevector <16 x i32> %mod, <16 x i32> poison, <16 x i32> zeroinitializer202 %shift = lshr <16 x i32> %a, %splat203 ret <16 x i32> %shift204}205 206define <32 x i16> @splatvar_modulo_shift_v32i16(<32 x i16> %a, <32 x i16> %b) nounwind {207; AVX512DQ-LABEL: splatvar_modulo_shift_v32i16:208; AVX512DQ: # %bb.0:209; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm2210; AVX512DQ-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1211; AVX512DQ-NEXT: vpsrlw %xmm1, %ymm2, %ymm2212; AVX512DQ-NEXT: vpsrlw %xmm1, %ymm0, %ymm0213; AVX512DQ-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0214; AVX512DQ-NEXT: retq215;216; AVX512BW-LABEL: splatvar_modulo_shift_v32i16:217; AVX512BW: # %bb.0:218; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1219; AVX512BW-NEXT: vpsrlw %xmm1, %zmm0, %zmm0220; AVX512BW-NEXT: retq221 %mod = and <32 x i16> %b, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>222 %splat = shufflevector <32 x i16> %mod, <32 x i16> poison, <32 x i32> zeroinitializer223 %shift = lshr <32 x i16> %a, %splat224 ret <32 x i16> %shift225}226 227define <64 x i8> @splatvar_modulo_shift_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {228; AVX512DQ-LABEL: splatvar_modulo_shift_v64i8:229; AVX512DQ: # %bb.0:230; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm2231; AVX512DQ-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1232; AVX512DQ-NEXT: vpsrlw %xmm1, %ymm2, %ymm2233; AVX512DQ-NEXT: vpsrlw %xmm1, %ymm0, %ymm0234; AVX512DQ-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0235; AVX512DQ-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2236; AVX512DQ-NEXT: vpsrlw %xmm1, %xmm2, %xmm1237; AVX512DQ-NEXT: vpsrlw $8, %xmm1, %xmm1238; AVX512DQ-NEXT: vpbroadcastb %xmm1, %ymm1239; AVX512DQ-NEXT: vinserti64x4 $1, %ymm1, %zmm1, %zmm1240; AVX512DQ-NEXT: vpandq %zmm1, %zmm0, %zmm0241; AVX512DQ-NEXT: retq242;243; AVX512BW-LABEL: splatvar_modulo_shift_v64i8:244; AVX512BW: # %bb.0:245; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1246; AVX512BW-NEXT: vpsrlw %xmm1, %zmm0, %zmm0247; AVX512BW-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2248; AVX512BW-NEXT: vpsrlw %xmm1, %xmm2, %xmm1249; AVX512BW-NEXT: vpsrlw $8, %xmm1, %xmm1250; AVX512BW-NEXT: vpbroadcastb %xmm1, %zmm1251; AVX512BW-NEXT: vpandq %zmm1, %zmm0, %zmm0252; AVX512BW-NEXT: retq253 %mod = and <64 x i8> %b, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>254 %splat = shufflevector <64 x i8> %mod, <64 x i8> poison, <64 x i32> zeroinitializer255 %shift = lshr <64 x i8> %a, %splat256 ret <64 x i8> %shift257}258 259;260; Constant Shifts261;262 263define <8 x i64> @constant_shift_v8i64(<8 x i64> %a) nounwind {264; ALL-LABEL: constant_shift_v8i64:265; ALL: # %bb.0:266; ALL-NEXT: vpsrlvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0267; ALL-NEXT: retq268 %shift = lshr <8 x i64> %a, <i64 1, i64 7, i64 31, i64 62, i64 1, i64 7, i64 31, i64 62>269 ret <8 x i64> %shift270}271 272define <16 x i32> @constant_shift_v16i32(<16 x i32> %a) nounwind {273; ALL-LABEL: constant_shift_v16i32:274; ALL: # %bb.0:275; ALL-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0276; ALL-NEXT: retq277 %shift = lshr <16 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 8, i32 7, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 8, i32 7>278 ret <16 x i32> %shift279}280 281define <32 x i16> @constant_shift_v32i16(<32 x i16> %a) nounwind {282; AVX512DQ-LABEL: constant_shift_v32i16:283; AVX512DQ: # %bb.0:284; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm1285; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm2 = [u,32768,16384,8192,4096,2048,1024,512,256,128,64,32,16,8,4,2]286; AVX512DQ-NEXT: vpmulhuw %ymm2, %ymm1, %ymm3287; AVX512DQ-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0],xmm3[1,2,3,4,5,6,7]288; AVX512DQ-NEXT: vpblendd {{.*#+}} ymm1 = ymm1[0,1,2,3],ymm3[4,5,6,7]289; AVX512DQ-NEXT: vpmulhuw %ymm2, %ymm0, %ymm2290; AVX512DQ-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm2[1,2,3,4,5,6,7]291; AVX512DQ-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm2[4,5,6,7]292; AVX512DQ-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0293; AVX512DQ-NEXT: retq294;295; AVX512BW-LABEL: constant_shift_v32i16:296; AVX512BW: # %bb.0:297; AVX512BW-NEXT: vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0298; AVX512BW-NEXT: retq299 %shift = lshr <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>300 ret <32 x i16> %shift301}302 303define <32 x i16> @constant_shift_v32i16_pairs(<32 x i16> %a) nounwind {304; AVX512DQ-LABEL: constant_shift_v32i16_pairs:305; AVX512DQ: # %bb.0:306; AVX512DQ-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0307; AVX512DQ-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0308; AVX512DQ-NEXT: retq309;310; AVX512BW-LABEL: constant_shift_v32i16_pairs:311; AVX512BW: # %bb.0:312; AVX512BW-NEXT: vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0313; AVX512BW-NEXT: retq314 %shift = lshr <32 x i16> %a, <i16 8, i16 8, i16 8, i16 8, i16 9, i16 9, i16 9, i16 9, i16 10, i16 10, i16 10, i16 10, i16 11, i16 11, i16 11, i16 11, i16 12, i16 12, i16 12, i16 12, i16 13, i16 13, i16 13, i16 13, i16 14, i16 14, i16 14, i16 14, i16 15, i16 15, i16 15, i16 15>315 ret <32 x i16> %shift316}317 318define <64 x i8> @constant_shift_v64i8_pairs(<64 x i8> %a) nounwind {319; AVX512DQ-LABEL: constant_shift_v64i8_pairs:320; AVX512DQ: # %bb.0:321; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm1322; AVX512DQ-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [512,16384,4096,1024,32768,16384,8192,4096,512,16384,4096,1024,32768,16384,8192,4096]323; AVX512DQ-NEXT: # ymm2 = mem[0,1,0,1]324; AVX512DQ-NEXT: vpmulhuw %ymm2, %ymm1, %ymm1325; AVX512DQ-NEXT: vpmulhuw %ymm2, %ymm0, %ymm0326; AVX512DQ-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0327; AVX512DQ-NEXT: vbroadcasti32x4 {{.*#+}} zmm1 = [1,1,63,63,15,15,3,3,127,127,63,63,31,31,15,15,1,1,63,63,15,15,3,3,127,127,63,63,31,31,15,15,1,1,63,63,15,15,3,3,127,127,63,63,31,31,15,15,1,1,63,63,15,15,3,3,127,127,63,63,31,31,15,15]328; AVX512DQ-NEXT: # zmm1 = mem[0,1,2,3,0,1,2,3,0,1,2,3,0,1,2,3]329; AVX512DQ-NEXT: vpandq %zmm0, %zmm1, %zmm0330; AVX512DQ-NEXT: retq331;332; AVX512BW-LABEL: constant_shift_v64i8_pairs:333; AVX512BW: # %bb.0:334; AVX512BW-NEXT: vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0335; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0336; AVX512BW-NEXT: retq337 %shift = lshr <64 x i8> %a, <i8 7, i8 7, i8 2, i8 2, i8 4, i8 4, i8 6, i8 6, i8 1, i8 1, i8 2, i8 2, i8 3, i8 3, i8 4, i8 4, i8 7, i8 7, i8 2, i8 2, i8 4, i8 4, i8 6, i8 6, i8 1, i8 1, i8 2, i8 2, i8 3, i8 3, i8 4, i8 4, i8 7, i8 7, i8 2, i8 2, i8 4, i8 4, i8 6, i8 6, i8 1, i8 1, i8 2, i8 2, i8 3, i8 3, i8 4, i8 4, i8 7, i8 7, i8 2, i8 2, i8 4, i8 4, i8 6, i8 6, i8 1, i8 1, i8 2, i8 2, i8 3, i8 3, i8 4, i8 4>338 ret <64 x i8> %shift339}340 341define <64 x i8> @constant_shift_v64i8_quads(<64 x i8> %a) nounwind {342; ALL-LABEL: constant_shift_v64i8_quads:343; ALL: # %bb.0:344; ALL-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0345; ALL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0346; ALL-NEXT: retq347 %shift = lshr <64 x i8> %a, <i8 4, i8 4, i8 4, i8 4, i8 5, i8 5, i8 5, i8 5, i8 6, i8 6, i8 6, i8 6, i8 7, i8 7, i8 7, i8 7, i8 0, i8 0, i8 0, i8 0, i8 1, i8 1, i8 1, i8 1, i8 2, i8 2, i8 2, i8 2, i8 3, i8 3, i8 3, i8 3, i8 4, i8 4, i8 4, i8 4, i8 5, i8 5, i8 5, i8 5, i8 6, i8 6, i8 6, i8 6, i8 7, i8 7, i8 7, i8 7, i8 0, i8 0, i8 0, i8 0, i8 1, i8 1, i8 1, i8 1, i8 2, i8 2, i8 2, i8 2, i8 3, i8 3, i8 3, i8 3>348 ret <64 x i8> %shift349}350 351define <64 x i8> @constant_shift_v64i8(<64 x i8> %a) nounwind {352; AVX512DQ-LABEL: constant_shift_v64i8:353; AVX512DQ: # %bb.0:354; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm1355; AVX512DQ-NEXT: vpxor %xmm2, %xmm2, %xmm2356; AVX512DQ-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm1[8],ymm2[8],ymm1[9],ymm2[9],ymm1[10],ymm2[10],ymm1[11],ymm2[11],ymm1[12],ymm2[12],ymm1[13],ymm2[13],ymm1[14],ymm2[14],ymm1[15],ymm2[15],ymm1[24],ymm2[24],ymm1[25],ymm2[25],ymm1[26],ymm2[26],ymm1[27],ymm2[27],ymm1[28],ymm2[28],ymm1[29],ymm2[29],ymm1[30],ymm2[30],ymm1[31],ymm2[31]357; AVX512DQ-NEXT: vbroadcasti128 {{.*#+}} ymm4 = [2,4,8,16,32,64,128,256,2,4,8,16,32,64,128,256]358; AVX512DQ-NEXT: # ymm4 = mem[0,1,0,1]359; AVX512DQ-NEXT: vpmullw %ymm4, %ymm3, %ymm3360; AVX512DQ-NEXT: vpsrlw $8, %ymm3, %ymm3361; AVX512DQ-NEXT: vpunpcklbw {{.*#+}} ymm1 = ymm1[0],ymm2[0],ymm1[1],ymm2[1],ymm1[2],ymm2[2],ymm1[3],ymm2[3],ymm1[4],ymm2[4],ymm1[5],ymm2[5],ymm1[6],ymm2[6],ymm1[7],ymm2[7],ymm1[16],ymm2[16],ymm1[17],ymm2[17],ymm1[18],ymm2[18],ymm1[19],ymm2[19],ymm1[20],ymm2[20],ymm1[21],ymm2[21],ymm1[22],ymm2[22],ymm1[23],ymm2[23]362; AVX512DQ-NEXT: vbroadcasti128 {{.*#+}} ymm5 = [256,128,64,32,16,8,4,2,256,128,64,32,16,8,4,2]363; AVX512DQ-NEXT: # ymm5 = mem[0,1,0,1]364; AVX512DQ-NEXT: vpmullw %ymm5, %ymm1, %ymm1365; AVX512DQ-NEXT: vpsrlw $8, %ymm1, %ymm1366; AVX512DQ-NEXT: vpackuswb %ymm3, %ymm1, %ymm1367; AVX512DQ-NEXT: vpunpckhbw {{.*#+}} ymm3 = ymm0[8],ymm2[8],ymm0[9],ymm2[9],ymm0[10],ymm2[10],ymm0[11],ymm2[11],ymm0[12],ymm2[12],ymm0[13],ymm2[13],ymm0[14],ymm2[14],ymm0[15],ymm2[15],ymm0[24],ymm2[24],ymm0[25],ymm2[25],ymm0[26],ymm2[26],ymm0[27],ymm2[27],ymm0[28],ymm2[28],ymm0[29],ymm2[29],ymm0[30],ymm2[30],ymm0[31],ymm2[31]368; AVX512DQ-NEXT: vpmullw %ymm4, %ymm3, %ymm3369; AVX512DQ-NEXT: vpsrlw $8, %ymm3, %ymm3370; AVX512DQ-NEXT: vpunpcklbw {{.*#+}} ymm0 = ymm0[0],ymm2[0],ymm0[1],ymm2[1],ymm0[2],ymm2[2],ymm0[3],ymm2[3],ymm0[4],ymm2[4],ymm0[5],ymm2[5],ymm0[6],ymm2[6],ymm0[7],ymm2[7],ymm0[16],ymm2[16],ymm0[17],ymm2[17],ymm0[18],ymm2[18],ymm0[19],ymm2[19],ymm0[20],ymm2[20],ymm0[21],ymm2[21],ymm0[22],ymm2[22],ymm0[23],ymm2[23]371; AVX512DQ-NEXT: vpmullw %ymm5, %ymm0, %ymm0372; AVX512DQ-NEXT: vpsrlw $8, %ymm0, %ymm0373; AVX512DQ-NEXT: vpackuswb %ymm3, %ymm0, %ymm0374; AVX512DQ-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0375; AVX512DQ-NEXT: retq376;377; AVX512BW-LABEL: constant_shift_v64i8:378; AVX512BW: # %bb.0:379; AVX512BW-NEXT: vpxor %xmm1, %xmm1, %xmm1380; AVX512BW-NEXT: vpunpckhbw {{.*#+}} zmm2 = zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[10],zmm1[10],zmm0[11],zmm1[11],zmm0[12],zmm1[12],zmm0[13],zmm1[13],zmm0[14],zmm1[14],zmm0[15],zmm1[15],zmm0[24],zmm1[24],zmm0[25],zmm1[25],zmm0[26],zmm1[26],zmm0[27],zmm1[27],zmm0[28],zmm1[28],zmm0[29],zmm1[29],zmm0[30],zmm1[30],zmm0[31],zmm1[31],zmm0[40],zmm1[40],zmm0[41],zmm1[41],zmm0[42],zmm1[42],zmm0[43],zmm1[43],zmm0[44],zmm1[44],zmm0[45],zmm1[45],zmm0[46],zmm1[46],zmm0[47],zmm1[47],zmm0[56],zmm1[56],zmm0[57],zmm1[57],zmm0[58],zmm1[58],zmm0[59],zmm1[59],zmm0[60],zmm1[60],zmm0[61],zmm1[61],zmm0[62],zmm1[62],zmm0[63],zmm1[63]381; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2382; AVX512BW-NEXT: vpsrlw $8, %zmm2, %zmm2383; AVX512BW-NEXT: vpunpcklbw {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[2],zmm1[2],zmm0[3],zmm1[3],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[6],zmm1[6],zmm0[7],zmm1[7],zmm0[16],zmm1[16],zmm0[17],zmm1[17],zmm0[18],zmm1[18],zmm0[19],zmm1[19],zmm0[20],zmm1[20],zmm0[21],zmm1[21],zmm0[22],zmm1[22],zmm0[23],zmm1[23],zmm0[32],zmm1[32],zmm0[33],zmm1[33],zmm0[34],zmm1[34],zmm0[35],zmm1[35],zmm0[36],zmm1[36],zmm0[37],zmm1[37],zmm0[38],zmm1[38],zmm0[39],zmm1[39],zmm0[48],zmm1[48],zmm0[49],zmm1[49],zmm0[50],zmm1[50],zmm0[51],zmm1[51],zmm0[52],zmm1[52],zmm0[53],zmm1[53],zmm0[54],zmm1[54],zmm0[55],zmm1[55]384; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0385; AVX512BW-NEXT: vpsrlw $8, %zmm0, %zmm0386; AVX512BW-NEXT: vpackuswb %zmm2, %zmm0, %zmm0387; AVX512BW-NEXT: retq388 %shift = lshr <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>389 ret <64 x i8> %shift390}391 392;393; Uniform Constant Shifts394;395 396define <8 x i64> @splatconstant_shift_v8i64(<8 x i64> %a) nounwind {397; ALL-LABEL: splatconstant_shift_v8i64:398; ALL: # %bb.0:399; ALL-NEXT: vpsrlq $7, %zmm0, %zmm0400; ALL-NEXT: retq401 %shift = lshr <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>402 ret <8 x i64> %shift403}404 405define <16 x i32> @splatconstant_shift_v16i32(<16 x i32> %a) nounwind {406; ALL-LABEL: splatconstant_shift_v16i32:407; ALL: # %bb.0:408; ALL-NEXT: vpsrld $5, %zmm0, %zmm0409; ALL-NEXT: retq410 %shift = lshr <16 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>411 ret <16 x i32> %shift412}413 414define <32 x i16> @splatconstant_shift_v32i16(<32 x i16> %a) nounwind {415; AVX512DQ-LABEL: splatconstant_shift_v32i16:416; AVX512DQ: # %bb.0:417; AVX512DQ-NEXT: vpsrlw $3, %ymm0, %ymm1418; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm0419; AVX512DQ-NEXT: vpsrlw $3, %ymm0, %ymm0420; AVX512DQ-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0421; AVX512DQ-NEXT: retq422;423; AVX512BW-LABEL: splatconstant_shift_v32i16:424; AVX512BW: # %bb.0:425; AVX512BW-NEXT: vpsrlw $3, %zmm0, %zmm0426; AVX512BW-NEXT: retq427 %shift = lshr <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>428 ret <32 x i16> %shift429}430 431define <64 x i8> @splatconstant_shift_v64i8(<64 x i8> %a) nounwind {432; AVX512DQ-LABEL: splatconstant_shift_v64i8:433; AVX512DQ: # %bb.0:434; AVX512DQ-NEXT: vpsrlw $3, %ymm0, %ymm1435; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm0436; AVX512DQ-NEXT: vpsrlw $3, %ymm0, %ymm0437; AVX512DQ-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0438; AVX512DQ-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0439; AVX512DQ-NEXT: retq440;441; AVX512BW-LABEL: splatconstant_shift_v64i8:442; AVX512BW: # %bb.0:443; AVX512BW-NEXT: vpsrlw $3, %zmm0, %zmm0444; AVX512BW-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0445; AVX512BW-NEXT: retq446 %shift = lshr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>447 ret <64 x i8> %shift448}449