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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512dq | FileCheck %s --check-prefixes=ALL,AVX512DQ3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefixes=ALL,AVX512BW4 5;6; Variable Shifts7;8 9define <8 x i64> @var_shift_v8i64(<8 x i64> %a, <8 x i64> %b) nounwind {10; ALL-LABEL: var_shift_v8i64:11; ALL: # %bb.0:12; ALL-NEXT: vpsllvq %zmm1, %zmm0, %zmm013; ALL-NEXT: retq14 %shift = shl <8 x i64> %a, %b15 ret <8 x i64> %shift16}17 18define <16 x i32> @var_shift_v16i32(<16 x i32> %a, <16 x i32> %b) nounwind {19; ALL-LABEL: var_shift_v16i32:20; ALL: # %bb.0:21; ALL-NEXT: vpsllvd %zmm1, %zmm0, %zmm022; ALL-NEXT: retq23 %shift = shl <16 x i32> %a, %b24 ret <16 x i32> %shift25}26 27define <32 x i16> @var_shift_v32i16(<32 x i16> %a, <32 x i16> %b) nounwind {28; AVX512DQ-LABEL: var_shift_v32i16:29; AVX512DQ: # %bb.0:30; AVX512DQ-NEXT: vpmovzxwd {{.*#+}} zmm2 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero31; AVX512DQ-NEXT: vpmovzxwd {{.*#+}} zmm3 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero32; AVX512DQ-NEXT: vpsllvd %zmm2, %zmm3, %zmm233; AVX512DQ-NEXT: vpmovdw %zmm2, %ymm234; AVX512DQ-NEXT: vextracti64x4 $1, %zmm1, %ymm135; AVX512DQ-NEXT: vpmovzxwd {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero36; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm037; AVX512DQ-NEXT: vpmovzxwd {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero38; AVX512DQ-NEXT: vpsllvd %zmm1, %zmm0, %zmm039; AVX512DQ-NEXT: vpmovdw %zmm0, %ymm040; AVX512DQ-NEXT: vinserti64x4 $1, %ymm0, %zmm2, %zmm041; AVX512DQ-NEXT: retq42;43; AVX512BW-LABEL: var_shift_v32i16:44; AVX512BW: # %bb.0:45; AVX512BW-NEXT: vpsllvw %zmm1, %zmm0, %zmm046; AVX512BW-NEXT: retq47 %shift = shl <32 x i16> %a, %b48 ret <32 x i16> %shift49}50 51define <64 x i8> @var_shift_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {52; AVX512DQ-LABEL: var_shift_v64i8:53; AVX512DQ: # %bb.0:54; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm255; AVX512DQ-NEXT: vpsllw $4, %ymm2, %ymm356; AVX512DQ-NEXT: vpbroadcastb {{.*#+}} ymm4 = [240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240,240]57; AVX512DQ-NEXT: vpand %ymm4, %ymm3, %ymm358; AVX512DQ-NEXT: vextracti64x4 $1, %zmm1, %ymm559; AVX512DQ-NEXT: vpsllw $5, %ymm5, %ymm560; AVX512DQ-NEXT: vpblendvb %ymm5, %ymm3, %ymm2, %ymm261; AVX512DQ-NEXT: vpsllw $2, %ymm2, %ymm362; AVX512DQ-NEXT: vpbroadcastb {{.*#+}} ymm6 = [252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252,252]63; AVX512DQ-NEXT: vpand %ymm6, %ymm3, %ymm364; AVX512DQ-NEXT: vpaddb %ymm5, %ymm5, %ymm565; AVX512DQ-NEXT: vpblendvb %ymm5, %ymm3, %ymm2, %ymm266; AVX512DQ-NEXT: vpaddb %ymm2, %ymm2, %ymm367; AVX512DQ-NEXT: vpaddb %ymm5, %ymm5, %ymm568; AVX512DQ-NEXT: vpblendvb %ymm5, %ymm3, %ymm2, %ymm269; AVX512DQ-NEXT: vpsllw $4, %ymm0, %ymm370; AVX512DQ-NEXT: vpand %ymm4, %ymm3, %ymm371; AVX512DQ-NEXT: vpsllw $5, %ymm1, %ymm172; AVX512DQ-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm073; AVX512DQ-NEXT: vpsllw $2, %ymm0, %ymm374; AVX512DQ-NEXT: vpand %ymm6, %ymm3, %ymm375; AVX512DQ-NEXT: vpaddb %ymm1, %ymm1, %ymm176; AVX512DQ-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm077; AVX512DQ-NEXT: vpaddb %ymm0, %ymm0, %ymm378; AVX512DQ-NEXT: vpaddb %ymm1, %ymm1, %ymm179; AVX512DQ-NEXT: vpblendvb %ymm1, %ymm3, %ymm0, %ymm080; AVX512DQ-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm081; AVX512DQ-NEXT: retq82;83; AVX512BW-LABEL: var_shift_v64i8:84; AVX512BW: # %bb.0:85; AVX512BW-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %zmm286; AVX512BW-NEXT: vpsllvw %zmm2, %zmm0, %zmm287; AVX512BW-NEXT: vpsrlw $8, %zmm1, %zmm188; AVX512BW-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm089; AVX512BW-NEXT: vpsllvw %zmm1, %zmm0, %zmm090; AVX512BW-NEXT: movabsq $6148914691236517205, %rax # imm = 0x555555555555555591; AVX512BW-NEXT: kmovq %rax, %k192; AVX512BW-NEXT: vmovdqu8 %zmm2, %zmm0 {%k1}93; AVX512BW-NEXT: retq94 %shift = shl <64 x i8> %a, %b95 ret <64 x i8> %shift96}97 98;99; Uniform Variable Shifts100;101 102define <8 x i64> @splatvar_shift_v8i64(<8 x i64> %a, <8 x i64> %b) nounwind {103; ALL-LABEL: splatvar_shift_v8i64:104; ALL: # %bb.0:105; ALL-NEXT: vpsllq %xmm1, %zmm0, %zmm0106; ALL-NEXT: retq107 %splat = shufflevector <8 x i64> %b, <8 x i64> poison, <8 x i32> zeroinitializer108 %shift = shl <8 x i64> %a, %splat109 ret <8 x i64> %shift110}111 112define <16 x i32> @splatvar_shift_v16i32(<16 x i32> %a, <16 x i32> %b) nounwind {113; ALL-LABEL: splatvar_shift_v16i32:114; ALL: # %bb.0:115; ALL-NEXT: vpmovzxdq {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero116; ALL-NEXT: vpslld %xmm1, %zmm0, %zmm0117; ALL-NEXT: retq118 %splat = shufflevector <16 x i32> %b, <16 x i32> poison, <16 x i32> zeroinitializer119 %shift = shl <16 x i32> %a, %splat120 ret <16 x i32> %shift121}122 123define <32 x i16> @splatvar_shift_v32i16(<32 x i16> %a, <32 x i16> %b) nounwind {124; AVX512DQ-LABEL: splatvar_shift_v32i16:125; AVX512DQ: # %bb.0:126; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm2127; AVX512DQ-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero128; AVX512DQ-NEXT: vpsllw %xmm1, %ymm2, %ymm2129; AVX512DQ-NEXT: vpsllw %xmm1, %ymm0, %ymm0130; AVX512DQ-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0131; AVX512DQ-NEXT: retq132;133; AVX512BW-LABEL: splatvar_shift_v32i16:134; AVX512BW: # %bb.0:135; AVX512BW-NEXT: vpmovzxwq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero136; AVX512BW-NEXT: vpsllw %xmm1, %zmm0, %zmm0137; AVX512BW-NEXT: retq138 %splat = shufflevector <32 x i16> %b, <32 x i16> poison, <32 x i32> zeroinitializer139 %shift = shl <32 x i16> %a, %splat140 ret <32 x i16> %shift141}142 143define <64 x i8> @splatvar_shift_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {144; AVX512DQ-LABEL: splatvar_shift_v64i8:145; AVX512DQ: # %bb.0:146; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm2147; AVX512DQ-NEXT: vpmovzxbq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[1],zero,zero,zero,zero,zero,zero,zero148; AVX512DQ-NEXT: vpsllw %xmm1, %ymm2, %ymm2149; AVX512DQ-NEXT: vpsllw %xmm1, %ymm0, %ymm0150; AVX512DQ-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0151; AVX512DQ-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2152; AVX512DQ-NEXT: vpsllw %xmm1, %xmm2, %xmm1153; AVX512DQ-NEXT: vpbroadcastb %xmm1, %ymm1154; AVX512DQ-NEXT: vinserti64x4 $1, %ymm1, %zmm1, %zmm1155; AVX512DQ-NEXT: vpandq %zmm1, %zmm0, %zmm0156; AVX512DQ-NEXT: retq157;158; AVX512BW-LABEL: splatvar_shift_v64i8:159; AVX512BW: # %bb.0:160; AVX512BW-NEXT: vpmovzxbq {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,zero,zero,zero,zero,xmm1[1],zero,zero,zero,zero,zero,zero,zero161; AVX512BW-NEXT: vpsllw %xmm1, %zmm0, %zmm0162; AVX512BW-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2163; AVX512BW-NEXT: vpsllw %xmm1, %xmm2, %xmm1164; AVX512BW-NEXT: vpbroadcastb %xmm1, %zmm1165; AVX512BW-NEXT: vpandq %zmm1, %zmm0, %zmm0166; AVX512BW-NEXT: retq167 %splat = shufflevector <64 x i8> %b, <64 x i8> poison, <64 x i32> zeroinitializer168 %shift = shl <64 x i8> %a, %splat169 ret <64 x i8> %shift170}171 172;173; Uniform Variable Modulo Shifts174;175 176define <8 x i64> @splatvar_modulo_shift_v8i64(<8 x i64> %a, <8 x i64> %b) nounwind {177; ALL-LABEL: splatvar_modulo_shift_v8i64:178; ALL: # %bb.0:179; ALL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1180; ALL-NEXT: vpsllq %xmm1, %zmm0, %zmm0181; ALL-NEXT: retq182 %mod = and <8 x i64> %b, <i64 63, i64 63, i64 63, i64 63, i64 63, i64 63, i64 63, i64 63>183 %splat = shufflevector <8 x i64> %mod, <8 x i64> poison, <8 x i32> zeroinitializer184 %shift = shl <8 x i64> %a, %splat185 ret <8 x i64> %shift186}187 188define <16 x i32> @splatvar_modulo_shift_v16i32(<16 x i32> %a, <16 x i32> %b) nounwind {189; ALL-LABEL: splatvar_modulo_shift_v16i32:190; ALL: # %bb.0:191; ALL-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1192; ALL-NEXT: vpslld %xmm1, %zmm0, %zmm0193; ALL-NEXT: retq194 %mod = and <16 x i32> %b, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>195 %splat = shufflevector <16 x i32> %mod, <16 x i32> poison, <16 x i32> zeroinitializer196 %shift = shl <16 x i32> %a, %splat197 ret <16 x i32> %shift198}199 200define <32 x i16> @splatvar_modulo_shift_v32i16(<32 x i16> %a, <32 x i16> %b) nounwind {201; AVX512DQ-LABEL: splatvar_modulo_shift_v32i16:202; AVX512DQ: # %bb.0:203; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm2204; AVX512DQ-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1205; AVX512DQ-NEXT: vpsllw %xmm1, %ymm2, %ymm2206; AVX512DQ-NEXT: vpsllw %xmm1, %ymm0, %ymm0207; AVX512DQ-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0208; AVX512DQ-NEXT: retq209;210; AVX512BW-LABEL: splatvar_modulo_shift_v32i16:211; AVX512BW: # %bb.0:212; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1213; AVX512BW-NEXT: vpsllw %xmm1, %zmm0, %zmm0214; AVX512BW-NEXT: retq215 %mod = and <32 x i16> %b, <i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15>216 %splat = shufflevector <32 x i16> %mod, <32 x i16> poison, <32 x i32> zeroinitializer217 %shift = shl <32 x i16> %a, %splat218 ret <32 x i16> %shift219}220 221define <64 x i8> @splatvar_modulo_shift_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {222; AVX512DQ-LABEL: splatvar_modulo_shift_v64i8:223; AVX512DQ: # %bb.0:224; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm2225; AVX512DQ-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1226; AVX512DQ-NEXT: vpsllw %xmm1, %ymm2, %ymm2227; AVX512DQ-NEXT: vpsllw %xmm1, %ymm0, %ymm0228; AVX512DQ-NEXT: vinserti64x4 $1, %ymm2, %zmm0, %zmm0229; AVX512DQ-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2230; AVX512DQ-NEXT: vpsllw %xmm1, %xmm2, %xmm1231; AVX512DQ-NEXT: vpbroadcastb %xmm1, %ymm1232; AVX512DQ-NEXT: vinserti64x4 $1, %ymm1, %zmm1, %zmm1233; AVX512DQ-NEXT: vpandq %zmm1, %zmm0, %zmm0234; AVX512DQ-NEXT: retq235;236; AVX512BW-LABEL: splatvar_modulo_shift_v64i8:237; AVX512BW: # %bb.0:238; AVX512BW-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1239; AVX512BW-NEXT: vpsllw %xmm1, %zmm0, %zmm0240; AVX512BW-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2241; AVX512BW-NEXT: vpsllw %xmm1, %xmm2, %xmm1242; AVX512BW-NEXT: vpbroadcastb %xmm1, %zmm1243; AVX512BW-NEXT: vpandq %zmm1, %zmm0, %zmm0244; AVX512BW-NEXT: retq245 %mod = and <64 x i8> %b, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>246 %splat = shufflevector <64 x i8> %mod, <64 x i8> poison, <64 x i32> zeroinitializer247 %shift = shl <64 x i8> %a, %splat248 ret <64 x i8> %shift249}250 251;252; Constant Shifts253;254 255define <8 x i64> @constant_shift_v8i64(<8 x i64> %a) nounwind {256; ALL-LABEL: constant_shift_v8i64:257; ALL: # %bb.0:258; ALL-NEXT: vpsllvq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0259; ALL-NEXT: retq260 %shift = shl <8 x i64> %a, <i64 1, i64 7, i64 31, i64 62, i64 1, i64 7, i64 31, i64 62>261 ret <8 x i64> %shift262}263 264define <16 x i32> @constant_shift_v16i32(<16 x i32> %a) nounwind {265; ALL-LABEL: constant_shift_v16i32:266; ALL: # %bb.0:267; ALL-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0268; ALL-NEXT: retq269 %shift = shl <16 x i32> %a, <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 8, i32 7, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 8, i32 7>270 ret <16 x i32> %shift271}272 273define <32 x i16> @constant_shift_v32i16(<32 x i16> %a) nounwind {274; AVX512DQ-LABEL: constant_shift_v32i16:275; AVX512DQ: # %bb.0:276; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm1277; AVX512DQ-NEXT: vmovdqa {{.*#+}} ymm2 = [1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768]278; AVX512DQ-NEXT: vpmullw %ymm2, %ymm1, %ymm1279; AVX512DQ-NEXT: vpmullw %ymm2, %ymm0, %ymm0280; AVX512DQ-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0281; AVX512DQ-NEXT: retq282;283; AVX512BW-LABEL: constant_shift_v32i16:284; AVX512BW: # %bb.0:285; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0286; AVX512BW-NEXT: retq287 %shift = shl <32 x i16> %a, <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15, i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8, i16 9, i16 10, i16 11, i16 12, i16 13, i16 14, i16 15>288 ret <32 x i16> %shift289}290 291define <32 x i16> @constant_shift_v32i16_pairs(<32 x i16> %a) nounwind {292; AVX512DQ-LABEL: constant_shift_v32i16_pairs:293; AVX512DQ: # %bb.0:294; AVX512DQ-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0295; AVX512DQ-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0296; AVX512DQ-NEXT: retq297;298; AVX512BW-LABEL: constant_shift_v32i16_pairs:299; AVX512BW: # %bb.0:300; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0301; AVX512BW-NEXT: retq302 %shift = shl <32 x i16> %a, <i16 0, i16 0, i16 1, i16 1, i16 3, i16 3, i16 2, i16 2, i16 6, i16 6, i16 7, i16 7, i16 5, i16 5, i16 4, i16 4, i16 12, i16 12, i16 13, i16 13, i16 15, i16 15, i16 14, i16 14, i16 10, i16 10, i16 11, i16 11, i16 9, i16 9, i16 8, i16 8>303 ret <32 x i16> %shift304}305 306define <64 x i8> @constant_shift_v64i8(<64 x i8> %a) nounwind {307; AVX512DQ-LABEL: constant_shift_v64i8:308; AVX512DQ: # %bb.0:309; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm1310; AVX512DQ-NEXT: vbroadcasti128 {{.*#+}} ymm2 = [1,2,4,8,16,32,64,128,128,64,32,16,8,4,2,1,1,2,4,8,16,32,64,128,128,64,32,16,8,4,2,1]311; AVX512DQ-NEXT: # ymm2 = mem[0,1,0,1]312; AVX512DQ-NEXT: vpmullw %ymm2, %ymm1, %ymm3313; AVX512DQ-NEXT: vpmullw %ymm2, %ymm0, %ymm2314; AVX512DQ-NEXT: vinserti64x4 $1, %ymm3, %zmm2, %zmm2315; AVX512DQ-NEXT: vbroadcasti128 {{.*#+}} ymm3 = [0,2,0,8,0,32,0,128,0,64,0,16,0,4,0,1,0,2,0,8,0,32,0,128,0,64,0,16,0,4,0,1]316; AVX512DQ-NEXT: # ymm3 = mem[0,1,0,1]317; AVX512DQ-NEXT: vpmaddubsw %ymm3, %ymm0, %ymm0318; AVX512DQ-NEXT: vpsllw $8, %ymm0, %ymm0319; AVX512DQ-NEXT: vpmaddubsw %ymm3, %ymm1, %ymm1320; AVX512DQ-NEXT: vpsllw $8, %ymm1, %ymm1321; AVX512DQ-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0322; AVX512DQ-NEXT: vpternlogd {{.*#+}} zmm0 = zmm0 | (zmm2 & m32bcst)323; AVX512DQ-NEXT: retq324;325; AVX512BW-LABEL: constant_shift_v64i8:326; AVX512BW: # %bb.0:327; AVX512BW-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1 # [1,2,4,8,16,32,64,128,128,64,32,16,8,4,2,1,1,2,4,8,16,32,64,128,128,64,32,16,8,4,2,1,1,2,4,8,16,32,64,128,128,64,32,16,8,4,2,1,1,2,4,8,16,32,64,128,128,64,32,16,8,4,2,1]328; AVX512BW-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [0,2,0,8,0,32,0,128,0,64,0,16,0,4,0,1,0,2,0,8,0,32,0,128,0,64,0,16,0,4,0,1,0,2,0,8,0,32,0,128,0,64,0,16,0,4,0,1,0,2,0,8,0,32,0,128,0,64,0,16,0,4,0,1]329; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm0330; AVX512BW-NEXT: vpternlogd {{.*#+}} zmm0 = zmm0 | (zmm1 & m32bcst)331; AVX512BW-NEXT: retq332 %shift = shl <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>333 ret <64 x i8> %shift334}335 336define <64 x i8> @constant_shift_v64i8_pairs(<64 x i8> %a) nounwind {337; AVX512DQ-LABEL: constant_shift_v64i8_pairs:338; AVX512DQ: # %bb.0:339; AVX512DQ-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1 # [8,128,64,4,128,1,128,2,32,1,16,128,64,2,16,1]340; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm0341; AVX512DQ-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # [64,8,16,2,4,64,16,2,2,32,32,64,4,64,16,16]342; AVX512DQ-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0343; AVX512DQ-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0344; AVX512DQ-NEXT: retq345;346; AVX512BW-LABEL: constant_shift_v64i8_pairs:347; AVX512BW: # %bb.0:348; AVX512BW-NEXT: vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0349; AVX512BW-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0350; AVX512BW-NEXT: retq351 %shift = shl <64 x i8> %a, <i8 3, i8 3, i8 7, i8 7, i8 6, i8 6, i8 2, i8 2, i8 7, i8 7, i8 0, i8 0, i8 7, i8 7, i8 1, i8 1, i8 5, i8 5, i8 0, i8 0, i8 4, i8 4, i8 7, i8 7, i8 6, i8 6, i8 1, i8 1, i8 4, i8 4, i8 0, i8 0, i8 6, i8 6, i8 3, i8 3, i8 4, i8 4, i8 1, i8 1, i8 2, i8 2, i8 6, i8 6, i8 4, i8 4, i8 1, i8 1, i8 1, i8 1, i8 5, i8 5, i8 5, i8 5, i8 6, i8 6, i8 2, i8 2, i8 6, i8 6, i8 4, i8 4, i8 4, i8 4>352 ret <64 x i8> %shift353}354 355define <64 x i8> @constant_shift_v64i8_quads(<64 x i8> %a) nounwind {356; ALL-LABEL: constant_shift_v64i8_quads:357; ALL: # %bb.0:358; ALL-NEXT: vpsllvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0359; ALL-NEXT: vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0360; ALL-NEXT: retq361 %shift = shl <64 x i8> %a, <i8 0, i8 0, i8 0, i8 0, i8 1, i8 1, i8 1, i8 1, i8 3, i8 3, i8 3, i8 3, i8 2, i8 2, i8 2, i8 2, i8 6, i8 6, i8 6, i8 6, i8 7, i8 7, i8 7, i8 7, i8 5, i8 5, i8 5, i8 5, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 4, i8 5, i8 5, i8 5, i8 5, i8 7, i8 7, i8 7, i8 7, i8 6, i8 6, i8 6, i8 6, i8 2, i8 2, i8 2, i8 2, i8 3, i8 3, i8 3, i8 3, i8 1, i8 1, i8 1, i8 1, i8 0, i8 0, i8 0, i8 0>362 ret <64 x i8> %shift363}364 365;366; Uniform Constant Shifts367;368 369define <8 x i64> @splatconstant_shift_v8i64(<8 x i64> %a) nounwind {370; ALL-LABEL: splatconstant_shift_v8i64:371; ALL: # %bb.0:372; ALL-NEXT: vpsllq $7, %zmm0, %zmm0373; ALL-NEXT: retq374 %shift = shl <8 x i64> %a, <i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7, i64 7>375 ret <8 x i64> %shift376}377 378define <16 x i32> @splatconstant_shift_v16i32(<16 x i32> %a) nounwind {379; ALL-LABEL: splatconstant_shift_v16i32:380; ALL: # %bb.0:381; ALL-NEXT: vpslld $5, %zmm0, %zmm0382; ALL-NEXT: retq383 %shift = shl <16 x i32> %a, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>384 ret <16 x i32> %shift385}386 387define <32 x i16> @splatconstant_shift_v32i16(<32 x i16> %a) nounwind {388; AVX512DQ-LABEL: splatconstant_shift_v32i16:389; AVX512DQ: # %bb.0:390; AVX512DQ-NEXT: vpsllw $3, %ymm0, %ymm1391; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm0392; AVX512DQ-NEXT: vpsllw $3, %ymm0, %ymm0393; AVX512DQ-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0394; AVX512DQ-NEXT: retq395;396; AVX512BW-LABEL: splatconstant_shift_v32i16:397; AVX512BW: # %bb.0:398; AVX512BW-NEXT: vpsllw $3, %zmm0, %zmm0399; AVX512BW-NEXT: retq400 %shift = shl <32 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>401 ret <32 x i16> %shift402}403 404define <64 x i8> @splatconstant_shift_v64i8(<64 x i8> %a) nounwind {405; AVX512DQ-LABEL: splatconstant_shift_v64i8:406; AVX512DQ: # %bb.0:407; AVX512DQ-NEXT: vpsllw $3, %ymm0, %ymm1408; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm0409; AVX512DQ-NEXT: vpsllw $3, %ymm0, %ymm0410; AVX512DQ-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0411; AVX512DQ-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0412; AVX512DQ-NEXT: retq413;414; AVX512BW-LABEL: splatconstant_shift_v64i8:415; AVX512BW: # %bb.0:416; AVX512BW-NEXT: vpsllw $3, %zmm0, %zmm0417; AVX512BW-NEXT: vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0418; AVX512BW-NEXT: retq419 %shift = shl <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>420 ret <64 x i8> %shift421}422