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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=SSE3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ssse3 | FileCheck %s --check-prefix=SSE4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.1 | FileCheck %s --check-prefix=SSE5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX6; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX7 8define <4 x i32> @load_zmov_4i32_to_0zzz(ptr%ptr) {9; SSE-LABEL: load_zmov_4i32_to_0zzz:10; SSE: # %bb.0: # %entry11; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero12; SSE-NEXT: retq13;14; AVX-LABEL: load_zmov_4i32_to_0zzz:15; AVX: # %bb.0: # %entry16; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero17; AVX-NEXT: retq18entry:19 %X = load <4 x i32>, ptr %ptr20 %Y = shufflevector <4 x i32> %X, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 4, i32 4, i32 4>21 ret <4 x i32>%Y22}23 24define <2 x i64> @load_zmov_2i64_to_0z(ptr%ptr) {25; SSE-LABEL: load_zmov_2i64_to_0z:26; SSE: # %bb.0: # %entry27; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero28; SSE-NEXT: retq29;30; AVX-LABEL: load_zmov_2i64_to_0z:31; AVX: # %bb.0: # %entry32; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero33; AVX-NEXT: retq34entry:35 %X = load <2 x i64>, ptr %ptr36 %Y = shufflevector <2 x i64> %X, <2 x i64> zeroinitializer, <2 x i32> <i32 0, i32 2>37 ret <2 x i64>%Y38}39 40define <4 x i32> @load_zmov_4i32_to_0zzz_volatile(ptr%ptr) {41; SSE-LABEL: load_zmov_4i32_to_0zzz_volatile:42; SSE: # %bb.0: # %entry43; SSE-NEXT: movaps (%rdi), %xmm144; SSE-NEXT: xorps %xmm0, %xmm045; SSE-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]46; SSE-NEXT: retq47;48; AVX-LABEL: load_zmov_4i32_to_0zzz_volatile:49; AVX: # %bb.0: # %entry50; AVX-NEXT: vmovaps (%rdi), %xmm051; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm152; AVX-NEXT: vmovss {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3]53; AVX-NEXT: retq54entry:55 %X = load volatile <4 x i32>, ptr %ptr56 %Y = shufflevector <4 x i32> %X, <4 x i32> zeroinitializer, <4 x i32> <i32 0, i32 4, i32 4, i32 4>57 ret <4 x i32>%Y58}59 60define <2 x i64> @load_zmov_2i64_to_0z_volatile(ptr%ptr) {61; SSE-LABEL: load_zmov_2i64_to_0z_volatile:62; SSE: # %bb.0: # %entry63; SSE-NEXT: movdqa (%rdi), %xmm064; SSE-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero65; SSE-NEXT: retq66;67; AVX-LABEL: load_zmov_2i64_to_0z_volatile:68; AVX: # %bb.0: # %entry69; AVX-NEXT: vmovdqa (%rdi), %xmm070; AVX-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero71; AVX-NEXT: retq72entry:73 %X = load volatile <2 x i64>, ptr %ptr74 %Y = shufflevector <2 x i64> %X, <2 x i64> zeroinitializer, <2 x i32> <i32 0, i32 2>75 ret <2 x i64>%Y76}77