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1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=core-avx2 -stop-after finalize-isel -o - %s | FileCheck %s3 4declare void @llvm.masked.store.v16f32.p0(<16 x float>, ptr, i32, <16 x i1>)5declare <16 x float> @llvm.masked.load.v16f32.p0(ptr, i32, <16 x i1>, <16 x float>)6 7define void @test_v16f(<16 x i32> %x) {8 ; CHECK-LABEL: name: test_v16f9 ; CHECK: bb.0.bb:10 ; CHECK-NEXT: liveins: $ymm0, $ymm111 ; CHECK-NEXT: {{ $}}12 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr256 = COPY $ymm113 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm014 ; CHECK-NEXT: [[AVX_SET0_:%[0-9]+]]:vr256 = AVX_SET015 ; CHECK-NEXT: [[VPCMPEQDYrr:%[0-9]+]]:vr256 = VPCMPEQDYrr [[COPY]], [[AVX_SET0_]]16 ; CHECK-NEXT: [[VPCMPEQDYrr1:%[0-9]+]]:vr256 = VPCMPEQDYrr [[COPY1]], [[AVX_SET0_]]17 ; CHECK-NEXT: [[VMASKMOVPSYrm:%[0-9]+]]:vr256 = VMASKMOVPSYrm [[VPCMPEQDYrr1]], %stack.0.stack_input_vec, 1, $noreg, 0, $noreg :: (load unknown-size from %ir.stack_input_vec, align 4)18 ; CHECK-NEXT: [[VMASKMOVPSYrm1:%[0-9]+]]:vr256 = VMASKMOVPSYrm [[VPCMPEQDYrr]], %stack.0.stack_input_vec, 1, $noreg, 32, $noreg :: (load unknown-size from %ir.stack_input_vec + 32, align 4)19 ; CHECK-NEXT: VMASKMOVPSYmr %stack.1.stack_output_vec, 1, $noreg, 32, $noreg, [[VPCMPEQDYrr]], killed [[VMASKMOVPSYrm1]] :: (store unknown-size into %ir.stack_output_vec + 32, align 4)20 ; CHECK-NEXT: VMASKMOVPSYmr %stack.1.stack_output_vec, 1, $noreg, 0, $noreg, [[VPCMPEQDYrr1]], killed [[VMASKMOVPSYrm]] :: (store unknown-size into %ir.stack_output_vec, align 4)21 ; CHECK-NEXT: RET 022bb:23 %stack_input_vec = alloca <16 x float>, align 6424 %stack_output_vec = alloca <16 x float>, align 6425 %mask = icmp eq <16 x i32> %x, zeroinitializer26 %masked_loaded_vec = call <16 x float> @llvm.masked.load.v16f32.p0(ptr nonnull %stack_input_vec, i32 4, <16 x i1> %mask, <16 x float> undef)27 call void @llvm.masked.store.v16f32.p0(<16 x float> %masked_loaded_vec, ptr nonnull %stack_output_vec, i32 4, <16 x i1> %mask)28 ret void29}30 31declare void @llvm.masked.store.v8f64.p0(<8 x double>, ptr, i32, <8 x i1>)32declare <8 x double> @llvm.masked.load.v8f64.p0(ptr, i32, <8 x i1>, <8 x double>)33 34define void @test_v8d(<8 x i64> %x) {35 ; CHECK-LABEL: name: test_v8d36 ; CHECK: bb.0.bb:37 ; CHECK-NEXT: liveins: $ymm0, $ymm138 ; CHECK-NEXT: {{ $}}39 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr256 = COPY $ymm140 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm041 ; CHECK-NEXT: [[AVX_SET0_:%[0-9]+]]:vr256 = AVX_SET042 ; CHECK-NEXT: [[VPCMPEQQYrr:%[0-9]+]]:vr256 = VPCMPEQQYrr [[COPY]], [[AVX_SET0_]]43 ; CHECK-NEXT: [[VPCMPEQQYrr1:%[0-9]+]]:vr256 = VPCMPEQQYrr [[COPY1]], [[AVX_SET0_]]44 ; CHECK-NEXT: [[VMASKMOVPDYrm:%[0-9]+]]:vr256 = VMASKMOVPDYrm [[VPCMPEQQYrr1]], %stack.0.stack_input_vec, 1, $noreg, 0, $noreg :: (load unknown-size from %ir.stack_input_vec, align 4)45 ; CHECK-NEXT: [[VMASKMOVPDYrm1:%[0-9]+]]:vr256 = VMASKMOVPDYrm [[VPCMPEQQYrr]], %stack.0.stack_input_vec, 1, $noreg, 32, $noreg :: (load unknown-size from %ir.stack_input_vec + 32, align 4)46 ; CHECK-NEXT: VMASKMOVPDYmr %stack.1.stack_output_vec, 1, $noreg, 32, $noreg, [[VPCMPEQQYrr]], killed [[VMASKMOVPDYrm1]] :: (store unknown-size into %ir.stack_output_vec + 32, align 4)47 ; CHECK-NEXT: VMASKMOVPDYmr %stack.1.stack_output_vec, 1, $noreg, 0, $noreg, [[VPCMPEQQYrr1]], killed [[VMASKMOVPDYrm]] :: (store unknown-size into %ir.stack_output_vec, align 4)48 ; CHECK-NEXT: RET 049bb:50 %stack_input_vec = alloca <8 x double>, align 6451 %stack_output_vec = alloca <8 x double>, align 6452 %mask = icmp eq <8 x i64> %x, zeroinitializer53 %masked_loaded_vec = call <8 x double> @llvm.masked.load.v8f64.p0(ptr nonnull %stack_input_vec, i32 4, <8 x i1> %mask, <8 x double> undef)54 call void @llvm.masked.store.v8f64.p0(<8 x double> %masked_loaded_vec, ptr nonnull %stack_output_vec, i32 4, <8 x i1> %mask)55 ret void56}57 58define <2 x double> @mload_constmask_v2f64(ptr %addr, <2 x double> %dst) {59 ; CHECK-LABEL: name: mload_constmask_v2f6460 ; CHECK: bb.0 (%ir-block.0):61 ; CHECK-NEXT: liveins: $rdi, $xmm062 ; CHECK-NEXT: {{ $}}63 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm064 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi65 ; CHECK-NEXT: [[VMOVHPDrm:%[0-9]+]]:vr128 = VMOVHPDrm [[COPY]], [[COPY1]], 1, $noreg, 8, $noreg :: (load (s64) from %ir.addr + 8, align 4)66 ; CHECK-NEXT: $xmm0 = COPY [[VMOVHPDrm]]67 ; CHECK-NEXT: RET 0, $xmm068 %res = call <2 x double> @llvm.masked.load.v2f64.p0(ptr %addr, i32 4, <2 x i1> <i1 0, i1 1>, <2 x double> %dst)69 ret <2 x double> %res70}71 72define void @one_mask_bit_set2(ptr %addr, <4 x float> %val) {73 ; CHECK-LABEL: name: one_mask_bit_set274 ; CHECK: bb.0 (%ir-block.0):75 ; CHECK-NEXT: liveins: $rdi, $xmm076 ; CHECK-NEXT: {{ $}}77 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr128 = COPY $xmm078 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdi79 ; CHECK-NEXT: VEXTRACTPSmri [[COPY1]], 1, $noreg, 8, $noreg, [[COPY]], 2 :: (store (s32) into %ir.addr + 8)80 ; CHECK-NEXT: RET 081 call void @llvm.masked.store.v4f32.p0(<4 x float> %val, ptr %addr, i32 4, <4 x i1><i1 false, i1 false, i1 true, i1 false>)82 ret void83}84 85declare <2 x double> @llvm.masked.load.v2f64.p0(ptr, i32, <2 x i1>, <2 x double>)86declare void @llvm.masked.store.v4f32.p0(<4 x float>, ptr, i32, <4 x i1>)87