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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=sse4.1 | FileCheck %s --check-prefix=SSE3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=AVX4 5define <2 x i64> @PR25554(<2 x i64> %v0, <2 x i64> %v1) {6; SSE-LABEL: PR25554:7; SSE: # %bb.0:8; SSE-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm09; SSE-NEXT: paddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm010; SSE-NEXT: retq11;12; AVX-LABEL: PR25554:13; AVX: # %bb.0:14; AVX-NEXT: vpor {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm015; AVX-NEXT: vpaddq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm016; AVX-NEXT: retq17 18 %c1 = or <2 x i64> %v0, <i64 1, i64 0>19 %c2 = add <2 x i64> %c1, <i64 0, i64 1>20 ret <2 x i64> %c221}22 23