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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver4 | FileCheck %s --check-prefixes=CHECK,AVX512VL-VNNI3; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=znver5 | FileCheck %s --check-prefixes=CHECK,AVX-VNNI4; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vnni,+fast-dpwssd | FileCheck %s --check-prefixes=CHECK,AVX512-VNNI5; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vnni,+avx512vl,+fast-dpwssd | FileCheck %s --check-prefixes=CHECK,AVX512VL-VNNI6 7define <16 x i32> @vpdpwssd_test(<16 x i32> %0, <16 x i32> %1, <16 x i32> %2) {8; CHECK-LABEL: vpdpwssd_test:9; CHECK: # %bb.0:10; CHECK-NEXT: vpdpwssd %zmm2, %zmm1, %zmm011; CHECK-NEXT: retq12 %4 = tail call <16 x i32> @llvm.x86.avx512.vpdpwssd.512(<16 x i32> %0, <16 x i32> %1, <16 x i32> %2)13 ret <16 x i32> %414}15 16define <16 x i32> @vpdpwssd_v16i32_accumulate(<32 x i16> %a0, <32 x i16> %a1, <16 x i32> %a2) {17; CHECK-LABEL: vpdpwssd_v16i32_accumulate:18; CHECK: # %bb.0:19; CHECK-NEXT: vpdpwssd %zmm1, %zmm0, %zmm220; CHECK-NEXT: vmovdqa64 %zmm2, %zmm021; CHECK-NEXT: retq22 %x0 = sext <32 x i16> %a0 to <32 x i32>23 %x1 = sext <32 x i16> %a1 to <32 x i32>24 %m = mul nsw <32 x i32> %x0, %x125 %lo = shufflevector <32 x i32> %m, <32 x i32> poison, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>26 %hi = shufflevector <32 x i32> %m, <32 x i32> poison, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>27 %r0 = add <16 x i32> %lo, %a228 %r1 = add <16 x i32> %r0, %hi29 ret <16 x i32> %r130}31 32define <8 x i32> @vpdpwssd_v8i32_accumulate(<16 x i16> %a0, <16 x i16> %a1, <8 x i32> %a2) {33; AVX512VL-VNNI-LABEL: vpdpwssd_v8i32_accumulate:34; AVX512VL-VNNI: # %bb.0:35; AVX512VL-VNNI-NEXT: vpdpwssd %ymm1, %ymm0, %ymm236; AVX512VL-VNNI-NEXT: vmovdqa %ymm2, %ymm037; AVX512VL-VNNI-NEXT: retq38;39; AVX-VNNI-LABEL: vpdpwssd_v8i32_accumulate:40; AVX-VNNI: # %bb.0:41; AVX-VNNI-NEXT: {vex} vpdpwssd %ymm1, %ymm0, %ymm242; AVX-VNNI-NEXT: vmovdqa %ymm2, %ymm043; AVX-VNNI-NEXT: retq44;45; AVX512-VNNI-LABEL: vpdpwssd_v8i32_accumulate:46; AVX512-VNNI: # %bb.0:47; AVX512-VNNI-NEXT: vpmaddwd %ymm1, %ymm0, %ymm048; AVX512-VNNI-NEXT: vpaddd %ymm2, %ymm0, %ymm049; AVX512-VNNI-NEXT: retq50 %x0 = sext <16 x i16> %a0 to <16 x i32>51 %x1 = sext <16 x i16> %a1 to <16 x i32>52 %m = mul nsw <16 x i32> %x0, %x153 %lo = shufflevector <16 x i32> %m, <16 x i32> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>54 %hi = shufflevector <16 x i32> %m, <16 x i32> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>55 %r0 = add <8 x i32> %hi, %a256 %r1 = add <8 x i32> %lo, %r057 ret <8 x i32> %r158}59 60define <4 x i32> @vpdpwssd_v4i32_accumulate(<8 x i16> %a0, <8 x i16> %a1, <4 x i32> %a2) {61; AVX512VL-VNNI-LABEL: vpdpwssd_v4i32_accumulate:62; AVX512VL-VNNI: # %bb.0:63; AVX512VL-VNNI-NEXT: vpdpwssd %xmm1, %xmm0, %xmm264; AVX512VL-VNNI-NEXT: vmovdqa %xmm2, %xmm065; AVX512VL-VNNI-NEXT: retq66;67; AVX-VNNI-LABEL: vpdpwssd_v4i32_accumulate:68; AVX-VNNI: # %bb.0:69; AVX-VNNI-NEXT: {vex} vpdpwssd %xmm1, %xmm0, %xmm270; AVX-VNNI-NEXT: vmovdqa %xmm2, %xmm071; AVX-VNNI-NEXT: retq72;73; AVX512-VNNI-LABEL: vpdpwssd_v4i32_accumulate:74; AVX512-VNNI: # %bb.0:75; AVX512-VNNI-NEXT: vpmaddwd %xmm1, %xmm0, %xmm076; AVX512-VNNI-NEXT: vpaddd %xmm2, %xmm0, %xmm077; AVX512-VNNI-NEXT: retq78 %x0 = sext <8 x i16> %a0 to <8 x i32>79 %x1 = sext <8 x i16> %a1 to <8 x i32>80 %m = mul nsw <8 x i32> %x0, %x181 %lo = shufflevector <8 x i32> %m, <8 x i32> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>82 %hi = shufflevector <8 x i32> %m, <8 x i32> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>83 %r0 = add <4 x i32> %lo, %a284 %r1 = add <4 x i32> %hi, %r085 ret <4 x i32> %r186}87