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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=SSE,SSE23; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse4.2 | FileCheck %s --check-prefixes=SSE,SSE424; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX15; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX26; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vl | FileCheck %s --check-prefixes=AVX512,AVX512F7; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vl,+avx512dq,+avx512bw | FileCheck %s --check-prefixes=AVX512,AVX512DQBW8 9; PR2892510 11define <4 x i32> @test1(<4 x i1> %cond, <4 x i32> %x) {12; SSE-LABEL: test1:13; SSE: # %bb.0:14; SSE-NEXT: pslld $31, %xmm015; SSE-NEXT: psrad $31, %xmm016; SSE-NEXT: pandn %xmm1, %xmm017; SSE-NEXT: retq18;19; AVX-LABEL: test1:20; AVX: # %bb.0:21; AVX-NEXT: vpslld $31, %xmm0, %xmm022; AVX-NEXT: vpsrad $31, %xmm0, %xmm023; AVX-NEXT: vpandn %xmm1, %xmm0, %xmm024; AVX-NEXT: retq25;26; AVX512F-LABEL: test1:27; AVX512F: # %bb.0:28; AVX512F-NEXT: vpslld $31, %xmm0, %xmm029; AVX512F-NEXT: vptestnmd %xmm0, %xmm0, %k130; AVX512F-NEXT: vmovdqa32 %xmm1, %xmm0 {%k1} {z}31; AVX512F-NEXT: retq32;33; AVX512DQBW-LABEL: test1:34; AVX512DQBW: # %bb.0:35; AVX512DQBW-NEXT: vpslld $31, %xmm0, %xmm036; AVX512DQBW-NEXT: vpmovd2m %xmm0, %k037; AVX512DQBW-NEXT: knotw %k0, %k138; AVX512DQBW-NEXT: vmovdqa32 %xmm1, %xmm0 {%k1} {z}39; AVX512DQBW-NEXT: retq40 %r = select <4 x i1> %cond, <4 x i32> zeroinitializer, <4 x i32> %x41 ret <4 x i32> %r42}43 44define <4 x i32> @test2(<4 x float> %a, <4 x float> %b, <4 x i32> %x) {45; SSE-LABEL: test2:46; SSE: # %bb.0:47; SSE-NEXT: cmpneqps %xmm1, %xmm048; SSE-NEXT: andps %xmm2, %xmm049; SSE-NEXT: retq50;51; AVX-LABEL: test2:52; AVX: # %bb.0:53; AVX-NEXT: vcmpneqps %xmm1, %xmm0, %xmm054; AVX-NEXT: vandps %xmm2, %xmm0, %xmm055; AVX-NEXT: retq56;57; AVX512-LABEL: test2:58; AVX512: # %bb.0:59; AVX512-NEXT: vcmpneqps %xmm1, %xmm0, %k160; AVX512-NEXT: vmovdqa32 %xmm2, %xmm0 {%k1} {z}61; AVX512-NEXT: retq62 %cond = fcmp oeq <4 x float> %a, %b63 %r = select <4 x i1> %cond, <4 x i32> zeroinitializer, <4 x i32> %x64 ret <4 x i32> %r65}66 67define float @fsel_zero_false_val(float %a, float %b, float %x) {68; SSE-LABEL: fsel_zero_false_val:69; SSE: # %bb.0:70; SSE-NEXT: cmpeqss %xmm1, %xmm071; SSE-NEXT: andps %xmm2, %xmm072; SSE-NEXT: retq73;74; AVX-LABEL: fsel_zero_false_val:75; AVX: # %bb.0:76; AVX-NEXT: vcmpeqss %xmm1, %xmm0, %xmm077; AVX-NEXT: vandps %xmm2, %xmm0, %xmm078; AVX-NEXT: retq79;80; AVX512-LABEL: fsel_zero_false_val:81; AVX512: # %bb.0:82; AVX512-NEXT: vcmpeqss %xmm1, %xmm0, %k183; AVX512-NEXT: vmovss %xmm2, %xmm2, %xmm0 {%k1} {z}84; AVX512-NEXT: retq85 %cond = fcmp oeq float %a, %b86 %r = select i1 %cond, float %x, float 0.087 ret float %r88}89 90define float @fsel_zero_true_val(float %a, float %b, float %x) {91; SSE-LABEL: fsel_zero_true_val:92; SSE: # %bb.0:93; SSE-NEXT: cmpeqss %xmm1, %xmm094; SSE-NEXT: andnps %xmm2, %xmm095; SSE-NEXT: retq96;97; AVX-LABEL: fsel_zero_true_val:98; AVX: # %bb.0:99; AVX-NEXT: vcmpeqss %xmm1, %xmm0, %xmm0100; AVX-NEXT: vandnps %xmm2, %xmm0, %xmm0101; AVX-NEXT: retq102;103; AVX512-LABEL: fsel_zero_true_val:104; AVX512: # %bb.0:105; AVX512-NEXT: vcmpeqss %xmm1, %xmm0, %k1106; AVX512-NEXT: vxorps %xmm0, %xmm0, %xmm0107; AVX512-NEXT: vmovss %xmm0, %xmm2, %xmm2 {%k1}108; AVX512-NEXT: vmovaps %xmm2, %xmm0109; AVX512-NEXT: retq110 %cond = fcmp oeq float %a, %b111 %r = select i1 %cond, float 0.0, float %x112 ret float %r113}114 115define double @fsel_nonzero_false_val(double %x, double %y, double %z) {116; SSE2-LABEL: fsel_nonzero_false_val:117; SSE2: # %bb.0:118; SSE2-NEXT: cmpeqsd %xmm1, %xmm0119; SSE2-NEXT: andpd %xmm0, %xmm2120; SSE2-NEXT: movsd {{.*#+}} xmm1 = [4.2E+1,0.0E+0]121; SSE2-NEXT: andnpd %xmm1, %xmm0122; SSE2-NEXT: orpd %xmm2, %xmm0123; SSE2-NEXT: retq124;125; SSE42-LABEL: fsel_nonzero_false_val:126; SSE42: # %bb.0:127; SSE42-NEXT: cmpeqsd %xmm1, %xmm0128; SSE42-NEXT: movapd {{.*#+}} xmm1 = [4.2E+1,4.2E+1]129; SSE42-NEXT: blendvpd %xmm0, %xmm2, %xmm1130; SSE42-NEXT: movapd %xmm1, %xmm0131; SSE42-NEXT: retq132;133; AVX-LABEL: fsel_nonzero_false_val:134; AVX: # %bb.0:135; AVX-NEXT: vcmpeqsd %xmm1, %xmm0, %xmm0136; AVX-NEXT: vmovddup {{.*#+}} xmm1 = [4.2E+1,4.2E+1]137; AVX-NEXT: # xmm1 = mem[0,0]138; AVX-NEXT: vblendvpd %xmm0, %xmm2, %xmm1, %xmm0139; AVX-NEXT: retq140;141; AVX512-LABEL: fsel_nonzero_false_val:142; AVX512: # %bb.0:143; AVX512-NEXT: vcmpeqsd %xmm1, %xmm0, %k1144; AVX512-NEXT: vmovsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]145; AVX512-NEXT: vmovsd %xmm2, %xmm0, %xmm0 {%k1}146; AVX512-NEXT: retq147 %cond = fcmp oeq double %x, %y148 %r = select i1 %cond, double %z, double 42.0149 ret double %r150}151 152define double @fsel_nonzero_true_val(double %x, double %y, double %z) {153; SSE2-LABEL: fsel_nonzero_true_val:154; SSE2: # %bb.0:155; SSE2-NEXT: cmpeqsd %xmm1, %xmm0156; SSE2-NEXT: movsd {{.*#+}} xmm1 = [4.2E+1,0.0E+0]157; SSE2-NEXT: andpd %xmm0, %xmm1158; SSE2-NEXT: andnpd %xmm2, %xmm0159; SSE2-NEXT: orpd %xmm1, %xmm0160; SSE2-NEXT: retq161;162; SSE42-LABEL: fsel_nonzero_true_val:163; SSE42: # %bb.0:164; SSE42-NEXT: cmpeqsd %xmm1, %xmm0165; SSE42-NEXT: blendvpd %xmm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2166; SSE42-NEXT: movapd %xmm2, %xmm0167; SSE42-NEXT: retq168;169; AVX-LABEL: fsel_nonzero_true_val:170; AVX: # %bb.0:171; AVX-NEXT: vcmpeqsd %xmm1, %xmm0, %xmm0172; AVX-NEXT: vblendvpd %xmm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm0173; AVX-NEXT: retq174;175; AVX512-LABEL: fsel_nonzero_true_val:176; AVX512: # %bb.0:177; AVX512-NEXT: vcmpeqsd %xmm1, %xmm0, %k1178; AVX512-NEXT: vmovsd {{.*#+}} xmm2 {%k1} = [4.2E+1,0.0E+0]179; AVX512-NEXT: vmovapd %xmm2, %xmm0180; AVX512-NEXT: retq181 %cond = fcmp oeq double %x, %y182 %r = select i1 %cond, double 42.0, double %z183 ret double %r184}185 186define double @fsel_nonzero_constants(double %x, double %y) {187; SSE-LABEL: fsel_nonzero_constants:188; SSE: # %bb.0:189; SSE-NEXT: cmpeqsd %xmm1, %xmm0190; SSE-NEXT: movq %xmm0, %rax191; SSE-NEXT: andl $1, %eax192; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero193; SSE-NEXT: retq194;195; AVX-LABEL: fsel_nonzero_constants:196; AVX: # %bb.0:197; AVX-NEXT: vcmpeqsd %xmm1, %xmm0, %xmm0198; AVX-NEXT: vmovddup {{.*#+}} xmm1 = [4.2E+1,4.2E+1]199; AVX-NEXT: # xmm1 = mem[0,0]200; AVX-NEXT: vblendvpd %xmm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0201; AVX-NEXT: retq202;203; AVX512-LABEL: fsel_nonzero_constants:204; AVX512: # %bb.0:205; AVX512-NEXT: vcmpeqsd %xmm1, %xmm0, %k1206; AVX512-NEXT: vmovsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]207; AVX512-NEXT: vmovsd {{.*#+}} xmm0 {%k1} = [1.2E+1,0.0E+0]208; AVX512-NEXT: retq209 %cond = fcmp oeq double %x, %y210 %r = select i1 %cond, double 12.0, double 42.0211 ret double %r212}213 214define <2 x double> @vsel_nonzero_constants(<2 x double> %x, <2 x double> %y) {215; SSE2-LABEL: vsel_nonzero_constants:216; SSE2: # %bb.0:217; SSE2-NEXT: cmplepd %xmm0, %xmm1218; SSE2-NEXT: movsd {{.*#+}} xmm2 = [4.2E+1,0.0E+0]219; SSE2-NEXT: movapd %xmm1, %xmm0220; SSE2-NEXT: andnpd %xmm2, %xmm0221; SSE2-NEXT: andpd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1222; SSE2-NEXT: orpd %xmm1, %xmm0223; SSE2-NEXT: retq224;225; SSE42-LABEL: vsel_nonzero_constants:226; SSE42: # %bb.0:227; SSE42-NEXT: cmplepd %xmm0, %xmm1228; SSE42-NEXT: movsd {{.*#+}} xmm2 = [4.2E+1,0.0E+0]229; SSE42-NEXT: movapd %xmm1, %xmm0230; SSE42-NEXT: blendvpd %xmm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2231; SSE42-NEXT: movapd %xmm2, %xmm0232; SSE42-NEXT: retq233;234; AVX-LABEL: vsel_nonzero_constants:235; AVX: # %bb.0:236; AVX-NEXT: vcmplepd %xmm0, %xmm1, %xmm0237; AVX-NEXT: vmovsd {{.*#+}} xmm1 = [4.2E+1,0.0E+0]238; AVX-NEXT: vblendvpd %xmm0, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0239; AVX-NEXT: retq240;241; AVX512-LABEL: vsel_nonzero_constants:242; AVX512: # %bb.0:243; AVX512-NEXT: vcmplepd %xmm0, %xmm1, %k1244; AVX512-NEXT: vmovsd {{.*#+}} xmm0 = [4.2E+1,0.0E+0]245; AVX512-NEXT: vmovapd {{.*#+}} xmm0 {%k1} = [1.2E+1,-1.0E+0]246; AVX512-NEXT: retq247 %cond = fcmp oge <2 x double> %x, %y248 %r = select <2 x i1> %cond, <2 x double> <double 12.0, double -1.0>, <2 x double> <double 42.0, double 0.0>249 ret <2 x double> %r250}251 252define <16 x i8> @signbit_mask_v16i8(<16 x i8> %a, <16 x i8> %b) {253; SSE-LABEL: signbit_mask_v16i8:254; SSE: # %bb.0:255; SSE-NEXT: pxor %xmm2, %xmm2256; SSE-NEXT: pcmpgtb %xmm0, %xmm2257; SSE-NEXT: pand %xmm1, %xmm2258; SSE-NEXT: movdqa %xmm2, %xmm0259; SSE-NEXT: retq260;261; AVX-LABEL: signbit_mask_v16i8:262; AVX: # %bb.0:263; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2264; AVX-NEXT: vpcmpgtb %xmm0, %xmm2, %xmm0265; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0266; AVX-NEXT: retq267;268; AVX512-LABEL: signbit_mask_v16i8:269; AVX512: # %bb.0:270; AVX512-NEXT: vpxor %xmm2, %xmm2, %xmm2271; AVX512-NEXT: vpcmpgtb %xmm0, %xmm2, %xmm0272; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0273; AVX512-NEXT: retq274 %cond = icmp slt <16 x i8> %a, zeroinitializer275 %r = select <16 x i1> %cond, <16 x i8> %b, <16 x i8> zeroinitializer276 ret <16 x i8> %r277}278 279define <8 x i16> @signbit_mask_v8i16(<8 x i16> %a, <8 x i16> %b) {280; SSE-LABEL: signbit_mask_v8i16:281; SSE: # %bb.0:282; SSE-NEXT: psraw $15, %xmm0283; SSE-NEXT: pand %xmm1, %xmm0284; SSE-NEXT: retq285;286; AVX-LABEL: signbit_mask_v8i16:287; AVX: # %bb.0:288; AVX-NEXT: vpsraw $15, %xmm0, %xmm0289; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0290; AVX-NEXT: retq291;292; AVX512-LABEL: signbit_mask_v8i16:293; AVX512: # %bb.0:294; AVX512-NEXT: vpsraw $15, %xmm0, %xmm0295; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0296; AVX512-NEXT: retq297 %cond = icmp slt <8 x i16> %a, zeroinitializer298 %r = select <8 x i1> %cond, <8 x i16> %b, <8 x i16> zeroinitializer299 ret <8 x i16> %r300}301 302define <4 x i32> @signbit_mask_v4i32(<4 x i32> %a, <4 x i32> %b) {303; SSE-LABEL: signbit_mask_v4i32:304; SSE: # %bb.0:305; SSE-NEXT: psrad $31, %xmm0306; SSE-NEXT: pand %xmm1, %xmm0307; SSE-NEXT: retq308;309; AVX-LABEL: signbit_mask_v4i32:310; AVX: # %bb.0:311; AVX-NEXT: vpsrad $31, %xmm0, %xmm0312; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0313; AVX-NEXT: retq314;315; AVX512-LABEL: signbit_mask_v4i32:316; AVX512: # %bb.0:317; AVX512-NEXT: vpsrad $31, %xmm0, %xmm0318; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0319; AVX512-NEXT: retq320 %cond = icmp slt <4 x i32> %a, zeroinitializer321 %r = select <4 x i1> %cond, <4 x i32> %b, <4 x i32> zeroinitializer322 ret <4 x i32> %r323}324 325define <2 x i64> @signbit_mask_v2i64(<2 x i64> %a, <2 x i64> %b) {326; SSE2-LABEL: signbit_mask_v2i64:327; SSE2: # %bb.0:328; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]329; SSE2-NEXT: psrad $31, %xmm0330; SSE2-NEXT: pand %xmm1, %xmm0331; SSE2-NEXT: retq332;333; SSE42-LABEL: signbit_mask_v2i64:334; SSE42: # %bb.0:335; SSE42-NEXT: pxor %xmm2, %xmm2336; SSE42-NEXT: pcmpgtq %xmm0, %xmm2337; SSE42-NEXT: pand %xmm1, %xmm2338; SSE42-NEXT: movdqa %xmm2, %xmm0339; SSE42-NEXT: retq340;341; AVX-LABEL: signbit_mask_v2i64:342; AVX: # %bb.0:343; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2344; AVX-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm0345; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0346; AVX-NEXT: retq347;348; AVX512-LABEL: signbit_mask_v2i64:349; AVX512: # %bb.0:350; AVX512-NEXT: vpsraq $63, %xmm0, %xmm0351; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0352; AVX512-NEXT: retq353 %cond = icmp slt <2 x i64> %a, zeroinitializer354 %r = select <2 x i1> %cond, <2 x i64> %b, <2 x i64> zeroinitializer355 ret <2 x i64> %r356}357 358; Swap cmp pred and select ops. This is logically equivalent to the above test.359 360define <2 x i64> @signbit_mask_swap_v2i64(<2 x i64> %a, <2 x i64> %b) {361; SSE2-LABEL: signbit_mask_swap_v2i64:362; SSE2: # %bb.0:363; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]364; SSE2-NEXT: psrad $31, %xmm0365; SSE2-NEXT: pand %xmm1, %xmm0366; SSE2-NEXT: retq367;368; SSE42-LABEL: signbit_mask_swap_v2i64:369; SSE42: # %bb.0:370; SSE42-NEXT: pxor %xmm2, %xmm2371; SSE42-NEXT: pcmpgtq %xmm0, %xmm2372; SSE42-NEXT: pand %xmm1, %xmm2373; SSE42-NEXT: movdqa %xmm2, %xmm0374; SSE42-NEXT: retq375;376; AVX-LABEL: signbit_mask_swap_v2i64:377; AVX: # %bb.0:378; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2379; AVX-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm0380; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0381; AVX-NEXT: retq382;383; AVX512-LABEL: signbit_mask_swap_v2i64:384; AVX512: # %bb.0:385; AVX512-NEXT: vpsraq $63, %xmm0, %xmm0386; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0387; AVX512-NEXT: retq388 %cond = icmp sgt <2 x i64> %a, <i64 -1, i64 -1>389 %r = select <2 x i1> %cond, <2 x i64> zeroinitializer, <2 x i64> %b390 ret <2 x i64> %r391}392 393define <32 x i8> @signbit_mask_v32i8(<32 x i8> %a, <32 x i8> %b) {394; SSE-LABEL: signbit_mask_v32i8:395; SSE: # %bb.0:396; SSE-NEXT: pxor %xmm4, %xmm4397; SSE-NEXT: pxor %xmm5, %xmm5398; SSE-NEXT: pcmpgtb %xmm0, %xmm5399; SSE-NEXT: pand %xmm2, %xmm5400; SSE-NEXT: pcmpgtb %xmm1, %xmm4401; SSE-NEXT: pand %xmm3, %xmm4402; SSE-NEXT: movdqa %xmm5, %xmm0403; SSE-NEXT: movdqa %xmm4, %xmm1404; SSE-NEXT: retq405;406; AVX1-LABEL: signbit_mask_v32i8:407; AVX1: # %bb.0:408; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2409; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3410; AVX1-NEXT: vpcmpgtb %xmm2, %xmm3, %xmm2411; AVX1-NEXT: vpcmpgtb %xmm0, %xmm3, %xmm0412; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0413; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0414; AVX1-NEXT: retq415;416; AVX2-LABEL: signbit_mask_v32i8:417; AVX2: # %bb.0:418; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2419; AVX2-NEXT: vpcmpgtb %ymm0, %ymm2, %ymm0420; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0421; AVX2-NEXT: retq422;423; AVX512-LABEL: signbit_mask_v32i8:424; AVX512: # %bb.0:425; AVX512-NEXT: vpxor %xmm2, %xmm2, %xmm2426; AVX512-NEXT: vpcmpgtb %ymm0, %ymm2, %ymm0427; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm0428; AVX512-NEXT: retq429 %cond = icmp slt <32 x i8> %a, zeroinitializer430 %r = select <32 x i1> %cond, <32 x i8> %b, <32 x i8> zeroinitializer431 ret <32 x i8> %r432}433 434define <16 x i16> @signbit_mask_v16i16(<16 x i16> %a, <16 x i16> %b) {435; SSE-LABEL: signbit_mask_v16i16:436; SSE: # %bb.0:437; SSE-NEXT: psraw $15, %xmm0438; SSE-NEXT: pand %xmm2, %xmm0439; SSE-NEXT: psraw $15, %xmm1440; SSE-NEXT: pand %xmm3, %xmm1441; SSE-NEXT: retq442;443; AVX1-LABEL: signbit_mask_v16i16:444; AVX1: # %bb.0:445; AVX1-NEXT: vpsraw $15, %xmm0, %xmm2446; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0447; AVX1-NEXT: vpsraw $15, %xmm0, %xmm0448; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0449; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0450; AVX1-NEXT: retq451;452; AVX2-LABEL: signbit_mask_v16i16:453; AVX2: # %bb.0:454; AVX2-NEXT: vpsraw $15, %ymm0, %ymm0455; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0456; AVX2-NEXT: retq457;458; AVX512-LABEL: signbit_mask_v16i16:459; AVX512: # %bb.0:460; AVX512-NEXT: vpsraw $15, %ymm0, %ymm0461; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm0462; AVX512-NEXT: retq463 %cond = icmp slt <16 x i16> %a, zeroinitializer464 %r = select <16 x i1> %cond, <16 x i16> %b, <16 x i16> zeroinitializer465 ret <16 x i16> %r466}467 468define <8 x i32> @signbit_mask_v8i32(<8 x i32> %a, <8 x i32> %b) {469; SSE-LABEL: signbit_mask_v8i32:470; SSE: # %bb.0:471; SSE-NEXT: psrad $31, %xmm0472; SSE-NEXT: pand %xmm2, %xmm0473; SSE-NEXT: psrad $31, %xmm1474; SSE-NEXT: pand %xmm3, %xmm1475; SSE-NEXT: retq476;477; AVX1-LABEL: signbit_mask_v8i32:478; AVX1: # %bb.0:479; AVX1-NEXT: vpsrad $31, %xmm0, %xmm2480; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0481; AVX1-NEXT: vpsrad $31, %xmm0, %xmm0482; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0483; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0484; AVX1-NEXT: retq485;486; AVX2-LABEL: signbit_mask_v8i32:487; AVX2: # %bb.0:488; AVX2-NEXT: vpsrad $31, %ymm0, %ymm0489; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0490; AVX2-NEXT: retq491;492; AVX512-LABEL: signbit_mask_v8i32:493; AVX512: # %bb.0:494; AVX512-NEXT: vpsrad $31, %ymm0, %ymm0495; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm0496; AVX512-NEXT: retq497 %cond = icmp slt <8 x i32> %a, zeroinitializer498 %r = select <8 x i1> %cond, <8 x i32> %b, <8 x i32> zeroinitializer499 ret <8 x i32> %r500}501 502; Swap cmp pred and select ops. This is logically equivalent to the above test.503 504define <8 x i32> @signbit_mask_swap_v8i32(<8 x i32> %a, <8 x i32> %b) {505; SSE-LABEL: signbit_mask_swap_v8i32:506; SSE: # %bb.0:507; SSE-NEXT: psrad $31, %xmm0508; SSE-NEXT: pand %xmm2, %xmm0509; SSE-NEXT: psrad $31, %xmm1510; SSE-NEXT: pand %xmm3, %xmm1511; SSE-NEXT: retq512;513; AVX1-LABEL: signbit_mask_swap_v8i32:514; AVX1: # %bb.0:515; AVX1-NEXT: vpsrad $31, %xmm0, %xmm2516; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0517; AVX1-NEXT: vpsrad $31, %xmm0, %xmm0518; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0519; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0520; AVX1-NEXT: retq521;522; AVX2-LABEL: signbit_mask_swap_v8i32:523; AVX2: # %bb.0:524; AVX2-NEXT: vpsrad $31, %ymm0, %ymm0525; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0526; AVX2-NEXT: retq527;528; AVX512-LABEL: signbit_mask_swap_v8i32:529; AVX512: # %bb.0:530; AVX512-NEXT: vpsrad $31, %ymm0, %ymm0531; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm0532; AVX512-NEXT: retq533 %cond = icmp sgt <8 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>534 %r = select <8 x i1> %cond, <8 x i32> zeroinitializer, <8 x i32> %b535 ret <8 x i32> %r536}537 538define <4 x i64> @signbit_mask_v4i64(<4 x i64> %a, <4 x i64> %b) {539; SSE2-LABEL: signbit_mask_v4i64:540; SSE2: # %bb.0:541; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]542; SSE2-NEXT: psrad $31, %xmm0543; SSE2-NEXT: pand %xmm2, %xmm0544; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]545; SSE2-NEXT: psrad $31, %xmm1546; SSE2-NEXT: pand %xmm3, %xmm1547; SSE2-NEXT: retq548;549; SSE42-LABEL: signbit_mask_v4i64:550; SSE42: # %bb.0:551; SSE42-NEXT: pxor %xmm4, %xmm4552; SSE42-NEXT: pxor %xmm5, %xmm5553; SSE42-NEXT: pcmpgtq %xmm0, %xmm5554; SSE42-NEXT: pand %xmm2, %xmm5555; SSE42-NEXT: pcmpgtq %xmm1, %xmm4556; SSE42-NEXT: pand %xmm3, %xmm4557; SSE42-NEXT: movdqa %xmm5, %xmm0558; SSE42-NEXT: movdqa %xmm4, %xmm1559; SSE42-NEXT: retq560;561; AVX1-LABEL: signbit_mask_v4i64:562; AVX1: # %bb.0:563; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2564; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3565; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2566; AVX1-NEXT: vpcmpgtq %xmm0, %xmm3, %xmm0567; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0568; AVX1-NEXT: vandps %ymm1, %ymm0, %ymm0569; AVX1-NEXT: retq570;571; AVX2-LABEL: signbit_mask_v4i64:572; AVX2: # %bb.0:573; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2574; AVX2-NEXT: vpcmpgtq %ymm0, %ymm2, %ymm0575; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm0576; AVX2-NEXT: retq577;578; AVX512-LABEL: signbit_mask_v4i64:579; AVX512: # %bb.0:580; AVX512-NEXT: vpsraq $63, %ymm0, %ymm0581; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm0582; AVX512-NEXT: retq583 %cond = icmp slt <4 x i64> %a, zeroinitializer584 %r = select <4 x i1> %cond, <4 x i64> %b, <4 x i64> zeroinitializer585 ret <4 x i64> %r586}587 588define <16 x i8> @signbit_setmask_v16i8(<16 x i8> %a, <16 x i8> %b) {589; SSE-LABEL: signbit_setmask_v16i8:590; SSE: # %bb.0:591; SSE-NEXT: pxor %xmm2, %xmm2592; SSE-NEXT: pcmpgtb %xmm0, %xmm2593; SSE-NEXT: por %xmm1, %xmm2594; SSE-NEXT: movdqa %xmm2, %xmm0595; SSE-NEXT: retq596;597; AVX-LABEL: signbit_setmask_v16i8:598; AVX: # %bb.0:599; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2600; AVX-NEXT: vpcmpgtb %xmm0, %xmm2, %xmm0601; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0602; AVX-NEXT: retq603;604; AVX512-LABEL: signbit_setmask_v16i8:605; AVX512: # %bb.0:606; AVX512-NEXT: vpxor %xmm2, %xmm2, %xmm2607; AVX512-NEXT: vpcmpgtb %xmm0, %xmm2, %xmm0608; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0609; AVX512-NEXT: retq610 %cond = icmp slt <16 x i8> %a, zeroinitializer611 %r = select <16 x i1> %cond, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8> %b612 ret <16 x i8> %r613}614 615; Swap cmp pred and select ops. This is logically equivalent to the above test.616 617define <16 x i8> @signbit_setmask_swap_v16i8(<16 x i8> %a, <16 x i8> %b) {618; SSE-LABEL: signbit_setmask_swap_v16i8:619; SSE: # %bb.0:620; SSE-NEXT: pxor %xmm2, %xmm2621; SSE-NEXT: pcmpgtb %xmm0, %xmm2622; SSE-NEXT: por %xmm1, %xmm2623; SSE-NEXT: movdqa %xmm2, %xmm0624; SSE-NEXT: retq625;626; AVX-LABEL: signbit_setmask_swap_v16i8:627; AVX: # %bb.0:628; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2629; AVX-NEXT: vpcmpgtb %xmm0, %xmm2, %xmm0630; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0631; AVX-NEXT: retq632;633; AVX512-LABEL: signbit_setmask_swap_v16i8:634; AVX512: # %bb.0:635; AVX512-NEXT: vpxor %xmm2, %xmm2, %xmm2636; AVX512-NEXT: vpcmpgtb %xmm0, %xmm2, %xmm0637; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0638; AVX512-NEXT: retq639 %cond = icmp sgt <16 x i8> %a, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>640 %r = select <16 x i1> %cond, <16 x i8> %b, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>641 ret <16 x i8> %r642}643 644define <8 x i16> @signbit_setmask_v8i16(<8 x i16> %a, <8 x i16> %b) {645; SSE-LABEL: signbit_setmask_v8i16:646; SSE: # %bb.0:647; SSE-NEXT: psraw $15, %xmm0648; SSE-NEXT: por %xmm1, %xmm0649; SSE-NEXT: retq650;651; AVX-LABEL: signbit_setmask_v8i16:652; AVX: # %bb.0:653; AVX-NEXT: vpsraw $15, %xmm0, %xmm0654; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0655; AVX-NEXT: retq656;657; AVX512-LABEL: signbit_setmask_v8i16:658; AVX512: # %bb.0:659; AVX512-NEXT: vpsraw $15, %xmm0, %xmm0660; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0661; AVX512-NEXT: retq662 %cond = icmp slt <8 x i16> %a, zeroinitializer663 %r = select <8 x i1> %cond, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <8 x i16> %b664 ret <8 x i16> %r665}666 667define <4 x i32> @signbit_setmask_v4i32(<4 x i32> %a, <4 x i32> %b) {668; SSE-LABEL: signbit_setmask_v4i32:669; SSE: # %bb.0:670; SSE-NEXT: psrad $31, %xmm0671; SSE-NEXT: por %xmm1, %xmm0672; SSE-NEXT: retq673;674; AVX-LABEL: signbit_setmask_v4i32:675; AVX: # %bb.0:676; AVX-NEXT: vpsrad $31, %xmm0, %xmm0677; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0678; AVX-NEXT: retq679;680; AVX512-LABEL: signbit_setmask_v4i32:681; AVX512: # %bb.0:682; AVX512-NEXT: vpsrad $31, %xmm0, %xmm0683; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0684; AVX512-NEXT: retq685 %cond = icmp slt <4 x i32> %a, zeroinitializer686 %r = select <4 x i1> %cond, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %b687 ret <4 x i32> %r688}689 690define <2 x i64> @signbit_setmask_v2i64(<2 x i64> %a, <2 x i64> %b) {691; SSE2-LABEL: signbit_setmask_v2i64:692; SSE2: # %bb.0:693; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]694; SSE2-NEXT: psrad $31, %xmm0695; SSE2-NEXT: por %xmm1, %xmm0696; SSE2-NEXT: retq697;698; SSE42-LABEL: signbit_setmask_v2i64:699; SSE42: # %bb.0:700; SSE42-NEXT: pxor %xmm2, %xmm2701; SSE42-NEXT: pcmpgtq %xmm0, %xmm2702; SSE42-NEXT: por %xmm1, %xmm2703; SSE42-NEXT: movdqa %xmm2, %xmm0704; SSE42-NEXT: retq705;706; AVX-LABEL: signbit_setmask_v2i64:707; AVX: # %bb.0:708; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2709; AVX-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm0710; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0711; AVX-NEXT: retq712;713; AVX512-LABEL: signbit_setmask_v2i64:714; AVX512: # %bb.0:715; AVX512-NEXT: vpsraq $63, %xmm0, %xmm0716; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0717; AVX512-NEXT: retq718 %cond = icmp slt <2 x i64> %a, zeroinitializer719 %r = select <2 x i1> %cond, <2 x i64> <i64 -1, i64 -1>, <2 x i64> %b720 ret <2 x i64> %r721}722 723define <32 x i8> @signbit_setmask_v32i8(<32 x i8> %a, <32 x i8> %b) {724; SSE-LABEL: signbit_setmask_v32i8:725; SSE: # %bb.0:726; SSE-NEXT: pxor %xmm4, %xmm4727; SSE-NEXT: pxor %xmm5, %xmm5728; SSE-NEXT: pcmpgtb %xmm0, %xmm5729; SSE-NEXT: por %xmm2, %xmm5730; SSE-NEXT: pcmpgtb %xmm1, %xmm4731; SSE-NEXT: por %xmm3, %xmm4732; SSE-NEXT: movdqa %xmm5, %xmm0733; SSE-NEXT: movdqa %xmm4, %xmm1734; SSE-NEXT: retq735;736; AVX1-LABEL: signbit_setmask_v32i8:737; AVX1: # %bb.0:738; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2739; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3740; AVX1-NEXT: vpcmpgtb %xmm2, %xmm3, %xmm2741; AVX1-NEXT: vpcmpgtb %xmm0, %xmm3, %xmm0742; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0743; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0744; AVX1-NEXT: retq745;746; AVX2-LABEL: signbit_setmask_v32i8:747; AVX2: # %bb.0:748; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2749; AVX2-NEXT: vpcmpgtb %ymm0, %ymm2, %ymm0750; AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0751; AVX2-NEXT: retq752;753; AVX512-LABEL: signbit_setmask_v32i8:754; AVX512: # %bb.0:755; AVX512-NEXT: vpxor %xmm2, %xmm2, %xmm2756; AVX512-NEXT: vpcmpgtb %ymm0, %ymm2, %ymm0757; AVX512-NEXT: vpor %ymm1, %ymm0, %ymm0758; AVX512-NEXT: retq759 %cond = icmp slt <32 x i8> %a, zeroinitializer760 %r = select <32 x i1> %cond, <32 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <32 x i8> %b761 ret <32 x i8> %r762}763 764define <16 x i16> @signbit_setmask_v16i16(<16 x i16> %a, <16 x i16> %b) {765; SSE-LABEL: signbit_setmask_v16i16:766; SSE: # %bb.0:767; SSE-NEXT: psraw $15, %xmm0768; SSE-NEXT: por %xmm2, %xmm0769; SSE-NEXT: psraw $15, %xmm1770; SSE-NEXT: por %xmm3, %xmm1771; SSE-NEXT: retq772;773; AVX1-LABEL: signbit_setmask_v16i16:774; AVX1: # %bb.0:775; AVX1-NEXT: vpsraw $15, %xmm0, %xmm2776; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0777; AVX1-NEXT: vpsraw $15, %xmm0, %xmm0778; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0779; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0780; AVX1-NEXT: retq781;782; AVX2-LABEL: signbit_setmask_v16i16:783; AVX2: # %bb.0:784; AVX2-NEXT: vpsraw $15, %ymm0, %ymm0785; AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0786; AVX2-NEXT: retq787;788; AVX512-LABEL: signbit_setmask_v16i16:789; AVX512: # %bb.0:790; AVX512-NEXT: vpsraw $15, %ymm0, %ymm0791; AVX512-NEXT: vpor %ymm1, %ymm0, %ymm0792; AVX512-NEXT: retq793 %cond = icmp slt <16 x i16> %a, zeroinitializer794 %r = select <16 x i1> %cond, <16 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>, <16 x i16> %b795 ret <16 x i16> %r796}797 798define <8 x i32> @signbit_setmask_v8i32(<8 x i32> %a, <8 x i32> %b) {799; SSE-LABEL: signbit_setmask_v8i32:800; SSE: # %bb.0:801; SSE-NEXT: psrad $31, %xmm0802; SSE-NEXT: por %xmm2, %xmm0803; SSE-NEXT: psrad $31, %xmm1804; SSE-NEXT: por %xmm3, %xmm1805; SSE-NEXT: retq806;807; AVX1-LABEL: signbit_setmask_v8i32:808; AVX1: # %bb.0:809; AVX1-NEXT: vpsrad $31, %xmm0, %xmm2810; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0811; AVX1-NEXT: vpsrad $31, %xmm0, %xmm0812; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm0813; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0814; AVX1-NEXT: retq815;816; AVX2-LABEL: signbit_setmask_v8i32:817; AVX2: # %bb.0:818; AVX2-NEXT: vpsrad $31, %ymm0, %ymm0819; AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0820; AVX2-NEXT: retq821;822; AVX512-LABEL: signbit_setmask_v8i32:823; AVX512: # %bb.0:824; AVX512-NEXT: vpsrad $31, %ymm0, %ymm0825; AVX512-NEXT: vpor %ymm1, %ymm0, %ymm0826; AVX512-NEXT: retq827 %cond = icmp slt <8 x i32> %a, zeroinitializer828 %r = select <8 x i1> %cond, <8 x i32> <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>, <8 x i32> %b829 ret <8 x i32> %r830}831 832define <4 x i64> @signbit_setmask_v4i64(<4 x i64> %a, <4 x i64> %b) {833; SSE2-LABEL: signbit_setmask_v4i64:834; SSE2: # %bb.0:835; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]836; SSE2-NEXT: psrad $31, %xmm0837; SSE2-NEXT: por %xmm2, %xmm0838; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]839; SSE2-NEXT: psrad $31, %xmm1840; SSE2-NEXT: por %xmm3, %xmm1841; SSE2-NEXT: retq842;843; SSE42-LABEL: signbit_setmask_v4i64:844; SSE42: # %bb.0:845; SSE42-NEXT: pxor %xmm4, %xmm4846; SSE42-NEXT: pxor %xmm5, %xmm5847; SSE42-NEXT: pcmpgtq %xmm0, %xmm5848; SSE42-NEXT: por %xmm2, %xmm5849; SSE42-NEXT: pcmpgtq %xmm1, %xmm4850; SSE42-NEXT: por %xmm3, %xmm4851; SSE42-NEXT: movdqa %xmm5, %xmm0852; SSE42-NEXT: movdqa %xmm4, %xmm1853; SSE42-NEXT: retq854;855; AVX1-LABEL: signbit_setmask_v4i64:856; AVX1: # %bb.0:857; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2858; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3859; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2860; AVX1-NEXT: vpcmpgtq %xmm0, %xmm3, %xmm0861; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0862; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0863; AVX1-NEXT: retq864;865; AVX2-LABEL: signbit_setmask_v4i64:866; AVX2: # %bb.0:867; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2868; AVX2-NEXT: vpcmpgtq %ymm0, %ymm2, %ymm0869; AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0870; AVX2-NEXT: retq871;872; AVX512-LABEL: signbit_setmask_v4i64:873; AVX512: # %bb.0:874; AVX512-NEXT: vpsraq $63, %ymm0, %ymm0875; AVX512-NEXT: vpor %ymm1, %ymm0, %ymm0876; AVX512-NEXT: retq877 %cond = icmp slt <4 x i64> %a, zeroinitializer878 %r = select <4 x i1> %cond, <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>, <4 x i64> %b879 ret <4 x i64> %r880}881 882; Swap cmp pred and select ops. This is logically equivalent to the above test.883 884define <4 x i64> @signbit_setmask_swap_v4i64(<4 x i64> %a, <4 x i64> %b) {885; SSE2-LABEL: signbit_setmask_swap_v4i64:886; SSE2: # %bb.0:887; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]888; SSE2-NEXT: psrad $31, %xmm0889; SSE2-NEXT: por %xmm2, %xmm0890; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]891; SSE2-NEXT: psrad $31, %xmm1892; SSE2-NEXT: por %xmm3, %xmm1893; SSE2-NEXT: retq894;895; SSE42-LABEL: signbit_setmask_swap_v4i64:896; SSE42: # %bb.0:897; SSE42-NEXT: pxor %xmm4, %xmm4898; SSE42-NEXT: pxor %xmm5, %xmm5899; SSE42-NEXT: pcmpgtq %xmm0, %xmm5900; SSE42-NEXT: por %xmm2, %xmm5901; SSE42-NEXT: pcmpgtq %xmm1, %xmm4902; SSE42-NEXT: por %xmm3, %xmm4903; SSE42-NEXT: movdqa %xmm5, %xmm0904; SSE42-NEXT: movdqa %xmm4, %xmm1905; SSE42-NEXT: retq906;907; AVX1-LABEL: signbit_setmask_swap_v4i64:908; AVX1: # %bb.0:909; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2910; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3911; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm2912; AVX1-NEXT: vpcmpgtq %xmm0, %xmm3, %xmm0913; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm0914; AVX1-NEXT: vorps %ymm1, %ymm0, %ymm0915; AVX1-NEXT: retq916;917; AVX2-LABEL: signbit_setmask_swap_v4i64:918; AVX2: # %bb.0:919; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2920; AVX2-NEXT: vpcmpgtq %ymm0, %ymm2, %ymm0921; AVX2-NEXT: vpor %ymm1, %ymm0, %ymm0922; AVX2-NEXT: retq923;924; AVX512-LABEL: signbit_setmask_swap_v4i64:925; AVX512: # %bb.0:926; AVX512-NEXT: vpsraq $63, %ymm0, %ymm0927; AVX512-NEXT: vpor %ymm1, %ymm0, %ymm0928; AVX512-NEXT: retq929 %cond = icmp sgt <4 x i64> %a, <i64 -1, i64 -1, i64 -1, i64 -1>930 %r = select <4 x i1> %cond, <4 x i64> %b, <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>931 ret <4 x i64> %r932}933 934define <16 x i8> @not_signbit_mask_v16i8(<16 x i8> %a, <16 x i8> %b) {935; SSE-LABEL: not_signbit_mask_v16i8:936; SSE: # %bb.0:937; SSE-NEXT: pcmpeqd %xmm2, %xmm2938; SSE-NEXT: pcmpgtb %xmm2, %xmm0939; SSE-NEXT: pand %xmm1, %xmm0940; SSE-NEXT: retq941;942; AVX-LABEL: not_signbit_mask_v16i8:943; AVX: # %bb.0:944; AVX-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2945; AVX-NEXT: vpcmpgtb %xmm2, %xmm0, %xmm0946; AVX-NEXT: vpand %xmm1, %xmm0, %xmm0947; AVX-NEXT: retq948;949; AVX512-LABEL: not_signbit_mask_v16i8:950; AVX512: # %bb.0:951; AVX512-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm2952; AVX512-NEXT: vpcmpgtb %xmm2, %xmm0, %xmm0953; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0954; AVX512-NEXT: retq955 %cond = icmp sgt <16 x i8> %a, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>956 %r = select <16 x i1> %cond, <16 x i8> %b, <16 x i8> zeroinitializer957 ret <16 x i8> %r958}959 960define <8 x i16> @not_signbit_mask_v8i16(<8 x i16> %a, <8 x i16> %b) {961; SSE-LABEL: not_signbit_mask_v8i16:962; SSE: # %bb.0:963; SSE-NEXT: psraw $15, %xmm0964; SSE-NEXT: pandn %xmm1, %xmm0965; SSE-NEXT: retq966;967; AVX-LABEL: not_signbit_mask_v8i16:968; AVX: # %bb.0:969; AVX-NEXT: vpsraw $15, %xmm0, %xmm0970; AVX-NEXT: vpandn %xmm1, %xmm0, %xmm0971; AVX-NEXT: retq972;973; AVX512-LABEL: not_signbit_mask_v8i16:974; AVX512: # %bb.0:975; AVX512-NEXT: vpsraw $15, %xmm0, %xmm0976; AVX512-NEXT: vpandn %xmm1, %xmm0, %xmm0977; AVX512-NEXT: retq978 %cond = icmp sgt <8 x i16> %a, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>979 %r = select <8 x i1> %cond, <8 x i16> %b, <8 x i16> zeroinitializer980 ret <8 x i16> %r981}982 983; Swap cmp pred and select ops. This is logically equivalent to the above test.984 985define <8 x i16> @not_signbit_mask_swap_v8i16(<8 x i16> %a, <8 x i16> %b) {986; SSE-LABEL: not_signbit_mask_swap_v8i16:987; SSE: # %bb.0:988; SSE-NEXT: psraw $15, %xmm0989; SSE-NEXT: pandn %xmm1, %xmm0990; SSE-NEXT: retq991;992; AVX-LABEL: not_signbit_mask_swap_v8i16:993; AVX: # %bb.0:994; AVX-NEXT: vpsraw $15, %xmm0, %xmm0995; AVX-NEXT: vpandn %xmm1, %xmm0, %xmm0996; AVX-NEXT: retq997;998; AVX512-LABEL: not_signbit_mask_swap_v8i16:999; AVX512: # %bb.0:1000; AVX512-NEXT: vpsraw $15, %xmm0, %xmm01001; AVX512-NEXT: vpandn %xmm1, %xmm0, %xmm01002; AVX512-NEXT: retq1003 %cond = icmp slt <8 x i16> %a, zeroinitializer1004 %r = select <8 x i1> %cond, <8 x i16> zeroinitializer, <8 x i16> %b1005 ret <8 x i16> %r1006}1007 1008define <4 x i32> @not_signbit_mask_v4i32(<4 x i32> %a, <4 x i32> %b) {1009; SSE-LABEL: not_signbit_mask_v4i32:1010; SSE: # %bb.0:1011; SSE-NEXT: psrad $31, %xmm01012; SSE-NEXT: pandn %xmm1, %xmm01013; SSE-NEXT: retq1014;1015; AVX-LABEL: not_signbit_mask_v4i32:1016; AVX: # %bb.0:1017; AVX-NEXT: vpsrad $31, %xmm0, %xmm01018; AVX-NEXT: vpandn %xmm1, %xmm0, %xmm01019; AVX-NEXT: retq1020;1021; AVX512-LABEL: not_signbit_mask_v4i32:1022; AVX512: # %bb.0:1023; AVX512-NEXT: vpsrad $31, %xmm0, %xmm01024; AVX512-NEXT: vpandn %xmm1, %xmm0, %xmm01025; AVX512-NEXT: retq1026 %cond = icmp sgt <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>1027 %r = select <4 x i1> %cond, <4 x i32> %b, <4 x i32> zeroinitializer1028 ret <4 x i32> %r1029}1030 1031define <2 x i64> @not_signbit_mask_v2i64(<2 x i64> %a, <2 x i64> %b) {1032; SSE2-LABEL: not_signbit_mask_v2i64:1033; SSE2: # %bb.0:1034; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]1035; SSE2-NEXT: pcmpeqd %xmm2, %xmm21036; SSE2-NEXT: pcmpgtd %xmm2, %xmm01037; SSE2-NEXT: pand %xmm1, %xmm01038; SSE2-NEXT: retq1039;1040; SSE42-LABEL: not_signbit_mask_v2i64:1041; SSE42: # %bb.0:1042; SSE42-NEXT: pcmpeqd %xmm2, %xmm21043; SSE42-NEXT: pcmpgtq %xmm2, %xmm01044; SSE42-NEXT: pand %xmm1, %xmm01045; SSE42-NEXT: retq1046;1047; AVX-LABEL: not_signbit_mask_v2i64:1048; AVX: # %bb.0:1049; AVX-NEXT: vpcmpeqd %xmm2, %xmm2, %xmm21050; AVX-NEXT: vpcmpgtq %xmm2, %xmm0, %xmm01051; AVX-NEXT: vpand %xmm1, %xmm0, %xmm01052; AVX-NEXT: retq1053;1054; AVX512-LABEL: not_signbit_mask_v2i64:1055; AVX512: # %bb.0:1056; AVX512-NEXT: vpsraq $63, %xmm0, %xmm01057; AVX512-NEXT: vpandn %xmm1, %xmm0, %xmm01058; AVX512-NEXT: retq1059 %cond = icmp sgt <2 x i64> %a, <i64 -1, i64 -1>1060 %r = select <2 x i1> %cond, <2 x i64> %b, <2 x i64> zeroinitializer1061 ret <2 x i64> %r1062}1063 1064define <32 x i8> @not_signbit_mask_v32i8(<32 x i8> %a, <32 x i8> %b) {1065; SSE-LABEL: not_signbit_mask_v32i8:1066; SSE: # %bb.0:1067; SSE-NEXT: pcmpeqd %xmm4, %xmm41068; SSE-NEXT: pcmpgtb %xmm4, %xmm01069; SSE-NEXT: pand %xmm2, %xmm01070; SSE-NEXT: pcmpgtb %xmm4, %xmm11071; SSE-NEXT: pand %xmm3, %xmm11072; SSE-NEXT: retq1073;1074; AVX1-LABEL: not_signbit_mask_v32i8:1075; AVX1: # %bb.0:1076; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm21077; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm31078; AVX1-NEXT: vpcmpgtb %xmm2, %xmm3, %xmm21079; AVX1-NEXT: vpcmpgtb %xmm0, %xmm3, %xmm01080; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm01081; AVX1-NEXT: vandnps %ymm1, %ymm0, %ymm01082; AVX1-NEXT: retq1083;1084; AVX2-LABEL: not_signbit_mask_v32i8:1085; AVX2: # %bb.0:1086; AVX2-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm21087; AVX2-NEXT: vpcmpgtb %ymm2, %ymm0, %ymm01088; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm01089; AVX2-NEXT: retq1090;1091; AVX512-LABEL: not_signbit_mask_v32i8:1092; AVX512: # %bb.0:1093; AVX512-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm21094; AVX512-NEXT: vpcmpgtb %ymm2, %ymm0, %ymm01095; AVX512-NEXT: vpand %ymm1, %ymm0, %ymm01096; AVX512-NEXT: retq1097 %cond = icmp sgt <32 x i8> %a, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>1098 %r = select <32 x i1> %cond, <32 x i8> %b, <32 x i8> zeroinitializer1099 ret <32 x i8> %r1100}1101 1102define <16 x i16> @not_signbit_mask_v16i16(<16 x i16> %a, <16 x i16> %b) {1103; SSE-LABEL: not_signbit_mask_v16i16:1104; SSE: # %bb.0:1105; SSE-NEXT: psraw $15, %xmm01106; SSE-NEXT: pandn %xmm2, %xmm01107; SSE-NEXT: psraw $15, %xmm11108; SSE-NEXT: pandn %xmm3, %xmm11109; SSE-NEXT: retq1110;1111; AVX1-LABEL: not_signbit_mask_v16i16:1112; AVX1: # %bb.0:1113; AVX1-NEXT: vpsraw $15, %xmm0, %xmm21114; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm01115; AVX1-NEXT: vpsraw $15, %xmm0, %xmm01116; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm01117; AVX1-NEXT: vandnps %ymm1, %ymm0, %ymm01118; AVX1-NEXT: retq1119;1120; AVX2-LABEL: not_signbit_mask_v16i16:1121; AVX2: # %bb.0:1122; AVX2-NEXT: vpsraw $15, %ymm0, %ymm01123; AVX2-NEXT: vpandn %ymm1, %ymm0, %ymm01124; AVX2-NEXT: retq1125;1126; AVX512-LABEL: not_signbit_mask_v16i16:1127; AVX512: # %bb.0:1128; AVX512-NEXT: vpsraw $15, %ymm0, %ymm01129; AVX512-NEXT: vpandn %ymm1, %ymm0, %ymm01130; AVX512-NEXT: retq1131 %cond = icmp sgt <16 x i16> %a, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>1132 %r = select <16 x i1> %cond, <16 x i16> %b, <16 x i16> zeroinitializer1133 ret <16 x i16> %r1134}1135 1136define <8 x i32> @not_signbit_mask_v8i32(<8 x i32> %a, <8 x i32> %b) {1137; SSE-LABEL: not_signbit_mask_v8i32:1138; SSE: # %bb.0:1139; SSE-NEXT: psrad $31, %xmm01140; SSE-NEXT: pandn %xmm2, %xmm01141; SSE-NEXT: psrad $31, %xmm11142; SSE-NEXT: pandn %xmm3, %xmm11143; SSE-NEXT: retq1144;1145; AVX1-LABEL: not_signbit_mask_v8i32:1146; AVX1: # %bb.0:1147; AVX1-NEXT: vpsrad $31, %xmm0, %xmm21148; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm01149; AVX1-NEXT: vpsrad $31, %xmm0, %xmm01150; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm01151; AVX1-NEXT: vandnps %ymm1, %ymm0, %ymm01152; AVX1-NEXT: retq1153;1154; AVX2-LABEL: not_signbit_mask_v8i32:1155; AVX2: # %bb.0:1156; AVX2-NEXT: vpsrad $31, %ymm0, %ymm01157; AVX2-NEXT: vpandn %ymm1, %ymm0, %ymm01158; AVX2-NEXT: retq1159;1160; AVX512-LABEL: not_signbit_mask_v8i32:1161; AVX512: # %bb.0:1162; AVX512-NEXT: vpsrad $31, %ymm0, %ymm01163; AVX512-NEXT: vpandn %ymm1, %ymm0, %ymm01164; AVX512-NEXT: retq1165 %cond = icmp sgt <8 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1, i32 -1>1166 %r = select <8 x i1> %cond, <8 x i32> %b, <8 x i32> zeroinitializer1167 ret <8 x i32> %r1168}1169 1170; Swap cmp pred and select ops. This is logically equivalent to the above test.1171 1172define <8 x i32> @not_signbit_mask_swap_v8i32(<8 x i32> %a, <8 x i32> %b) {1173; SSE-LABEL: not_signbit_mask_swap_v8i32:1174; SSE: # %bb.0:1175; SSE-NEXT: psrad $31, %xmm01176; SSE-NEXT: pandn %xmm2, %xmm01177; SSE-NEXT: psrad $31, %xmm11178; SSE-NEXT: pandn %xmm3, %xmm11179; SSE-NEXT: retq1180;1181; AVX1-LABEL: not_signbit_mask_swap_v8i32:1182; AVX1: # %bb.0:1183; AVX1-NEXT: vpsrad $31, %xmm0, %xmm21184; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm01185; AVX1-NEXT: vpsrad $31, %xmm0, %xmm01186; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm2, %ymm01187; AVX1-NEXT: vandnps %ymm1, %ymm0, %ymm01188; AVX1-NEXT: retq1189;1190; AVX2-LABEL: not_signbit_mask_swap_v8i32:1191; AVX2: # %bb.0:1192; AVX2-NEXT: vpsrad $31, %ymm0, %ymm01193; AVX2-NEXT: vpandn %ymm1, %ymm0, %ymm01194; AVX2-NEXT: retq1195;1196; AVX512-LABEL: not_signbit_mask_swap_v8i32:1197; AVX512: # %bb.0:1198; AVX512-NEXT: vpsrad $31, %ymm0, %ymm01199; AVX512-NEXT: vpandn %ymm1, %ymm0, %ymm01200; AVX512-NEXT: retq1201 %cond = icmp slt <8 x i32> %a, zeroinitializer1202 %r = select <8 x i1> %cond, <8 x i32> zeroinitializer, <8 x i32> %b1203 ret <8 x i32> %r1204}1205 1206define <4 x i64> @not_signbit_mask_v4i64(<4 x i64> %a, <4 x i64> %b) {1207; SSE2-LABEL: not_signbit_mask_v4i64:1208; SSE2: # %bb.0:1209; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]1210; SSE2-NEXT: pcmpeqd %xmm4, %xmm41211; SSE2-NEXT: pcmpgtd %xmm4, %xmm01212; SSE2-NEXT: pand %xmm2, %xmm01213; SSE2-NEXT: pshufd {{.*#+}} xmm1 = xmm1[1,1,3,3]1214; SSE2-NEXT: pcmpgtd %xmm4, %xmm11215; SSE2-NEXT: pand %xmm3, %xmm11216; SSE2-NEXT: retq1217;1218; SSE42-LABEL: not_signbit_mask_v4i64:1219; SSE42: # %bb.0:1220; SSE42-NEXT: pcmpeqd %xmm4, %xmm41221; SSE42-NEXT: pcmpgtq %xmm4, %xmm01222; SSE42-NEXT: pand %xmm2, %xmm01223; SSE42-NEXT: pcmpgtq %xmm4, %xmm11224; SSE42-NEXT: pand %xmm3, %xmm11225; SSE42-NEXT: retq1226;1227; AVX1-LABEL: not_signbit_mask_v4i64:1228; AVX1: # %bb.0:1229; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm21230; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm31231; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm21232; AVX1-NEXT: vpcmpgtq %xmm0, %xmm3, %xmm01233; AVX1-NEXT: vinsertf128 $1, %xmm2, %ymm0, %ymm01234; AVX1-NEXT: vandnps %ymm1, %ymm0, %ymm01235; AVX1-NEXT: retq1236;1237; AVX2-LABEL: not_signbit_mask_v4i64:1238; AVX2: # %bb.0:1239; AVX2-NEXT: vpcmpeqd %ymm2, %ymm2, %ymm21240; AVX2-NEXT: vpcmpgtq %ymm2, %ymm0, %ymm01241; AVX2-NEXT: vpand %ymm1, %ymm0, %ymm01242; AVX2-NEXT: retq1243;1244; AVX512-LABEL: not_signbit_mask_v4i64:1245; AVX512: # %bb.0:1246; AVX512-NEXT: vpsraq $63, %ymm0, %ymm01247; AVX512-NEXT: vpandn %ymm1, %ymm0, %ymm01248; AVX512-NEXT: retq1249 %cond = icmp sgt <4 x i64> %a, <i64 -1, i64 -1, i64 -1, i64 -1>1250 %r = select <4 x i1> %cond, <4 x i64> %b, <4 x i64> zeroinitializer1251 ret <4 x i64> %r1252}1253