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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X863; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X644 5; test vector shifts converted to proper SSE2 vector shifts when the shift6; amounts are the same.7 8; Note that x86 does have ashr9 10define void @shift1a(<2 x i64> %val, ptr %dst) nounwind {11; X86-LABEL: shift1a:12; X86: # %bb.0: # %entry13; X86-NEXT: movl {{[0-9]+}}(%esp), %eax14; X86-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]15; X86-NEXT: movdqa %xmm0, %xmm116; X86-NEXT: psrad $31, %xmm117; X86-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]18; X86-NEXT: movdqa %xmm0, (%eax)19; X86-NEXT: retl20;21; X64-LABEL: shift1a:22; X64: # %bb.0: # %entry23; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,3,2,3]24; X64-NEXT: movdqa %xmm0, %xmm125; X64-NEXT: psrad $31, %xmm126; X64-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1]27; X64-NEXT: movdqa %xmm0, (%rdi)28; X64-NEXT: retq29entry:30 %ashr = ashr <2 x i64> %val, < i64 32, i64 32 >31 store <2 x i64> %ashr, ptr %dst32 ret void33}34 35define void @shift2a(<4 x i32> %val, ptr %dst) nounwind {36; X86-LABEL: shift2a:37; X86: # %bb.0: # %entry38; X86-NEXT: movl {{[0-9]+}}(%esp), %eax39; X86-NEXT: psrad $5, %xmm040; X86-NEXT: movdqa %xmm0, (%eax)41; X86-NEXT: retl42;43; X64-LABEL: shift2a:44; X64: # %bb.0: # %entry45; X64-NEXT: psrad $5, %xmm046; X64-NEXT: movdqa %xmm0, (%rdi)47; X64-NEXT: retq48entry:49 %ashr = ashr <4 x i32> %val, < i32 5, i32 5, i32 5, i32 5 >50 store <4 x i32> %ashr, ptr %dst51 ret void52}53 54define void @shift2b(<4 x i32> %val, ptr %dst, i32 %amt) nounwind {55; X86-LABEL: shift2b:56; X86: # %bb.0: # %entry57; X86-NEXT: movl {{[0-9]+}}(%esp), %eax58; X86-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero59; X86-NEXT: psrad %xmm1, %xmm060; X86-NEXT: movdqa %xmm0, (%eax)61; X86-NEXT: retl62;63; X64-LABEL: shift2b:64; X64: # %bb.0: # %entry65; X64-NEXT: movd %esi, %xmm166; X64-NEXT: psrad %xmm1, %xmm067; X64-NEXT: movdqa %xmm0, (%rdi)68; X64-NEXT: retq69entry:70 %0 = insertelement <4 x i32> undef, i32 %amt, i32 071 %1 = insertelement <4 x i32> %0, i32 %amt, i32 172 %2 = insertelement <4 x i32> %1, i32 %amt, i32 273 %3 = insertelement <4 x i32> %2, i32 %amt, i32 374 %ashr = ashr <4 x i32> %val, %375 store <4 x i32> %ashr, ptr %dst76 ret void77}78 79define void @shift3a(<8 x i16> %val, ptr %dst) nounwind {80; X86-LABEL: shift3a:81; X86: # %bb.0: # %entry82; X86-NEXT: movl {{[0-9]+}}(%esp), %eax83; X86-NEXT: psraw $5, %xmm084; X86-NEXT: movdqa %xmm0, (%eax)85; X86-NEXT: retl86;87; X64-LABEL: shift3a:88; X64: # %bb.0: # %entry89; X64-NEXT: psraw $5, %xmm090; X64-NEXT: movdqa %xmm0, (%rdi)91; X64-NEXT: retq92entry:93 %ashr = ashr <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >94 store <8 x i16> %ashr, ptr %dst95 ret void96}97 98define void @shift3b(<8 x i16> %val, ptr %dst, i16 %amt) nounwind {99; X86-LABEL: shift3b:100; X86: # %bb.0: # %entry101; X86-NEXT: movl {{[0-9]+}}(%esp), %eax102; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx103; X86-NEXT: movd %ecx, %xmm1104; X86-NEXT: psraw %xmm1, %xmm0105; X86-NEXT: movdqa %xmm0, (%eax)106; X86-NEXT: retl107;108; X64-LABEL: shift3b:109; X64: # %bb.0: # %entry110; X64-NEXT: movzwl %si, %eax111; X64-NEXT: movd %eax, %xmm1112; X64-NEXT: psraw %xmm1, %xmm0113; X64-NEXT: movdqa %xmm0, (%rdi)114; X64-NEXT: retq115entry:116 %0 = insertelement <8 x i16> undef, i16 %amt, i32 0117 %1 = insertelement <8 x i16> %0, i16 %amt, i32 1118 %2 = insertelement <8 x i16> %1, i16 %amt, i32 2119 %3 = insertelement <8 x i16> %2, i16 %amt, i32 3120 %4 = insertelement <8 x i16> %3, i16 %amt, i32 4121 %5 = insertelement <8 x i16> %4, i16 %amt, i32 5122 %6 = insertelement <8 x i16> %5, i16 %amt, i32 6123 %7 = insertelement <8 x i16> %6, i16 %amt, i32 7124 %ashr = ashr <8 x i16> %val, %7125 store <8 x i16> %ashr, ptr %dst126 ret void127}128