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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=i686-windows-msvc < %s | FileCheck -check-prefix=CHECK32 %s3; RUN: llc -mtriple=x86_64-windows-msvc < %s | FileCheck -check-prefix=CHECK64 %s4 5define i64 @test_sdiv_i64(i64 %a, i64 %b) {6; CHECK32-LABEL: test_sdiv_i64:7; CHECK32: # %bb.0:8; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)9; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)10; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)11; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)12; CHECK32-NEXT: calll __alldiv13; CHECK32-NEXT: retl14;15; CHECK64-LABEL: test_sdiv_i64:16; CHECK64: # %bb.0:17; CHECK64-NEXT: movq %rdx, %r818; CHECK64-NEXT: movq %rcx, %rax19; CHECK64-NEXT: cqto20; CHECK64-NEXT: idivq %r821; CHECK64-NEXT: retq22 %ret = sdiv i64 %a, %b23 ret i64 %ret24}25 26define i64 @test_srem_i64(i64 %a, i64 %b) {27; CHECK32-LABEL: test_srem_i64:28; CHECK32: # %bb.0:29; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)30; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)31; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)32; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)33; CHECK32-NEXT: calll __allrem34; CHECK32-NEXT: retl35;36; CHECK64-LABEL: test_srem_i64:37; CHECK64: # %bb.0:38; CHECK64-NEXT: movq %rdx, %r839; CHECK64-NEXT: movq %rcx, %rax40; CHECK64-NEXT: cqto41; CHECK64-NEXT: idivq %r842; CHECK64-NEXT: movq %rdx, %rax43; CHECK64-NEXT: retq44 %ret = srem i64 %a, %b45 ret i64 %ret46}47 48define i64 @test_udiv_i64(i64 %a, i64 %b) {49; CHECK32-LABEL: test_udiv_i64:50; CHECK32: # %bb.0:51; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)52; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)53; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)54; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)55; CHECK32-NEXT: calll __aulldiv56; CHECK32-NEXT: retl57;58; CHECK64-LABEL: test_udiv_i64:59; CHECK64: # %bb.0:60; CHECK64-NEXT: movq %rdx, %r861; CHECK64-NEXT: movq %rcx, %rax62; CHECK64-NEXT: xorl %edx, %edx63; CHECK64-NEXT: divq %r864; CHECK64-NEXT: retq65 %ret = udiv i64 %a, %b66 ret i64 %ret67}68 69define i64 @test_urem_i64(i64 %a, i64 %b) {70; CHECK32-LABEL: test_urem_i64:71; CHECK32: # %bb.0:72; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)73; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)74; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)75; CHECK32-NEXT: pushl {{[0-9]+}}(%esp)76; CHECK32-NEXT: calll __aullrem77; CHECK32-NEXT: retl78;79; CHECK64-LABEL: test_urem_i64:80; CHECK64: # %bb.0:81; CHECK64-NEXT: movq %rdx, %r882; CHECK64-NEXT: movq %rcx, %rax83; CHECK64-NEXT: xorl %edx, %edx84; CHECK64-NEXT: divq %r885; CHECK64-NEXT: movq %rdx, %rax86; CHECK64-NEXT: retq87 %ret = urem i64 %a, %b88 ret i64 %ret89}90 91define i64 @test_mul_i64(i64 %a, i64 %b) {92; CHECK32-LABEL: test_mul_i64:93; CHECK32: # %bb.0:94; CHECK32-NEXT: pushl %esi95; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %ecx96; CHECK32-NEXT: movl {{[0-9]+}}(%esp), %esi97; CHECK32-NEXT: movl %ecx, %eax98; CHECK32-NEXT: mull %esi99; CHECK32-NEXT: imull {{[0-9]+}}(%esp), %ecx100; CHECK32-NEXT: addl %ecx, %edx101; CHECK32-NEXT: imull {{[0-9]+}}(%esp), %esi102; CHECK32-NEXT: addl %esi, %edx103; CHECK32-NEXT: popl %esi104; CHECK32-NEXT: retl105;106; CHECK64-LABEL: test_mul_i64:107; CHECK64: # %bb.0:108; CHECK64-NEXT: movq %rcx, %rax109; CHECK64-NEXT: imulq %rdx, %rax110; CHECK64-NEXT: retq111 %ret = mul i64 %a, %b112 ret i64 %ret113}114