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1; RUN: llc < %s -mtriple=x86_64-none-none-gnux32 -mcpu=generic | FileCheck %s2; RUN: llc < %s -mtriple=x86_64-none-none-gnux32 -mcpu=generic -fast-isel | FileCheck %s3; Bug 228594;5; x32 pointers are 32-bits wide. x86-64 indirect branches use the full 64-bit6; registers. Therefore, x32 CodeGen needs to zero extend indirectbr's target to7; 64-bit.8 9define i8 @test1() nounwind ssp {10entry:11 %0 = select i1 undef, ; <ptr> [#uses=1]12 ptr blockaddress(@test1, %bb),13 ptr blockaddress(@test1, %bb6)14 indirectbr ptr %0, [label %bb, label %bb6]15bb: ; preds = %entry16 ret i8 117 18bb6: ; preds = %entry19 ret i8 220}21; CHECK-LABEL: @test122; We are looking for a movl ???, %r32 followed by a 64-bit jmp through the23; same register.24; CHECK: movl {{.*}}, %{{e|r}}[[REG:.[^d]*]]{{d?}}25; CHECK-NEXT: jmpq *%r[[REG]]26 27