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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=bdver1 | FileCheck %s3 4; Verify that for the architectures that are known to have poor latency5; double precision shift instructions we generate alternative sequence6; of instructions with lower latencies instead of shld instruction.7 8;uint64_t lshift1(uint64_t a, uint64_t b)9;{10; return (a << 1) | (b >> 63);11;}12 13define i64 @lshift1(i64 %a, i64 %b) nounwind readnone uwtable {14; CHECK-LABEL: lshift1:15; CHECK: # %bb.0: # %entry16; CHECK-NEXT: shrq $63, %rsi17; CHECK-NEXT: leaq (%rsi,%rdi,2), %rax18; CHECK-NEXT: retq19entry:20 %shl = shl i64 %a, 121 %shr = lshr i64 %b, 6322 %or = or i64 %shr, %shl23 ret i64 %or24}25 26;uint64_t lshift2(uint64_t a, uint64_t b)27;{28; return (a << 2) | (b >> 62);29;}30 31define i64 @lshift2(i64 %a, i64 %b) nounwind readnone uwtable {32; CHECK-LABEL: lshift2:33; CHECK: # %bb.0: # %entry34; CHECK-NEXT: shrq $62, %rsi35; CHECK-NEXT: leaq (%rsi,%rdi,4), %rax36; CHECK-NEXT: retq37entry:38 %shl = shl i64 %a, 239 %shr = lshr i64 %b, 6240 %or = or i64 %shr, %shl41 ret i64 %or42}43 44;uint64_t lshift7(uint64_t a, uint64_t b)45;{46; return (a << 7) | (b >> 57);47;}48 49define i64 @lshift7(i64 %a, i64 %b) nounwind readnone uwtable {50; CHECK-LABEL: lshift7:51; CHECK: # %bb.0: # %entry52; CHECK-NEXT: shrq $57, %rsi53; CHECK-NEXT: shlq $7, %rdi54; CHECK-NEXT: leaq (%rdi,%rsi), %rax55; CHECK-NEXT: retq56entry:57 %shl = shl i64 %a, 758 %shr = lshr i64 %b, 5759 %or = or i64 %shr, %shl60 ret i64 %or61}62 63;uint64_t lshift63(uint64_t a, uint64_t b)64;{65; return (a << 63) | (b >> 1);66;}67 68define i64 @lshift63(i64 %a, i64 %b) nounwind readnone uwtable {69; CHECK-LABEL: lshift63:70; CHECK: # %bb.0: # %entry71; CHECK-NEXT: shrq %rsi72; CHECK-NEXT: shlq $63, %rdi73; CHECK-NEXT: leaq (%rdi,%rsi), %rax74; CHECK-NEXT: retq75entry:76 %shl = shl i64 %a, 6377 %shr = lshr i64 %b, 178 %or = or i64 %shr, %shl79 ret i64 %or80}81