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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=bdver1 | FileCheck %s3 4; Verify that for the architectures that are known to have poor latency5; double precision shift instructions we generate alternative sequence6; of instructions with lower latencies instead of shrd instruction.7 8;uint64_t rshift1(uint64_t a, uint64_t b)9;{10; return (a >> 1) | (b << 63);11;}12 13define i64 @rshift1(i64 %a, i64 %b) nounwind readnone uwtable {14; CHECK-LABEL: rshift1:15; CHECK: # %bb.0:16; CHECK-NEXT: shrq %rdi17; CHECK-NEXT: shlq $63, %rsi18; CHECK-NEXT: leaq (%rsi,%rdi), %rax19; CHECK-NEXT: retq20 %1 = lshr i64 %a, 121 %2 = shl i64 %b, 6322 %3 = or i64 %2, %123 ret i64 %324}25 26;uint64_t rshift2(uint64_t a, uint64_t b)27;{28; return (a >> 2) | (b << 62);29;}30 31define i64 @rshift2(i64 %a, i64 %b) nounwind readnone uwtable {32; CHECK-LABEL: rshift2:33; CHECK: # %bb.0:34; CHECK-NEXT: shrq $2, %rdi35; CHECK-NEXT: shlq $62, %rsi36; CHECK-NEXT: leaq (%rsi,%rdi), %rax37; CHECK-NEXT: retq38 %1 = lshr i64 %a, 239 %2 = shl i64 %b, 6240 %3 = or i64 %2, %141 ret i64 %342}43 44;uint64_t rshift7(uint64_t a, uint64_t b)45;{46; return (a >> 7) | (b << 57);47;}48 49define i64 @rshift7(i64 %a, i64 %b) nounwind readnone uwtable {50; CHECK-LABEL: rshift7:51; CHECK: # %bb.0:52; CHECK-NEXT: shrq $7, %rdi53; CHECK-NEXT: shlq $57, %rsi54; CHECK-NEXT: leaq (%rsi,%rdi), %rax55; CHECK-NEXT: retq56 %1 = lshr i64 %a, 757 %2 = shl i64 %b, 5758 %3 = or i64 %2, %159 ret i64 %360}61 62;uint64_t rshift63(uint64_t a, uint64_t b)63;{64; return (a >> 63) | (b << 1);65;}66 67define i64 @rshift63(i64 %a, i64 %b) nounwind readnone uwtable {68; CHECK-LABEL: rshift63:69; CHECK: # %bb.0:70; CHECK-NEXT: shrq $63, %rdi71; CHECK-NEXT: leaq (%rdi,%rsi,2), %rax72; CHECK-NEXT: retq73 %1 = lshr i64 %a, 6374 %2 = shl i64 %b, 175 %3 = or i64 %2, %176 ret i64 %377}78