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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s3 4; Various tests for ands that should be implemented with movzx, but aren't due5; demanded bits shortcomings.6 7; The backend will insert a zext to promote the shift to i32.8define i16 @test1(i16 %x) {9; CHECK-LABEL: test1:10; CHECK: # %bb.0:11; CHECK-NEXT: movzwl %di, %eax12; CHECK-NEXT: shrl %eax13; CHECK-NEXT: # kill: def $ax killed $ax killed $eax14; CHECK-NEXT: retq15 %y = lshr i16 %x, 116 ret i16 %y17}18 19define i32 @test2(i32 %x) {20; CHECK-LABEL: test2:21; CHECK: # %bb.0:22; CHECK-NEXT: movzwl %di, %eax23; CHECK-NEXT: shrl %eax24; CHECK-NEXT: retq25 %y = and i32 %x, 6553526 %z = lshr i32 %y, 127 ret i32 %z28}29 30define i32 @test3(i32 %x) {31; CHECK-LABEL: test3:32; CHECK: # %bb.0:33; CHECK-NEXT: movzbl %dil, %eax34; CHECK-NEXT: shrl %eax35; CHECK-NEXT: retq36 %y = and i32 %x, 25537 %z = lshr i32 %y, 138 ret i32 %z39}40 41define i16 @test4(i16 %x) {42; CHECK-LABEL: test4:43; CHECK: # %bb.0:44; CHECK-NEXT: movzbl %dil, %eax45; CHECK-NEXT: shrl %eax46; CHECK-NEXT: # kill: def $ax killed $ax killed $eax47; CHECK-NEXT: retq48 %y = and i16 %x, 25549 %z = lshr i16 %y, 150 ret i16 %z51}52 53define i16 @test5(i16 %x) {54; CHECK-LABEL: test5:55; CHECK: # %bb.0:56; CHECK-NEXT: movzwl %di, %eax57; CHECK-NEXT: shrl $9, %eax58; CHECK-NEXT: # kill: def $ax killed $ax killed $eax59; CHECK-NEXT: retq60 %y = lshr i16 %x, 961 ret i16 %y62}63 64define i32 @test6(i32 %x) {65; CHECK-LABEL: test6:66; CHECK: # %bb.0:67; CHECK-NEXT: movzwl %di, %eax68; CHECK-NEXT: shrl $9, %eax69; CHECK-NEXT: retq70 %y = and i32 %x, 6553571 %z = lshr i32 %y, 972 ret i32 %z73}74 75; TODO: We could turn this and into a zero extend.76define i32 @test7(i32 %x) {77; CHECK-LABEL: test7:78; CHECK: # %bb.0:79; CHECK-NEXT: orl $1, %edi80; CHECK-NEXT: movzwl %di, %eax81; CHECK-NEXT: retq82 %y = and i32 %x, 6553483 %z = or i32 %y, 184 ret i32 %z85}86 87; We actually get a movzx on this one, but only because we canonicalize the and88; after the or before SimplifyDemandedBits messes it up.89define i32 @test8(i32 %x) {90; CHECK-LABEL: test8:91; CHECK: # %bb.0:92; CHECK-NEXT: orl $1, %edi93; CHECK-NEXT: movzwl %di, %eax94; CHECK-NEXT: retq95 %y = and i32 %x, 6553596 %z = or i32 %y, 197 ret i32 %z98}99 100define i64 @add_neg_one(i64 %x) {101; CHECK-LABEL: add_neg_one:102; CHECK: # %bb.0:103; CHECK-NEXT: leal -1(%rdi), %eax104; CHECK-NEXT: andl %edi, %eax105; CHECK-NEXT: movzwl %ax, %eax106; CHECK-NEXT: retq107 %a1 = and i64 %x, 65535108 %a2 = add i64 %x, 65535109 %r = and i64 %a1, %a2110 ret i64 %r111}112 113define i64 @sub_neg_one(i64 %x) {114; CHECK-LABEL: sub_neg_one:115; CHECK: # %bb.0:116; CHECK-NEXT: leal -65535(%rdi), %eax117; CHECK-NEXT: andl %edi, %eax118; CHECK-NEXT: movzwl %ax, %eax119; CHECK-NEXT: retq120 %a1 = and i64 %x, 65535121 %a2 = sub i64 %x, 65535122 %r = and i64 %a1, %a2123 ret i64 %r124}125 126define i64 @mul_neg_one(i64 %x) {127; CHECK-LABEL: mul_neg_one:128; CHECK: # %bb.0:129; CHECK-NEXT: movl %edi, %eax130; CHECK-NEXT: negl %eax131; CHECK-NEXT: andl %edi, %eax132; CHECK-NEXT: movzwl %ax, %eax133; CHECK-NEXT: retq134 %a1 = and i64 %x, 65535135 %a2 = mul i64 %x, 65535136 %r = and i64 %a1, %a2137 ret i64 %r138}139 140define i32 @PR36689(ptr) {141; CHECK-LABEL: PR36689:142; CHECK: # %bb.0:143; CHECK-NEXT: movzwl (%rdi), %eax144; CHECK-NEXT: orl $255, %eax145; CHECK-NEXT: retq146 %2 = load i32, ptr %0147 %3 = and i32 %2, 65280148 %4 = or i32 %3, 255149 ret i32 %4150}151