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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s3 4define void @t() nounwind ssp {5; CHECK-LABEL: t:6; CHECK: ## %bb.0: ## %entry7; CHECK-NEXT: xorl %eax, %eax8; CHECK-NEXT: testb %al, %al9; CHECK-NEXT: jne LBB0_610; CHECK-NEXT: ## %bb.1: ## %if.end.i11; CHECK-NEXT: xorl %eax, %eax12; CHECK-NEXT: testb %al, %al13; CHECK-NEXT: je LBB0_214; CHECK-NEXT: LBB0_6: ## %return15; CHECK-NEXT: retq16; CHECK-NEXT: LBB0_2: ## %if.end17; CHECK-NEXT: movb $1, %al18; CHECK-NEXT: testb %al, %al19; CHECK-NEXT: xorl %eax, %eax20; CHECK-NEXT: testb %al, %al21; CHECK-NEXT: jne LBB0_522; CHECK-NEXT: ## %bb.3: ## %cond.true19023; CHECK-NEXT: xorl %eax, %eax24; CHECK-NEXT: testb %al, %al25; CHECK-NEXT: jne LBB0_526; CHECK-NEXT: ## %bb.4: ## %cond.true22527; CHECK-NEXT: xorl %eax, %eax28; CHECK-NEXT: testb %al, %al29; CHECK-NEXT: LBB0_5: ## %cond.false20530; CHECK-NEXT: ud231entry:32 br i1 undef, label %return, label %if.end.i33 34if.end.i: ; preds = %entry35 %tmp7.i = load i32, ptr undef, align 436 br i1 undef, label %return, label %if.end37 38if.end: ; preds = %if.end.i39 %tmp138 = select i1 undef, i32 0, i32 %tmp7.i40 %tmp867 = zext i32 %tmp138 to i6441 br label %while.cond42 43while.cond: ; preds = %while.body, %if.end44 %tmp869 = sub i64 %tmp867, 045 %scale2.0 = trunc i64 %tmp869 to i3246 %cmp149 = icmp eq i32 %scale2.0, 047 br i1 %cmp149, label %while.end, label %land.rhs48 49land.rhs: ; preds = %while.cond50 br i1 undef, label %while.body, label %while.end51 52while.body: ; preds = %land.rhs53 br label %while.cond54 55while.end: ; preds = %land.rhs, %while.cond56 br i1 undef, label %cond.false205, label %cond.true19057 58cond.true190: ; preds = %while.end59 br i1 undef, label %cond.false242, label %cond.true22560 61cond.false205: ; preds = %while.end62 unreachable63 64cond.true225: ; preds = %cond.true19065 br i1 undef, label %cond.false280, label %cond.true27166 67cond.false242: ; preds = %cond.true19068 unreachable69 70cond.true271: ; preds = %cond.true22571 unreachable72 73cond.false280: ; preds = %cond.true22574 unreachable75 76return: ; preds = %if.end.i, %entry77 ret void78}79