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1; RUN: llc < %s -mtriple=i686-- | FileCheck -check-prefix=X86 %s2; RUN: llc < %s -mtriple=x86_64-- | FileCheck -check-prefix=X64 %s3 4; X86-NOT: and5 6; X64-NOT: and7; X64-NOT: movzbq8; X64-NOT: movzwq9; X64-NOT: movzlq10 11; These should use movzbl instead of 'and 255'.12; This related to not having a ZERO_EXTEND_REG opcode.13 14define i32 @a(i32 %d) nounwind {15 %e = add i32 %d, 116 %retval = and i32 %e, 25517 ret i32 %retval18}19define i32 @b(float %d) nounwind {20 %tmp12 = fptoui float %d to i821 %retval = zext i8 %tmp12 to i3222 ret i32 %retval23}24define i32 @c(i32 %d) nounwind {25 %e = add i32 %d, 126 %retval = and i32 %e, 6553527 ret i32 %retval28}29define i64 @d(i64 %d) nounwind {30 %e = add i64 %d, 131 %retval = and i64 %e, 25532 ret i64 %retval33}34define i64 @e(i64 %d) nounwind {35 %e = add i64 %d, 136 %retval = and i64 %e, 6553537 ret i64 %retval38}39define i64 @f(i64 %d) nounwind {40 %e = add i64 %d, 141 %retval = and i64 %e, 429496729542 ret i64 %retval43}44 45define i32 @g(i8 %d) nounwind {46 %e = add i8 %d, 147 %retval = zext i8 %e to i3248 ret i32 %retval49}50define i32 @h(i16 %d) nounwind {51 %e = add i16 %d, 152 %retval = zext i16 %e to i3253 ret i32 %retval54}55define i64 @i(i8 %d) nounwind {56 %e = add i8 %d, 157 %retval = zext i8 %e to i6458 ret i64 %retval59}60define i64 @j(i16 %d) nounwind {61 %e = add i16 %d, 162 %retval = zext i16 %e to i6463 ret i64 %retval64}65define i64 @k(i32 %d) nounwind {66 %e = add i32 %d, 167 %retval = zext i32 %e to i6468 ret i64 %retval69}70