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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=x86_64-linux-gnu -mcpu=atom | FileCheck %s3; <rdar://problem/8006248>4 5; This randomly started passing after an unrelated change, if it fails again it6; might be worth looking at PR12324: misched bringup.7 8@llvm.used = appending global [1 x ptr] [ptr @func], section "llvm.metadata"9 10define void @func(ptr %a, ptr %b, ptr %c, ptr %d) nounwind {11; CHECK-LABEL: func:12; CHECK: # %bb.0: # %entry13; CHECK-NEXT: movslq (%rsi), %rax14; CHECK-NEXT: movl $4, %esi15; CHECK-NEXT: subq %rax, %rsi16; CHECK-NEXT: movq (%rdx), %rax17; CHECK-NEXT: movswl 8(%rdi), %edx18; CHECK-NEXT: movswl (%rax,%rsi,2), %eax19; CHECK-NEXT: imull %edx, %eax20; CHECK-NEXT: addl $2138875574, %eax # imm = 0x7F7CA6B621; CHECK-NEXT: cmpl $2138875574, %eax # imm = 0x7F7CA6B622; CHECK-NEXT: setl %dl23; CHECK-NEXT: cmpl $-8608074, %eax # imm = 0xFF7CA6B624; CHECK-NEXT: setge %sil25; CHECK-NEXT: andb %dl, %sil26; CHECK-NEXT: movzbl %sil, %edx27; CHECK-NEXT: movslq %eax, %rsi28; CHECK-NEXT: movq %rsi, %rdi29; CHECK-NEXT: negl %edx30; CHECK-NEXT: subq %rax, %rdi31; CHECK-NEXT: xorl %eax, %eax32; CHECK-NEXT: testl $-2, %edx33; CHECK-NEXT: cmovneq %rax, %rdi34; CHECK-NEXT: testl %esi, %esi35; CHECK-NEXT: cmovnsq %rax, %rdi36; CHECK-NEXT: movq (%rcx), %rax37; CHECK-NEXT: subq %rdi, %rsi38; CHECK-NEXT: leaq -2138875574(%rax,%rsi), %rax39; CHECK-NEXT: movq %rax, (%rcx)40; CHECK-NEXT: retq41entry:42 %tmp103 = getelementptr inbounds [40 x i16], ptr %a, i64 0, i64 443 %tmp104 = load i16, ptr %tmp103, align 244 %tmp105 = sext i16 %tmp104 to i3245 %tmp106 = load i32, ptr %b, align 446 %tmp107 = sub nsw i32 4, %tmp10647 %tmp108 = load ptr, ptr %c, align 848 %tmp109 = sext i32 %tmp107 to i6449 %tmp110 = getelementptr inbounds i16, ptr %tmp108, i64 %tmp10950 %tmp111 = load i16, ptr %tmp110, align 151 %tmp112 = sext i16 %tmp111 to i3252 %tmp = mul i32 355244649, %tmp11253 %tmp1 = mul i32 %tmp, %tmp10554 %tmp2 = add i32 %tmp1, 213887557455 %tmp3 = add i32 %tmp2, 154699108856 %tmp4 = mul i32 %tmp3, 212248725757 %tmp5 = icmp sge i32 %tmp4, 213887557458 %tmp6 = icmp slt i32 %tmp4, -860807459 %tmp7 = or i1 %tmp5, %tmp660 %outSign = select i1 %tmp7, i32 1, i32 -161 %tmp8 = icmp slt i32 %tmp4, 062 %tmp9 = icmp eq i32 %outSign, 163 %tmp10 = and i1 %tmp8, %tmp964 %tmp11 = sext i32 %tmp4 to i6465 %tmp12 = add i64 %tmp11, 508979227924543515366 %tmp13 = sub i64 %tmp12, 213887557467 %tmp14 = zext i32 %tmp4 to i6468 %tmp15 = sub i64 %tmp11, %tmp1469 %tmp16 = select i1 %tmp10, i64 %tmp15, i64 070 %tmp17 = sub i64 %tmp13, %tmp1671 %tmp18 = mul i64 %tmp17, 454013315501355459572 %tmp19 = sub i64 %tmp18, 538658624403870485173 %tmp20 = add i64 %tmp19, -136805735811094721774 %tmp21 = mul i64 %tmp20, -42203740284085081775 %tmp115 = load i64, ptr %d, align 876 %alphaX = mul i64 468858157810230901, %tmp2177 %alphaXbetaY = add i64 %alphaX, %tmp11578 %transformed = add i64 %alphaXbetaY, 904014518298185247579 store i64 %transformed, ptr %d, align 880 ret void81}82