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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefixes=X863; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=X644 5define i32 @i32_zext_shift_i16_zext_i1(i1 %a0) nounwind {6; X86-LABEL: i32_zext_shift_i16_zext_i1:7; X86: # %bb.0:8; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax9; X86-NEXT: andl $1, %eax10; X86-NEXT: shll $5, %eax11; X86-NEXT: retl12;13; X64-LABEL: i32_zext_shift_i16_zext_i1:14; X64: # %bb.0:15; X64-NEXT: movl %edi, %eax16; X64-NEXT: andl $1, %eax17; X64-NEXT: shll $5, %eax18; X64-NEXT: retq19 %t0 = zext i1 %a0 to i1620 %t1 = shl i16 %t0, 521 %t2 = zext i16 %t1 to i3222 ret i32 %t223}24 25define i32 @i32_zext_shift_i16_zext_i8(i8 %a0) nounwind {26; X86-LABEL: i32_zext_shift_i16_zext_i8:27; X86: # %bb.0:28; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax29; X86-NEXT: shll $5, %eax30; X86-NEXT: retl31;32; X64-LABEL: i32_zext_shift_i16_zext_i8:33; X64: # %bb.0:34; X64-NEXT: movzbl %dil, %eax35; X64-NEXT: shll $5, %eax36; X64-NEXT: retq37 %t0 = zext i8 %a0 to i1638 %t1 = shl i16 %t0, 539 %t2 = zext i16 %t1 to i3240 ret i32 %t241}42 43define i64 @i64_zext_shift_i16_zext_i8(i8 %a0) nounwind {44; X86-LABEL: i64_zext_shift_i16_zext_i8:45; X86: # %bb.0:46; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax47; X86-NEXT: shll $5, %eax48; X86-NEXT: xorl %edx, %edx49; X86-NEXT: retl50;51; X64-LABEL: i64_zext_shift_i16_zext_i8:52; X64: # %bb.0:53; X64-NEXT: movzbl %dil, %eax54; X64-NEXT: shll $5, %eax55; X64-NEXT: retq56 %t0 = zext i8 %a0 to i1657 %t1 = shl i16 %t0, 558 %t2 = zext i16 %t1 to i6459 ret i64 %t260}61 62define i64 @i64_zext_shift_i32_zext_i8(i8 %a0) nounwind {63; X86-LABEL: i64_zext_shift_i32_zext_i8:64; X86: # %bb.0:65; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax66; X86-NEXT: shll $3, %eax67; X86-NEXT: xorl %edx, %edx68; X86-NEXT: retl69;70; X64-LABEL: i64_zext_shift_i32_zext_i8:71; X64: # %bb.0:72; X64-NEXT: movzbl %dil, %eax73; X64-NEXT: shll $3, %eax74; X64-NEXT: retq75 %t0 = zext i8 %a0 to i3276 %t1 = shl i32 %t0, 377 %t2 = zext i32 %t1 to i6478 ret i64 %t279}80 81define i64 @i64_zext_shift_i32_zext_i16(i16 %a0) nounwind {82; X86-LABEL: i64_zext_shift_i32_zext_i16:83; X86: # %bb.0:84; X86-NEXT: movzwl {{[0-9]+}}(%esp), %eax85; X86-NEXT: shll $5, %eax86; X86-NEXT: xorl %edx, %edx87; X86-NEXT: retl88;89; X64-LABEL: i64_zext_shift_i32_zext_i16:90; X64: # %bb.0:91; X64-NEXT: movzwl %di, %eax92; X64-NEXT: shll $5, %eax93; X64-NEXT: retq94 %t0 = zext i16 %a0 to i3295 %t1 = shl i32 %t0, 596 %t2 = zext i32 %t1 to i6497 ret i64 %t298}99 100define i128 @i128_zext_shift_i64_zext_i8(i8 %a0) nounwind {101; X86-LABEL: i128_zext_shift_i64_zext_i8:102; X86: # %bb.0:103; X86-NEXT: movl {{[0-9]+}}(%esp), %eax104; X86-NEXT: movzbl {{[0-9]+}}(%esp), %ecx105; X86-NEXT: shll $4, %ecx106; X86-NEXT: movl %ecx, (%eax)107; X86-NEXT: movl $0, 12(%eax)108; X86-NEXT: movl $0, 8(%eax)109; X86-NEXT: movl $0, 4(%eax)110; X86-NEXT: retl $4111;112; X64-LABEL: i128_zext_shift_i64_zext_i8:113; X64: # %bb.0:114; X64-NEXT: movzbl %dil, %eax115; X64-NEXT: shll $4, %eax116; X64-NEXT: xorl %edx, %edx117; X64-NEXT: retq118 %t0 = zext i8 %a0 to i64119 %t1 = shl i64 %t0, 4120 %t2 = zext i64 %t1 to i128121 ret i128 %t2122}123 124define i128 @i128_zext_shift_i64_zext_i16(i16 %a0) nounwind {125; X86-LABEL: i128_zext_shift_i64_zext_i16:126; X86: # %bb.0:127; X86-NEXT: movl {{[0-9]+}}(%esp), %eax128; X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx129; X86-NEXT: shll $7, %ecx130; X86-NEXT: movl %ecx, (%eax)131; X86-NEXT: movl $0, 12(%eax)132; X86-NEXT: movl $0, 8(%eax)133; X86-NEXT: movl $0, 4(%eax)134; X86-NEXT: retl $4135;136; X64-LABEL: i128_zext_shift_i64_zext_i16:137; X64: # %bb.0:138; X64-NEXT: movzwl %di, %eax139; X64-NEXT: shll $7, %eax140; X64-NEXT: xorl %edx, %edx141; X64-NEXT: retq142 %t0 = zext i16 %a0 to i64143 %t1 = shl i64 %t0,7144 %t2 = zext i64 %t1 to i128145 ret i128 %t2146}147