51 lines · plain
1; RUN: llc < %s -mtriple=xcore | FileCheck %s2; RUN: llc < %s -mtriple=xcore -regalloc=basic | FileCheck %s3define i64 @umul_lohi(i32 %a, i32 %b) {4entry:5 %0 = zext i32 %a to i646 %1 = zext i32 %b to i647 %2 = mul i64 %1, %08 ret i64 %29}10; CHECK-LABEL: umul_lohi:11; CHECK: ldc [[REG:r[0-9]+]], 012; CHECK-NEXT: lmul {{.*}}, [[REG]], [[REG]]13; CHECK-NEXT: retsp 014 15define i64 @smul_lohi(i32 %a, i32 %b) {16entry:17 %0 = sext i32 %a to i6418 %1 = sext i32 %b to i6419 %2 = mul i64 %1, %020 ret i64 %221}22; CHECK-LABEL: smul_lohi:23; CHECK: ldc24; CHECK-NEXT: mov25; CHECK-NEXT: maccs26; CHECK: retsp 027 28define i64 @mul64(i64 %a, i64 %b) {29entry:30 %0 = mul i64 %a, %b31 ret i64 %032}33; CHECK-LABEL: mul64:34; CHECK: ldc35; CHECK-NEXT: lmul36; CHECK-NEXT: mul37; CHECK-NEXT: lmul38 39define i64 @mul64_2(i64 %a, i32 %b) {40entry:41 %0 = zext i32 %b to i6442 %1 = mul i64 %a, %043 ret i64 %144}45; CHECK-LABEL: mul64_2:46; CHECK: ldc47; CHECK-NEXT: lmul48; CHECK-NEXT: mul49; CHECK-NEXT: add r1,50; CHECK: retsp 051