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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=xtensa -mattr=+fp -verify-machineinstrs < %s | FileCheck -check-prefix=XTENSA %s3 4define float @fadd_s(float %a, float %b) nounwind {5; XTENSA-LABEL: fadd_s:6; XTENSA: # %bb.0:7; XTENSA-NEXT: wfr f8, a38; XTENSA-NEXT: wfr f9, a29; XTENSA-NEXT: add.s f8, f9, f810; XTENSA-NEXT: rfr a2, f811; XTENSA-NEXT: ret12 %res = fadd float %a, %b13 ret float %res14}15 16define float @fsub_s(float %a, float %b) nounwind {17; XTENSA-LABEL: fsub_s:18; XTENSA: # %bb.0:19; XTENSA-NEXT: wfr f8, a320; XTENSA-NEXT: wfr f9, a221; XTENSA-NEXT: sub.s f8, f9, f822; XTENSA-NEXT: rfr a2, f823; XTENSA-NEXT: ret24 %res = fsub float %a, %b25 ret float %res26}27 28define float @fmul_s(float %a, float %b) nounwind {29; XTENSA-LABEL: fmul_s:30; XTENSA: # %bb.0:31; XTENSA-NEXT: wfr f8, a332; XTENSA-NEXT: wfr f9, a233; XTENSA-NEXT: mul.s f8, f9, f834; XTENSA-NEXT: rfr a2, f835; XTENSA-NEXT: ret36 %res = fmul float %a, %b37 ret float %res38}39 40define float @fdiv_s(float %a, float %b) nounwind {41; XTENSA-LABEL: fdiv_s:42; XTENSA: # %bb.0:43; XTENSA-NEXT: addi a8, a1, -1644; XTENSA-NEXT: or a1, a8, a845; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill46; XTENSA-NEXT: l32r a8, .LCPI3_047; XTENSA-NEXT: callx0 a848; XTENSA-NEXT: l32i a0, a1, 0 # 4-byte Folded Reload49; XTENSA-NEXT: addi a8, a1, 1650; XTENSA-NEXT: or a1, a8, a851; XTENSA-NEXT: ret52 %res = fdiv float %a, %b53 ret float %res54}55 56declare float @llvm.sqrt.f32(float)57 58define float @fsqrt_s(float %a) nounwind {59; XTENSA-LABEL: fsqrt_s:60; XTENSA: # %bb.0:61; XTENSA-NEXT: addi a8, a1, -1662; XTENSA-NEXT: or a1, a8, a863; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill64; XTENSA-NEXT: l32r a8, .LCPI4_065; XTENSA-NEXT: callx0 a866; XTENSA-NEXT: l32i a0, a1, 0 # 4-byte Folded Reload67; XTENSA-NEXT: addi a8, a1, 1668; XTENSA-NEXT: or a1, a8, a869; XTENSA-NEXT: ret70 %res = call float @llvm.sqrt.f32(float %a)71 ret float %res72}73 74declare float @llvm.fabs.f32(float)75 76define float @fabs_s(float %a, float %b) nounwind {77; XTENSA-LABEL: fabs_s:78; XTENSA: # %bb.0:79; XTENSA-NEXT: wfr f8, a380; XTENSA-NEXT: wfr f9, a281; XTENSA-NEXT: add.s f8, f9, f882; XTENSA-NEXT: abs.s f9, f883; XTENSA-NEXT: add.s f8, f9, f884; XTENSA-NEXT: rfr a2, f885; XTENSA-NEXT: ret86 %fa = fadd float %a, %b87 %call_res = call float @llvm.fabs.f32(float %fa)88 %res = fadd float %call_res, %fa89 ret float %res90}91 92declare float @llvm.minnum.f32(float, float)93 94define float @fmin_s(float %a, float %b) nounwind {95; XTENSA-LABEL: fmin_s:96; XTENSA: # %bb.0:97; XTENSA-NEXT: addi a8, a1, -1698; XTENSA-NEXT: or a1, a8, a899; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill100; XTENSA-NEXT: l32r a8, .LCPI6_0101; XTENSA-NEXT: callx0 a8102; XTENSA-NEXT: l32i a0, a1, 0 # 4-byte Folded Reload103; XTENSA-NEXT: addi a8, a1, 16104; XTENSA-NEXT: or a1, a8, a8105; XTENSA-NEXT: ret106 %res = call float @llvm.minnum.f32(float %a, float %b)107 ret float %res108}109 110declare float @llvm.maxnum.f32(float, float)111 112define float @fmax_s(float %a, float %b) nounwind {113; XTENSA-LABEL: fmax_s:114; XTENSA: # %bb.0:115; XTENSA-NEXT: addi a8, a1, -16116; XTENSA-NEXT: or a1, a8, a8117; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill118; XTENSA-NEXT: l32r a8, .LCPI7_0119; XTENSA-NEXT: callx0 a8120; XTENSA-NEXT: l32i a0, a1, 0 # 4-byte Folded Reload121; XTENSA-NEXT: addi a8, a1, 16122; XTENSA-NEXT: or a1, a8, a8123; XTENSA-NEXT: ret124 %res = call float @llvm.maxnum.f32(float %a, float %b)125 ret float %res126}127 128declare float @llvm.fma.f32(float, float, float)129 130define float @fmadd_s(float %a, float %b, float %c) nounwind {131; XTENSA-LABEL: fmadd_s:132; XTENSA: # %bb.0:133; XTENSA-NEXT: wfr f8, a3134; XTENSA-NEXT: wfr f9, a2135; XTENSA-NEXT: wfr f10, a4136; XTENSA-NEXT: madd.s f10, f9, f8137; XTENSA-NEXT: rfr a2, f10138; XTENSA-NEXT: ret139 %res = call float @llvm.fma.f32(float %a, float %b, float %c)140 ret float %res141}142 143define float @fmsub_s(float %a, float %b, float %c) nounwind {144; XTENSA-LABEL: fmsub_s:145; XTENSA: # %bb.0:146; XTENSA-NEXT: l32r a8, .LCPI9_0147; XTENSA-NEXT: wfr f8, a8148; XTENSA-NEXT: wfr f9, a4149; XTENSA-NEXT: add.s f8, f9, f8150; XTENSA-NEXT: neg.s f8, f8151; XTENSA-NEXT: wfr f9, a3152; XTENSA-NEXT: wfr f10, a2153; XTENSA-NEXT: madd.s f8, f10, f9154; XTENSA-NEXT: rfr a2, f8155; XTENSA-NEXT: ret156 %c_ = fadd float 0.0, %c ; avoid negation using xor157 %negc = fsub float -0.0, %c_158 %res = call float @llvm.fma.f32(float %a, float %b, float %negc)159 ret float %res160}161 162define float @fnmadd_s(float %a, float %b, float %c) nounwind {163; XTENSA-LABEL: fnmadd_s:164; XTENSA: # %bb.0:165; XTENSA-NEXT: l32r a8, .LCPI10_0166; XTENSA-NEXT: wfr f8, a8167; XTENSA-NEXT: wfr f9, a2168; XTENSA-NEXT: add.s f9, f9, f8169; XTENSA-NEXT: neg.s f9, f9170; XTENSA-NEXT: wfr f10, a4171; XTENSA-NEXT: add.s f8, f10, f8172; XTENSA-NEXT: neg.s f8, f8173; XTENSA-NEXT: wfr f10, a3174; XTENSA-NEXT: madd.s f8, f9, f10175; XTENSA-NEXT: rfr a2, f8176; XTENSA-NEXT: ret177 %a_ = fadd float 0.0, %a178 %c_ = fadd float 0.0, %c179 %nega = fsub float -0.0, %a_180 %negc = fsub float -0.0, %c_181 %res = call float @llvm.fma.f32(float %nega, float %b, float %negc)182 ret float %res183}184 185define float @fnmadd_s_2(float %a, float %b, float %c) nounwind {186; XTENSA-LABEL: fnmadd_s_2:187; XTENSA: # %bb.0:188; XTENSA-NEXT: l32r a8, .LCPI11_0189; XTENSA-NEXT: wfr f8, a8190; XTENSA-NEXT: wfr f9, a3191; XTENSA-NEXT: add.s f9, f9, f8192; XTENSA-NEXT: neg.s f9, f9193; XTENSA-NEXT: wfr f10, a4194; XTENSA-NEXT: add.s f8, f10, f8195; XTENSA-NEXT: neg.s f8, f8196; XTENSA-NEXT: wfr f10, a2197; XTENSA-NEXT: madd.s f8, f10, f9198; XTENSA-NEXT: rfr a2, f8199; XTENSA-NEXT: ret200 %b_ = fadd float 0.0, %b201 %c_ = fadd float 0.0, %c202 %negb = fsub float -0.0, %b_203 %negc = fsub float -0.0, %c_204 %res = call float @llvm.fma.f32(float %a, float %negb, float %negc)205 ret float %res206}207 208define float @fnmadd_s_3(float %a, float %b, float %c) nounwind {209; XTENSA-LABEL: fnmadd_s_3:210; XTENSA: # %bb.0:211; XTENSA-NEXT: wfr f8, a3212; XTENSA-NEXT: wfr f9, a2213; XTENSA-NEXT: wfr f10, a4214; XTENSA-NEXT: madd.s f10, f9, f8215; XTENSA-NEXT: rfr a8, f10216; XTENSA-NEXT: l32r a9, .LCPI12_0217; XTENSA-NEXT: xor a2, a8, a9218; XTENSA-NEXT: ret219 %res = call float @llvm.fma.f32(float %a, float %b, float %c)220 %neg = fneg float %res221 ret float %neg222}223 224define float @fnmadd_nsz(float %a, float %b, float %c) nounwind {225; XTENSA-LABEL: fnmadd_nsz:226; XTENSA: # %bb.0:227; XTENSA-NEXT: wfr f8, a3228; XTENSA-NEXT: wfr f9, a2229; XTENSA-NEXT: wfr f10, a4230; XTENSA-NEXT: madd.s f10, f9, f8231; XTENSA-NEXT: rfr a8, f10232; XTENSA-NEXT: l32r a9, .LCPI13_0233; XTENSA-NEXT: xor a2, a8, a9234; XTENSA-NEXT: ret235 %res = call nsz float @llvm.fma.f32(float %a, float %b, float %c)236 %neg = fneg nsz float %res237 ret float %neg238}239 240define float @fnmsub_s(float %a, float %b, float %c) nounwind {241; XTENSA-LABEL: fnmsub_s:242; XTENSA: # %bb.0:243; XTENSA-NEXT: l32r a8, .LCPI14_0244; XTENSA-NEXT: wfr f8, a8245; XTENSA-NEXT: wfr f9, a2246; XTENSA-NEXT: add.s f8, f9, f8247; XTENSA-NEXT: neg.s f8, f8248; XTENSA-NEXT: wfr f9, a3249; XTENSA-NEXT: wfr f10, a4250; XTENSA-NEXT: madd.s f10, f8, f9251; XTENSA-NEXT: rfr a2, f10252; XTENSA-NEXT: ret253 %a_ = fadd float 0.0, %a254 %nega = fsub float -0.0, %a_255 %res = call float @llvm.fma.f32(float %nega, float %b, float %c)256 ret float %res257}258 259define float @fnmsub_s_2(float %a, float %b, float %c) nounwind {260; XTENSA-LABEL: fnmsub_s_2:261; XTENSA: # %bb.0:262; XTENSA-NEXT: l32r a8, .LCPI15_0263; XTENSA-NEXT: wfr f8, a8264; XTENSA-NEXT: wfr f9, a3265; XTENSA-NEXT: add.s f8, f9, f8266; XTENSA-NEXT: neg.s f8, f8267; XTENSA-NEXT: wfr f9, a2268; XTENSA-NEXT: wfr f10, a4269; XTENSA-NEXT: madd.s f10, f9, f8270; XTENSA-NEXT: rfr a2, f10271; XTENSA-NEXT: ret272 %b_ = fadd float 0.0, %b273 %negb = fsub float -0.0, %b_274 %res = call float @llvm.fma.f32(float %a, float %negb, float %c)275 ret float %res276}277 278define float @fmadd_s_contract(float %a, float %b, float %c) nounwind {279; XTENSA-LABEL: fmadd_s_contract:280; XTENSA: # %bb.0:281; XTENSA-NEXT: wfr f8, a3282; XTENSA-NEXT: wfr f9, a2283; XTENSA-NEXT: mul.s f8, f9, f8284; XTENSA-NEXT: wfr f9, a4285; XTENSA-NEXT: add.s f8, f8, f9286; XTENSA-NEXT: rfr a2, f8287; XTENSA-NEXT: ret288 %fm = fmul contract float %a, %b289 %res = fadd contract float %fm, %c290 ret float %res291}292 293define float @fmsub_s_contract(float %a, float %b, float %c) nounwind {294; XTENSA-LABEL: fmsub_s_contract:295; XTENSA: # %bb.0:296; XTENSA-NEXT: l32r a8, .LCPI17_0297; XTENSA-NEXT: wfr f8, a8298; XTENSA-NEXT: wfr f9, a4299; XTENSA-NEXT: add.s f8, f9, f8300; XTENSA-NEXT: wfr f9, a3301; XTENSA-NEXT: wfr f10, a2302; XTENSA-NEXT: mul.s f9, f10, f9303; XTENSA-NEXT: sub.s f8, f9, f8304; XTENSA-NEXT: rfr a2, f8305; XTENSA-NEXT: ret306 %c_ = fadd float 0.0, %c ; avoid negation using xor307 %fm = fmul contract float %a, %b308 %res = fsub contract float %fm, %c_309 ret float %res310}311 312define float @fnmadd_s_contract(float %a, float %b, float %c) nounwind {313; XTENSA-LABEL: fnmadd_s_contract:314; XTENSA: # %bb.0:315; XTENSA-NEXT: l32r a8, .LCPI18_0316; XTENSA-NEXT: wfr f8, a8317; XTENSA-NEXT: wfr f9, a3318; XTENSA-NEXT: add.s f9, f9, f8319; XTENSA-NEXT: wfr f10, a2320; XTENSA-NEXT: add.s f10, f10, f8321; XTENSA-NEXT: mul.s f9, f10, f9322; XTENSA-NEXT: neg.s f9, f9323; XTENSA-NEXT: wfr f10, a4324; XTENSA-NEXT: add.s f8, f10, f8325; XTENSA-NEXT: sub.s f8, f9, f8326; XTENSA-NEXT: rfr a2, f8327; XTENSA-NEXT: ret328 %a_ = fadd float 0.0, %a ; avoid negation using xor329 %b_ = fadd float 0.0, %b ; avoid negation using xor330 %c_ = fadd float 0.0, %c ; avoid negation using xor331 %fm = fmul contract float %a_, %b_332 %fn = fneg float %fm333 %res = fsub contract float %fn, %c_334 ret float %res335}336 337define float @fnmsub_s_contract(float %a, float %b, float %c) nounwind {338; XTENSA-LABEL: fnmsub_s_contract:339; XTENSA: # %bb.0:340; XTENSA-NEXT: l32r a8, .LCPI19_0341; XTENSA-NEXT: wfr f8, a8342; XTENSA-NEXT: wfr f9, a3343; XTENSA-NEXT: add.s f9, f9, f8344; XTENSA-NEXT: wfr f10, a2345; XTENSA-NEXT: add.s f8, f10, f8346; XTENSA-NEXT: mul.s f8, f8, f9347; XTENSA-NEXT: wfr f9, a4348; XTENSA-NEXT: sub.s f8, f9, f8349; XTENSA-NEXT: rfr a2, f8350; XTENSA-NEXT: ret351 %a_ = fadd float 0.0, %a ; avoid negation using xor352 %b_ = fadd float 0.0, %b ; avoid negation using xor353 %fm = fmul contract float %a_, %b_354 %res = fsub contract float %c, %fm355 ret float %res356}357 358declare float @llvm.powi.f32(float, i32)359 360define float @powi_f32(float %a, i32 %b) nounwind {361; XTENSA-LABEL: powi_f32:362; XTENSA: # %bb.0:363; XTENSA-NEXT: addi a8, a1, -16364; XTENSA-NEXT: or a1, a8, a8365; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill366; XTENSA-NEXT: l32r a8, .LCPI20_0367; XTENSA-NEXT: callx0 a8368; XTENSA-NEXT: l32i a0, a1, 0 # 4-byte Folded Reload369; XTENSA-NEXT: addi a8, a1, 16370; XTENSA-NEXT: or a1, a8, a8371; XTENSA-NEXT: ret372 373 %res = call float @llvm.powi.f32(float %a, i32 %b)374 ret float %res375}376 377declare float @llvm.sin.f32(float)378 379define float @sin_f32(float %a) nounwind {380; XTENSA-LABEL: sin_f32:381; XTENSA: # %bb.0:382; XTENSA-NEXT: addi a8, a1, -16383; XTENSA-NEXT: or a1, a8, a8384; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill385; XTENSA-NEXT: l32r a8, .LCPI21_0386; XTENSA-NEXT: callx0 a8387; XTENSA-NEXT: l32i a0, a1, 0 # 4-byte Folded Reload388; XTENSA-NEXT: addi a8, a1, 16389; XTENSA-NEXT: or a1, a8, a8390; XTENSA-NEXT: ret391 %res = call float @llvm.sin.f32(float %a)392 ret float %res393}394 395declare float @llvm.cos.f32(float)396 397define float @cos_f32(float %a) nounwind {398; XTENSA-LABEL: cos_f32:399; XTENSA: # %bb.0:400; XTENSA-NEXT: addi a8, a1, -16401; XTENSA-NEXT: or a1, a8, a8402; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill403; XTENSA-NEXT: l32r a8, .LCPI22_0404; XTENSA-NEXT: callx0 a8405; XTENSA-NEXT: l32i a0, a1, 0 # 4-byte Folded Reload406; XTENSA-NEXT: addi a8, a1, 16407; XTENSA-NEXT: or a1, a8, a8408; XTENSA-NEXT: ret409 %res = call float @llvm.cos.f32(float %a)410 ret float %res411}412declare float @llvm.exp.f32(float)413 414define float @exp_f32(float %a) nounwind {415; XTENSA-LABEL: exp_f32:416; XTENSA: # %bb.0:417; XTENSA-NEXT: addi a8, a1, -16418; XTENSA-NEXT: or a1, a8, a8419; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill420; XTENSA-NEXT: l32r a8, .LCPI23_0421; XTENSA-NEXT: callx0 a8422; XTENSA-NEXT: l32i a0, a1, 0 # 4-byte Folded Reload423; XTENSA-NEXT: addi a8, a1, 16424; XTENSA-NEXT: or a1, a8, a8425; XTENSA-NEXT: ret426 %res = call float @llvm.exp.f32(float %a)427 ret float %res428}429 430define float @log_f32(float %a) nounwind {431; XTENSA-LABEL: log_f32:432; XTENSA: # %bb.0:433; XTENSA-NEXT: addi a8, a1, -16434; XTENSA-NEXT: or a1, a8, a8435; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill436; XTENSA-NEXT: l32r a8, .LCPI24_0437; XTENSA-NEXT: callx0 a8438; XTENSA-NEXT: l32i a0, a1, 0 # 4-byte Folded Reload439; XTENSA-NEXT: addi a8, a1, 16440; XTENSA-NEXT: or a1, a8, a8441; XTENSA-NEXT: ret442 %res = call float @llvm.log.f32(float %a)443 ret float %res444}445 446declare float @llvm.log10.f32(float)447 448define float @log10_f32(float %a) nounwind {449; XTENSA-LABEL: log10_f32:450; XTENSA: # %bb.0:451; XTENSA-NEXT: addi a8, a1, -16452; XTENSA-NEXT: or a1, a8, a8453; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill454; XTENSA-NEXT: l32r a8, .LCPI25_0455; XTENSA-NEXT: callx0 a8456; XTENSA-NEXT: l32i a0, a1, 0 # 4-byte Folded Reload457; XTENSA-NEXT: addi a8, a1, 16458; XTENSA-NEXT: or a1, a8, a8459; XTENSA-NEXT: ret460 %res = call float @llvm.log10.f32(float %a)461 ret float %res462}463 464declare float @llvm.log2.f32(float)465 466define float @log2_f32(float %a) nounwind {467; XTENSA-LABEL: log2_f32:468; XTENSA: # %bb.0:469; XTENSA-NEXT: addi a8, a1, -16470; XTENSA-NEXT: or a1, a8, a8471; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill472; XTENSA-NEXT: l32r a8, .LCPI26_0473; XTENSA-NEXT: callx0 a8474; XTENSA-NEXT: l32i a0, a1, 0 # 4-byte Folded Reload475; XTENSA-NEXT: addi a8, a1, 16476; XTENSA-NEXT: or a1, a8, a8477; XTENSA-NEXT: ret478 %res = call float @llvm.log2.f32(float %a)479 ret float %res480}481 482declare float @llvm.floor.f32(float)483 484define float @floor_f32(float %a) nounwind {485; XTENSA-LABEL: floor_f32:486; XTENSA: # %bb.0:487; XTENSA-NEXT: addi a8, a1, -16488; XTENSA-NEXT: or a1, a8, a8489; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill490; XTENSA-NEXT: l32r a8, .LCPI27_0491; XTENSA-NEXT: callx0 a8492; XTENSA-NEXT: l32i a0, a1, 0 # 4-byte Folded Reload493; XTENSA-NEXT: addi a8, a1, 16494; XTENSA-NEXT: or a1, a8, a8495; XTENSA-NEXT: ret496 %res = call float @llvm.floor.f32(float %a)497 ret float %res498}499 500declare float @llvm.ceil.f32(float)501 502define float @ceil_f32(float %a) nounwind {503; XTENSA-LABEL: ceil_f32:504; XTENSA: # %bb.0:505; XTENSA-NEXT: addi a8, a1, -16506; XTENSA-NEXT: or a1, a8, a8507; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill508; XTENSA-NEXT: l32r a8, .LCPI28_0509; XTENSA-NEXT: callx0 a8510; XTENSA-NEXT: l32i a0, a1, 0 # 4-byte Folded Reload511; XTENSA-NEXT: addi a8, a1, 16512; XTENSA-NEXT: or a1, a8, a8513; XTENSA-NEXT: ret514 %res = call float @llvm.ceil.f32(float %a)515 ret float %res516}517declare float @llvm.rint.f32(float)518 519define float @rint_f32(float %a) nounwind {520; XTENSA-LABEL: rint_f32:521; XTENSA: # %bb.0:522; XTENSA-NEXT: addi a8, a1, -16523; XTENSA-NEXT: or a1, a8, a8524; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill525; XTENSA-NEXT: l32r a8, .LCPI29_0526; XTENSA-NEXT: callx0 a8527; XTENSA-NEXT: l32i a0, a1, 0 # 4-byte Folded Reload528; XTENSA-NEXT: addi a8, a1, 16529; XTENSA-NEXT: or a1, a8, a8530; XTENSA-NEXT: ret531 %res = call float @llvm.rint.f32(float %a)532 ret float %res533}534 535declare float @llvm.nearbyint.f32(float)536 537define float @nearbyint_f32(float %a) nounwind {538; XTENSA-LABEL: nearbyint_f32:539; XTENSA: # %bb.0:540; XTENSA-NEXT: addi a8, a1, -16541; XTENSA-NEXT: or a1, a8, a8542; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill543; XTENSA-NEXT: l32r a8, .LCPI30_0544; XTENSA-NEXT: callx0 a8545; XTENSA-NEXT: l32i a0, a1, 0 # 4-byte Folded Reload546; XTENSA-NEXT: addi a8, a1, 16547; XTENSA-NEXT: or a1, a8, a8548; XTENSA-NEXT: ret549 %res = call float @llvm.nearbyint.f32(float %a)550 ret float %res551}552 553declare float @llvm.round.f32(float)554 555define float @round_f32(float %a) nounwind {556; XTENSA-LABEL: round_f32:557; XTENSA: # %bb.0:558; XTENSA-NEXT: addi a8, a1, -16559; XTENSA-NEXT: or a1, a8, a8560; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill561; XTENSA-NEXT: l32r a8, .LCPI31_0562; XTENSA-NEXT: callx0 a8563; XTENSA-NEXT: l32i a0, a1, 0 # 4-byte Folded Reload564; XTENSA-NEXT: addi a8, a1, 16565; XTENSA-NEXT: or a1, a8, a8566; XTENSA-NEXT: ret567 %res = call float @llvm.round.f32(float %a)568 ret float %res569}570 571define float @fneg_s(float %a) nounwind {572; XTENSA-LABEL: fneg_s:573; XTENSA: # %bb.0:574; XTENSA-NEXT: l32r a8, .LCPI32_0575; XTENSA-NEXT: and a2, a2, a8576; XTENSA-NEXT: ret577 %res = call float @llvm.fabs.f32(float %a)578 ret float %res579}580 581define i32 @fptosi(float %f) {582; XTENSA-LABEL: fptosi:583; XTENSA: .cfi_startproc584; XTENSA-NEXT: # %bb.0:585; XTENSA-NEXT: wfr f8, a2586; XTENSA-NEXT: trunc.s a2, f8, 0587; XTENSA-NEXT: ret588 %conv = fptosi float %f to i32589 ret i32 %conv590}591 592define i32 @fptoui(float %f) {593; XTENSA-LABEL: fptoui:594; XTENSA: .cfi_startproc595; XTENSA-NEXT: # %bb.0:596; XTENSA-NEXT: wfr f8, a2597; XTENSA-NEXT: utrunc.s a2, f8, 0598; XTENSA-NEXT: ret599 %conv = fptoui float %f to i32600 ret i32 %conv601}602 603define float @copysign_f32(float %a, float %b) {604; XTENSA-LABEL: copysign_f32:605; XTENSA: .cfi_startproc606; XTENSA-NEXT: # %bb.0: # %entry607; XTENSA-NEXT: l32r a8, .LCPI35_0608; XTENSA-NEXT: and a8, a3, a8609; XTENSA-NEXT: l32r a9, .LCPI35_1610; XTENSA-NEXT: and a9, a2, a9611; XTENSA-NEXT: wfr f8, a9612; XTENSA-NEXT: movi a9, 0613; XTENSA-NEXT: beq a8, a9, .LBB35_2614; XTENSA-NEXT: # %bb.1:615; XTENSA-NEXT: neg.s f8, f8616; XTENSA-NEXT: .LBB35_2: # %entry617; XTENSA-NEXT: rfr a2, f8618; XTENSA-NEXT: ret619entry:620 %c = call float @llvm.copysign.f32(float %a, float %b)621 ret float %c622}623