41 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=xtensa < %s \3; RUN: | FileCheck -check-prefix=XTENSA %s4 5@gi = external global i326 7define i32 @constraint_r(i32 %a) {8; XTENSA-LABEL: constraint_r:9; XTENSA: l32r a8, .LCPI0_010; XTENSA-NEXT: l32i a8, a8, 011; XTENSA-NEXT: #APP12; XTENSA-NEXT: add a2, a2, a813; XTENSA-NEXT: #NO_APP14; XTENSA-NEXT: ret15 %1 = load i32, ptr @gi16 %2 = tail call i32 asm "add $0, $1, $2", "=r,r,r"(i32 %a, i32 %1)17 ret i32 %218}19 20define i32 @constraint_i(i32 %a) {21; XTENSA-LABEL: constraint_i:22; XTENSA: #APP23; XTENSA-NEXT: addi a2, a2, 11324; XTENSA-NEXT: #NO_APP25; XTENSA-NEXT: ret26 %1 = load i32, ptr @gi27 %2 = tail call i32 asm "addi $0, $1, $2", "=r,r,i"(i32 %a, i32 113)28 ret i32 %229}30 31define i32 @explicit_register_a3(i32 %a) nounwind {32; XTENSA-LABEL: explicit_register_a3:33; XTENSA: or a3, a2, a234; XTENSA-NEXT: #APP35; XTENSA-NEXT: addi a2, a3, 136; XTENSA-NEXT: #NO_APP37; XTENSA-NEXT: ret38 %1 = tail call i32 asm "addi $0, $1, 1", "=r,{a3}"(i32 %a)39 ret i32 %140}41