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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=xtensa -verify-machineinstrs < %s \3; RUN: | FileCheck -check-prefix=XTENSA %s4; RUN: llc -mtriple=xtensa -mattr=+div32 -verify-machineinstrs < %s \5; RUN: | FileCheck -check-prefix=XTENSA-DIV %s6 7define i32 @srem(i32 signext %a0, i32 signext %a1) nounwind readnone {8; XTENSA-LABEL: srem:9; XTENSA: # %bb.0: # %entry10; XTENSA-NEXT: addi a8, a1, -1611; XTENSA-NEXT: or a1, a8, a812; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill13; XTENSA-NEXT: l32r a8, .LCPI0_014; XTENSA-NEXT: callx0 a815; XTENSA-NEXT: l32i a0, a1, 0 # 4-byte Folded Reload16; XTENSA-NEXT: addi a8, a1, 1617; XTENSA-NEXT: or a1, a8, a818; XTENSA-NEXT: ret19;20; XTENSA-DIV-LABEL: srem:21; XTENSA-DIV: # %bb.0: # %entry22; XTENSA-DIV-NEXT: rems a2, a2, a323; XTENSA-DIV-NEXT: ret24entry:25 %rem = srem i32 %a0, %a126 ret i32 %rem27}28 29define i32 @urem(i32 signext %a0, i32 signext %a1) nounwind readnone {30; XTENSA-LABEL: urem:31; XTENSA: # %bb.0: # %entry32; XTENSA-NEXT: addi a8, a1, -1633; XTENSA-NEXT: or a1, a8, a834; XTENSA-NEXT: s32i a0, a1, 0 # 4-byte Folded Spill35; XTENSA-NEXT: l32r a8, .LCPI1_036; XTENSA-NEXT: callx0 a837; XTENSA-NEXT: l32i a0, a1, 0 # 4-byte Folded Reload38; XTENSA-NEXT: addi a8, a1, 1639; XTENSA-NEXT: or a1, a8, a840; XTENSA-NEXT: ret41;42; XTENSA-DIV-LABEL: urem:43; XTENSA-DIV: # %bb.0: # %entry44; XTENSA-DIV-NEXT: remu a2, a2, a345; XTENSA-DIV-NEXT: ret46entry:47 %rem = urem i32 %a0, %a148 ret i32 %rem49}50