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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=xtensa -verify-machineinstrs < %s \3; RUN: | FileCheck -check-prefix=XTENSA %s4 5define i32 @rotl_32(i32 %x, i32 %y) nounwind {6; XTENSA-LABEL: rotl_32:7; XTENSA: ssl a38; XTENSA-NEXT: sll a8, a29; XTENSA-NEXT: movi a9, 3210; XTENSA-NEXT: sub a9, a9, a311; XTENSA-NEXT: ssr a912; XTENSA-NEXT: srl a9, a213; XTENSA-NEXT: or a2, a8, a914; XTENSA-NEXT: ret15 %z = sub i32 32, %y16 %b = shl i32 %x, %y17 %c = lshr i32 %x, %z18 %d = or i32 %b, %c19 ret i32 %d20}21 22define i32 @rotr_32(i32 %x, i32 %y) nounwind {23; XTENSA-LABEL: rotr_32:24; XTENSA: ssr a325; XTENSA-NEXT: srl a8, a226; XTENSA-NEXT: movi a9, 3227; XTENSA-NEXT: sub a9, a9, a328; XTENSA-NEXT: ssl a929; XTENSA-NEXT: sll a9, a230; XTENSA-NEXT: or a2, a8, a931; XTENSA-NEXT: ret32 %z = sub i32 32, %y33 %b = lshr i32 %x, %y34 %c = shl i32 %x, %z35 %d = or i32 %b, %c36 ret i32 %d37}38 39define i64 @rotl_64(i64 %x, i64 %y) nounwind {40; XTENSA-LABEL: rotl_64:41; XTENSA: movi a8, 6442; XTENSA-NEXT: sub a8, a8, a443; XTENSA-NEXT: ssr a844; XTENSA-NEXT: src a11, a3, a245; XTENSA-NEXT: movi a9, 3246; XTENSA-NEXT: sub a9, a9, a447; XTENSA-NEXT: ssr a948; XTENSA-NEXT: srl a7, a349; XTENSA-NEXT: movi a10, 050; XTENSA-NEXT: blt a9, a10, .LBB2_251; XTENSA-NEXT: # %bb.1:52; XTENSA-NEXT: or a11, a7, a753; XTENSA-NEXT: .LBB2_2:54; XTENSA-NEXT: ssl a455; XTENSA-NEXT: sll a7, a256; XTENSA-NEXT: addi a5, a4, -3257; XTENSA-NEXT: blt a5, a10, .LBB2_458; XTENSA-NEXT: # %bb.3:59; XTENSA-NEXT: or a7, a10, a1060; XTENSA-NEXT: .LBB2_4:61; XTENSA-NEXT: ssl a462; XTENSA-NEXT: src a6, a3, a263; XTENSA-NEXT: ssl a564; XTENSA-NEXT: sll a4, a265; XTENSA-NEXT: blt a5, a10, .LBB2_666; XTENSA-NEXT: # %bb.5:67; XTENSA-NEXT: or a6, a4, a468; XTENSA-NEXT: .LBB2_6:69; XTENSA-NEXT: or a2, a7, a1170; XTENSA-NEXT: ssr a871; XTENSA-NEXT: srl a8, a372; XTENSA-NEXT: blt a9, a10, .LBB2_873; XTENSA-NEXT: # %bb.7:74; XTENSA-NEXT: or a8, a10, a1075; XTENSA-NEXT: .LBB2_8:76; XTENSA-NEXT: or a3, a6, a877; XTENSA-NEXT: ret78 %z = sub i64 64, %y79 %b = shl i64 %x, %y80 %c = lshr i64 %x, %z81 %d = or i64 %b, %c82 ret i64 %d83}84 85define i64 @rotr_64(i64 %x, i64 %y) nounwind {86; XTENSA-LABEL: rotr_64:87; XTENSA: ssr a488; XTENSA-NEXT: src a10, a3, a289; XTENSA-NEXT: addi a8, a4, -3290; XTENSA-NEXT: ssr a891; XTENSA-NEXT: srl a11, a392; XTENSA-NEXT: movi a9, 093; XTENSA-NEXT: blt a8, a9, .LBB3_294; XTENSA-NEXT: # %bb.1:95; XTENSA-NEXT: or a10, a11, a1196; XTENSA-NEXT: .LBB3_2:97; XTENSA-NEXT: movi a11, 3298; XTENSA-NEXT: sub a7, a11, a499; XTENSA-NEXT: movi a11, 64100; XTENSA-NEXT: sub a11, a11, a4101; XTENSA-NEXT: ssl a11102; XTENSA-NEXT: sll a6, a2103; XTENSA-NEXT: blt a7, a9, .LBB3_4104; XTENSA-NEXT: # %bb.3:105; XTENSA-NEXT: or a6, a9, a9106; XTENSA-NEXT: .LBB3_4:107; XTENSA-NEXT: ssl a11108; XTENSA-NEXT: src a11, a3, a2109; XTENSA-NEXT: ssl a7110; XTENSA-NEXT: sll a5, a2111; XTENSA-NEXT: blt a7, a9, .LBB3_6112; XTENSA-NEXT: # %bb.5:113; XTENSA-NEXT: or a11, a5, a5114; XTENSA-NEXT: .LBB3_6:115; XTENSA-NEXT: or a2, a10, a6116; XTENSA-NEXT: ssr a4117; XTENSA-NEXT: srl a10, a3118; XTENSA-NEXT: blt a8, a9, .LBB3_8119; XTENSA-NEXT: # %bb.7:120; XTENSA-NEXT: or a10, a9, a9121; XTENSA-NEXT: .LBB3_8:122; XTENSA-NEXT: or a3, a10, a11123; XTENSA-NEXT: ret124 %z = sub i64 64, %y125 %b = lshr i64 %x, %y126 %c = shl i64 %x, %z127 %d = or i64 %b, %c128 ret i64 %d129}130 131define i32 @rotl_32_mask(i32 %x, i32 %y) nounwind {132; XTENSA-LABEL: rotl_32_mask:133; XTENSA: ssl a3134; XTENSA-NEXT: sll a8, a2135; XTENSA-NEXT: neg a9, a3136; XTENSA-NEXT: movi a10, 31137; XTENSA-NEXT: and a9, a9, a10138; XTENSA-NEXT: ssr a9139; XTENSA-NEXT: srl a9, a2140; XTENSA-NEXT: or a2, a8, a9141; XTENSA-NEXT: ret142 %z = sub i32 0, %y143 %and = and i32 %z, 31144 %b = shl i32 %x, %y145 %c = lshr i32 %x, %and146 %d = or i32 %b, %c147 ret i32 %d148}149 150define i32 @rotl_32_mask_and_63_and_31(i32 %x, i32 %y) nounwind {151; XTENSA-LABEL: rotl_32_mask_and_63_and_31:152; XTENSA: movi a8, 63153; XTENSA-NEXT: and a8, a3, a8154; XTENSA-NEXT: ssl a8155; XTENSA-NEXT: sll a8, a2156; XTENSA-NEXT: neg a9, a3157; XTENSA-NEXT: movi a10, 31158; XTENSA-NEXT: and a9, a9, a10159; XTENSA-NEXT: ssr a9160; XTENSA-NEXT: srl a9, a2161; XTENSA-NEXT: or a2, a8, a9162; XTENSA-NEXT: ret163 %a = and i32 %y, 63164 %b = shl i32 %x, %a165 %c = sub i32 0, %y166 %d = and i32 %c, 31167 %e = lshr i32 %x, %d168 %f = or i32 %b, %e169 ret i32 %f170}171 172define i32 @rotr_32_mask(i32 %x, i32 %y) nounwind {173; XTENSA-LABEL: rotr_32_mask:174; XTENSA: ssr a3175; XTENSA-NEXT: srl a8, a2176; XTENSA-NEXT: neg a9, a3177; XTENSA-NEXT: movi a10, 31178; XTENSA-NEXT: and a9, a9, a10179; XTENSA-NEXT: ssl a9180; XTENSA-NEXT: sll a9, a2181; XTENSA-NEXT: or a2, a8, a9182; XTENSA-NEXT: ret183 %z = sub i32 0, %y184 %and = and i32 %z, 31185 %b = lshr i32 %x, %y186 %c = shl i32 %x, %and187 %d = or i32 %b, %c188 ret i32 %d189}190 191define i32 @rotr_32_mask_and_63_and_31(i32 %x, i32 %y) nounwind {192; XTENSA-LABEL: rotr_32_mask_and_63_and_31:193; XTENSA: movi a8, 63194; XTENSA-NEXT: and a8, a3, a8195; XTENSA-NEXT: ssr a8196; XTENSA-NEXT: srl a8, a2197; XTENSA-NEXT: neg a9, a3198; XTENSA-NEXT: movi a10, 31199; XTENSA-NEXT: and a9, a9, a10200; XTENSA-NEXT: ssl a9201; XTENSA-NEXT: sll a9, a2202; XTENSA-NEXT: or a2, a8, a9203; XTENSA-NEXT: ret204 %a = and i32 %y, 63205 %b = lshr i32 %x, %a206 %c = sub i32 0, %y207 %d = and i32 %c, 31208 %e = shl i32 %x, %d209 %f = or i32 %b, %e210 ret i32 %f211}212 213define i64 @rotl_64_mask(i64 %x, i64 %y) nounwind {214; XTENSA-LABEL: rotl_64_mask:215; XTENSA: ssl a4216; XTENSA-NEXT: src a10, a3, a2217; XTENSA-NEXT: addi a8, a4, -32218; XTENSA-NEXT: ssl a8219; XTENSA-NEXT: sll a11, a2220; XTENSA-NEXT: movi a9, 0221; XTENSA-NEXT: blt a8, a9, .LBB8_2222; XTENSA-NEXT: # %bb.1:223; XTENSA-NEXT: or a10, a11, a11224; XTENSA-NEXT: .LBB8_2:225; XTENSA-NEXT: neg a11, a4226; XTENSA-NEXT: movi a7, 63227; XTENSA-NEXT: and a7, a11, a7228; XTENSA-NEXT: ssr a7229; XTENSA-NEXT: srl a11, a3230; XTENSA-NEXT: addi a6, a7, -32231; XTENSA-NEXT: blt a6, a9, .LBB8_4232; XTENSA-NEXT: # %bb.3:233; XTENSA-NEXT: or a11, a9, a9234; XTENSA-NEXT: .LBB8_4:235; XTENSA-NEXT: ssr a7236; XTENSA-NEXT: src a7, a3, a2237; XTENSA-NEXT: ssr a6238; XTENSA-NEXT: srl a5, a3239; XTENSA-NEXT: blt a6, a9, .LBB8_6240; XTENSA-NEXT: # %bb.5:241; XTENSA-NEXT: or a7, a5, a5242; XTENSA-NEXT: .LBB8_6:243; XTENSA-NEXT: or a3, a10, a11244; XTENSA-NEXT: ssl a4245; XTENSA-NEXT: sll a10, a2246; XTENSA-NEXT: blt a8, a9, .LBB8_8247; XTENSA-NEXT: # %bb.7:248; XTENSA-NEXT: or a10, a9, a9249; XTENSA-NEXT: .LBB8_8:250; XTENSA-NEXT: or a2, a10, a7251; XTENSA-NEXT: ret252 %z = sub i64 0, %y253 %and = and i64 %z, 63254 %b = shl i64 %x, %y255 %c = lshr i64 %x, %and256 %d = or i64 %b, %c257 ret i64 %d258}259 260define i64 @rotl_64_mask_and_127_and_63(i64 %x, i64 %y) nounwind {261; XTENSA-LABEL: rotl_64_mask_and_127_and_63:262; XTENSA: movi a8, 127263; XTENSA-NEXT: and a8, a4, a8264; XTENSA-NEXT: ssl a8265; XTENSA-NEXT: src a11, a3, a2266; XTENSA-NEXT: addi a9, a8, -32267; XTENSA-NEXT: ssl a9268; XTENSA-NEXT: sll a7, a2269; XTENSA-NEXT: movi a10, 0270; XTENSA-NEXT: blt a9, a10, .LBB9_2271; XTENSA-NEXT: # %bb.1:272; XTENSA-NEXT: or a11, a7, a7273; XTENSA-NEXT: .LBB9_2:274; XTENSA-NEXT: neg a7, a4275; XTENSA-NEXT: movi a6, 63276; XTENSA-NEXT: and a6, a7, a6277; XTENSA-NEXT: ssr a6278; XTENSA-NEXT: srl a7, a3279; XTENSA-NEXT: addi a5, a6, -32280; XTENSA-NEXT: blt a5, a10, .LBB9_4281; XTENSA-NEXT: # %bb.3:282; XTENSA-NEXT: or a7, a10, a10283; XTENSA-NEXT: .LBB9_4:284; XTENSA-NEXT: ssr a6285; XTENSA-NEXT: src a6, a3, a2286; XTENSA-NEXT: ssr a5287; XTENSA-NEXT: srl a4, a3288; XTENSA-NEXT: blt a5, a10, .LBB9_6289; XTENSA-NEXT: # %bb.5:290; XTENSA-NEXT: or a6, a4, a4291; XTENSA-NEXT: .LBB9_6:292; XTENSA-NEXT: or a3, a11, a7293; XTENSA-NEXT: ssl a8294; XTENSA-NEXT: sll a8, a2295; XTENSA-NEXT: blt a9, a10, .LBB9_8296; XTENSA-NEXT: # %bb.7:297; XTENSA-NEXT: or a8, a10, a10298; XTENSA-NEXT: .LBB9_8:299; XTENSA-NEXT: or a2, a8, a6300; XTENSA-NEXT: ret301 %a = and i64 %y, 127302 %b = shl i64 %x, %a303 %c = sub i64 0, %y304 %d = and i64 %c, 63305 %e = lshr i64 %x, %d306 %f = or i64 %b, %e307 ret i64 %f308}309 310define i64 @rotr_64_mask(i64 %x, i64 %y) nounwind {311; XTENSA-LABEL: rotr_64_mask:312; XTENSA: ssr a4313; XTENSA-NEXT: src a10, a3, a2314; XTENSA-NEXT: addi a8, a4, -32315; XTENSA-NEXT: ssr a8316; XTENSA-NEXT: srl a11, a3317; XTENSA-NEXT: movi a9, 0318; XTENSA-NEXT: blt a8, a9, .LBB10_2319; XTENSA-NEXT: # %bb.1:320; XTENSA-NEXT: or a10, a11, a11321; XTENSA-NEXT: .LBB10_2:322; XTENSA-NEXT: neg a11, a4323; XTENSA-NEXT: movi a7, 63324; XTENSA-NEXT: and a7, a11, a7325; XTENSA-NEXT: ssl a7326; XTENSA-NEXT: sll a11, a2327; XTENSA-NEXT: addi a6, a7, -32328; XTENSA-NEXT: blt a6, a9, .LBB10_4329; XTENSA-NEXT: # %bb.3:330; XTENSA-NEXT: or a11, a9, a9331; XTENSA-NEXT: .LBB10_4:332; XTENSA-NEXT: ssl a7333; XTENSA-NEXT: src a7, a3, a2334; XTENSA-NEXT: ssl a6335; XTENSA-NEXT: sll a5, a2336; XTENSA-NEXT: blt a6, a9, .LBB10_6337; XTENSA-NEXT: # %bb.5:338; XTENSA-NEXT: or a7, a5, a5339; XTENSA-NEXT: .LBB10_6:340; XTENSA-NEXT: or a2, a10, a11341; XTENSA-NEXT: ssr a4342; XTENSA-NEXT: srl a10, a3343; XTENSA-NEXT: blt a8, a9, .LBB10_8344; XTENSA-NEXT: # %bb.7:345; XTENSA-NEXT: or a10, a9, a9346; XTENSA-NEXT: .LBB10_8:347; XTENSA-NEXT: or a3, a10, a7348; XTENSA-NEXT: ret349 %z = sub i64 0, %y350 %and = and i64 %z, 63351 %b = lshr i64 %x, %y352 %c = shl i64 %x, %and353 %d = or i64 %b, %c354 ret i64 %d355}356 357define i64 @rotr_64_mask_and_127_and_63(i64 %x, i64 %y) nounwind {358; XTENSA-LABEL: rotr_64_mask_and_127_and_63:359; XTENSA: movi a8, 127360; XTENSA-NEXT: and a8, a4, a8361; XTENSA-NEXT: ssr a8362; XTENSA-NEXT: src a11, a3, a2363; XTENSA-NEXT: addi a9, a8, -32364; XTENSA-NEXT: ssr a9365; XTENSA-NEXT: srl a7, a3366; XTENSA-NEXT: movi a10, 0367; XTENSA-NEXT: blt a9, a10, .LBB11_2368; XTENSA-NEXT: # %bb.1:369; XTENSA-NEXT: or a11, a7, a7370; XTENSA-NEXT: .LBB11_2:371; XTENSA-NEXT: neg a7, a4372; XTENSA-NEXT: movi a6, 63373; XTENSA-NEXT: and a6, a7, a6374; XTENSA-NEXT: ssl a6375; XTENSA-NEXT: sll a7, a2376; XTENSA-NEXT: addi a5, a6, -32377; XTENSA-NEXT: blt a5, a10, .LBB11_4378; XTENSA-NEXT: # %bb.3:379; XTENSA-NEXT: or a7, a10, a10380; XTENSA-NEXT: .LBB11_4:381; XTENSA-NEXT: ssl a6382; XTENSA-NEXT: src a6, a3, a2383; XTENSA-NEXT: ssl a5384; XTENSA-NEXT: sll a4, a2385; XTENSA-NEXT: blt a5, a10, .LBB11_6386; XTENSA-NEXT: # %bb.5:387; XTENSA-NEXT: or a6, a4, a4388; XTENSA-NEXT: .LBB11_6:389; XTENSA-NEXT: or a2, a11, a7390; XTENSA-NEXT: ssr a8391; XTENSA-NEXT: srl a8, a3392; XTENSA-NEXT: blt a9, a10, .LBB11_8393; XTENSA-NEXT: # %bb.7:394; XTENSA-NEXT: or a8, a10, a10395; XTENSA-NEXT: .LBB11_8:396; XTENSA-NEXT: or a3, a8, a6397; XTENSA-NEXT: ret398 %a = and i64 %y, 127399 %b = lshr i64 %x, %a400 %c = sub i64 0, %y401 %d = and i64 %c, 63402 %e = shl i64 %x, %d403 %f = or i64 %b, %e404 ret i64 %f405}406 407define signext i32 @rotl_32_mask_shared(i32 signext %a, i32 signext %b, i32 signext %amt) nounwind {408; XTENSA-LABEL: rotl_32_mask_shared:409; XTENSA: movi a8, 31410; XTENSA-NEXT: and a9, a4, a8411; XTENSA-NEXT: ssl a9412; XTENSA-NEXT: sll a10, a2413; XTENSA-NEXT: neg a11, a4414; XTENSA-NEXT: and a8, a11, a8415; XTENSA-NEXT: ssr a8416; XTENSA-NEXT: srl a8, a2417; XTENSA-NEXT: or a8, a10, a8418; XTENSA-NEXT: ssl a9419; XTENSA-NEXT: sll a9, a3420; XTENSA-NEXT: add a2, a8, a9421; XTENSA-NEXT: ret422 %maskedamt = and i32 %amt, 31423 %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %maskedamt)424 %2 = shl i32 %b, %maskedamt425 %3 = add i32 %1, %2426 ret i32 %3427}428declare i32 @llvm.fshl.i32(i32, i32, i32)429 430define signext i32 @rotr_32_mask_shared(i32 signext %a, i32 signext %b, i32 signext %amt) nounwind {431; XTENSA-LABEL: rotr_32_mask_shared:432; XTENSA: movi a8, 31433; XTENSA-NEXT: and a9, a4, a8434; XTENSA-NEXT: ssr a9435; XTENSA-NEXT: srl a10, a2436; XTENSA-NEXT: neg a11, a4437; XTENSA-NEXT: and a8, a11, a8438; XTENSA-NEXT: ssl a8439; XTENSA-NEXT: sll a8, a2440; XTENSA-NEXT: or a8, a10, a8441; XTENSA-NEXT: ssl a9442; XTENSA-NEXT: sll a9, a3443; XTENSA-NEXT: add a2, a8, a9444; XTENSA-NEXT: ret445 %maskedamt = and i32 %amt, 31446 %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %maskedamt)447 %2 = shl i32 %b, %maskedamt448 %3 = add i32 %1, %2449 ret i32 %3450}451declare i32 @llvm.fshr.i32(i32, i32, i32)452 453define signext i32 @rotl_32_mask_multiple(i32 signext %a, i32 signext %b, i32 signext %amt) nounwind {454; XTENSA-LABEL: rotl_32_mask_multiple:455; XTENSA: movi a8, 31456; XTENSA-NEXT: and a9, a4, a8457; XTENSA-NEXT: ssl a9458; XTENSA-NEXT: sll a10, a3459; XTENSA-NEXT: neg a11, a4460; XTENSA-NEXT: and a8, a11, a8461; XTENSA-NEXT: ssr a8462; XTENSA-NEXT: srl a11, a3463; XTENSA-NEXT: or a10, a10, a11464; XTENSA-NEXT: ssl a9465; XTENSA-NEXT: sll a9, a2466; XTENSA-NEXT: ssr a8467; XTENSA-NEXT: srl a8, a2468; XTENSA-NEXT: or a8, a9, a8469; XTENSA-NEXT: add a2, a8, a10470; XTENSA-NEXT: ret471 %maskedamt = and i32 %amt, 31472 %1 = tail call i32 @llvm.fshl.i32(i32 %a, i32 %a, i32 %maskedamt)473 %2 = tail call i32 @llvm.fshl.i32(i32 %b, i32 %b, i32 %maskedamt)474 %3 = add i32 %1, %2475 ret i32 %3476}477 478define signext i32 @rotr_32_mask_multiple(i32 signext %a, i32 signext %b, i32 signext %amt) nounwind {479; XTENSA-LABEL: rotr_32_mask_multiple:480; XTENSA: movi a8, 31481; XTENSA-NEXT: and a9, a4, a8482; XTENSA-NEXT: ssr a9483; XTENSA-NEXT: srl a10, a3484; XTENSA-NEXT: neg a11, a4485; XTENSA-NEXT: and a8, a11, a8486; XTENSA-NEXT: ssl a8487; XTENSA-NEXT: sll a11, a3488; XTENSA-NEXT: or a10, a10, a11489; XTENSA-NEXT: ssr a9490; XTENSA-NEXT: srl a9, a2491; XTENSA-NEXT: ssl a8492; XTENSA-NEXT: sll a8, a2493; XTENSA-NEXT: or a8, a9, a8494; XTENSA-NEXT: add a2, a8, a10495; XTENSA-NEXT: ret496 %maskedamt = and i32 %amt, 31497 %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 %maskedamt)498 %2 = tail call i32 @llvm.fshr.i32(i32 %b, i32 %b, i32 %maskedamt)499 %3 = add i32 %1, %2500 ret i32 %3501}502