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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=xtensa -verify-machineinstrs < %s \3; RUN: | FileCheck %s4 5define i32 @lshl(i32 %x, i32 %y) nounwind {6; CHECK-LABEL: lshl:7; CHECK: ssl a38; CHECK-NEXT: sll a2, a29; CHECK-NEXT: ret10 %c = shl i32 %x, %y11 ret i32 %c12}13 14define i32 @lshl_imm_1(i32 %x) nounwind {15; CHECK-LABEL: lshl_imm_1:16; CHECK: slli a2, a2, 117; CHECK-NEXT: ret18 %c = shl i32 %x, 119 ret i32 %c20}21 22define i32 @lshl_imm_10(i32 %x) nounwind {23; CHECK-LABEL: lshl_imm_10:24; CHECK: slli a2, a2, 1025; CHECK-NEXT: ret26 %c = shl i32 %x, 1027 ret i32 %c28}29 30define i32 @lshl_imm_31(i32 %x) nounwind {31; CHECK-LABEL: lshl_imm_31:32; CHECK: slli a2, a2, 3133; CHECK-NEXT: ret34 %c = shl i32 %x, 3135 ret i32 %c36}37 38define i32 @lshr(i32 %x, i32 %y) nounwind {39; CHECK-LABEL: lshr:40; CHECK: ssr a341; CHECK-NEXT: srl a2, a242; CHECK-NEXT: ret43 %c = lshr i32 %x, %y44 ret i32 %c45}46 47define i32 @lshr_imm_1(i32 %x) nounwind {48; CHECK-LABEL: lshr_imm_1:49; CHECK: srli a2, a2, 150; CHECK-NEXT: ret51 %c = lshr i32 %x, 152 ret i32 %c53}54 55define i32 @lshr_imm_15(i32 %x) nounwind {56; CHECK-LABEL: lshr_imm_15:57; CHECK: srli a2, a2, 1558; CHECK-NEXT: ret59 %c = lshr i32 %x, 1560 ret i32 %c61}62 63define i32 @lshr_imm_20(i32 %x) nounwind {64; CHECK-LABEL: lshr_imm_20:65; CHECK: extui a2, a2, 20, 1266; CHECK-NEXT: ret67 %c = lshr i32 %x, 2068 ret i32 %c69}70 71define i32 @ashr(i32 %x, i32 %y) nounwind {72; CHECK-LABEL: ashr:73; CHECK: ssr a374; CHECK-NEXT: sra a2, a275; CHECK-NEXT: ret76 %c = ashr i32 %x, %y77 ret i32 %c78}79 80define i32 @ashr_imm_1(i32 %x) nounwind {81; CHECK-LABEL: ashr_imm_1:82; CHECK: srai a2, a2, 183; CHECK-NEXT: ret84 %c = ashr i32 %x, 185 ret i32 %c86}87 88define i32 @ashr_imm_10(i32 %x) nounwind {89; CHECK-LABEL: ashr_imm_10:90; CHECK: srai a2, a2, 1091; CHECK-NEXT: ret92 %c = ashr i32 %x, 1093 ret i32 %c94}95 96define i32 @ashr_imm_31(i32 %x) nounwind {97; CHECK-LABEL: ashr_imm_31:98; CHECK: srai a2, a2, 3199; CHECK-NEXT: ret100 %c = ashr i32 %x, 31101 ret i32 %c102}103 104define i64 @lshl_64(i64 %x, i64 %y) nounwind {105; CHECK-LABEL: lshl_64:106; CHECK: ssl a4107; CHECK-NEXT: src a3, a3, a2108; CHECK-NEXT: addi a8, a4, -32109; CHECK-NEXT: ssl a8110; CHECK-NEXT: sll a10, a2111; CHECK-NEXT: movi a9, 0112; CHECK-NEXT: blt a8, a9, .LBB12_2113; CHECK-NEXT: # %bb.1:114; CHECK-NEXT: or a3, a10, a10115; CHECK-NEXT: .LBB12_2:116; CHECK-NEXT: ssl a4117; CHECK-NEXT: sll a2, a2118; CHECK-NEXT: blt a8, a9, .LBB12_4119; CHECK-NEXT: # %bb.3:120; CHECK-NEXT: or a2, a9, a9121; CHECK-NEXT: .LBB12_4:122; CHECK-NEXT: ret123 %c = shl i64 %x, %y124 ret i64 %c125}126 127define i64 @lshr_64(i64 %x, i64 %y) nounwind {128; CHECK-LABEL: lshr_64:129; CHECK: ssr a4130; CHECK-NEXT: src a2, a3, a2131; CHECK-NEXT: addi a8, a4, -32132; CHECK-NEXT: ssr a8133; CHECK-NEXT: srl a10, a3134; CHECK-NEXT: movi a9, 0135; CHECK-NEXT: blt a8, a9, .LBB13_2136; CHECK-NEXT: # %bb.1:137; CHECK-NEXT: or a2, a10, a10138; CHECK-NEXT: .LBB13_2:139; CHECK-NEXT: ssr a4140; CHECK-NEXT: srl a3, a3141; CHECK-NEXT: blt a8, a9, .LBB13_4142; CHECK-NEXT: # %bb.3:143; CHECK-NEXT: or a3, a9, a9144; CHECK-NEXT: .LBB13_4:145; CHECK-NEXT: ret146 %c = lshr i64 %x, %y147 ret i64 %c148}149 150define i64 @ashr_64(i64 %x, i64 %y) nounwind {151; CHECK-LABEL: ashr_64:152; CHECK: ssr a4153; CHECK-NEXT: src a2, a3, a2154; CHECK-NEXT: addi a9, a4, -32155; CHECK-NEXT: ssr a9156; CHECK-NEXT: sra a8, a3157; CHECK-NEXT: movi a10, 0158; CHECK-NEXT: blt a9, a10, .LBB14_2159; CHECK-NEXT: # %bb.1:160; CHECK-NEXT: or a2, a8, a8161; CHECK-NEXT: .LBB14_2:162; CHECK-NEXT: ssr a4163; CHECK-NEXT: sra a8, a3164; CHECK-NEXT: blt a9, a10, .LBB14_4165; CHECK-NEXT: # %bb.3:166; CHECK-NEXT: srai a8, a3, 31167; CHECK-NEXT: .LBB14_4:168; CHECK-NEXT: or a3, a8, a8169; CHECK-NEXT: ret170 %c = ashr i64 %x, %y171 ret i64 %c172}173