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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=xtensa -verify-machineinstrs < %s \3; RUN: | FileCheck %s4 5@x_i8 = common dso_local global i8 0, align 86@y_i8 = common dso_local global i8 0, align 87@x_i16 = common dso_local global i16 0, align 88@y_i16 = common dso_local global i16 0, align 89@x_i32 = common dso_local global i32 0, align 810@y_i32 = common dso_local global i32 0, align 811@x_i64 = common dso_local global i64 0, align 812@y_i64 = common dso_local global i64 0, align 813@x_float = common dso_local global float 0.0, align 814@y_float = common dso_local global float 0.0, align 815@x_double = common dso_local global double 0.0, align 816@y_double = common dso_local global double 0.0, align 817@x_vec = common dso_local global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 818@y_vec = common dso_local global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 819 20define void @test() {21; CHECK-LABEL: test:22; CHECK: l32r a8, .LCPI0_023; CHECK-NEXT: memw24; CHECK-NEXT: l8ui a8, a8, 025; CHECK-NEXT: l32r a9, .LCPI0_126; CHECK-NEXT: memw27; CHECK-NEXT: s8i a8, a9, 028; CHECK-NEXT: l32r a8, .LCPI0_229; CHECK-NEXT: memw30; CHECK-NEXT: l16ui a8, a8, 031; CHECK-NEXT: l32r a9, .LCPI0_332; CHECK-NEXT: memw33; CHECK-NEXT: s16i a8, a9, 034; CHECK-NEXT: l32r a8, .LCPI0_435; CHECK-NEXT: memw36; CHECK-NEXT: l32i a8, a8, 037; CHECK-NEXT: l32r a9, .LCPI0_538; CHECK-NEXT: memw39; CHECK-NEXT: s32i a8, a9, 040; CHECK-NEXT: ret41 42entry:43 %a = load volatile i8, ptr @x_i8, align 444 store volatile i8 %a, ptr @y_i8, align 445 %b = load volatile i16, ptr @x_i16, align 446 store volatile i16 %b, ptr @y_i16, align 447 %c = load volatile i32, ptr @x_i32, align 448 store volatile i32 %c, ptr @y_i32, align 449 ret void50}51 52 53define void @test_i8() {54; CHECK-LABEL: test_i8:55; CHECK: l32r a8, .LCPI1_056; CHECK-NEXT: memw57; CHECK-NEXT: l8ui a8, a8, 058; CHECK-NEXT: l32r a9, .LCPI1_159; CHECK-NEXT: memw60; CHECK-NEXT: s8i a8, a9, 061; CHECK-NEXT: ret62entry:63 %a = load volatile i8, ptr @x_i8, align 464 store volatile i8 %a, ptr @y_i8, align 465 ret void66}67 68define void @test_i16() {69; CHECK-LABEL: test_i16:70; CHECK: l32r a8, .LCPI2_071; CHECK-NEXT: memw72; CHECK-NEXT: l16ui a8, a8, 073; CHECK-NEXT: l32r a9, .LCPI2_174; CHECK-NEXT: memw75; CHECK-NEXT: s16i a8, a9, 076; CHECK-NEXT: ret77entry:78 %a = load volatile i16, ptr @x_i16, align 479 store volatile i16 %a, ptr @y_i16, align 480 ret void81}82 83define void @test_i32() {84; CHECK-LABEL: test_i32:85; CHECK: l32r a8, .LCPI3_086; CHECK-NEXT: memw87; CHECK-NEXT: l32i a8, a8, 088; CHECK-NEXT: l32r a9, .LCPI3_189; CHECK-NEXT: memw90; CHECK-NEXT: s32i a8, a9, 091; CHECK-NEXT: ret92entry:93 %a = load volatile i32, ptr @x_i32, align 494 store volatile i32 %a, ptr @y_i32, align 495 ret void96}97 98define void @test_i64() {99; CHECK-LABEL: test_i64:100; CHECK: l32r a8, .LCPI4_0101; CHECK-NEXT: memw102; CHECK-NEXT: l32i a9, a8, 0103; CHECK-NEXT: memw104; CHECK-NEXT: l32i a8, a8, 4105; CHECK-NEXT: l32r a10, .LCPI4_1106; CHECK-NEXT: memw107; CHECK-NEXT: s32i a8, a10, 4108; CHECK-NEXT: memw109; CHECK-NEXT: s32i a9, a10, 0110; CHECK-NEXT: ret111entry:112 %a = load volatile i64, ptr @x_i64, align 4113 store volatile i64 %a, ptr @y_i64, align 4114 ret void115}116 117define void @test_float() {118; CHECK-LABEL: test_float:119; CHECK: l32r a8, .LCPI5_0120; CHECK-NEXT: memw121; CHECK-NEXT: l32i a8, a8, 0122; CHECK-NEXT: l32r a9, .LCPI5_1123; CHECK-NEXT: memw124; CHECK-NEXT: s32i a8, a9, 0125; CHECK-NEXT: ret126entry:127 %a = load volatile float, ptr @x_float, align 4128 store volatile float %a, ptr @y_float, align 4129 ret void130}131 132define void @test_double() {133; CHECK-LABEL: test_double:134; CHECK: l32r a8, .LCPI6_0135; CHECK-NEXT: memw136; CHECK-NEXT: l32i a9, a8, 0137; CHECK-NEXT: memw138; CHECK-NEXT: l32i a8, a8, 4139; CHECK-NEXT: l32r a10, .LCPI6_1140; CHECK-NEXT: memw141; CHECK-NEXT: s32i a8, a10, 4142; CHECK-NEXT: memw143; CHECK-NEXT: s32i a9, a10, 0144; CHECK-NEXT: ret145entry:146 %a = load volatile double, ptr @x_double, align 4147 store volatile double %a, ptr @y_double, align 4148 ret void149}150 151define void @test_vec() {152; CHECK-LABEL: test_vec:153; CHECK: l32r a8, .LCPI7_0154; CHECK-NEXT: memw155; CHECK-NEXT: l32i a9, a8, 0156; CHECK-NEXT: memw157; CHECK-NEXT: l32i a10, a8, 4158; CHECK-NEXT: memw159; CHECK-NEXT: l32i a11, a8, 8160; CHECK-NEXT: memw161; CHECK-NEXT: l32i a8, a8, 12162; CHECK-NEXT: l32r a7, .LCPI7_1163; CHECK-NEXT: memw164; CHECK-NEXT: s32i a8, a7, 12165; CHECK-NEXT: memw166; CHECK-NEXT: s32i a11, a7, 8167; CHECK-NEXT: memw168; CHECK-NEXT: s32i a10, a7, 4169; CHECK-NEXT: memw170; CHECK-NEXT: s32i a9, a7, 0171; CHECK-NEXT: ret172entry:173 %a = load volatile <4 x i32>, ptr @x_vec, align 4174 store volatile <4 x i32> %a, ptr @y_vec, align 4175 ret void176}177