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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 32; RUN: opt < %s -passes=asan -S | FileCheck %s3; RUN: opt < %s -passes=asan -asan-recover -S | FileCheck %s --check-prefix=RECOV4target triple = "amdgcn-amd-amdhsa"5 6define protected amdgpu_kernel void @generic_store(ptr addrspace(1) %p, i32 %i) sanitize_address {7; CHECK-LABEL: define protected amdgpu_kernel void @generic_store(8; CHECK-SAME: ptr addrspace(1) [[P:%.*]], i32 [[I:%.*]]) #[[ATTR0:[0-9]+]] {9; CHECK-NEXT: entry:10; CHECK-NEXT: [[Q:%.*]] = addrspacecast ptr addrspace(1) [[P]] to ptr11; CHECK-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[Q]])12; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[Q]])13; CHECK-NEXT: [[TMP2:%.*]] = or i1 [[TMP0]], [[TMP1]]14; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true15; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP21:%.*]]16; CHECK: 4:17; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[Q]] to i6418; CHECK-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 319; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 214745088020; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr21; CHECK-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 122; CHECK-NEXT: [[TMP10:%.*]] = icmp ne i8 [[TMP9]], 023; CHECK-NEXT: [[TMP11:%.*]] = and i64 [[TMP5]], 724; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[TMP11]], 325; CHECK-NEXT: [[TMP13:%.*]] = trunc i64 [[TMP12]] to i826; CHECK-NEXT: [[TMP14:%.*]] = icmp sge i8 [[TMP13]], [[TMP9]]27; CHECK-NEXT: [[TMP15:%.*]] = and i1 [[TMP10]], [[TMP14]]28; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP15]])29; CHECK-NEXT: [[TMP17:%.*]] = icmp ne i64 [[TMP16]], 030; CHECK-NEXT: br i1 [[TMP17]], label [[ASAN_REPORT:%.*]], label [[TMP20:%.*]], !prof [[PROF0:![0-9]+]]31; CHECK: asan.report:32; CHECK-NEXT: br i1 [[TMP15]], label [[TMP18:%.*]], label [[TMP19:%.*]]33; CHECK: 18:34; CHECK-NEXT: call void @__asan_report_store4(i64 [[TMP5]]) #[[ATTR5:[0-9]+]]35; CHECK-NEXT: call void @llvm.amdgcn.unreachable()36; CHECK-NEXT: br label [[TMP19]]37; CHECK: 19:38; CHECK-NEXT: br label [[TMP20]]39; CHECK: 20:40; CHECK-NEXT: br label [[TMP21]]41; CHECK: 21:42; CHECK-NEXT: store i32 0, ptr [[Q]], align 443; CHECK-NEXT: ret void44;45; RECOV-LABEL: define protected amdgpu_kernel void @generic_store(46; RECOV-SAME: ptr addrspace(1) [[P:%.*]], i32 [[I:%.*]]) #[[ATTR0:[0-9]+]] {47; RECOV-NEXT: entry:48; RECOV-NEXT: [[Q:%.*]] = addrspacecast ptr addrspace(1) [[P]] to ptr49; RECOV-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[Q]])50; RECOV-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[Q]])51; RECOV-NEXT: [[TMP2:%.*]] = or i1 [[TMP0]], [[TMP1]]52; RECOV-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true53; RECOV-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP17:%.*]]54; RECOV: 4:55; RECOV-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[Q]] to i6456; RECOV-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 357; RECOV-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 214745088058; RECOV-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr59; RECOV-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 160; RECOV-NEXT: [[TMP10:%.*]] = icmp ne i8 [[TMP9]], 061; RECOV-NEXT: [[TMP11:%.*]] = and i64 [[TMP5]], 762; RECOV-NEXT: [[TMP12:%.*]] = add i64 [[TMP11]], 363; RECOV-NEXT: [[TMP13:%.*]] = trunc i64 [[TMP12]] to i864; RECOV-NEXT: [[TMP14:%.*]] = icmp sge i8 [[TMP13]], [[TMP9]]65; RECOV-NEXT: [[TMP15:%.*]] = and i1 [[TMP10]], [[TMP14]]66; RECOV-NEXT: br i1 [[TMP15]], label [[ASAN_REPORT:%.*]], label [[TMP16:%.*]], !prof [[PROF0:![0-9]+]]67; RECOV: asan.report:68; RECOV-NEXT: call void @__asan_report_store4_noabort(i64 [[TMP5]]) #[[ATTR3:[0-9]+]]69; RECOV-NEXT: br label [[TMP16]]70; RECOV: 16:71; RECOV-NEXT: br label [[TMP17]]72; RECOV: 17:73; RECOV-NEXT: store i32 0, ptr [[Q]], align 474; RECOV-NEXT: ret void75;76entry:77 78 %q = addrspacecast ptr addrspace(1) %p to ptr79 store i32 0, ptr %q, align 480 ret void81}82 83define protected amdgpu_kernel void @generic_load(ptr addrspace(1) %p, i32 %i) sanitize_address {84; CHECK-LABEL: define protected amdgpu_kernel void @generic_load(85; CHECK-SAME: ptr addrspace(1) [[P:%.*]], i32 [[I:%.*]]) #[[ATTR0]] {86; CHECK-NEXT: entry:87; CHECK-NEXT: [[Q:%.*]] = addrspacecast ptr addrspace(1) [[P]] to ptr88; CHECK-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[Q]])89; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[Q]])90; CHECK-NEXT: [[TMP2:%.*]] = or i1 [[TMP0]], [[TMP1]]91; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true92; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP21:%.*]]93; CHECK: 4:94; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[Q]] to i6495; CHECK-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 396; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 214745088097; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr98; CHECK-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 199; CHECK-NEXT: [[TMP10:%.*]] = icmp ne i8 [[TMP9]], 0100; CHECK-NEXT: [[TMP11:%.*]] = and i64 [[TMP5]], 7101; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[TMP11]], 3102; CHECK-NEXT: [[TMP13:%.*]] = trunc i64 [[TMP12]] to i8103; CHECK-NEXT: [[TMP14:%.*]] = icmp sge i8 [[TMP13]], [[TMP9]]104; CHECK-NEXT: [[TMP15:%.*]] = and i1 [[TMP10]], [[TMP14]]105; CHECK-NEXT: [[TMP16:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP15]])106; CHECK-NEXT: [[TMP17:%.*]] = icmp ne i64 [[TMP16]], 0107; CHECK-NEXT: br i1 [[TMP17]], label [[ASAN_REPORT:%.*]], label [[TMP20:%.*]], !prof [[PROF0]]108; CHECK: asan.report:109; CHECK-NEXT: br i1 [[TMP15]], label [[TMP18:%.*]], label [[TMP19:%.*]]110; CHECK: 18:111; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP5]]) #[[ATTR5]]112; CHECK-NEXT: call void @llvm.amdgcn.unreachable()113; CHECK-NEXT: br label [[TMP19]]114; CHECK: 19:115; CHECK-NEXT: br label [[TMP20]]116; CHECK: 20:117; CHECK-NEXT: br label [[TMP21]]118; CHECK: 21:119; CHECK-NEXT: [[R:%.*]] = load i32, ptr [[Q]], align 4120; CHECK-NEXT: ret void121;122; RECOV-LABEL: define protected amdgpu_kernel void @generic_load(123; RECOV-SAME: ptr addrspace(1) [[P:%.*]], i32 [[I:%.*]]) #[[ATTR0]] {124; RECOV-NEXT: entry:125; RECOV-NEXT: [[Q:%.*]] = addrspacecast ptr addrspace(1) [[P]] to ptr126; RECOV-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[Q]])127; RECOV-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[Q]])128; RECOV-NEXT: [[TMP2:%.*]] = or i1 [[TMP0]], [[TMP1]]129; RECOV-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true130; RECOV-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP17:%.*]]131; RECOV: 4:132; RECOV-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[Q]] to i64133; RECOV-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 3134; RECOV-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 2147450880135; RECOV-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr136; RECOV-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1137; RECOV-NEXT: [[TMP10:%.*]] = icmp ne i8 [[TMP9]], 0138; RECOV-NEXT: [[TMP11:%.*]] = and i64 [[TMP5]], 7139; RECOV-NEXT: [[TMP12:%.*]] = add i64 [[TMP11]], 3140; RECOV-NEXT: [[TMP13:%.*]] = trunc i64 [[TMP12]] to i8141; RECOV-NEXT: [[TMP14:%.*]] = icmp sge i8 [[TMP13]], [[TMP9]]142; RECOV-NEXT: [[TMP15:%.*]] = and i1 [[TMP10]], [[TMP14]]143; RECOV-NEXT: br i1 [[TMP15]], label [[ASAN_REPORT:%.*]], label [[TMP16:%.*]], !prof [[PROF0]]144; RECOV: asan.report:145; RECOV-NEXT: call void @__asan_report_load4_noabort(i64 [[TMP5]]) #[[ATTR3]]146; RECOV-NEXT: br label [[TMP16]]147; RECOV: 16:148; RECOV-NEXT: br label [[TMP17]]149; RECOV: 17:150; RECOV-NEXT: [[R:%.*]] = load i32, ptr [[Q]], align 4151; RECOV-NEXT: ret void152;153entry:154 155 %q = addrspacecast ptr addrspace(1) %p to ptr156 %r = load i32, ptr %q, align 4157 ret void158}159 160define protected amdgpu_kernel void @generic_store_8(ptr addrspace(1) %p) sanitize_address {161; CHECK-LABEL: define protected amdgpu_kernel void @generic_store_8(162; CHECK-SAME: ptr addrspace(1) [[P:%.*]]) #[[ATTR0]] {163; CHECK-NEXT: entry:164; CHECK-NEXT: [[Q:%.*]] = addrspacecast ptr addrspace(1) [[P]] to ptr165; CHECK-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[Q]])166; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[Q]])167; CHECK-NEXT: [[TMP2:%.*]] = or i1 [[TMP0]], [[TMP1]]168; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true169; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP16:%.*]]170; CHECK: 4:171; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[Q]] to i64172; CHECK-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 3173; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 2147450880174; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr175; CHECK-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1176; CHECK-NEXT: [[TMP10:%.*]] = icmp ne i8 [[TMP9]], 0177; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP10]])178; CHECK-NEXT: [[TMP12:%.*]] = icmp ne i64 [[TMP11]], 0179; CHECK-NEXT: br i1 [[TMP12]], label [[ASAN_REPORT:%.*]], label [[TMP15:%.*]], !prof [[PROF0]]180; CHECK: asan.report:181; CHECK-NEXT: br i1 [[TMP10]], label [[TMP13:%.*]], label [[TMP14:%.*]]182; CHECK: 13:183; CHECK-NEXT: call void @__asan_report_store8(i64 [[TMP5]]) #[[ATTR5]]184; CHECK-NEXT: call void @llvm.amdgcn.unreachable()185; CHECK-NEXT: br label [[TMP14]]186; CHECK: 14:187; CHECK-NEXT: br label [[TMP15]]188; CHECK: 15:189; CHECK-NEXT: br label [[TMP16]]190; CHECK: 16:191; CHECK-NEXT: store i64 0, ptr [[Q]], align 8192; CHECK-NEXT: ret void193;194; RECOV-LABEL: define protected amdgpu_kernel void @generic_store_8(195; RECOV-SAME: ptr addrspace(1) [[P:%.*]]) #[[ATTR0]] {196; RECOV-NEXT: entry:197; RECOV-NEXT: [[Q:%.*]] = addrspacecast ptr addrspace(1) [[P]] to ptr198; RECOV-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[Q]])199; RECOV-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[Q]])200; RECOV-NEXT: [[TMP2:%.*]] = or i1 [[TMP0]], [[TMP1]]201; RECOV-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true202; RECOV-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]203; RECOV: 4:204; RECOV-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[Q]] to i64205; RECOV-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 3206; RECOV-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 2147450880207; RECOV-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr208; RECOV-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1209; RECOV-NEXT: [[TMP10:%.*]] = icmp ne i8 [[TMP9]], 0210; RECOV-NEXT: br i1 [[TMP10]], label [[ASAN_REPORT:%.*]], label [[TMP11:%.*]], !prof [[PROF0]]211; RECOV: asan.report:212; RECOV-NEXT: call void @__asan_report_store8_noabort(i64 [[TMP5]]) #[[ATTR3]]213; RECOV-NEXT: br label [[TMP11]]214; RECOV: 11:215; RECOV-NEXT: br label [[TMP12]]216; RECOV: 12:217; RECOV-NEXT: store i64 0, ptr [[Q]], align 8218; RECOV-NEXT: ret void219;220entry:221 %q = addrspacecast ptr addrspace(1) %p to ptr222 store i64 0, ptr %q, align 8223 ret void224}225 226define protected amdgpu_kernel void @generic_load_8(ptr addrspace(1) %p) sanitize_address {227; CHECK-LABEL: define protected amdgpu_kernel void @generic_load_8(228; CHECK-SAME: ptr addrspace(1) [[P:%.*]]) #[[ATTR0]] {229; CHECK-NEXT: entry:230; CHECK-NEXT: [[Q:%.*]] = addrspacecast ptr addrspace(1) [[P]] to ptr231; CHECK-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[Q]])232; CHECK-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[Q]])233; CHECK-NEXT: [[TMP2:%.*]] = or i1 [[TMP0]], [[TMP1]]234; CHECK-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true235; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP16:%.*]]236; CHECK: 4:237; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[Q]] to i64238; CHECK-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 3239; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 2147450880240; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr241; CHECK-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1242; CHECK-NEXT: [[TMP10:%.*]] = icmp ne i8 [[TMP9]], 0243; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.amdgcn.ballot.i64(i1 [[TMP10]])244; CHECK-NEXT: [[TMP12:%.*]] = icmp ne i64 [[TMP11]], 0245; CHECK-NEXT: br i1 [[TMP12]], label [[ASAN_REPORT:%.*]], label [[TMP15:%.*]], !prof [[PROF0]]246; CHECK: asan.report:247; CHECK-NEXT: br i1 [[TMP10]], label [[TMP13:%.*]], label [[TMP14:%.*]]248; CHECK: 13:249; CHECK-NEXT: call void @__asan_report_load8(i64 [[TMP5]]) #[[ATTR5]]250; CHECK-NEXT: call void @llvm.amdgcn.unreachable()251; CHECK-NEXT: br label [[TMP14]]252; CHECK: 14:253; CHECK-NEXT: br label [[TMP15]]254; CHECK: 15:255; CHECK-NEXT: br label [[TMP16]]256; CHECK: 16:257; CHECK-NEXT: [[R:%.*]] = load i64, ptr [[Q]], align 8258; CHECK-NEXT: ret void259;260; RECOV-LABEL: define protected amdgpu_kernel void @generic_load_8(261; RECOV-SAME: ptr addrspace(1) [[P:%.*]]) #[[ATTR0]] {262; RECOV-NEXT: entry:263; RECOV-NEXT: [[Q:%.*]] = addrspacecast ptr addrspace(1) [[P]] to ptr264; RECOV-NEXT: [[TMP0:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[Q]])265; RECOV-NEXT: [[TMP1:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[Q]])266; RECOV-NEXT: [[TMP2:%.*]] = or i1 [[TMP0]], [[TMP1]]267; RECOV-NEXT: [[TMP3:%.*]] = xor i1 [[TMP2]], true268; RECOV-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]269; RECOV: 4:270; RECOV-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[Q]] to i64271; RECOV-NEXT: [[TMP6:%.*]] = lshr i64 [[TMP5]], 3272; RECOV-NEXT: [[TMP7:%.*]] = add i64 [[TMP6]], 2147450880273; RECOV-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr274; RECOV-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP8]], align 1275; RECOV-NEXT: [[TMP10:%.*]] = icmp ne i8 [[TMP9]], 0276; RECOV-NEXT: br i1 [[TMP10]], label [[ASAN_REPORT:%.*]], label [[TMP11:%.*]], !prof [[PROF0]]277; RECOV: asan.report:278; RECOV-NEXT: call void @__asan_report_load8_noabort(i64 [[TMP5]]) #[[ATTR3]]279; RECOV-NEXT: br label [[TMP11]]280; RECOV: 11:281; RECOV-NEXT: br label [[TMP12]]282; RECOV: 12:283; RECOV-NEXT: [[R:%.*]] = load i64, ptr [[Q]], align 8284; RECOV-NEXT: ret void285;286entry:287 %q = addrspacecast ptr addrspace(1) %p to ptr288 %r = load i64, ptr %q, align 8289 ret void290}291