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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -mtriple=riscv64 -mattr=+v -passes=asan \3; RUN: -asan-instrumentation-with-call-threshold=0 -S | FileCheck %s4; REQUIRES: riscv-registered-target5 6declare <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32(7 <vscale x 1 x i32>,8 <vscale x 1 x i32>*,9 i64)10define <vscale x 1 x i32> @intrinsic_vle_v_nxv1i32_nxv1i32(<vscale x 1 x i32>* align 4 %0, i64 %1) sanitize_address {11; CHECK-LABEL: @intrinsic_vle_v_nxv1i32_nxv1i32(12; CHECK-NEXT: entry:13; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 814; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[TMP1:%.*]], 015; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]16; CHECK: 4:17; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()18; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP1]], i64 [[TMP5]])19; CHECK-NEXT: br label [[DOTSPLIT:%.*]]20; CHECK: .split:21; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]22; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]23; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]24; CHECK: 8:25; CHECK-NEXT: [[TMP9:%.*]] = getelementptr <vscale x 1 x i32>, ptr [[TMP0:%.*]], i64 0, i64 [[IV]]26; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i6427; CHECK-NEXT: call void @__asan_load4(i64 [[TMP10]])28; CHECK-NEXT: br label [[TMP11]]29; CHECK: 11:30; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 131; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]32; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]33; CHECK: .split.split:34; CHECK-NEXT: br label [[TMP12]]35; CHECK: 12:36; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr [[TMP0]], i64 [[TMP1]])37; CHECK-NEXT: ret <vscale x 1 x i32> [[A]]38;39entry:40 %a = call <vscale x 1 x i32> @llvm.riscv.vle.nxv1i32(41 <vscale x 1 x i32> poison,42 <vscale x 1 x i32>* %0,43 i64 %1)44 ret <vscale x 1 x i32> %a45}46 47declare <vscale x 1 x i32> @llvm.riscv.vle.mask.nxv1i32(48 <vscale x 1 x i32>,49 <vscale x 1 x i32>*,50 <vscale x 1 x i1>,51 i64,52 i64)53define <vscale x 1 x i32> @intrinsic_vle_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* align 4 %1, <vscale x 1 x i1> %2, i64 %3) sanitize_address {54; CHECK-LABEL: @intrinsic_vle_mask_v_nxv1i32_nxv1i32(55; CHECK-NEXT: entry:56; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 857; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP3:%.*]], 058; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP14:%.*]]59; CHECK: 6:60; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64()61; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP3]], i64 [[TMP7]])62; CHECK-NEXT: br label [[DOTSPLIT:%.*]]63; CHECK: .split:64; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP6]] ], [ [[IV_NEXT:%.*]], [[TMP13:%.*]] ]65; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x i1> [[TMP2:%.*]], i64 [[IV]]66; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP13]]67; CHECK: 10:68; CHECK-NEXT: [[TMP11:%.*]] = getelementptr <vscale x 1 x i32>, ptr [[TMP1:%.*]], i64 0, i64 [[IV]]69; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[TMP11]] to i6470; CHECK-NEXT: call void @__asan_load4(i64 [[TMP12]])71; CHECK-NEXT: br label [[TMP13]]72; CHECK: 13:73; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 174; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP8]]75; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]76; CHECK: .split.split:77; CHECK-NEXT: br label [[TMP14]]78; CHECK: 14:79; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vle.mask.nxv1i32.p0.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], <vscale x 1 x i1> [[TMP2]], i64 [[TMP3]], i64 1)80; CHECK-NEXT: ret <vscale x 1 x i32> [[A]]81;82entry:83 %a = call <vscale x 1 x i32> @llvm.riscv.vle.mask.nxv1i32(84 <vscale x 1 x i32> %0,85 <vscale x 1 x i32>* %1,86 <vscale x 1 x i1> %2,87 i64 %3, i64 1)88 ret <vscale x 1 x i32> %a89}90 91declare void @llvm.riscv.vse.nxv1i32(92 <vscale x 1 x i32>,93 <vscale x 1 x i32>*,94 i64)95define void @intrinsic_vse_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* align 4 %1, i64 %2) sanitize_address {96; CHECK-LABEL: @intrinsic_vse_v_nxv1i32_nxv1i32(97; CHECK-NEXT: entry:98; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 899; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP2:%.*]], 0100; CHECK-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP13:%.*]]101; CHECK: 5:102; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64()103; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 [[TMP6]])104; CHECK-NEXT: br label [[DOTSPLIT:%.*]]105; CHECK: .split:106; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP5]] ], [ [[IV_NEXT:%.*]], [[TMP12:%.*]] ]107; CHECK-NEXT: [[TMP8:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]108; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP12]]109; CHECK: 9:110; CHECK-NEXT: [[TMP10:%.*]] = getelementptr <vscale x 1 x i32>, ptr [[TMP1:%.*]], i64 0, i64 [[IV]]111; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[TMP10]] to i64112; CHECK-NEXT: call void @__asan_store4(i64 [[TMP11]])113; CHECK-NEXT: br label [[TMP12]]114; CHECK: 12:115; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1116; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP7]]117; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]118; CHECK: .split.split:119; CHECK-NEXT: br label [[TMP13]]120; CHECK: 13:121; CHECK-NEXT: call void @llvm.riscv.vse.nxv1i32.p0.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], i64 [[TMP2]])122; CHECK-NEXT: ret void123;124entry:125 call void @llvm.riscv.vse.nxv1i32(126 <vscale x 1 x i32> %0,127 <vscale x 1 x i32>* %1,128 i64 %2)129 ret void130}131 132declare void @llvm.riscv.vse.mask.nxv1i32(133 <vscale x 1 x i32>,134 <vscale x 1 x i32>*,135 <vscale x 1 x i1>,136 i64)137define void @intrinsic_vse_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* align 4 %1, <vscale x 1 x i1> %2, i64 %3) sanitize_address {138; CHECK-LABEL: @intrinsic_vse_mask_v_nxv1i32_nxv1i32(139; CHECK-NEXT: entry:140; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8141; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP3:%.*]], 0142; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP14:%.*]]143; CHECK: 6:144; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64()145; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP3]], i64 [[TMP7]])146; CHECK-NEXT: br label [[DOTSPLIT:%.*]]147; CHECK: .split:148; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP6]] ], [ [[IV_NEXT:%.*]], [[TMP13:%.*]] ]149; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x i1> [[TMP2:%.*]], i64 [[IV]]150; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP13]]151; CHECK: 10:152; CHECK-NEXT: [[TMP11:%.*]] = getelementptr <vscale x 1 x i32>, ptr [[TMP1:%.*]], i64 0, i64 [[IV]]153; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[TMP11]] to i64154; CHECK-NEXT: call void @__asan_store4(i64 [[TMP12]])155; CHECK-NEXT: br label [[TMP13]]156; CHECK: 13:157; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1158; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP8]]159; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]160; CHECK: .split.split:161; CHECK-NEXT: br label [[TMP14]]162; CHECK: 14:163; CHECK-NEXT: call void @llvm.riscv.vse.mask.nxv1i32.p0.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], <vscale x 1 x i1> [[TMP2]], i64 [[TMP3]])164; CHECK-NEXT: ret void165;166entry:167 call void @llvm.riscv.vse.mask.nxv1i32(168 <vscale x 1 x i32> %0,169 <vscale x 1 x i32>* %1,170 <vscale x 1 x i1> %2,171 i64 %3)172 ret void173}174 175 176declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, i64, i64)177declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, <vscale x 1 x i1>, i64, i64, i64)178 179define <vscale x 1 x i32> @test_vlseg2_nxv1i32(ptr %base, i64 %vl) sanitize_address {180; CHECK-LABEL: @test_vlseg2_nxv1i32(181; CHECK-NEXT: entry:182; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8183; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0184; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP10:%.*]]185; CHECK: 2:186; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()187; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])188; CHECK-NEXT: br label [[DOTSPLIT:%.*]]189; CHECK: .split:190; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]191; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]192; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]193; CHECK: 6:194; CHECK-NEXT: [[TMP7:%.*]] = getelementptr <vscale x 1 x i64>, ptr [[BASE:%.*]], i64 0, i64 [[IV]]195; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64196; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP8]], i64 8)197; CHECK-NEXT: br label [[TMP9]]198; CHECK: 9:199; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1200; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]201; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]202; CHECK: .split.split:203; CHECK-NEXT: br label [[TMP10]]204; CHECK: 10:205; CHECK-NEXT: [[TMP24:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr [[BASE]], i64 [[VL]], i64 5)206; CHECK-NEXT: [[TMP25:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_2t(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[TMP24]], i32 1)207; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP25]]208;209entry:210 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.triscv.vector.tuple_nxv4i8_2t(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %base, i64 %vl, i64 5)211 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_2t(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, i32 1)212 ret <vscale x 1 x i32> %1213}214 215define <vscale x 1 x i32> @test_vlseg2_mask_nxv1i32(ptr %base, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {216; CHECK-LABEL: @test_vlseg2_mask_nxv1i32(217; CHECK-NEXT: entry:218; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8219; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0220; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP10:%.*]]221; CHECK: 2:222; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()223; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])224; CHECK-NEXT: br label [[DOTSPLIT:%.*]]225; CHECK: .split:226; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]227; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]228; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]229; CHECK: 6:230; CHECK-NEXT: [[TMP7:%.*]] = getelementptr <vscale x 1 x i64>, ptr [[BASE:%.*]], i64 0, i64 [[IV]]231; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64232; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP8]], i64 8)233; CHECK-NEXT: br label [[TMP9]]234; CHECK: 9:235; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1236; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]237; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]238; CHECK: .split.split:239; CHECK-NEXT: br label [[TMP10]]240; CHECK: 10:241; CHECK-NEXT: [[TMP24:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)242; CHECK-NEXT: [[TMP25:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_2t(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[TMP24]], i32 1)243; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP25]]244;245entry:246 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1, i64 5)247 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_2t(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, i32 1)248 ret <vscale x 1 x i32> %1249}250 251 252declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, i64, i64)253declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, <vscale x 1 x i1>, i64, i64, i64)254 255define <vscale x 1 x i32> @test_vlseg3_nxv1i32(ptr %base, i64 %vl) sanitize_address {256; CHECK-LABEL: @test_vlseg3_nxv1i32(257; CHECK-NEXT: entry:258; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8259; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0260; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP10:%.*]]261; CHECK: 2:262; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()263; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])264; CHECK-NEXT: br label [[DOTSPLIT:%.*]]265; CHECK: .split:266; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]267; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]268; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]269; CHECK: 6:270; CHECK-NEXT: [[TMP7:%.*]] = getelementptr <vscale x 1 x i96>, ptr [[BASE:%.*]], i64 0, i64 [[IV]]271; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64272; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP8]], i64 12)273; CHECK-NEXT: br label [[TMP9]]274; CHECK: 9:275; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1276; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]277; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]278; CHECK: .split.split:279; CHECK-NEXT: br label [[TMP10]]280; CHECK: 10:281; CHECK-NEXT: [[TMP36:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr [[BASE]], i64 [[VL]], i64 5)282; CHECK-NEXT: [[TMP37:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_3t(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[TMP36]], i32 1)283; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP37]]284;285entry:286 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.triscv.vector.tuple_nxv4i8_3t(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %base, i64 %vl, i64 5)287 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_3t(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, i32 1)288 ret <vscale x 1 x i32> %1289}290 291define <vscale x 1 x i32> @test_vlseg3_mask_nxv1i32(ptr %base, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {292; CHECK-LABEL: @test_vlseg3_mask_nxv1i32(293; CHECK-NEXT: entry:294; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8295; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0296; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP10:%.*]]297; CHECK: 2:298; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()299; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])300; CHECK-NEXT: br label [[DOTSPLIT:%.*]]301; CHECK: .split:302; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]303; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]304; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]305; CHECK: 6:306; CHECK-NEXT: [[TMP7:%.*]] = getelementptr <vscale x 1 x i96>, ptr [[BASE:%.*]], i64 0, i64 [[IV]]307; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64308; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP8]], i64 12)309; CHECK-NEXT: br label [[TMP9]]310; CHECK: 9:311; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1312; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]313; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]314; CHECK: .split.split:315; CHECK-NEXT: br label [[TMP10]]316; CHECK: 10:317; CHECK-NEXT: [[TMP36:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)318; CHECK-NEXT: [[TMP37:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_3t(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[TMP36]], i32 1)319; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP37]]320;321entry:322 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1, i64 5)323 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_3t(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, i32 1)324 ret <vscale x 1 x i32> %1325}326 327 328declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, i64, i64)329declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, <vscale x 1 x i1>, i64, i64, i64)330 331define <vscale x 1 x i32> @test_vlseg4_nxv1i32(ptr %base, i64 %vl) sanitize_address {332; CHECK-LABEL: @test_vlseg4_nxv1i32(333; CHECK-NEXT: entry:334; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8335; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0336; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP10:%.*]]337; CHECK: 2:338; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()339; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])340; CHECK-NEXT: br label [[DOTSPLIT:%.*]]341; CHECK: .split:342; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]343; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]344; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]345; CHECK: 6:346; CHECK-NEXT: [[TMP7:%.*]] = getelementptr <vscale x 1 x i128>, ptr [[BASE:%.*]], i64 0, i64 [[IV]]347; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64348; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP8]], i64 16)349; CHECK-NEXT: br label [[TMP9]]350; CHECK: 9:351; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1352; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]353; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]354; CHECK: .split.split:355; CHECK-NEXT: br label [[TMP10]]356; CHECK: 10:357; CHECK-NEXT: [[TMP48:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr [[BASE]], i64 [[VL]], i64 5)358; CHECK-NEXT: [[TMP49:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_4t(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[TMP48]], i32 1)359; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP49]]360;361entry:362 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.triscv.vector.tuple_nxv4i8_4t(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %base, i64 %vl, i64 5)363 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_4t(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, i32 1)364 ret <vscale x 1 x i32> %1365}366 367define <vscale x 1 x i32> @test_vlseg4_mask_nxv1i32(ptr %base, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {368; CHECK-LABEL: @test_vlseg4_mask_nxv1i32(369; CHECK-NEXT: entry:370; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8371; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0372; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP10:%.*]]373; CHECK: 2:374; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()375; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])376; CHECK-NEXT: br label [[DOTSPLIT:%.*]]377; CHECK: .split:378; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]379; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]380; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]381; CHECK: 6:382; CHECK-NEXT: [[TMP7:%.*]] = getelementptr <vscale x 1 x i128>, ptr [[BASE:%.*]], i64 0, i64 [[IV]]383; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64384; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP8]], i64 16)385; CHECK-NEXT: br label [[TMP9]]386; CHECK: 9:387; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1388; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]389; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]390; CHECK: .split.split:391; CHECK-NEXT: br label [[TMP10]]392; CHECK: 10:393; CHECK-NEXT: [[TMP48:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)394; CHECK-NEXT: [[TMP49:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_4t(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[TMP48]], i32 1)395; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP49]]396;397entry:398 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1, i64 5)399 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_4t(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, i32 1)400 ret <vscale x 1 x i32> %1401}402 403 404declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, i64, i64)405declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, <vscale x 1 x i1>, i64, i64, i64)406 407define <vscale x 1 x i32> @test_vlseg5_nxv1i32(ptr %base, i64 %vl) sanitize_address {408; CHECK-LABEL: @test_vlseg5_nxv1i32(409; CHECK-NEXT: entry:410; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8411; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0412; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP10:%.*]]413; CHECK: 2:414; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()415; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])416; CHECK-NEXT: br label [[DOTSPLIT:%.*]]417; CHECK: .split:418; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]419; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]420; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]421; CHECK: 6:422; CHECK-NEXT: [[TMP7:%.*]] = getelementptr <vscale x 1 x i160>, ptr [[BASE:%.*]], i64 0, i64 [[IV]]423; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64424; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP8]], i64 20)425; CHECK-NEXT: br label [[TMP9]]426; CHECK: 9:427; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1428; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]429; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]430; CHECK: .split.split:431; CHECK-NEXT: br label [[TMP10]]432; CHECK: 10:433; CHECK-NEXT: [[TMP60:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr [[BASE]], i64 [[VL]], i64 5)434; CHECK-NEXT: [[TMP61:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_5t(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[TMP60]], i32 1)435; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP61]]436;437entry:438 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.triscv.vector.tuple_nxv4i8_5t(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %base, i64 %vl, i64 5)439 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_5t(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, i32 1)440 ret <vscale x 1 x i32> %1441}442 443define <vscale x 1 x i32> @test_vlseg5_mask_nxv1i32(ptr %base, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {444; CHECK-LABEL: @test_vlseg5_mask_nxv1i32(445; CHECK-NEXT: entry:446; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8447; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0448; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP10:%.*]]449; CHECK: 2:450; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()451; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])452; CHECK-NEXT: br label [[DOTSPLIT:%.*]]453; CHECK: .split:454; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]455; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]456; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]457; CHECK: 6:458; CHECK-NEXT: [[TMP7:%.*]] = getelementptr <vscale x 1 x i160>, ptr [[BASE:%.*]], i64 0, i64 [[IV]]459; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64460; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP8]], i64 20)461; CHECK-NEXT: br label [[TMP9]]462; CHECK: 9:463; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1464; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]465; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]466; CHECK: .split.split:467; CHECK-NEXT: br label [[TMP10]]468; CHECK: 10:469; CHECK-NEXT: [[TMP60:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)470; CHECK-NEXT: [[TMP61:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_5t(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[TMP60]], i32 1)471; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP61]]472;473entry:474 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1, i64 5)475 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_5t(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, i32 1)476 ret <vscale x 1 x i32> %1477}478 479 480declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, i64, i64)481declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, <vscale x 1 x i1>, i64, i64, i64)482 483define <vscale x 1 x i32> @test_vlseg6_nxv1i32(ptr %base, i64 %vl) sanitize_address {484; CHECK-LABEL: @test_vlseg6_nxv1i32(485; CHECK-NEXT: entry:486; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8487; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0488; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP10:%.*]]489; CHECK: 2:490; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()491; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])492; CHECK-NEXT: br label [[DOTSPLIT:%.*]]493; CHECK: .split:494; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]495; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]496; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]497; CHECK: 6:498; CHECK-NEXT: [[TMP7:%.*]] = getelementptr <vscale x 1 x i192>, ptr [[BASE:%.*]], i64 0, i64 [[IV]]499; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64500; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP8]], i64 24)501; CHECK-NEXT: br label [[TMP9]]502; CHECK: 9:503; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1504; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]505; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]506; CHECK: .split.split:507; CHECK-NEXT: br label [[TMP10]]508; CHECK: 10:509; CHECK-NEXT: [[TMP72:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr [[BASE]], i64 [[VL]], i64 5)510; CHECK-NEXT: [[TMP73:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_6t(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[TMP72]], i32 1)511; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP73]]512;513entry:514 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.triscv.vector.tuple_nxv4i8_6t(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %base, i64 %vl, i64 5)515 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_6t(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, i32 1)516 ret <vscale x 1 x i32> %1517}518 519define <vscale x 1 x i32> @test_vlseg6_mask_nxv1i32(ptr %base, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {520; CHECK-LABEL: @test_vlseg6_mask_nxv1i32(521; CHECK-NEXT: entry:522; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8523; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0524; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP10:%.*]]525; CHECK: 2:526; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()527; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])528; CHECK-NEXT: br label [[DOTSPLIT:%.*]]529; CHECK: .split:530; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]531; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]532; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]533; CHECK: 6:534; CHECK-NEXT: [[TMP7:%.*]] = getelementptr <vscale x 1 x i192>, ptr [[BASE:%.*]], i64 0, i64 [[IV]]535; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64536; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP8]], i64 24)537; CHECK-NEXT: br label [[TMP9]]538; CHECK: 9:539; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1540; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]541; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]542; CHECK: .split.split:543; CHECK-NEXT: br label [[TMP10]]544; CHECK: 10:545; CHECK-NEXT: [[TMP72:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)546; CHECK-NEXT: [[TMP73:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_6t(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[TMP72]], i32 1)547; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP73]]548;549entry:550 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1, i64 5)551 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_6t(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, i32 1)552 ret <vscale x 1 x i32> %1553}554 555 556declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, i64, i64)557declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, <vscale x 1 x i1>, i64, i64, i64)558 559define <vscale x 1 x i32> @test_vlseg7_nxv1i32(ptr %base, i64 %vl) sanitize_address {560; CHECK-LABEL: @test_vlseg7_nxv1i32(561; CHECK-NEXT: entry:562; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8563; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0564; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP10:%.*]]565; CHECK: 2:566; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()567; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])568; CHECK-NEXT: br label [[DOTSPLIT:%.*]]569; CHECK: .split:570; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]571; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]572; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]573; CHECK: 6:574; CHECK-NEXT: [[TMP7:%.*]] = getelementptr <vscale x 1 x i224>, ptr [[BASE:%.*]], i64 0, i64 [[IV]]575; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64576; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP8]], i64 28)577; CHECK-NEXT: br label [[TMP9]]578; CHECK: 9:579; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1580; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]581; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]582; CHECK: .split.split:583; CHECK-NEXT: br label [[TMP10]]584; CHECK: 10:585; CHECK-NEXT: [[TMP84:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr [[BASE]], i64 [[VL]], i64 5)586; CHECK-NEXT: [[TMP85:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_7t(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[TMP84]], i32 1)587; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP85]]588;589entry:590 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.triscv.vector.tuple_nxv4i8_7t(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %base, i64 %vl, i64 5)591 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_7t(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, i32 1)592 ret <vscale x 1 x i32> %1593}594 595define <vscale x 1 x i32> @test_vlseg7_mask_nxv1i32(ptr %base, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {596; CHECK-LABEL: @test_vlseg7_mask_nxv1i32(597; CHECK-NEXT: entry:598; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8599; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0600; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP10:%.*]]601; CHECK: 2:602; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()603; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])604; CHECK-NEXT: br label [[DOTSPLIT:%.*]]605; CHECK: .split:606; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]607; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]608; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]609; CHECK: 6:610; CHECK-NEXT: [[TMP7:%.*]] = getelementptr <vscale x 1 x i224>, ptr [[BASE:%.*]], i64 0, i64 [[IV]]611; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64612; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP8]], i64 28)613; CHECK-NEXT: br label [[TMP9]]614; CHECK: 9:615; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1616; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]617; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]618; CHECK: .split.split:619; CHECK-NEXT: br label [[TMP10]]620; CHECK: 10:621; CHECK-NEXT: [[TMP84:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)622; CHECK-NEXT: [[TMP85:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_7t(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[TMP84]], i32 1)623; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP85]]624;625entry:626 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1, i64 5)627 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_7t(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, i32 1)628 ret <vscale x 1 x i32> %1629}630 631 632declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, i64, i64)633declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, <vscale x 1 x i1>, i64, i64, i64)634 635define <vscale x 1 x i32> @test_vlseg8_nxv1i32(ptr %base, i64 %vl) sanitize_address {636; CHECK-LABEL: @test_vlseg8_nxv1i32(637; CHECK-NEXT: entry:638; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8639; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0640; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP10:%.*]]641; CHECK: 2:642; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()643; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])644; CHECK-NEXT: br label [[DOTSPLIT:%.*]]645; CHECK: .split:646; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]647; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]648; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]649; CHECK: 6:650; CHECK-NEXT: [[TMP7:%.*]] = getelementptr <vscale x 1 x i256>, ptr [[BASE:%.*]], i64 0, i64 [[IV]]651; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64652; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP8]], i64 32)653; CHECK-NEXT: br label [[TMP9]]654; CHECK: 9:655; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1656; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]657; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]658; CHECK: .split.split:659; CHECK-NEXT: br label [[TMP10]]660; CHECK: 10:661; CHECK-NEXT: [[TMP96:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr [[BASE]], i64 [[VL]], i64 5)662; CHECK-NEXT: [[TMP97:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_8t(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[TMP96]], i32 1)663; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP97]]664;665entry:666 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.triscv.vector.tuple_nxv4i8_8t(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %base, i64 %vl, i64 5)667 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_8t(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, i32 1)668 ret <vscale x 1 x i32> %1669}670 671define <vscale x 1 x i32> @test_vlseg8_mask_nxv1i32(ptr %base, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {672; CHECK-LABEL: @test_vlseg8_mask_nxv1i32(673; CHECK-NEXT: entry:674; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8675; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0676; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP10:%.*]]677; CHECK: 2:678; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()679; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])680; CHECK-NEXT: br label [[DOTSPLIT:%.*]]681; CHECK: .split:682; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]683; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]684; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]685; CHECK: 6:686; CHECK-NEXT: [[TMP7:%.*]] = getelementptr <vscale x 1 x i256>, ptr [[BASE:%.*]], i64 0, i64 [[IV]]687; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64688; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP8]], i64 32)689; CHECK-NEXT: br label [[TMP9]]690; CHECK: 9:691; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1692; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]693; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]694; CHECK: .split.split:695; CHECK-NEXT: br label [[TMP10]]696; CHECK: 10:697; CHECK-NEXT: [[TMP96:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)698; CHECK-NEXT: [[TMP97:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_8t(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[TMP96]], i32 1)699; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP97]]700;701entry:702 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %base, <vscale x 1 x i1> %mask, i64 %vl, i64 1, i64 5)703 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_8t(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, i32 1)704 ret <vscale x 1 x i32> %1705}706 707 708declare void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, i64, i64)709declare void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, <vscale x 1 x i1>, i64, i64)710 711define void @test_vsseg2_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, i64 %vl) sanitize_address {712; CHECK-LABEL: @test_vsseg2_nxv1i32(713; CHECK-NEXT: entry:714; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8715; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0716; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP10:%.*]]717; CHECK: 2:718; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()719; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])720; CHECK-NEXT: br label [[DOTSPLIT:%.*]]721; CHECK: .split:722; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]723; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]724; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]725; CHECK: 6:726; CHECK-NEXT: [[TMP7:%.*]] = getelementptr <vscale x 1 x i64>, ptr [[BASE:%.*]], i64 0, i64 [[IV]]727; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64728; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP8]], i64 8)729; CHECK-NEXT: br label [[TMP9]]730; CHECK: 9:731; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1732; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]733; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]734; CHECK: .split.split:735; CHECK-NEXT: br label [[TMP10]]736; CHECK: 10:737; CHECK-NEXT: tail call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[VAL:%.*]], ptr [[BASE]], i64 [[VL]], i64 5)738; CHECK-NEXT: ret void739;740entry:741 tail call void @llvm.riscv.vsseg2.triscv.vector.tuple_nxv4i8_2t(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, i64 %vl, i64 5)742 ret void743}744 745define void @test_vsseg2_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {746; CHECK-LABEL: @test_vsseg2_mask_nxv1i32(747; CHECK-NEXT: entry:748; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8749; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0750; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP10:%.*]]751; CHECK: 2:752; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()753; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])754; CHECK-NEXT: br label [[DOTSPLIT:%.*]]755; CHECK: .split:756; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]757; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]758; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]759; CHECK: 6:760; CHECK-NEXT: [[TMP7:%.*]] = getelementptr <vscale x 1 x i64>, ptr [[BASE:%.*]], i64 0, i64 [[IV]]761; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64762; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP8]], i64 8)763; CHECK-NEXT: br label [[TMP9]]764; CHECK: 9:765; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1766; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]767; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]768; CHECK: .split.split:769; CHECK-NEXT: br label [[TMP10]]770; CHECK: 10:771; CHECK-NEXT: tail call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)772; CHECK-NEXT: ret void773;774entry:775 tail call void @llvm.riscv.vsseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i1> %mask, i64 %vl, i64 5)776 ret void777}778 779 780declare void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, i64, i64)781declare void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, <vscale x 1 x i1>, i64, i64)782 783define void @test_vsseg3_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, i64 %vl) sanitize_address {784; CHECK-LABEL: @test_vsseg3_nxv1i32(785; CHECK-NEXT: entry:786; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8787; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0788; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP10:%.*]]789; CHECK: 2:790; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()791; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])792; CHECK-NEXT: br label [[DOTSPLIT:%.*]]793; CHECK: .split:794; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]795; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]796; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]797; CHECK: 6:798; CHECK-NEXT: [[TMP7:%.*]] = getelementptr <vscale x 1 x i96>, ptr [[BASE:%.*]], i64 0, i64 [[IV]]799; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64800; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP8]], i64 12)801; CHECK-NEXT: br label [[TMP9]]802; CHECK: 9:803; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1804; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]805; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]806; CHECK: .split.split:807; CHECK-NEXT: br label [[TMP10]]808; CHECK: 10:809; CHECK-NEXT: tail call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[VAL:%.*]], ptr [[BASE]], i64 [[VL]], i64 5)810; CHECK-NEXT: ret void811;812entry:813 tail call void @llvm.riscv.vsseg3.triscv.vector.tuple_nxv4i8_3t(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, i64 %vl, i64 5)814 ret void815}816 817define void @test_vsseg3_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {818; CHECK-LABEL: @test_vsseg3_mask_nxv1i32(819; CHECK-NEXT: entry:820; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8821; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0822; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP10:%.*]]823; CHECK: 2:824; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()825; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])826; CHECK-NEXT: br label [[DOTSPLIT:%.*]]827; CHECK: .split:828; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]829; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]830; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]831; CHECK: 6:832; CHECK-NEXT: [[TMP7:%.*]] = getelementptr <vscale x 1 x i96>, ptr [[BASE:%.*]], i64 0, i64 [[IV]]833; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64834; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP8]], i64 12)835; CHECK-NEXT: br label [[TMP9]]836; CHECK: 9:837; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1838; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]839; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]840; CHECK: .split.split:841; CHECK-NEXT: br label [[TMP10]]842; CHECK: 10:843; CHECK-NEXT: tail call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)844; CHECK-NEXT: ret void845;846entry:847 tail call void @llvm.riscv.vsseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i1> %mask, i64 %vl, i64 5)848 ret void849}850 851 852declare void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, i64, i64)853declare void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, <vscale x 1 x i1>, i64, i64)854 855define void @test_vsseg4_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, i64 %vl) sanitize_address {856; CHECK-LABEL: @test_vsseg4_nxv1i32(857; CHECK-NEXT: entry:858; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8859; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0860; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP10:%.*]]861; CHECK: 2:862; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()863; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])864; CHECK-NEXT: br label [[DOTSPLIT:%.*]]865; CHECK: .split:866; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]867; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]868; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]869; CHECK: 6:870; CHECK-NEXT: [[TMP7:%.*]] = getelementptr <vscale x 1 x i128>, ptr [[BASE:%.*]], i64 0, i64 [[IV]]871; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64872; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP8]], i64 16)873; CHECK-NEXT: br label [[TMP9]]874; CHECK: 9:875; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1876; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]877; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]878; CHECK: .split.split:879; CHECK-NEXT: br label [[TMP10]]880; CHECK: 10:881; CHECK-NEXT: tail call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[VAL:%.*]], ptr [[BASE]], i64 [[VL]], i64 5)882; CHECK-NEXT: ret void883;884entry:885 tail call void @llvm.riscv.vsseg4.triscv.vector.tuple_nxv4i8_4t(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, i64 %vl, i64 5)886 ret void887}888 889define void @test_vsseg4_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {890; CHECK-LABEL: @test_vsseg4_mask_nxv1i32(891; CHECK-NEXT: entry:892; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8893; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0894; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP10:%.*]]895; CHECK: 2:896; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()897; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])898; CHECK-NEXT: br label [[DOTSPLIT:%.*]]899; CHECK: .split:900; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]901; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]902; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]903; CHECK: 6:904; CHECK-NEXT: [[TMP7:%.*]] = getelementptr <vscale x 1 x i128>, ptr [[BASE:%.*]], i64 0, i64 [[IV]]905; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64906; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP8]], i64 16)907; CHECK-NEXT: br label [[TMP9]]908; CHECK: 9:909; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1910; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]911; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]912; CHECK: .split.split:913; CHECK-NEXT: br label [[TMP10]]914; CHECK: 10:915; CHECK-NEXT: tail call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)916; CHECK-NEXT: ret void917;918entry:919 tail call void @llvm.riscv.vsseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i1> %mask, i64 %vl, i64 5)920 ret void921}922 923 924declare void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, i64, i64)925declare void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, <vscale x 1 x i1>, i64, i64)926 927define void @test_vsseg5_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, i64 %vl) sanitize_address {928; CHECK-LABEL: @test_vsseg5_nxv1i32(929; CHECK-NEXT: entry:930; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8931; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0932; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP10:%.*]]933; CHECK: 2:934; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()935; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])936; CHECK-NEXT: br label [[DOTSPLIT:%.*]]937; CHECK: .split:938; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]939; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]940; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]941; CHECK: 6:942; CHECK-NEXT: [[TMP7:%.*]] = getelementptr <vscale x 1 x i160>, ptr [[BASE:%.*]], i64 0, i64 [[IV]]943; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64944; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP8]], i64 20)945; CHECK-NEXT: br label [[TMP9]]946; CHECK: 9:947; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1948; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]949; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]950; CHECK: .split.split:951; CHECK-NEXT: br label [[TMP10]]952; CHECK: 10:953; CHECK-NEXT: tail call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[VAL:%.*]], ptr [[BASE]], i64 [[VL]], i64 5)954; CHECK-NEXT: ret void955;956entry:957 tail call void @llvm.riscv.vsseg5.triscv.vector.tuple_nxv4i8_5t(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, i64 %vl, i64 5)958 ret void959}960 961define void @test_vsseg5_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {962; CHECK-LABEL: @test_vsseg5_mask_nxv1i32(963; CHECK-NEXT: entry:964; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 8965; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 0966; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP10:%.*]]967; CHECK: 2:968; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()969; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])970; CHECK-NEXT: br label [[DOTSPLIT:%.*]]971; CHECK: .split:972; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]973; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]974; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]975; CHECK: 6:976; CHECK-NEXT: [[TMP7:%.*]] = getelementptr <vscale x 1 x i160>, ptr [[BASE:%.*]], i64 0, i64 [[IV]]977; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i64978; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP8]], i64 20)979; CHECK-NEXT: br label [[TMP9]]980; CHECK: 9:981; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1982; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]983; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]984; CHECK: .split.split:985; CHECK-NEXT: br label [[TMP10]]986; CHECK: 10:987; CHECK-NEXT: tail call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)988; CHECK-NEXT: ret void989;990entry:991 tail call void @llvm.riscv.vsseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i1> %mask, i64 %vl, i64 5)992 ret void993}994 995 996declare void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, i64, i64)997declare void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, <vscale x 1 x i1>, i64, i64)998 999define void @test_vsseg6_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, i64 %vl) sanitize_address {1000; CHECK-LABEL: @test_vsseg6_nxv1i32(1001; CHECK-NEXT: entry:1002; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 81003; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 01004; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP10:%.*]]1005; CHECK: 2:1006; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()1007; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])1008; CHECK-NEXT: br label [[DOTSPLIT:%.*]]1009; CHECK: .split:1010; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]1011; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]1012; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]1013; CHECK: 6:1014; CHECK-NEXT: [[TMP7:%.*]] = getelementptr <vscale x 1 x i192>, ptr [[BASE:%.*]], i64 0, i64 [[IV]]1015; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i641016; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP8]], i64 24)1017; CHECK-NEXT: br label [[TMP9]]1018; CHECK: 9:1019; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11020; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]1021; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]1022; CHECK: .split.split:1023; CHECK-NEXT: br label [[TMP10]]1024; CHECK: 10:1025; CHECK-NEXT: tail call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[VAL:%.*]], ptr [[BASE]], i64 [[VL]], i64 5)1026; CHECK-NEXT: ret void1027;1028entry:1029 tail call void @llvm.riscv.vsseg6.triscv.vector.tuple_nxv4i8_6t(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, i64 %vl, i64 5)1030 ret void1031}1032 1033define void @test_vsseg6_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {1034; CHECK-LABEL: @test_vsseg6_mask_nxv1i32(1035; CHECK-NEXT: entry:1036; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 81037; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 01038; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP10:%.*]]1039; CHECK: 2:1040; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()1041; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])1042; CHECK-NEXT: br label [[DOTSPLIT:%.*]]1043; CHECK: .split:1044; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]1045; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]1046; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]1047; CHECK: 6:1048; CHECK-NEXT: [[TMP7:%.*]] = getelementptr <vscale x 1 x i192>, ptr [[BASE:%.*]], i64 0, i64 [[IV]]1049; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i641050; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP8]], i64 24)1051; CHECK-NEXT: br label [[TMP9]]1052; CHECK: 9:1053; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11054; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]1055; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]1056; CHECK: .split.split:1057; CHECK-NEXT: br label [[TMP10]]1058; CHECK: 10:1059; CHECK-NEXT: tail call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)1060; CHECK-NEXT: ret void1061;1062entry:1063 tail call void @llvm.riscv.vsseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i1> %mask, i64 %vl, i64 5)1064 ret void1065}1066 1067 1068declare void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, i64, i64)1069declare void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, <vscale x 1 x i1>, i64, i64)1070 1071define void @test_vsseg7_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, i64 %vl) sanitize_address {1072; CHECK-LABEL: @test_vsseg7_nxv1i32(1073; CHECK-NEXT: entry:1074; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 81075; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 01076; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP10:%.*]]1077; CHECK: 2:1078; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()1079; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])1080; CHECK-NEXT: br label [[DOTSPLIT:%.*]]1081; CHECK: .split:1082; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]1083; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]1084; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]1085; CHECK: 6:1086; CHECK-NEXT: [[TMP7:%.*]] = getelementptr <vscale x 1 x i224>, ptr [[BASE:%.*]], i64 0, i64 [[IV]]1087; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i641088; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP8]], i64 28)1089; CHECK-NEXT: br label [[TMP9]]1090; CHECK: 9:1091; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11092; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]1093; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]1094; CHECK: .split.split:1095; CHECK-NEXT: br label [[TMP10]]1096; CHECK: 10:1097; CHECK-NEXT: tail call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[VAL:%.*]], ptr [[BASE]], i64 [[VL]], i64 5)1098; CHECK-NEXT: ret void1099;1100entry:1101 tail call void @llvm.riscv.vsseg7.triscv.vector.tuple_nxv4i8_7t(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, i64 %vl, i64 5)1102 ret void1103}1104 1105define void @test_vsseg7_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {1106; CHECK-LABEL: @test_vsseg7_mask_nxv1i32(1107; CHECK-NEXT: entry:1108; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 81109; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 01110; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP10:%.*]]1111; CHECK: 2:1112; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()1113; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])1114; CHECK-NEXT: br label [[DOTSPLIT:%.*]]1115; CHECK: .split:1116; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]1117; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]1118; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]1119; CHECK: 6:1120; CHECK-NEXT: [[TMP7:%.*]] = getelementptr <vscale x 1 x i224>, ptr [[BASE:%.*]], i64 0, i64 [[IV]]1121; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i641122; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP8]], i64 28)1123; CHECK-NEXT: br label [[TMP9]]1124; CHECK: 9:1125; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11126; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]1127; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]1128; CHECK: .split.split:1129; CHECK-NEXT: br label [[TMP10]]1130; CHECK: 10:1131; CHECK-NEXT: tail call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)1132; CHECK-NEXT: ret void1133;1134entry:1135 tail call void @llvm.riscv.vsseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i1> %mask, i64 %vl, i64 5)1136 ret void1137}1138 1139 1140declare void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, i64, i64)1141declare void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, <vscale x 1 x i1>, i64, i64)1142 1143define void @test_vsseg8_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, i64 %vl) sanitize_address {1144; CHECK-LABEL: @test_vsseg8_nxv1i32(1145; CHECK-NEXT: entry:1146; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 81147; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 01148; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP10:%.*]]1149; CHECK: 2:1150; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()1151; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])1152; CHECK-NEXT: br label [[DOTSPLIT:%.*]]1153; CHECK: .split:1154; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]1155; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]1156; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]1157; CHECK: 6:1158; CHECK-NEXT: [[TMP7:%.*]] = getelementptr <vscale x 1 x i256>, ptr [[BASE:%.*]], i64 0, i64 [[IV]]1159; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i641160; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP8]], i64 32)1161; CHECK-NEXT: br label [[TMP9]]1162; CHECK: 9:1163; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11164; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]1165; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]1166; CHECK: .split.split:1167; CHECK-NEXT: br label [[TMP10]]1168; CHECK: 10:1169; CHECK-NEXT: tail call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[VAL:%.*]], ptr [[BASE]], i64 [[VL]], i64 5)1170; CHECK-NEXT: ret void1171;1172entry:1173 tail call void @llvm.riscv.vsseg8.triscv.vector.tuple_nxv4i8_8t(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, i64 %vl, i64 5)1174 ret void1175}1176 1177define void @test_vsseg8_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {1178; CHECK-LABEL: @test_vsseg8_mask_nxv1i32(1179; CHECK-NEXT: entry:1180; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 81181; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 01182; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP10:%.*]]1183; CHECK: 2:1184; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()1185; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])1186; CHECK-NEXT: br label [[DOTSPLIT:%.*]]1187; CHECK: .split:1188; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP9:%.*]] ]1189; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]1190; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP9]]1191; CHECK: 6:1192; CHECK-NEXT: [[TMP7:%.*]] = getelementptr <vscale x 1 x i256>, ptr [[BASE:%.*]], i64 0, i64 [[IV]]1193; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[TMP7]] to i641194; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP8]], i64 32)1195; CHECK-NEXT: br label [[TMP9]]1196; CHECK: 9:1197; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11198; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]1199; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]1200; CHECK: .split.split:1201; CHECK-NEXT: br label [[TMP10]]1202; CHECK: 10:1203; CHECK-NEXT: tail call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)1204; CHECK-NEXT: ret void1205;1206entry:1207 tail call void @llvm.riscv.vsseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i1> %mask, i64 %vl, i64 5)1208 ret void1209}1210 1211 1212; Test stride load1213declare <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32(1214 <vscale x 1 x i32>,1215 <vscale x 1 x i32>*,1216 i64,1217 i64);1218 1219define <vscale x 1 x i32> @intrinsic_vlse_v_nxv1i32_nxv1i32(<vscale x 1 x i32>* align 4 %0, i64 %1, i64 %2) sanitize_address {1220; CHECK-LABEL: @intrinsic_vlse_v_nxv1i32_nxv1i32(1221; CHECK-NEXT: entry:1222; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 81223; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP2:%.*]], 01224; CHECK-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP14:%.*]]1225; CHECK: 5:1226; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64()1227; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 [[TMP6]])1228; CHECK-NEXT: br label [[DOTSPLIT:%.*]]1229; CHECK: .split:1230; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP5]] ], [ [[IV_NEXT:%.*]], [[TMP13:%.*]] ]1231; CHECK-NEXT: [[TMP8:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]1232; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP13]]1233; CHECK: 9:1234; CHECK-NEXT: [[TMP10:%.*]] = mul i64 [[IV]], [[TMP1:%.*]]1235; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[TMP0:%.*]], i64 [[TMP10]]1236; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[TMP11]] to i641237; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP12]], i64 4)1238; CHECK-NEXT: br label [[TMP13]]1239; CHECK: 13:1240; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11241; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP7]]1242; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]1243; CHECK: .split.split:1244; CHECK-NEXT: br label [[TMP14]]1245; CHECK: 14:1246; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr [[TMP0]], i64 [[TMP1]], i64 [[TMP2]])1247; CHECK-NEXT: ret <vscale x 1 x i32> [[A]]1248;1249entry:1250 %a = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32(1251 <vscale x 1 x i32> poison,1252 <vscale x 1 x i32>* %0,1253 i64 %1,1254 i64 %2)1255 1256 ret <vscale x 1 x i32> %a1257}1258 1259declare <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32(1260 <vscale x 1 x i32>,1261 <vscale x 1 x i32>*,1262 i64,1263 <vscale x 1 x i1>,1264 i64,1265 i64);1266 1267define <vscale x 1 x i32> @intrinsic_vlse_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) sanitize_address {1268; CHECK-LABEL: @intrinsic_vlse_mask_v_nxv1i32_nxv1i32(1269; CHECK-NEXT: entry:1270; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 81271; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i64 [[TMP4:%.*]], 01272; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP16:%.*]]1273; CHECK: 7:1274; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()1275; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP4]], i64 [[TMP8]])1276; CHECK-NEXT: br label [[DOTSPLIT:%.*]]1277; CHECK: .split:1278; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[TMP15:%.*]] ]1279; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 1 x i1> [[TMP3:%.*]], i64 [[IV]]1280; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP15]]1281; CHECK: 11:1282; CHECK-NEXT: [[TMP12:%.*]] = mul i64 [[IV]], [[TMP2:%.*]]1283; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[TMP1:%.*]], i64 [[TMP12]]1284; CHECK-NEXT: [[TMP14:%.*]] = ptrtoint ptr [[TMP13]] to i641285; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP14]], i64 4)1286; CHECK-NEXT: br label [[TMP15]]1287; CHECK: 15:1288; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11289; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP9]]1290; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]1291; CHECK: .split.split:1292; CHECK-NEXT: br label [[TMP16]]1293; CHECK: 16:1294; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32.p0.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], i64 [[TMP2]], <vscale x 1 x i1> [[TMP3]], i64 [[TMP4]], i64 1)1295; CHECK-NEXT: ret <vscale x 1 x i32> [[A]]1296;1297entry:1298 %a = call <vscale x 1 x i32> @llvm.riscv.vlse.mask.nxv1i32(1299 <vscale x 1 x i32> %0,1300 <vscale x 1 x i32>* %1,1301 i64 %2,1302 <vscale x 1 x i1> %3,1303 i64 %4, i64 1)1304 1305 ret <vscale x 1 x i32> %a1306}1307 1308; Test stride store1309declare void @llvm.riscv.vsse.nxv1i32(1310 <vscale x 1 x i32>,1311 <vscale x 1 x i32>*,1312 i64,1313 i64);1314 1315define void @intrinsic_vsse_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, i64 %2, i64 %3) sanitize_address {1316; CHECK-LABEL: @intrinsic_vsse_v_nxv1i32_nxv1i32(1317; CHECK-NEXT: entry:1318; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 81319; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i64 [[TMP3:%.*]], 01320; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP15:%.*]]1321; CHECK: 6:1322; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64()1323; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP3]], i64 [[TMP7]])1324; CHECK-NEXT: br label [[DOTSPLIT:%.*]]1325; CHECK: .split:1326; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP6]] ], [ [[IV_NEXT:%.*]], [[TMP14:%.*]] ]1327; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]1328; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP14]]1329; CHECK: 10:1330; CHECK-NEXT: [[TMP11:%.*]] = mul i64 [[IV]], [[TMP2:%.*]]1331; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[TMP1:%.*]], i64 [[TMP11]]1332; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[TMP12]] to i641333; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP13]], i64 4)1334; CHECK-NEXT: br label [[TMP14]]1335; CHECK: 14:1336; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11337; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP8]]1338; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]1339; CHECK: .split.split:1340; CHECK-NEXT: br label [[TMP15]]1341; CHECK: 15:1342; CHECK-NEXT: call void @llvm.riscv.vsse.nxv1i32.p0.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], i64 [[TMP2]], i64 [[TMP3]])1343; CHECK-NEXT: ret void1344;1345entry:1346 call void @llvm.riscv.vsse.nxv1i32(1347 <vscale x 1 x i32> %0,1348 <vscale x 1 x i32>* %1,1349 i64 %2,1350 i64 %3)1351 1352 ret void1353}1354 1355declare void @llvm.riscv.vsse.mask.nxv1i32(1356 <vscale x 1 x i32>,1357 <vscale x 1 x i32>*,1358 i64,1359 <vscale x 1 x i1>,1360 i64);1361 1362define void @intrinsic_vsse_mask_v_nxv1i32_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, i64 %2, <vscale x 1 x i1> %3, i64 %4) sanitize_address {1363; CHECK-LABEL: @intrinsic_vsse_mask_v_nxv1i32_nxv1i32(1364; CHECK-NEXT: entry:1365; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 81366; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i64 [[TMP4:%.*]], 01367; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP16:%.*]]1368; CHECK: 7:1369; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()1370; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP4]], i64 [[TMP8]])1371; CHECK-NEXT: br label [[DOTSPLIT:%.*]]1372; CHECK: .split:1373; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[TMP15:%.*]] ]1374; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 1 x i1> [[TMP3:%.*]], i64 [[IV]]1375; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP15]]1376; CHECK: 11:1377; CHECK-NEXT: [[TMP12:%.*]] = mul i64 [[IV]], [[TMP2:%.*]]1378; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[TMP1:%.*]], i64 [[TMP12]]1379; CHECK-NEXT: [[TMP14:%.*]] = ptrtoint ptr [[TMP13]] to i641380; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP14]], i64 4)1381; CHECK-NEXT: br label [[TMP15]]1382; CHECK: 15:1383; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11384; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP9]]1385; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]1386; CHECK: .split.split:1387; CHECK-NEXT: br label [[TMP16]]1388; CHECK: 16:1389; CHECK-NEXT: call void @llvm.riscv.vsse.mask.nxv1i32.p0.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], i64 [[TMP2]], <vscale x 1 x i1> [[TMP3]], i64 [[TMP4]])1390; CHECK-NEXT: ret void1391;1392entry:1393 call void @llvm.riscv.vsse.mask.nxv1i32(1394 <vscale x 1 x i32> %0,1395 <vscale x 1 x i32>* %1,1396 i64 %2,1397 <vscale x 1 x i1> %3,1398 i64 %4)1399 1400 ret void1401}1402 1403 1404declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, i64, i64, i64)1405declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, i64, <vscale x 1 x i1>, i64, i64, i64)1406 1407define <vscale x 1 x i32> @test_vlsseg2_nxv1i32(ptr %base, i64 %offset, i64 %vl) sanitize_address {1408; CHECK-LABEL: @test_vlsseg2_nxv1i32(1409; CHECK-NEXT: entry:1410; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 81411; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 01412; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]1413; CHECK: 2:1414; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()1415; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])1416; CHECK-NEXT: br label [[DOTSPLIT:%.*]]1417; CHECK: .split:1418; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]1419; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]1420; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]1421; CHECK: 6:1422; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]1423; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]1424; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i641425; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP9]], i64 8)1426; CHECK-NEXT: br label [[TMP10]]1427; CHECK: 10:1428; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11429; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]1430; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]1431; CHECK: .split.split:1432; CHECK-NEXT: br label [[TMP11]]1433; CHECK: 11:1434; CHECK-NEXT: [[TMP24:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]], i64 5)1435; CHECK-NEXT: [[TMP25:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_2t(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[TMP24]], i32 1)1436; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP25]]1437;1438entry:1439 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.triscv.vector.tuple_nxv4i8_2t(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %base, i64 %offset, i64 %vl, i64 5)1440 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_2t(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, i32 1)1441 ret <vscale x 1 x i32> %11442}1443 1444define <vscale x 1 x i32> @test_vlsseg2_mask_nxv1i32(ptr %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {1445; CHECK-LABEL: @test_vlsseg2_mask_nxv1i32(1446; CHECK-NEXT: entry:1447; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 81448; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 01449; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]1450; CHECK: 2:1451; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()1452; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])1453; CHECK-NEXT: br label [[DOTSPLIT:%.*]]1454; CHECK: .split:1455; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]1456; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]1457; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]1458; CHECK: 6:1459; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]1460; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]1461; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i641462; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP9]], i64 8)1463; CHECK-NEXT: br label [[TMP10]]1464; CHECK: 10:1465; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11466; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]1467; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]1468; CHECK: .split.split:1469; CHECK-NEXT: br label [[TMP11]]1470; CHECK: 11:1471; CHECK-NEXT: [[TMP24:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)1472; CHECK-NEXT: [[TMP25:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_2t(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[TMP24]], i32 1)1473; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP25]]1474;1475entry:1476 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vlsseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1, i64 5)1477 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_2t(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, i32 1)1478 ret <vscale x 1 x i32> %11479}1480 1481 1482declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, i64, i64, i64)1483declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, i64, <vscale x 1 x i1>, i64, i64, i64)1484 1485define <vscale x 1 x i32> @test_vlsseg3_nxv1i32(ptr %base, i64 %offset, i64 %vl) sanitize_address {1486; CHECK-LABEL: @test_vlsseg3_nxv1i32(1487; CHECK-NEXT: entry:1488; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 81489; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 01490; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]1491; CHECK: 2:1492; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()1493; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])1494; CHECK-NEXT: br label [[DOTSPLIT:%.*]]1495; CHECK: .split:1496; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]1497; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]1498; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]1499; CHECK: 6:1500; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]1501; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]1502; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i641503; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP9]], i64 12)1504; CHECK-NEXT: br label [[TMP10]]1505; CHECK: 10:1506; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11507; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]1508; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]1509; CHECK: .split.split:1510; CHECK-NEXT: br label [[TMP11]]1511; CHECK: 11:1512; CHECK-NEXT: [[TMP36:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]], i64 5)1513; CHECK-NEXT: [[TMP37:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_3t(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[TMP36]], i32 1)1514; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP37]]1515;1516entry:1517 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.triscv.vector.tuple_nxv4i8_3t(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %base, i64 %offset, i64 %vl, i64 5)1518 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_3t(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, i32 1)1519 ret <vscale x 1 x i32> %11520}1521 1522define <vscale x 1 x i32> @test_vlsseg3_mask_nxv1i32(ptr %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {1523; CHECK-LABEL: @test_vlsseg3_mask_nxv1i32(1524; CHECK-NEXT: entry:1525; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 81526; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 01527; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]1528; CHECK: 2:1529; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()1530; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])1531; CHECK-NEXT: br label [[DOTSPLIT:%.*]]1532; CHECK: .split:1533; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]1534; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]1535; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]1536; CHECK: 6:1537; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]1538; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]1539; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i641540; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP9]], i64 12)1541; CHECK-NEXT: br label [[TMP10]]1542; CHECK: 10:1543; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11544; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]1545; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]1546; CHECK: .split.split:1547; CHECK-NEXT: br label [[TMP11]]1548; CHECK: 11:1549; CHECK-NEXT: [[TMP36:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)1550; CHECK-NEXT: [[TMP37:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_3t(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[TMP36]], i32 1)1551; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP37]]1552;1553entry:1554 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vlsseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1, i64 5)1555 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_3t(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, i32 1)1556 ret <vscale x 1 x i32> %11557}1558 1559 1560declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, i64, i64, i64)1561declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, i64, <vscale x 1 x i1>, i64, i64, i64)1562 1563define <vscale x 1 x i32> @test_vlsseg4_nxv1i32(ptr %base, i64 %offset, i64 %vl) sanitize_address {1564; CHECK-LABEL: @test_vlsseg4_nxv1i32(1565; CHECK-NEXT: entry:1566; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 81567; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 01568; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]1569; CHECK: 2:1570; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()1571; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])1572; CHECK-NEXT: br label [[DOTSPLIT:%.*]]1573; CHECK: .split:1574; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]1575; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]1576; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]1577; CHECK: 6:1578; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]1579; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]1580; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i641581; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP9]], i64 16)1582; CHECK-NEXT: br label [[TMP10]]1583; CHECK: 10:1584; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11585; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]1586; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]1587; CHECK: .split.split:1588; CHECK-NEXT: br label [[TMP11]]1589; CHECK: 11:1590; CHECK-NEXT: [[TMP48:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]], i64 5)1591; CHECK-NEXT: [[TMP49:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_4t(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[TMP48]], i32 1)1592; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP49]]1593;1594entry:1595 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.triscv.vector.tuple_nxv4i8_4t(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %base, i64 %offset, i64 %vl, i64 5)1596 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_4t(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, i32 1)1597 ret <vscale x 1 x i32> %11598}1599 1600define <vscale x 1 x i32> @test_vlsseg4_mask_nxv1i32(ptr %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {1601; CHECK-LABEL: @test_vlsseg4_mask_nxv1i32(1602; CHECK-NEXT: entry:1603; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 81604; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 01605; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]1606; CHECK: 2:1607; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()1608; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])1609; CHECK-NEXT: br label [[DOTSPLIT:%.*]]1610; CHECK: .split:1611; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]1612; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]1613; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]1614; CHECK: 6:1615; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]1616; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]1617; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i641618; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP9]], i64 16)1619; CHECK-NEXT: br label [[TMP10]]1620; CHECK: 10:1621; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11622; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]1623; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]1624; CHECK: .split.split:1625; CHECK-NEXT: br label [[TMP11]]1626; CHECK: 11:1627; CHECK-NEXT: [[TMP48:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)1628; CHECK-NEXT: [[TMP49:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_4t(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[TMP48]], i32 1)1629; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP49]]1630;1631entry:1632 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vlsseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1, i64 5)1633 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_4t(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, i32 1)1634 ret <vscale x 1 x i32> %11635}1636 1637 1638declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, i64, i64, i64)1639declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, i64, <vscale x 1 x i1>, i64, i64, i64)1640 1641define <vscale x 1 x i32> @test_vlsseg5_nxv1i32(ptr %base, i64 %offset, i64 %vl) sanitize_address {1642; CHECK-LABEL: @test_vlsseg5_nxv1i32(1643; CHECK-NEXT: entry:1644; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 81645; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 01646; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]1647; CHECK: 2:1648; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()1649; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])1650; CHECK-NEXT: br label [[DOTSPLIT:%.*]]1651; CHECK: .split:1652; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]1653; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]1654; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]1655; CHECK: 6:1656; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]1657; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]1658; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i641659; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP9]], i64 20)1660; CHECK-NEXT: br label [[TMP10]]1661; CHECK: 10:1662; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11663; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]1664; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]1665; CHECK: .split.split:1666; CHECK-NEXT: br label [[TMP11]]1667; CHECK: 11:1668; CHECK-NEXT: [[TMP60:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]], i64 5)1669; CHECK-NEXT: [[TMP61:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_5t(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[TMP60]], i32 1)1670; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP61]]1671;1672entry:1673 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.triscv.vector.tuple_nxv4i8_5t(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %base, i64 %offset, i64 %vl, i64 5)1674 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_5t(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, i32 1)1675 ret <vscale x 1 x i32> %11676}1677 1678define <vscale x 1 x i32> @test_vlsseg5_mask_nxv1i32(ptr %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {1679; CHECK-LABEL: @test_vlsseg5_mask_nxv1i32(1680; CHECK-NEXT: entry:1681; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 81682; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 01683; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]1684; CHECK: 2:1685; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()1686; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])1687; CHECK-NEXT: br label [[DOTSPLIT:%.*]]1688; CHECK: .split:1689; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]1690; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]1691; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]1692; CHECK: 6:1693; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]1694; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]1695; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i641696; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP9]], i64 20)1697; CHECK-NEXT: br label [[TMP10]]1698; CHECK: 10:1699; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11700; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]1701; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]1702; CHECK: .split.split:1703; CHECK-NEXT: br label [[TMP11]]1704; CHECK: 11:1705; CHECK-NEXT: [[TMP60:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)1706; CHECK-NEXT: [[TMP61:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_5t(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[TMP60]], i32 1)1707; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP61]]1708;1709entry:1710 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vlsseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1, i64 5)1711 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_5t(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, i32 1)1712 ret <vscale x 1 x i32> %11713}1714 1715 1716declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, i64, i64, i64)1717declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, i64, <vscale x 1 x i1>, i64, i64, i64)1718 1719define <vscale x 1 x i32> @test_vlsseg6_nxv1i32(ptr %base, i64 %offset, i64 %vl) sanitize_address {1720; CHECK-LABEL: @test_vlsseg6_nxv1i32(1721; CHECK-NEXT: entry:1722; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 81723; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 01724; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]1725; CHECK: 2:1726; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()1727; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])1728; CHECK-NEXT: br label [[DOTSPLIT:%.*]]1729; CHECK: .split:1730; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]1731; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]1732; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]1733; CHECK: 6:1734; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]1735; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]1736; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i641737; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP9]], i64 24)1738; CHECK-NEXT: br label [[TMP10]]1739; CHECK: 10:1740; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11741; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]1742; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]1743; CHECK: .split.split:1744; CHECK-NEXT: br label [[TMP11]]1745; CHECK: 11:1746; CHECK-NEXT: [[TMP72:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]], i64 5)1747; CHECK-NEXT: [[TMP73:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_6t(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[TMP72]], i32 1)1748; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP73]]1749;1750entry:1751 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.triscv.vector.tuple_nxv4i8_6t(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %base, i64 %offset, i64 %vl, i64 5)1752 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_6t(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, i32 1)1753 ret <vscale x 1 x i32> %11754}1755 1756define <vscale x 1 x i32> @test_vlsseg6_mask_nxv1i32(ptr %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {1757; CHECK-LABEL: @test_vlsseg6_mask_nxv1i32(1758; CHECK-NEXT: entry:1759; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 81760; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 01761; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]1762; CHECK: 2:1763; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()1764; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])1765; CHECK-NEXT: br label [[DOTSPLIT:%.*]]1766; CHECK: .split:1767; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]1768; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]1769; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]1770; CHECK: 6:1771; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]1772; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]1773; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i641774; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP9]], i64 24)1775; CHECK-NEXT: br label [[TMP10]]1776; CHECK: 10:1777; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11778; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]1779; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]1780; CHECK: .split.split:1781; CHECK-NEXT: br label [[TMP11]]1782; CHECK: 11:1783; CHECK-NEXT: [[TMP72:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)1784; CHECK-NEXT: [[TMP73:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_6t(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[TMP72]], i32 1)1785; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP73]]1786;1787entry:1788 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vlsseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1, i64 5)1789 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_6t(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, i32 1)1790 ret <vscale x 1 x i32> %11791}1792 1793 1794declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, i64, i64, i64)1795declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, i64, <vscale x 1 x i1>, i64, i64, i64)1796 1797define <vscale x 1 x i32> @test_vlsseg7_nxv1i32(ptr %base, i64 %offset, i64 %vl) sanitize_address {1798; CHECK-LABEL: @test_vlsseg7_nxv1i32(1799; CHECK-NEXT: entry:1800; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 81801; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 01802; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]1803; CHECK: 2:1804; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()1805; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])1806; CHECK-NEXT: br label [[DOTSPLIT:%.*]]1807; CHECK: .split:1808; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]1809; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]1810; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]1811; CHECK: 6:1812; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]1813; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]1814; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i641815; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP9]], i64 28)1816; CHECK-NEXT: br label [[TMP10]]1817; CHECK: 10:1818; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11819; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]1820; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]1821; CHECK: .split.split:1822; CHECK-NEXT: br label [[TMP11]]1823; CHECK: 11:1824; CHECK-NEXT: [[TMP84:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]], i64 5)1825; CHECK-NEXT: [[TMP85:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_7t(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[TMP84]], i32 1)1826; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP85]]1827;1828entry:1829 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.triscv.vector.tuple_nxv4i8_7t(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %base, i64 %offset, i64 %vl, i64 5)1830 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_7t(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, i32 1)1831 ret <vscale x 1 x i32> %11832}1833 1834define <vscale x 1 x i32> @test_vlsseg7_mask_nxv1i32(ptr %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {1835; CHECK-LABEL: @test_vlsseg7_mask_nxv1i32(1836; CHECK-NEXT: entry:1837; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 81838; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 01839; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]1840; CHECK: 2:1841; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()1842; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])1843; CHECK-NEXT: br label [[DOTSPLIT:%.*]]1844; CHECK: .split:1845; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]1846; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]1847; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]1848; CHECK: 6:1849; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]1850; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]1851; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i641852; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP9]], i64 28)1853; CHECK-NEXT: br label [[TMP10]]1854; CHECK: 10:1855; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11856; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]1857; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]1858; CHECK: .split.split:1859; CHECK-NEXT: br label [[TMP11]]1860; CHECK: 11:1861; CHECK-NEXT: [[TMP84:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)1862; CHECK-NEXT: [[TMP85:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_7t(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[TMP84]], i32 1)1863; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP85]]1864;1865entry:1866 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vlsseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1, i64 5)1867 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_7t(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, i32 1)1868 ret <vscale x 1 x i32> %11869}1870 1871 1872declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, i64, i64, i64)1873declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, i64, <vscale x 1 x i1>, i64, i64, i64)1874 1875define <vscale x 1 x i32> @test_vlsseg8_nxv1i32(ptr %base, i64 %offset, i64 %vl) sanitize_address {1876; CHECK-LABEL: @test_vlsseg8_nxv1i32(1877; CHECK-NEXT: entry:1878; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 81879; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 01880; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]1881; CHECK: 2:1882; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()1883; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])1884; CHECK-NEXT: br label [[DOTSPLIT:%.*]]1885; CHECK: .split:1886; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]1887; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]1888; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]1889; CHECK: 6:1890; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]1891; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]1892; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i641893; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP9]], i64 32)1894; CHECK-NEXT: br label [[TMP10]]1895; CHECK: 10:1896; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11897; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]1898; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]1899; CHECK: .split.split:1900; CHECK-NEXT: br label [[TMP11]]1901; CHECK: 11:1902; CHECK-NEXT: [[TMP96:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]], i64 5)1903; CHECK-NEXT: [[TMP97:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_8t(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[TMP96]], i32 1)1904; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP97]]1905;1906entry:1907 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.triscv.vector.tuple_nxv4i8_8t(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %base, i64 %offset, i64 %vl, i64 5)1908 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_8t(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, i32 1)1909 ret <vscale x 1 x i32> %11910}1911 1912define <vscale x 1 x i32> @test_vlsseg8_mask_nxv1i32(ptr %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {1913; CHECK-LABEL: @test_vlsseg8_mask_nxv1i32(1914; CHECK-NEXT: entry:1915; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 81916; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 01917; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]1918; CHECK: 2:1919; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()1920; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])1921; CHECK-NEXT: br label [[DOTSPLIT:%.*]]1922; CHECK: .split:1923; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]1924; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]1925; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]1926; CHECK: 6:1927; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]1928; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]1929; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i641930; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP9]], i64 32)1931; CHECK-NEXT: br label [[TMP10]]1932; CHECK: 10:1933; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11934; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]1935; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]1936; CHECK: .split.split:1937; CHECK-NEXT: br label [[TMP11]]1938; CHECK: 11:1939; CHECK-NEXT: [[TMP96:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)1940; CHECK-NEXT: [[TMP97:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_8t(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[TMP96]], i32 1)1941; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP97]]1942;1943entry:1944 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vlsseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 1, i64 5)1945 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_8t(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, i32 1)1946 ret <vscale x 1 x i32> %11947}1948 1949 1950declare void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, i64, i64, i64)1951declare void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, i64, <vscale x 1 x i1>, i64, i64)1952 1953define void @test_vssseg2_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, i64 %offset, i64 %vl) sanitize_address {1954; CHECK-LABEL: @test_vssseg2_nxv1i32(1955; CHECK-NEXT: entry:1956; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 81957; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 01958; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]1959; CHECK: 2:1960; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()1961; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])1962; CHECK-NEXT: br label [[DOTSPLIT:%.*]]1963; CHECK: .split:1964; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]1965; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]1966; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]1967; CHECK: 6:1968; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]1969; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]1970; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i641971; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP9]], i64 8)1972; CHECK-NEXT: br label [[TMP10]]1973; CHECK: 10:1974; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 11975; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]1976; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]1977; CHECK: .split.split:1978; CHECK-NEXT: br label [[TMP11]]1979; CHECK: 11:1980; CHECK-NEXT: tail call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[VAL:%.*]], ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]], i64 5)1981; CHECK-NEXT: ret void1982;1983entry:1984 tail call void @llvm.riscv.vssseg2.triscv.vector.tuple_nxv4i8_2t(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, i64 %offset, i64 %vl, i64 5)1985 ret void1986}1987 1988define void @test_vssseg2_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {1989; CHECK-LABEL: @test_vssseg2_mask_nxv1i32(1990; CHECK-NEXT: entry:1991; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 81992; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 01993; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]1994; CHECK: 2:1995; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()1996; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])1997; CHECK-NEXT: br label [[DOTSPLIT:%.*]]1998; CHECK: .split:1999; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]2000; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]2001; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]2002; CHECK: 6:2003; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]2004; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]2005; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i642006; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP9]], i64 8)2007; CHECK-NEXT: br label [[TMP10]]2008; CHECK: 10:2009; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 12010; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]2011; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]2012; CHECK: .split.split:2013; CHECK-NEXT: br label [[TMP11]]2014; CHECK: 11:2015; CHECK-NEXT: tail call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[VAL:%.*]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)2016; CHECK-NEXT: ret void2017;2018entry:2019 tail call void @llvm.riscv.vssseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 5)2020 ret void2021}2022 2023 2024declare void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, i64, i64, i64)2025declare void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, i64, <vscale x 1 x i1>, i64, i64)2026 2027define void @test_vssseg3_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, i64 %offset, i64 %vl) sanitize_address {2028; CHECK-LABEL: @test_vssseg3_nxv1i32(2029; CHECK-NEXT: entry:2030; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 82031; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 02032; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]2033; CHECK: 2:2034; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()2035; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])2036; CHECK-NEXT: br label [[DOTSPLIT:%.*]]2037; CHECK: .split:2038; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]2039; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]2040; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]2041; CHECK: 6:2042; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]2043; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]2044; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i642045; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP9]], i64 12)2046; CHECK-NEXT: br label [[TMP10]]2047; CHECK: 10:2048; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 12049; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]2050; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]2051; CHECK: .split.split:2052; CHECK-NEXT: br label [[TMP11]]2053; CHECK: 11:2054; CHECK-NEXT: tail call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[VAL:%.*]], ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]], i64 5)2055; CHECK-NEXT: ret void2056;2057entry:2058 tail call void @llvm.riscv.vssseg3.triscv.vector.tuple_nxv4i8_3t(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, i64 %offset, i64 %vl, i64 5)2059 ret void2060}2061 2062define void @test_vssseg3_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {2063; CHECK-LABEL: @test_vssseg3_mask_nxv1i32(2064; CHECK-NEXT: entry:2065; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 82066; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 02067; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]2068; CHECK: 2:2069; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()2070; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])2071; CHECK-NEXT: br label [[DOTSPLIT:%.*]]2072; CHECK: .split:2073; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]2074; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]2075; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]2076; CHECK: 6:2077; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]2078; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]2079; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i642080; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP9]], i64 12)2081; CHECK-NEXT: br label [[TMP10]]2082; CHECK: 10:2083; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 12084; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]2085; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]2086; CHECK: .split.split:2087; CHECK-NEXT: br label [[TMP11]]2088; CHECK: 11:2089; CHECK-NEXT: tail call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[VAL:%.*]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)2090; CHECK-NEXT: ret void2091;2092entry:2093 tail call void @llvm.riscv.vssseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 5)2094 ret void2095}2096 2097 2098declare void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, i64, i64, i64)2099declare void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, i64, <vscale x 1 x i1>, i64, i64)2100 2101define void @test_vssseg4_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, i64 %offset, i64 %vl) sanitize_address {2102; CHECK-LABEL: @test_vssseg4_nxv1i32(2103; CHECK-NEXT: entry:2104; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 82105; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 02106; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]2107; CHECK: 2:2108; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()2109; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])2110; CHECK-NEXT: br label [[DOTSPLIT:%.*]]2111; CHECK: .split:2112; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]2113; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]2114; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]2115; CHECK: 6:2116; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]2117; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]2118; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i642119; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP9]], i64 16)2120; CHECK-NEXT: br label [[TMP10]]2121; CHECK: 10:2122; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 12123; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]2124; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]2125; CHECK: .split.split:2126; CHECK-NEXT: br label [[TMP11]]2127; CHECK: 11:2128; CHECK-NEXT: tail call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[VAL:%.*]], ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]], i64 5)2129; CHECK-NEXT: ret void2130;2131entry:2132 tail call void @llvm.riscv.vssseg4.triscv.vector.tuple_nxv4i8_4t(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, i64 %offset, i64 %vl, i64 5)2133 ret void2134}2135 2136define void @test_vssseg4_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {2137; CHECK-LABEL: @test_vssseg4_mask_nxv1i32(2138; CHECK-NEXT: entry:2139; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 82140; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 02141; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]2142; CHECK: 2:2143; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()2144; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])2145; CHECK-NEXT: br label [[DOTSPLIT:%.*]]2146; CHECK: .split:2147; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]2148; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]2149; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]2150; CHECK: 6:2151; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]2152; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]2153; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i642154; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP9]], i64 16)2155; CHECK-NEXT: br label [[TMP10]]2156; CHECK: 10:2157; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 12158; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]2159; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]2160; CHECK: .split.split:2161; CHECK-NEXT: br label [[TMP11]]2162; CHECK: 11:2163; CHECK-NEXT: tail call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[VAL:%.*]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)2164; CHECK-NEXT: ret void2165;2166entry:2167 tail call void @llvm.riscv.vssseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 5)2168 ret void2169}2170 2171 2172declare void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, i64, i64, i64)2173declare void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, i64, <vscale x 1 x i1>, i64, i64)2174 2175define void @test_vssseg5_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, i64 %offset, i64 %vl) sanitize_address {2176; CHECK-LABEL: @test_vssseg5_nxv1i32(2177; CHECK-NEXT: entry:2178; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 82179; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 02180; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]2181; CHECK: 2:2182; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()2183; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])2184; CHECK-NEXT: br label [[DOTSPLIT:%.*]]2185; CHECK: .split:2186; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]2187; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]2188; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]2189; CHECK: 6:2190; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]2191; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]2192; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i642193; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP9]], i64 20)2194; CHECK-NEXT: br label [[TMP10]]2195; CHECK: 10:2196; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 12197; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]2198; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]2199; CHECK: .split.split:2200; CHECK-NEXT: br label [[TMP11]]2201; CHECK: 11:2202; CHECK-NEXT: tail call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[VAL:%.*]], ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]], i64 5)2203; CHECK-NEXT: ret void2204;2205entry:2206 tail call void @llvm.riscv.vssseg5.triscv.vector.tuple_nxv4i8_5t(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, i64 %offset, i64 %vl, i64 5)2207 ret void2208}2209 2210define void @test_vssseg5_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {2211; CHECK-LABEL: @test_vssseg5_mask_nxv1i32(2212; CHECK-NEXT: entry:2213; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 82214; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 02215; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]2216; CHECK: 2:2217; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()2218; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])2219; CHECK-NEXT: br label [[DOTSPLIT:%.*]]2220; CHECK: .split:2221; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]2222; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]2223; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]2224; CHECK: 6:2225; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]2226; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]2227; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i642228; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP9]], i64 20)2229; CHECK-NEXT: br label [[TMP10]]2230; CHECK: 10:2231; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 12232; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]2233; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]2234; CHECK: .split.split:2235; CHECK-NEXT: br label [[TMP11]]2236; CHECK: 11:2237; CHECK-NEXT: tail call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[VAL:%.*]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)2238; CHECK-NEXT: ret void2239;2240entry:2241 tail call void @llvm.riscv.vssseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 5)2242 ret void2243}2244 2245 2246declare void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, i64, i64, i64)2247declare void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, i64, <vscale x 1 x i1>, i64, i64)2248 2249define void @test_vssseg6_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, i64 %offset, i64 %vl) sanitize_address {2250; CHECK-LABEL: @test_vssseg6_nxv1i32(2251; CHECK-NEXT: entry:2252; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 82253; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 02254; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]2255; CHECK: 2:2256; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()2257; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])2258; CHECK-NEXT: br label [[DOTSPLIT:%.*]]2259; CHECK: .split:2260; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]2261; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]2262; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]2263; CHECK: 6:2264; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]2265; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]2266; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i642267; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP9]], i64 24)2268; CHECK-NEXT: br label [[TMP10]]2269; CHECK: 10:2270; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 12271; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]2272; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]2273; CHECK: .split.split:2274; CHECK-NEXT: br label [[TMP11]]2275; CHECK: 11:2276; CHECK-NEXT: tail call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[VAL:%.*]], ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]], i64 5)2277; CHECK-NEXT: ret void2278;2279entry:2280 tail call void @llvm.riscv.vssseg6.triscv.vector.tuple_nxv4i8_6t(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, i64 %offset, i64 %vl, i64 5)2281 ret void2282}2283 2284define void @test_vssseg6_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {2285; CHECK-LABEL: @test_vssseg6_mask_nxv1i32(2286; CHECK-NEXT: entry:2287; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 82288; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 02289; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]2290; CHECK: 2:2291; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()2292; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])2293; CHECK-NEXT: br label [[DOTSPLIT:%.*]]2294; CHECK: .split:2295; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]2296; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]2297; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]2298; CHECK: 6:2299; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]2300; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]2301; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i642302; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP9]], i64 24)2303; CHECK-NEXT: br label [[TMP10]]2304; CHECK: 10:2305; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 12306; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]2307; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]2308; CHECK: .split.split:2309; CHECK-NEXT: br label [[TMP11]]2310; CHECK: 11:2311; CHECK-NEXT: tail call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[VAL:%.*]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)2312; CHECK-NEXT: ret void2313;2314entry:2315 tail call void @llvm.riscv.vssseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 5)2316 ret void2317}2318 2319 2320declare void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, i64, i64, i64)2321declare void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, i64, <vscale x 1 x i1>, i64, i64)2322 2323define void @test_vssseg7_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, i64 %offset, i64 %vl) sanitize_address {2324; CHECK-LABEL: @test_vssseg7_nxv1i32(2325; CHECK-NEXT: entry:2326; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 82327; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 02328; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]2329; CHECK: 2:2330; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()2331; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])2332; CHECK-NEXT: br label [[DOTSPLIT:%.*]]2333; CHECK: .split:2334; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]2335; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]2336; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]2337; CHECK: 6:2338; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]2339; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]2340; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i642341; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP9]], i64 28)2342; CHECK-NEXT: br label [[TMP10]]2343; CHECK: 10:2344; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 12345; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]2346; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]2347; CHECK: .split.split:2348; CHECK-NEXT: br label [[TMP11]]2349; CHECK: 11:2350; CHECK-NEXT: tail call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[VAL:%.*]], ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]], i64 5)2351; CHECK-NEXT: ret void2352;2353entry:2354 tail call void @llvm.riscv.vssseg7.triscv.vector.tuple_nxv4i8_7t(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, i64 %offset, i64 %vl, i64 5)2355 ret void2356}2357 2358define void @test_vssseg7_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {2359; CHECK-LABEL: @test_vssseg7_mask_nxv1i32(2360; CHECK-NEXT: entry:2361; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 82362; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 02363; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]2364; CHECK: 2:2365; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()2366; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])2367; CHECK-NEXT: br label [[DOTSPLIT:%.*]]2368; CHECK: .split:2369; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]2370; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]2371; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]2372; CHECK: 6:2373; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]2374; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]2375; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i642376; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP9]], i64 28)2377; CHECK-NEXT: br label [[TMP10]]2378; CHECK: 10:2379; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 12380; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]2381; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]2382; CHECK: .split.split:2383; CHECK-NEXT: br label [[TMP11]]2384; CHECK: 11:2385; CHECK-NEXT: tail call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[VAL:%.*]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)2386; CHECK-NEXT: ret void2387;2388entry:2389 tail call void @llvm.riscv.vssseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 5)2390 ret void2391}2392 2393 2394declare void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, i64, i64, i64)2395declare void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, i64, <vscale x 1 x i1>, i64, i64)2396 2397define void @test_vssseg8_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, i64 %offset, i64 %vl) sanitize_address {2398; CHECK-LABEL: @test_vssseg8_nxv1i32(2399; CHECK-NEXT: entry:2400; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 82401; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 02402; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]2403; CHECK: 2:2404; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()2405; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])2406; CHECK-NEXT: br label [[DOTSPLIT:%.*]]2407; CHECK: .split:2408; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]2409; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]2410; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]2411; CHECK: 6:2412; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]2413; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]2414; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i642415; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP9]], i64 32)2416; CHECK-NEXT: br label [[TMP10]]2417; CHECK: 10:2418; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 12419; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]2420; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]2421; CHECK: .split.split:2422; CHECK-NEXT: br label [[TMP11]]2423; CHECK: 11:2424; CHECK-NEXT: tail call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t.p0.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[VAL:%.*]], ptr [[BASE]], i64 [[OFFSET]], i64 [[VL]], i64 5)2425; CHECK-NEXT: ret void2426;2427entry:2428 tail call void @llvm.riscv.vssseg8.triscv.vector.tuple_nxv4i8_8t(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, i64 %offset, i64 %vl, i64 5)2429 ret void2430}2431 2432define void @test_vssseg8_mask_nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, i64 %offset, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {2433; CHECK-LABEL: @test_vssseg8_mask_nxv1i32(2434; CHECK-NEXT: entry:2435; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 82436; CHECK-NEXT: [[TMP1:%.*]] = icmp ne i64 [[VL:%.*]], 02437; CHECK-NEXT: br i1 [[TMP1]], label [[TMP2:%.*]], label [[TMP11:%.*]]2438; CHECK: 2:2439; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64()2440; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP3]])2441; CHECK-NEXT: br label [[DOTSPLIT:%.*]]2442; CHECK: .split:2443; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP2]] ], [ [[IV_NEXT:%.*]], [[TMP10:%.*]] ]2444; CHECK-NEXT: [[TMP5:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]2445; CHECK-NEXT: br i1 [[TMP5]], label [[TMP6:%.*]], label [[TMP10]]2446; CHECK: 6:2447; CHECK-NEXT: [[TMP7:%.*]] = mul i64 [[IV]], [[OFFSET:%.*]]2448; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[BASE:%.*]], i64 [[TMP7]]2449; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[TMP8]] to i642450; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP9]], i64 32)2451; CHECK-NEXT: br label [[TMP10]]2452; CHECK: 10:2453; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 12454; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP4]]2455; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]2456; CHECK: .split.split:2457; CHECK-NEXT: br label [[TMP11]]2458; CHECK: 11:2459; CHECK-NEXT: tail call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.i64.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[VAL:%.*]], ptr [[BASE]], i64 [[OFFSET]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)2460; CHECK-NEXT: ret void2461;2462entry:2463 tail call void @llvm.riscv.vssseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, i64 %offset, <vscale x 1 x i1> %mask, i64 %vl, i64 5)2464 ret void2465}2466 2467 2468; Test stride value is a multiple of pointer alignment.2469define <vscale x 1 x i32> @intrinsic_vlse_v_nxv1i32_nxv1i32_align(<vscale x 1 x i32>* align 4 %0, i64 %1, i64 %2) sanitize_address {2470; CHECK-LABEL: @intrinsic_vlse_v_nxv1i32_nxv1i32_align(2471; CHECK-NEXT: entry:2472; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 82473; CHECK-NEXT: [[TMP4:%.*]] = icmp ne i64 [[TMP2:%.*]], 02474; CHECK-NEXT: br i1 [[TMP4]], label [[TMP5:%.*]], label [[TMP14:%.*]]2475; CHECK: 5:2476; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64()2477; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 [[TMP6]])2478; CHECK-NEXT: br label [[DOTSPLIT:%.*]]2479; CHECK: .split:2480; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP5]] ], [ [[IV_NEXT:%.*]], [[TMP13:%.*]] ]2481; CHECK-NEXT: [[TMP8:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]2482; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP13]]2483; CHECK: 9:2484; CHECK-NEXT: [[TMP10:%.*]] = mul i64 [[IV]], 42485; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[TMP0:%.*]], i64 [[TMP10]]2486; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[TMP11]] to i642487; CHECK-NEXT: call void @__asan_load4(i64 [[TMP12]])2488; CHECK-NEXT: br label [[TMP13]]2489; CHECK: 13:2490; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 12491; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP7]]2492; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]2493; CHECK: .split.split:2494; CHECK-NEXT: br label [[TMP14]]2495; CHECK: 14:2496; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32.p0.i64(<vscale x 1 x i32> poison, ptr [[TMP0]], i64 4, i64 [[TMP2]])2497; CHECK-NEXT: ret <vscale x 1 x i32> [[A]]2498;2499entry:2500 %a = call <vscale x 1 x i32> @llvm.riscv.vlse.nxv1i32(2501 <vscale x 1 x i32> poison,2502 <vscale x 1 x i32>* %0,2503 i64 4,2504 i64 %2)2505 2506 ret <vscale x 1 x i32> %a2507}2508 2509declare <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i16(2510 <vscale x 1 x i32>,2511 <vscale x 1 x i32>*,2512 <vscale x 1 x i16>,2513 i64);2514 2515define <vscale x 1 x i32> @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32>* %0, <vscale x 1 x i16> %1, i64 %2) sanitize_address {2516; CHECK-LABEL: @intrinsic_vloxei_v_nxv1i32_nxv1i32_nxv1i16(2517; CHECK-NEXT: entry:2518; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 82519; CHECK-NEXT: [[TMP4:%.*]] = zext <vscale x 1 x i16> [[TMP1:%.*]] to <vscale x 1 x i64>2520; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0:%.*]], <vscale x 1 x i64> [[TMP4]]2521; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i64 [[TMP2:%.*]], 02522; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP15:%.*]]2523; CHECK: 7:2524; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()2525; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 [[TMP8]])2526; CHECK-NEXT: br label [[DOTSPLIT:%.*]]2527; CHECK: .split:2528; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[TMP14:%.*]] ]2529; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]2530; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP14]]2531; CHECK: 11:2532; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x ptr> [[TMP5]], i64 [[IV]]2533; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[TMP12]] to i642534; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP13]], i64 4)2535; CHECK-NEXT: br label [[TMP14]]2536; CHECK: 14:2537; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 12538; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP9]]2539; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]2540; CHECK: .split.split:2541; CHECK-NEXT: br label [[TMP15]]2542; CHECK: 15:2543; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.p0.nxv1i16.i64(<vscale x 1 x i32> poison, ptr [[TMP0]], <vscale x 1 x i16> [[TMP1]], i64 [[TMP2]])2544; CHECK-NEXT: ret <vscale x 1 x i32> [[A]]2545;2546entry:2547 %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.nxv1i32.nxv1i16(2548 <vscale x 1 x i32> poison,2549 <vscale x 1 x i32>* %0,2550 <vscale x 1 x i16> %1,2551 i64 %2)2552 2553 ret <vscale x 1 x i32> %a2554}2555 2556declare <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i16(2557 <vscale x 1 x i32>,2558 <vscale x 1 x i32>*,2559 <vscale x 1 x i16>,2560 <vscale x 1 x i1>,2561 i64,2562 i64);2563 2564define <vscale x 1 x i32> @intrinsic_vloxei_mask_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) sanitize_address {2565; CHECK-LABEL: @intrinsic_vloxei_mask_v_nxv1i32_nxv1i32_nxv1i16(2566; CHECK-NEXT: entry:2567; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 82568; CHECK-NEXT: [[TMP6:%.*]] = zext <vscale x 1 x i16> [[TMP2:%.*]] to <vscale x 1 x i64>2569; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP1:%.*]], <vscale x 1 x i64> [[TMP6]]2570; CHECK-NEXT: [[TMP8:%.*]] = icmp ne i64 [[TMP4:%.*]], 02571; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP17:%.*]]2572; CHECK: 9:2573; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()2574; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP4]], i64 [[TMP10]])2575; CHECK-NEXT: br label [[DOTSPLIT:%.*]]2576; CHECK: .split:2577; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP9]] ], [ [[IV_NEXT:%.*]], [[TMP16:%.*]] ]2578; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x i1> [[TMP3:%.*]], i64 [[IV]]2579; CHECK-NEXT: br i1 [[TMP12]], label [[TMP13:%.*]], label [[TMP16]]2580; CHECK: 13:2581; CHECK-NEXT: [[TMP14:%.*]] = extractelement <vscale x 1 x ptr> [[TMP7]], i64 [[IV]]2582; CHECK-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[TMP14]] to i642583; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP15]], i64 4)2584; CHECK-NEXT: br label [[TMP16]]2585; CHECK: 16:2586; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 12587; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP11]]2588; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]2589; CHECK: .split.split:2590; CHECK-NEXT: br label [[TMP17]]2591; CHECK: 17:2592; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.p0.nxv1i16.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], <vscale x 1 x i16> [[TMP2]], <vscale x 1 x i1> [[TMP3]], i64 [[TMP4]], i64 1)2593; CHECK-NEXT: ret <vscale x 1 x i32> [[A]]2594;2595entry:2596 %a = call <vscale x 1 x i32> @llvm.riscv.vloxei.mask.nxv1i32.nxv1i16(2597 <vscale x 1 x i32> %0,2598 <vscale x 1 x i32>* %1,2599 <vscale x 1 x i16> %2,2600 <vscale x 1 x i1> %3,2601 i64 %4, i64 1)2602 2603 ret <vscale x 1 x i32> %a2604}2605 2606declare <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i16(2607 <vscale x 1 x float>,2608 <vscale x 1 x float>*,2609 <vscale x 1 x i16>,2610 i64);2611 2612define <vscale x 1 x float> @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i16(<vscale x 1 x float>* %0, <vscale x 1 x i16> %1, i64 %2) sanitize_address {2613; CHECK-LABEL: @intrinsic_vloxei_v_nxv1f32_nxv1f32_nxv1i16(2614; CHECK-NEXT: entry:2615; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 82616; CHECK-NEXT: [[TMP4:%.*]] = zext <vscale x 1 x i16> [[TMP1:%.*]] to <vscale x 1 x i64>2617; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0:%.*]], <vscale x 1 x i64> [[TMP4]]2618; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i64 [[TMP2:%.*]], 02619; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP15:%.*]]2620; CHECK: 7:2621; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()2622; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 [[TMP8]])2623; CHECK-NEXT: br label [[DOTSPLIT:%.*]]2624; CHECK: .split:2625; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[TMP14:%.*]] ]2626; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]2627; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP14]]2628; CHECK: 11:2629; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x ptr> [[TMP5]], i64 [[IV]]2630; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[TMP12]] to i642631; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP13]], i64 4)2632; CHECK-NEXT: br label [[TMP14]]2633; CHECK: 14:2634; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 12635; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP9]]2636; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]2637; CHECK: .split.split:2638; CHECK-NEXT: br label [[TMP15]]2639; CHECK: 15:2640; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.p0.nxv1i16.i64(<vscale x 1 x float> poison, ptr [[TMP0]], <vscale x 1 x i16> [[TMP1]], i64 [[TMP2]])2641; CHECK-NEXT: ret <vscale x 1 x float> [[A]]2642;2643entry:2644 %a = call <vscale x 1 x float> @llvm.riscv.vloxei.nxv1f32.nxv1i16(2645 <vscale x 1 x float> poison,2646 <vscale x 1 x float>* %0,2647 <vscale x 1 x i16> %1,2648 i64 %2)2649 2650 ret <vscale x 1 x float> %a2651}2652 2653declare <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16(2654 <vscale x 1 x i32>,2655 <vscale x 1 x i32>*,2656 <vscale x 1 x i16>,2657 i64);2658 2659define <vscale x 1 x i32> @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32>* %0, <vscale x 1 x i16> %1, i64 %2) sanitize_address {2660; CHECK-LABEL: @intrinsic_vluxei_v_nxv1i32_nxv1i32_nxv1i16(2661; CHECK-NEXT: entry:2662; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 82663; CHECK-NEXT: [[TMP4:%.*]] = zext <vscale x 1 x i16> [[TMP1:%.*]] to <vscale x 1 x i64>2664; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[TMP0:%.*]], <vscale x 1 x i64> [[TMP4]]2665; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i64 [[TMP2:%.*]], 02666; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP15:%.*]]2667; CHECK: 7:2668; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64()2669; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP2]], i64 [[TMP8]])2670; CHECK-NEXT: br label [[DOTSPLIT:%.*]]2671; CHECK: .split:2672; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP7]] ], [ [[IV_NEXT:%.*]], [[TMP14:%.*]] ]2673; CHECK-NEXT: [[TMP10:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]2674; CHECK-NEXT: br i1 [[TMP10]], label [[TMP11:%.*]], label [[TMP14]]2675; CHECK: 11:2676; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x ptr> [[TMP5]], i64 [[IV]]2677; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[TMP12]] to i642678; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP13]], i64 4)2679; CHECK-NEXT: br label [[TMP14]]2680; CHECK: 14:2681; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 12682; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP9]]2683; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]2684; CHECK: .split.split:2685; CHECK-NEXT: br label [[TMP15]]2686; CHECK: 15:2687; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.p0.nxv1i16.i64(<vscale x 1 x i32> poison, ptr [[TMP0]], <vscale x 1 x i16> [[TMP1]], i64 [[TMP2]])2688; CHECK-NEXT: ret <vscale x 1 x i32> [[A]]2689;2690entry:2691 %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.nxv1i32.nxv1i16(2692 <vscale x 1 x i32> poison,2693 <vscale x 1 x i32>* %0,2694 <vscale x 1 x i16> %1,2695 i64 %2)2696 2697 ret <vscale x 1 x i32> %a2698}2699 2700declare <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i16(2701 <vscale x 1 x i32>,2702 <vscale x 1 x i32>*,2703 <vscale x 1 x i16>,2704 <vscale x 1 x i1>,2705 i64,2706 i64);2707 2708define <vscale x 1 x i32> @intrinsic_vluxei_mask_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) sanitize_address {2709; CHECK-LABEL: @intrinsic_vluxei_mask_v_nxv1i32_nxv1i32_nxv1i16(2710; CHECK-NEXT: entry:2711; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 82712; CHECK-NEXT: [[TMP6:%.*]] = zext <vscale x 1 x i16> [[TMP2:%.*]] to <vscale x 1 x i64>2713; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP1:%.*]], <vscale x 1 x i64> [[TMP6]]2714; CHECK-NEXT: [[TMP8:%.*]] = icmp ne i64 [[TMP4:%.*]], 02715; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP17:%.*]]2716; CHECK: 9:2717; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()2718; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP4]], i64 [[TMP10]])2719; CHECK-NEXT: br label [[DOTSPLIT:%.*]]2720; CHECK: .split:2721; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP9]] ], [ [[IV_NEXT:%.*]], [[TMP16:%.*]] ]2722; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x i1> [[TMP3:%.*]], i64 [[IV]]2723; CHECK-NEXT: br i1 [[TMP12]], label [[TMP13:%.*]], label [[TMP16]]2724; CHECK: 13:2725; CHECK-NEXT: [[TMP14:%.*]] = extractelement <vscale x 1 x ptr> [[TMP7]], i64 [[IV]]2726; CHECK-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[TMP14]] to i642727; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP15]], i64 4)2728; CHECK-NEXT: br label [[TMP16]]2729; CHECK: 16:2730; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 12731; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP11]]2732; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]2733; CHECK: .split.split:2734; CHECK-NEXT: br label [[TMP17]]2735; CHECK: 17:2736; CHECK-NEXT: [[A:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.p0.nxv1i16.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], <vscale x 1 x i16> [[TMP2]], <vscale x 1 x i1> [[TMP3]], i64 [[TMP4]], i64 1)2737; CHECK-NEXT: ret <vscale x 1 x i32> [[A]]2738;2739entry:2740 %a = call <vscale x 1 x i32> @llvm.riscv.vluxei.mask.nxv1i32.nxv1i16(2741 <vscale x 1 x i32> %0,2742 <vscale x 1 x i32>* %1,2743 <vscale x 1 x i16> %2,2744 <vscale x 1 x i1> %3,2745 i64 %4, i64 1)2746 2747 ret <vscale x 1 x i32> %a2748}2749 2750declare void @llvm.riscv.vsoxei.nxv1i32.nxv1i16(2751 <vscale x 1 x i32>,2752 <vscale x 1 x i32>*,2753 <vscale x 1 x i16>,2754 i64);2755 2756define void @intrinsic_vsoxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i16> %2, i64 %3) sanitize_address {2757; CHECK-LABEL: @intrinsic_vsoxei_v_nxv1i32_nxv1i32_nxv1i16(2758; CHECK-NEXT: entry:2759; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 82760; CHECK-NEXT: [[TMP5:%.*]] = zext <vscale x 1 x i16> [[TMP2:%.*]] to <vscale x 1 x i64>2761; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[TMP1:%.*]], <vscale x 1 x i64> [[TMP5]]2762; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i64 [[TMP3:%.*]], 02763; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP16:%.*]]2764; CHECK: 8:2765; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()2766; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP3]], i64 [[TMP9]])2767; CHECK-NEXT: br label [[DOTSPLIT:%.*]]2768; CHECK: .split:2769; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP8]] ], [ [[IV_NEXT:%.*]], [[TMP15:%.*]] ]2770; CHECK-NEXT: [[TMP11:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]2771; CHECK-NEXT: br i1 [[TMP11]], label [[TMP12:%.*]], label [[TMP15]]2772; CHECK: 12:2773; CHECK-NEXT: [[TMP13:%.*]] = extractelement <vscale x 1 x ptr> [[TMP6]], i64 [[IV]]2774; CHECK-NEXT: [[TMP14:%.*]] = ptrtoint ptr [[TMP13]] to i642775; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP14]], i64 4)2776; CHECK-NEXT: br label [[TMP15]]2777; CHECK: 15:2778; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 12779; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP10]]2780; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]2781; CHECK: .split.split:2782; CHECK-NEXT: br label [[TMP16]]2783; CHECK: 16:2784; CHECK-NEXT: call void @llvm.riscv.vsoxei.nxv1i32.p0.nxv1i16.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], <vscale x 1 x i16> [[TMP2]], i64 [[TMP3]])2785; CHECK-NEXT: ret void2786;2787entry:2788 call void @llvm.riscv.vsoxei.nxv1i32.nxv1i16(2789 <vscale x 1 x i32> %0,2790 <vscale x 1 x i32>* %1,2791 <vscale x 1 x i16> %2,2792 i64 %3)2793 2794 ret void2795}2796 2797declare void @llvm.riscv.vsoxei.mask.nxv1i32.nxv1i16(2798 <vscale x 1 x i32>,2799 <vscale x 1 x i32>*,2800 <vscale x 1 x i16>,2801 <vscale x 1 x i1>,2802 i64);2803 2804define void @intrinsic_vsoxei_mask_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) sanitize_address {2805; CHECK-LABEL: @intrinsic_vsoxei_mask_v_nxv1i32_nxv1i32_nxv1i16(2806; CHECK-NEXT: entry:2807; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 82808; CHECK-NEXT: [[TMP6:%.*]] = zext <vscale x 1 x i16> [[TMP2:%.*]] to <vscale x 1 x i64>2809; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP1:%.*]], <vscale x 1 x i64> [[TMP6]]2810; CHECK-NEXT: [[TMP8:%.*]] = icmp ne i64 [[TMP4:%.*]], 02811; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP17:%.*]]2812; CHECK: 9:2813; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()2814; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP4]], i64 [[TMP10]])2815; CHECK-NEXT: br label [[DOTSPLIT:%.*]]2816; CHECK: .split:2817; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP9]] ], [ [[IV_NEXT:%.*]], [[TMP16:%.*]] ]2818; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x i1> [[TMP3:%.*]], i64 [[IV]]2819; CHECK-NEXT: br i1 [[TMP12]], label [[TMP13:%.*]], label [[TMP16]]2820; CHECK: 13:2821; CHECK-NEXT: [[TMP14:%.*]] = extractelement <vscale x 1 x ptr> [[TMP7]], i64 [[IV]]2822; CHECK-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[TMP14]] to i642823; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP15]], i64 4)2824; CHECK-NEXT: br label [[TMP16]]2825; CHECK: 16:2826; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 12827; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP11]]2828; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]2829; CHECK: .split.split:2830; CHECK-NEXT: br label [[TMP17]]2831; CHECK: 17:2832; CHECK-NEXT: call void @llvm.riscv.vsoxei.mask.nxv1i32.p0.nxv1i16.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], <vscale x 1 x i16> [[TMP2]], <vscale x 1 x i1> [[TMP3]], i64 [[TMP4]])2833; CHECK-NEXT: ret void2834;2835entry:2836 call void @llvm.riscv.vsoxei.mask.nxv1i32.nxv1i16(2837 <vscale x 1 x i32> %0,2838 <vscale x 1 x i32>* %1,2839 <vscale x 1 x i16> %2,2840 <vscale x 1 x i1> %3,2841 i64 %4)2842 2843 ret void2844}2845 2846declare void @llvm.riscv.vsuxei.nxv1i32.nxv1i16(2847 <vscale x 1 x i32>,2848 <vscale x 1 x i32>*,2849 <vscale x 1 x i16>,2850 i64);2851 2852define void @intrinsic_vsuxei_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i16> %2, i64 %3) sanitize_address {2853; CHECK-LABEL: @intrinsic_vsuxei_v_nxv1i32_nxv1i32_nxv1i16(2854; CHECK-NEXT: entry:2855; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 82856; CHECK-NEXT: [[TMP5:%.*]] = zext <vscale x 1 x i16> [[TMP2:%.*]] to <vscale x 1 x i64>2857; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[TMP1:%.*]], <vscale x 1 x i64> [[TMP5]]2858; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i64 [[TMP3:%.*]], 02859; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP16:%.*]]2860; CHECK: 8:2861; CHECK-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64()2862; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP3]], i64 [[TMP9]])2863; CHECK-NEXT: br label [[DOTSPLIT:%.*]]2864; CHECK: .split:2865; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP8]] ], [ [[IV_NEXT:%.*]], [[TMP15:%.*]] ]2866; CHECK-NEXT: [[TMP11:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]2867; CHECK-NEXT: br i1 [[TMP11]], label [[TMP12:%.*]], label [[TMP15]]2868; CHECK: 12:2869; CHECK-NEXT: [[TMP13:%.*]] = extractelement <vscale x 1 x ptr> [[TMP6]], i64 [[IV]]2870; CHECK-NEXT: [[TMP14:%.*]] = ptrtoint ptr [[TMP13]] to i642871; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP14]], i64 4)2872; CHECK-NEXT: br label [[TMP15]]2873; CHECK: 15:2874; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 12875; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP10]]2876; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]2877; CHECK: .split.split:2878; CHECK-NEXT: br label [[TMP16]]2879; CHECK: 16:2880; CHECK-NEXT: call void @llvm.riscv.vsuxei.nxv1i32.p0.nxv1i16.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], <vscale x 1 x i16> [[TMP2]], i64 [[TMP3]])2881; CHECK-NEXT: ret void2882;2883entry:2884 call void @llvm.riscv.vsuxei.nxv1i32.nxv1i16(2885 <vscale x 1 x i32> %0,2886 <vscale x 1 x i32>* %1,2887 <vscale x 1 x i16> %2,2888 i64 %3)2889 2890 ret void2891}2892 2893declare void @llvm.riscv.vsuxei.mask.nxv1i32.nxv1i16(2894 <vscale x 1 x i32>,2895 <vscale x 1 x i32>*,2896 <vscale x 1 x i16>,2897 <vscale x 1 x i1>,2898 i64);2899 2900define void @intrinsic_vsuxei_mask_v_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i32> %0, <vscale x 1 x i32>* %1, <vscale x 1 x i16> %2, <vscale x 1 x i1> %3, i64 %4) sanitize_address {2901; CHECK-LABEL: @intrinsic_vsuxei_mask_v_nxv1i32_nxv1i32_nxv1i16(2902; CHECK-NEXT: entry:2903; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 82904; CHECK-NEXT: [[TMP6:%.*]] = zext <vscale x 1 x i16> [[TMP2:%.*]] to <vscale x 1 x i64>2905; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP1:%.*]], <vscale x 1 x i64> [[TMP6]]2906; CHECK-NEXT: [[TMP8:%.*]] = icmp ne i64 [[TMP4:%.*]], 02907; CHECK-NEXT: br i1 [[TMP8]], label [[TMP9:%.*]], label [[TMP17:%.*]]2908; CHECK: 9:2909; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64()2910; CHECK-NEXT: [[TMP11:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP4]], i64 [[TMP10]])2911; CHECK-NEXT: br label [[DOTSPLIT:%.*]]2912; CHECK: .split:2913; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP9]] ], [ [[IV_NEXT:%.*]], [[TMP16:%.*]] ]2914; CHECK-NEXT: [[TMP12:%.*]] = extractelement <vscale x 1 x i1> [[TMP3:%.*]], i64 [[IV]]2915; CHECK-NEXT: br i1 [[TMP12]], label [[TMP13:%.*]], label [[TMP16]]2916; CHECK: 13:2917; CHECK-NEXT: [[TMP14:%.*]] = extractelement <vscale x 1 x ptr> [[TMP7]], i64 [[IV]]2918; CHECK-NEXT: [[TMP15:%.*]] = ptrtoint ptr [[TMP14]] to i642919; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP15]], i64 4)2920; CHECK-NEXT: br label [[TMP16]]2921; CHECK: 16:2922; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 12923; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP11]]2924; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]2925; CHECK: .split.split:2926; CHECK-NEXT: br label [[TMP17]]2927; CHECK: 17:2928; CHECK-NEXT: call void @llvm.riscv.vsuxei.mask.nxv1i32.p0.nxv1i16.i64(<vscale x 1 x i32> [[TMP0:%.*]], ptr [[TMP1]], <vscale x 1 x i16> [[TMP2]], <vscale x 1 x i1> [[TMP3]], i64 [[TMP4]])2929; CHECK-NEXT: ret void2930;2931entry:2932 call void @llvm.riscv.vsuxei.mask.nxv1i32.nxv1i16(2933 <vscale x 1 x i32> %0,2934 <vscale x 1 x i32>* %1,2935 <vscale x 1 x i16> %2,2936 <vscale x 1 x i1> %3,2937 i64 %4)2938 2939 ret void2940}2941 2942 2943declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, <vscale x 1 x i16>, i64, i64)2944declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64, i64)2945 2946define <vscale x 1 x i32> @test_vloxseg2_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {2947; CHECK-LABEL: @test_vloxseg2_nxv1i32_nxv1i16(2948; CHECK-NEXT: entry:2949; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 82950; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>2951; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]2952; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 02953; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]2954; CHECK: 4:2955; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()2956; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])2957; CHECK-NEXT: br label [[DOTSPLIT:%.*]]2958; CHECK: .split:2959; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]2960; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]2961; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]2962; CHECK: 8:2963; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]2964; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i642965; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP10]], i64 8)2966; CHECK-NEXT: br label [[TMP11]]2967; CHECK: 11:2968; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 12969; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]2970; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]2971; CHECK: .split.split:2972; CHECK-NEXT: br label [[TMP12]]2973; CHECK: 12:2974; CHECK-NEXT: [[TMP25:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)2975; CHECK-NEXT: [[TMP26:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_2t(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[TMP25]], i32 1)2976; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP26]]2977;2978entry:2979 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.triscv.vector.tuple_nxv4i8_2t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)2980 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_2t(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, i32 1)2981 ret <vscale x 1 x i32> %12982}2983 2984define <vscale x 1 x i32> @test_vloxseg2_mask_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {2985; CHECK-LABEL: @test_vloxseg2_mask_nxv1i32_nxv1i16(2986; CHECK-NEXT: entry:2987; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 82988; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>2989; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]2990; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 02991; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]2992; CHECK: 4:2993; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()2994; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])2995; CHECK-NEXT: br label [[DOTSPLIT:%.*]]2996; CHECK: .split:2997; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]2998; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]2999; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]3000; CHECK: 8:3001; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]3002; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i643003; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP10]], i64 8)3004; CHECK-NEXT: br label [[TMP11]]3005; CHECK: 11:3006; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 13007; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]3008; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]3009; CHECK: .split.split:3010; CHECK-NEXT: br label [[TMP12]]3011; CHECK: 12:3012; CHECK-NEXT: [[TMP25:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)3013; CHECK-NEXT: [[TMP26:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_2t(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[TMP25]], i32 1)3014; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP26]]3015;3016entry:3017 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vloxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv4i1.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1, i64 5)3018 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_2t(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, i32 1)3019 ret <vscale x 1 x i32> %13020}3021 3022 3023declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, <vscale x 1 x i16>, i64, i64)3024declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64, i64)3025 3026define <vscale x 1 x i32> @test_vloxseg3_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {3027; CHECK-LABEL: @test_vloxseg3_nxv1i32_nxv1i16(3028; CHECK-NEXT: entry:3029; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 83030; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>3031; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]3032; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 03033; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]3034; CHECK: 4:3035; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()3036; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])3037; CHECK-NEXT: br label [[DOTSPLIT:%.*]]3038; CHECK: .split:3039; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]3040; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]3041; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]3042; CHECK: 8:3043; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]3044; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i643045; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP10]], i64 12)3046; CHECK-NEXT: br label [[TMP11]]3047; CHECK: 11:3048; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 13049; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]3050; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]3051; CHECK: .split.split:3052; CHECK-NEXT: br label [[TMP12]]3053; CHECK: 12:3054; CHECK-NEXT: [[TMP37:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)3055; CHECK-NEXT: [[TMP38:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_3t(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[TMP37]], i32 1)3056; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP38]]3057;3058entry:3059 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.triscv.vector.tuple_nxv4i8_3t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)3060 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_3t(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, i32 1)3061 ret <vscale x 1 x i32> %13062}3063 3064define <vscale x 1 x i32> @test_vloxseg3_mask_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {3065; CHECK-LABEL: @test_vloxseg3_mask_nxv1i32_nxv1i16(3066; CHECK-NEXT: entry:3067; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 83068; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>3069; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]3070; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 03071; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]3072; CHECK: 4:3073; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()3074; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])3075; CHECK-NEXT: br label [[DOTSPLIT:%.*]]3076; CHECK: .split:3077; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]3078; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]3079; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]3080; CHECK: 8:3081; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]3082; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i643083; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP10]], i64 12)3084; CHECK-NEXT: br label [[TMP11]]3085; CHECK: 11:3086; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 13087; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]3088; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]3089; CHECK: .split.split:3090; CHECK-NEXT: br label [[TMP12]]3091; CHECK: 12:3092; CHECK-NEXT: [[TMP37:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)3093; CHECK-NEXT: [[TMP38:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_3t(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[TMP37]], i32 1)3094; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP38]]3095;3096entry:3097 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vloxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv4i1.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1, i64 5)3098 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_3t(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, i32 1)3099 ret <vscale x 1 x i32> %13100}3101 3102 3103declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, <vscale x 1 x i16>, i64, i64)3104declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64, i64)3105 3106define <vscale x 1 x i32> @test_vloxseg4_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {3107; CHECK-LABEL: @test_vloxseg4_nxv1i32_nxv1i16(3108; CHECK-NEXT: entry:3109; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 83110; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>3111; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]3112; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 03113; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]3114; CHECK: 4:3115; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()3116; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])3117; CHECK-NEXT: br label [[DOTSPLIT:%.*]]3118; CHECK: .split:3119; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]3120; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]3121; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]3122; CHECK: 8:3123; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]3124; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i643125; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP10]], i64 16)3126; CHECK-NEXT: br label [[TMP11]]3127; CHECK: 11:3128; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 13129; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]3130; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]3131; CHECK: .split.split:3132; CHECK-NEXT: br label [[TMP12]]3133; CHECK: 12:3134; CHECK-NEXT: [[TMP49:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)3135; CHECK-NEXT: [[TMP50:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_4t(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[TMP49]], i32 1)3136; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP50]]3137;3138entry:3139 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.triscv.vector.tuple_nxv4i8_4t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)3140 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_4t(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, i32 1)3141 ret <vscale x 1 x i32> %13142}3143 3144define <vscale x 1 x i32> @test_vloxseg4_mask_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {3145; CHECK-LABEL: @test_vloxseg4_mask_nxv1i32_nxv1i16(3146; CHECK-NEXT: entry:3147; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 83148; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>3149; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]3150; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 03151; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]3152; CHECK: 4:3153; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()3154; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])3155; CHECK-NEXT: br label [[DOTSPLIT:%.*]]3156; CHECK: .split:3157; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]3158; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]3159; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]3160; CHECK: 8:3161; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]3162; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i643163; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP10]], i64 16)3164; CHECK-NEXT: br label [[TMP11]]3165; CHECK: 11:3166; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 13167; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]3168; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]3169; CHECK: .split.split:3170; CHECK-NEXT: br label [[TMP12]]3171; CHECK: 12:3172; CHECK-NEXT: [[TMP49:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)3173; CHECK-NEXT: [[TMP50:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_4t(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[TMP49]], i32 1)3174; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP50]]3175;3176entry:3177 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vloxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv4i1.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1, i64 5)3178 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_4t(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, i32 1)3179 ret <vscale x 1 x i32> %13180}3181 3182 3183declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, <vscale x 1 x i16>, i64, i64)3184declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64, i64)3185 3186define <vscale x 1 x i32> @test_vloxseg5_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {3187; CHECK-LABEL: @test_vloxseg5_nxv1i32_nxv1i16(3188; CHECK-NEXT: entry:3189; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 83190; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>3191; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]3192; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 03193; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]3194; CHECK: 4:3195; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()3196; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])3197; CHECK-NEXT: br label [[DOTSPLIT:%.*]]3198; CHECK: .split:3199; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]3200; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]3201; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]3202; CHECK: 8:3203; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]3204; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i643205; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP10]], i64 20)3206; CHECK-NEXT: br label [[TMP11]]3207; CHECK: 11:3208; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 13209; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]3210; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]3211; CHECK: .split.split:3212; CHECK-NEXT: br label [[TMP12]]3213; CHECK: 12:3214; CHECK-NEXT: [[TMP61:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)3215; CHECK-NEXT: [[TMP62:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_5t(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[TMP61]], i32 1)3216; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP62]]3217;3218entry:3219 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.triscv.vector.tuple_nxv4i8_5t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)3220 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_5t(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, i32 1)3221 ret <vscale x 1 x i32> %13222}3223 3224define <vscale x 1 x i32> @test_vloxseg5_mask_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {3225; CHECK-LABEL: @test_vloxseg5_mask_nxv1i32_nxv1i16(3226; CHECK-NEXT: entry:3227; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 83228; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>3229; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]3230; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 03231; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]3232; CHECK: 4:3233; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()3234; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])3235; CHECK-NEXT: br label [[DOTSPLIT:%.*]]3236; CHECK: .split:3237; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]3238; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]3239; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]3240; CHECK: 8:3241; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]3242; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i643243; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP10]], i64 20)3244; CHECK-NEXT: br label [[TMP11]]3245; CHECK: 11:3246; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 13247; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]3248; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]3249; CHECK: .split.split:3250; CHECK-NEXT: br label [[TMP12]]3251; CHECK: 12:3252; CHECK-NEXT: [[TMP61:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)3253; CHECK-NEXT: [[TMP62:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_5t(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[TMP61]], i32 1)3254; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP62]]3255;3256entry:3257 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vloxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv4i1.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1, i64 5)3258 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_5t(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, i32 1)3259 ret <vscale x 1 x i32> %13260}3261 3262 3263declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, <vscale x 1 x i16>, i64, i64)3264declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64, i64)3265 3266define <vscale x 1 x i32> @test_vloxseg6_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {3267; CHECK-LABEL: @test_vloxseg6_nxv1i32_nxv1i16(3268; CHECK-NEXT: entry:3269; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 83270; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>3271; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]3272; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 03273; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]3274; CHECK: 4:3275; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()3276; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])3277; CHECK-NEXT: br label [[DOTSPLIT:%.*]]3278; CHECK: .split:3279; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]3280; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]3281; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]3282; CHECK: 8:3283; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]3284; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i643285; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP10]], i64 24)3286; CHECK-NEXT: br label [[TMP11]]3287; CHECK: 11:3288; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 13289; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]3290; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]3291; CHECK: .split.split:3292; CHECK-NEXT: br label [[TMP12]]3293; CHECK: 12:3294; CHECK-NEXT: [[TMP73:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)3295; CHECK-NEXT: [[TMP74:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_6t(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[TMP73]], i32 1)3296; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP74]]3297;3298entry:3299 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.triscv.vector.tuple_nxv4i8_6t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)3300 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_6t(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, i32 1)3301 ret <vscale x 1 x i32> %13302}3303 3304define <vscale x 1 x i32> @test_vloxseg6_mask_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {3305; CHECK-LABEL: @test_vloxseg6_mask_nxv1i32_nxv1i16(3306; CHECK-NEXT: entry:3307; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 83308; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>3309; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]3310; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 03311; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]3312; CHECK: 4:3313; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()3314; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])3315; CHECK-NEXT: br label [[DOTSPLIT:%.*]]3316; CHECK: .split:3317; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]3318; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]3319; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]3320; CHECK: 8:3321; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]3322; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i643323; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP10]], i64 24)3324; CHECK-NEXT: br label [[TMP11]]3325; CHECK: 11:3326; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 13327; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]3328; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]3329; CHECK: .split.split:3330; CHECK-NEXT: br label [[TMP12]]3331; CHECK: 12:3332; CHECK-NEXT: [[TMP73:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)3333; CHECK-NEXT: [[TMP74:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_6t(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[TMP73]], i32 1)3334; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP74]]3335;3336entry:3337 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vloxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv4i1.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1, i64 5)3338 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_6t(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, i32 1)3339 ret <vscale x 1 x i32> %13340}3341 3342 3343declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, <vscale x 1 x i16>, i64, i64)3344declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64, i64)3345 3346define <vscale x 1 x i32> @test_vloxseg7_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {3347; CHECK-LABEL: @test_vloxseg7_nxv1i32_nxv1i16(3348; CHECK-NEXT: entry:3349; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 83350; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>3351; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]3352; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 03353; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]3354; CHECK: 4:3355; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()3356; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])3357; CHECK-NEXT: br label [[DOTSPLIT:%.*]]3358; CHECK: .split:3359; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]3360; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]3361; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]3362; CHECK: 8:3363; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]3364; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i643365; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP10]], i64 28)3366; CHECK-NEXT: br label [[TMP11]]3367; CHECK: 11:3368; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 13369; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]3370; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]3371; CHECK: .split.split:3372; CHECK-NEXT: br label [[TMP12]]3373; CHECK: 12:3374; CHECK-NEXT: [[TMP85:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)3375; CHECK-NEXT: [[TMP86:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_7t(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[TMP85]], i32 1)3376; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP86]]3377;3378entry:3379 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.triscv.vector.tuple_nxv4i8_7t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)3380 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_7t(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, i32 1)3381 ret <vscale x 1 x i32> %13382}3383 3384define <vscale x 1 x i32> @test_vloxseg7_mask_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {3385; CHECK-LABEL: @test_vloxseg7_mask_nxv1i32_nxv1i16(3386; CHECK-NEXT: entry:3387; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 83388; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>3389; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]3390; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 03391; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]3392; CHECK: 4:3393; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()3394; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])3395; CHECK-NEXT: br label [[DOTSPLIT:%.*]]3396; CHECK: .split:3397; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]3398; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]3399; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]3400; CHECK: 8:3401; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]3402; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i643403; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP10]], i64 28)3404; CHECK-NEXT: br label [[TMP11]]3405; CHECK: 11:3406; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 13407; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]3408; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]3409; CHECK: .split.split:3410; CHECK-NEXT: br label [[TMP12]]3411; CHECK: 12:3412; CHECK-NEXT: [[TMP85:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)3413; CHECK-NEXT: [[TMP86:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_7t(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[TMP85]], i32 1)3414; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP86]]3415;3416entry:3417 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vloxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv4i1.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1, i64 5)3418 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_7t(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, i32 1)3419 ret <vscale x 1 x i32> %13420}3421 3422 3423declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, <vscale x 1 x i16>, i64, i64)3424declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64, i64)3425 3426define <vscale x 1 x i32> @test_vloxseg8_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {3427; CHECK-LABEL: @test_vloxseg8_nxv1i32_nxv1i16(3428; CHECK-NEXT: entry:3429; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 83430; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>3431; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]3432; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 03433; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]3434; CHECK: 4:3435; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()3436; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])3437; CHECK-NEXT: br label [[DOTSPLIT:%.*]]3438; CHECK: .split:3439; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]3440; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]3441; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]3442; CHECK: 8:3443; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]3444; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i643445; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP10]], i64 32)3446; CHECK-NEXT: br label [[TMP11]]3447; CHECK: 11:3448; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 13449; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]3450; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]3451; CHECK: .split.split:3452; CHECK-NEXT: br label [[TMP12]]3453; CHECK: 12:3454; CHECK-NEXT: [[TMP97:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)3455; CHECK-NEXT: [[TMP98:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_8t(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[TMP97]], i32 1)3456; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP98]]3457;3458entry:3459 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.triscv.vector.tuple_nxv4i8_8t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)3460 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_8t(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, i32 1)3461 ret <vscale x 1 x i32> %13462}3463 3464define <vscale x 1 x i32> @test_vloxseg8_mask_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {3465; CHECK-LABEL: @test_vloxseg8_mask_nxv1i32_nxv1i16(3466; CHECK-NEXT: entry:3467; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 83468; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>3469; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]3470; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 03471; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]3472; CHECK: 4:3473; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()3474; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])3475; CHECK-NEXT: br label [[DOTSPLIT:%.*]]3476; CHECK: .split:3477; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]3478; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]3479; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]3480; CHECK: 8:3481; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]3482; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i643483; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP10]], i64 32)3484; CHECK-NEXT: br label [[TMP11]]3485; CHECK: 11:3486; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 13487; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]3488; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]3489; CHECK: .split.split:3490; CHECK-NEXT: br label [[TMP12]]3491; CHECK: 12:3492; CHECK-NEXT: [[TMP97:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)3493; CHECK-NEXT: [[TMP98:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_8t(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[TMP97]], i32 1)3494; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP98]]3495;3496entry:3497 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vloxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv4i1.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1, i64 5)3498 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_8t(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, i32 1)3499 ret <vscale x 1 x i32> %13500}3501 3502 3503declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, <vscale x 1 x i16>, i64, i64)3504declare target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64, i64)3505 3506define <vscale x 1 x i32> @test_vluxseg2_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {3507; CHECK-LABEL: @test_vluxseg2_nxv1i32_nxv1i16(3508; CHECK-NEXT: entry:3509; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 83510; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>3511; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]3512; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 03513; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]3514; CHECK: 4:3515; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()3516; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])3517; CHECK-NEXT: br label [[DOTSPLIT:%.*]]3518; CHECK: .split:3519; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]3520; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]3521; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]3522; CHECK: 8:3523; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]3524; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i643525; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP10]], i64 8)3526; CHECK-NEXT: br label [[TMP11]]3527; CHECK: 11:3528; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 13529; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]3530; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]3531; CHECK: .split.split:3532; CHECK-NEXT: br label [[TMP12]]3533; CHECK: 12:3534; CHECK-NEXT: [[TMP25:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)3535; CHECK-NEXT: [[TMP26:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_2t(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[TMP25]], i32 1)3536; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP26]]3537;3538entry:3539 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.triscv.vector.tuple_nxv4i8_2t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)3540 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_2t(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, i32 1)3541 ret <vscale x 1 x i32> %13542}3543 3544define <vscale x 1 x i32> @test_vluxseg2_mask_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {3545; CHECK-LABEL: @test_vluxseg2_mask_nxv1i32_nxv1i16(3546; CHECK-NEXT: entry:3547; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 83548; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>3549; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]3550; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 03551; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]3552; CHECK: 4:3553; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()3554; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])3555; CHECK-NEXT: br label [[DOTSPLIT:%.*]]3556; CHECK: .split:3557; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]3558; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]3559; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]3560; CHECK: 8:3561; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]3562; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i643563; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP10]], i64 8)3564; CHECK-NEXT: br label [[TMP11]]3565; CHECK: 11:3566; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 13567; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]3568; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]3569; CHECK: .split.split:3570; CHECK-NEXT: br label [[TMP12]]3571; CHECK: 12:3572; CHECK-NEXT: [[TMP25:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)3573; CHECK-NEXT: [[TMP26:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_2t(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[TMP25]], i32 1)3574; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP26]]3575;3576entry:3577 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 2) @llvm.riscv.vluxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv4i1.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) poison, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1, i64 5)3578 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_2t(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %0, i32 1)3579 ret <vscale x 1 x i32> %13580}3581 3582 3583declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, <vscale x 1 x i16>, i64, i64)3584declare target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64, i64)3585 3586define <vscale x 1 x i32> @test_vluxseg3_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {3587; CHECK-LABEL: @test_vluxseg3_nxv1i32_nxv1i16(3588; CHECK-NEXT: entry:3589; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 83590; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>3591; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]3592; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 03593; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]3594; CHECK: 4:3595; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()3596; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])3597; CHECK-NEXT: br label [[DOTSPLIT:%.*]]3598; CHECK: .split:3599; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]3600; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]3601; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]3602; CHECK: 8:3603; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]3604; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i643605; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP10]], i64 12)3606; CHECK-NEXT: br label [[TMP11]]3607; CHECK: 11:3608; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 13609; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]3610; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]3611; CHECK: .split.split:3612; CHECK-NEXT: br label [[TMP12]]3613; CHECK: 12:3614; CHECK-NEXT: [[TMP37:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)3615; CHECK-NEXT: [[TMP38:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_3t(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[TMP37]], i32 1)3616; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP38]]3617;3618entry:3619 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.triscv.vector.tuple_nxv4i8_3t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)3620 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_3t(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, i32 1)3621 ret <vscale x 1 x i32> %13622}3623 3624define <vscale x 1 x i32> @test_vluxseg3_mask_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {3625; CHECK-LABEL: @test_vluxseg3_mask_nxv1i32_nxv1i16(3626; CHECK-NEXT: entry:3627; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 83628; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>3629; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]3630; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 03631; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]3632; CHECK: 4:3633; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()3634; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])3635; CHECK-NEXT: br label [[DOTSPLIT:%.*]]3636; CHECK: .split:3637; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]3638; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]3639; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]3640; CHECK: 8:3641; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]3642; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i643643; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP10]], i64 12)3644; CHECK-NEXT: br label [[TMP11]]3645; CHECK: 11:3646; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 13647; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]3648; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]3649; CHECK: .split.split:3650; CHECK-NEXT: br label [[TMP12]]3651; CHECK: 12:3652; CHECK-NEXT: [[TMP37:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)3653; CHECK-NEXT: [[TMP38:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_3t(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[TMP37]], i32 1)3654; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP38]]3655;3656entry:3657 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 3) @llvm.riscv.vluxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv4i1.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) poison, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1, i64 5)3658 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_3t(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %0, i32 1)3659 ret <vscale x 1 x i32> %13660}3661 3662 3663declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, <vscale x 1 x i16>, i64, i64)3664declare target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64, i64)3665 3666define <vscale x 1 x i32> @test_vluxseg4_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {3667; CHECK-LABEL: @test_vluxseg4_nxv1i32_nxv1i16(3668; CHECK-NEXT: entry:3669; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 83670; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>3671; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]3672; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 03673; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]3674; CHECK: 4:3675; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()3676; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])3677; CHECK-NEXT: br label [[DOTSPLIT:%.*]]3678; CHECK: .split:3679; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]3680; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]3681; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]3682; CHECK: 8:3683; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]3684; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i643685; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP10]], i64 16)3686; CHECK-NEXT: br label [[TMP11]]3687; CHECK: 11:3688; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 13689; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]3690; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]3691; CHECK: .split.split:3692; CHECK-NEXT: br label [[TMP12]]3693; CHECK: 12:3694; CHECK-NEXT: [[TMP49:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)3695; CHECK-NEXT: [[TMP50:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_4t(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[TMP49]], i32 1)3696; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP50]]3697;3698entry:3699 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.triscv.vector.tuple_nxv4i8_4t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)3700 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_4t(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, i32 1)3701 ret <vscale x 1 x i32> %13702}3703 3704define <vscale x 1 x i32> @test_vluxseg4_mask_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {3705; CHECK-LABEL: @test_vluxseg4_mask_nxv1i32_nxv1i16(3706; CHECK-NEXT: entry:3707; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 83708; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>3709; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]3710; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 03711; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]3712; CHECK: 4:3713; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()3714; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])3715; CHECK-NEXT: br label [[DOTSPLIT:%.*]]3716; CHECK: .split:3717; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]3718; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]3719; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]3720; CHECK: 8:3721; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]3722; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i643723; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP10]], i64 16)3724; CHECK-NEXT: br label [[TMP11]]3725; CHECK: 11:3726; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 13727; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]3728; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]3729; CHECK: .split.split:3730; CHECK-NEXT: br label [[TMP12]]3731; CHECK: 12:3732; CHECK-NEXT: [[TMP49:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)3733; CHECK-NEXT: [[TMP50:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_4t(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[TMP49]], i32 1)3734; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP50]]3735;3736entry:3737 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 4) @llvm.riscv.vluxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv4i1.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) poison, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1, i64 5)3738 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_4t(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %0, i32 1)3739 ret <vscale x 1 x i32> %13740}3741 3742 3743declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, <vscale x 1 x i16>, i64, i64)3744declare target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64, i64)3745 3746define <vscale x 1 x i32> @test_vluxseg5_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {3747; CHECK-LABEL: @test_vluxseg5_nxv1i32_nxv1i16(3748; CHECK-NEXT: entry:3749; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 83750; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>3751; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]3752; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 03753; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]3754; CHECK: 4:3755; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()3756; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])3757; CHECK-NEXT: br label [[DOTSPLIT:%.*]]3758; CHECK: .split:3759; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]3760; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]3761; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]3762; CHECK: 8:3763; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]3764; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i643765; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP10]], i64 20)3766; CHECK-NEXT: br label [[TMP11]]3767; CHECK: 11:3768; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 13769; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]3770; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]3771; CHECK: .split.split:3772; CHECK-NEXT: br label [[TMP12]]3773; CHECK: 12:3774; CHECK-NEXT: [[TMP61:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)3775; CHECK-NEXT: [[TMP62:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_5t(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[TMP61]], i32 1)3776; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP62]]3777;3778entry:3779 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.triscv.vector.tuple_nxv4i8_5t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)3780 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_5t(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, i32 1)3781 ret <vscale x 1 x i32> %13782}3783 3784define <vscale x 1 x i32> @test_vluxseg5_mask_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {3785; CHECK-LABEL: @test_vluxseg5_mask_nxv1i32_nxv1i16(3786; CHECK-NEXT: entry:3787; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 83788; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>3789; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]3790; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 03791; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]3792; CHECK: 4:3793; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()3794; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])3795; CHECK-NEXT: br label [[DOTSPLIT:%.*]]3796; CHECK: .split:3797; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]3798; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]3799; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]3800; CHECK: 8:3801; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]3802; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i643803; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP10]], i64 20)3804; CHECK-NEXT: br label [[TMP11]]3805; CHECK: 11:3806; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 13807; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]3808; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]3809; CHECK: .split.split:3810; CHECK-NEXT: br label [[TMP12]]3811; CHECK: 12:3812; CHECK-NEXT: [[TMP61:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)3813; CHECK-NEXT: [[TMP62:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_5t(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[TMP61]], i32 1)3814; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP62]]3815;3816entry:3817 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 5) @llvm.riscv.vluxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv4i1.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) poison, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1, i64 5)3818 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_5t(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %0, i32 1)3819 ret <vscale x 1 x i32> %13820}3821 3822 3823declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, <vscale x 1 x i16>, i64, i64)3824declare target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64, i64)3825 3826define <vscale x 1 x i32> @test_vluxseg6_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {3827; CHECK-LABEL: @test_vluxseg6_nxv1i32_nxv1i16(3828; CHECK-NEXT: entry:3829; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 83830; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>3831; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]3832; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 03833; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]3834; CHECK: 4:3835; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()3836; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])3837; CHECK-NEXT: br label [[DOTSPLIT:%.*]]3838; CHECK: .split:3839; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]3840; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]3841; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]3842; CHECK: 8:3843; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]3844; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i643845; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP10]], i64 24)3846; CHECK-NEXT: br label [[TMP11]]3847; CHECK: 11:3848; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 13849; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]3850; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]3851; CHECK: .split.split:3852; CHECK-NEXT: br label [[TMP12]]3853; CHECK: 12:3854; CHECK-NEXT: [[TMP73:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)3855; CHECK-NEXT: [[TMP74:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_6t(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[TMP73]], i32 1)3856; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP74]]3857;3858entry:3859 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.triscv.vector.tuple_nxv4i8_6t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)3860 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_6t(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, i32 1)3861 ret <vscale x 1 x i32> %13862}3863 3864define <vscale x 1 x i32> @test_vluxseg6_mask_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {3865; CHECK-LABEL: @test_vluxseg6_mask_nxv1i32_nxv1i16(3866; CHECK-NEXT: entry:3867; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 83868; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>3869; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]3870; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 03871; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]3872; CHECK: 4:3873; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()3874; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])3875; CHECK-NEXT: br label [[DOTSPLIT:%.*]]3876; CHECK: .split:3877; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]3878; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]3879; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]3880; CHECK: 8:3881; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]3882; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i643883; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP10]], i64 24)3884; CHECK-NEXT: br label [[TMP11]]3885; CHECK: 11:3886; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 13887; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]3888; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]3889; CHECK: .split.split:3890; CHECK-NEXT: br label [[TMP12]]3891; CHECK: 12:3892; CHECK-NEXT: [[TMP73:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)3893; CHECK-NEXT: [[TMP74:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_6t(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[TMP73]], i32 1)3894; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP74]]3895;3896entry:3897 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 6) @llvm.riscv.vluxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv4i1.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) poison, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1, i64 5)3898 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_6t(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %0, i32 1)3899 ret <vscale x 1 x i32> %13900}3901 3902 3903declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, <vscale x 1 x i16>, i64, i64)3904declare target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64, i64)3905 3906define <vscale x 1 x i32> @test_vluxseg7_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {3907; CHECK-LABEL: @test_vluxseg7_nxv1i32_nxv1i16(3908; CHECK-NEXT: entry:3909; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 83910; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>3911; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]3912; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 03913; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]3914; CHECK: 4:3915; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()3916; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])3917; CHECK-NEXT: br label [[DOTSPLIT:%.*]]3918; CHECK: .split:3919; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]3920; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]3921; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]3922; CHECK: 8:3923; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]3924; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i643925; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP10]], i64 28)3926; CHECK-NEXT: br label [[TMP11]]3927; CHECK: 11:3928; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 13929; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]3930; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]3931; CHECK: .split.split:3932; CHECK-NEXT: br label [[TMP12]]3933; CHECK: 12:3934; CHECK-NEXT: [[TMP85:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)3935; CHECK-NEXT: [[TMP86:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_7t(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[TMP85]], i32 1)3936; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP86]]3937;3938entry:3939 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.triscv.vector.tuple_nxv4i8_7t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)3940 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_7t(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, i32 1)3941 ret <vscale x 1 x i32> %13942}3943 3944define <vscale x 1 x i32> @test_vluxseg7_mask_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {3945; CHECK-LABEL: @test_vluxseg7_mask_nxv1i32_nxv1i16(3946; CHECK-NEXT: entry:3947; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 83948; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>3949; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]3950; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 03951; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]3952; CHECK: 4:3953; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()3954; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])3955; CHECK-NEXT: br label [[DOTSPLIT:%.*]]3956; CHECK: .split:3957; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]3958; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]3959; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]3960; CHECK: 8:3961; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]3962; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i643963; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP10]], i64 28)3964; CHECK-NEXT: br label [[TMP11]]3965; CHECK: 11:3966; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 13967; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]3968; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]3969; CHECK: .split.split:3970; CHECK-NEXT: br label [[TMP12]]3971; CHECK: 12:3972; CHECK-NEXT: [[TMP85:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)3973; CHECK-NEXT: [[TMP86:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_7t(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[TMP85]], i32 1)3974; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP86]]3975;3976entry:3977 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 7) @llvm.riscv.vluxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv4i1.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) poison, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1, i64 5)3978 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_7t(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %0, i32 1)3979 ret <vscale x 1 x i32> %13980}3981 3982 3983declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, <vscale x 1 x i16>, i64, i64)3984declare target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, <vscale x 1 x i16>, <vscale x 1 x i1>, i64, i64, i64)3985 3986define <vscale x 1 x i32> @test_vluxseg8_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {3987; CHECK-LABEL: @test_vluxseg8_nxv1i32_nxv1i16(3988; CHECK-NEXT: entry:3989; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 83990; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>3991; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]3992; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 03993; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]3994; CHECK: 4:3995; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()3996; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])3997; CHECK-NEXT: br label [[DOTSPLIT:%.*]]3998; CHECK: .split:3999; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]4000; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]4001; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]4002; CHECK: 8:4003; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]4004; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i644005; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP10]], i64 32)4006; CHECK-NEXT: br label [[TMP11]]4007; CHECK: 11:4008; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 14009; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]4010; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]4011; CHECK: .split.split:4012; CHECK-NEXT: br label [[TMP12]]4013; CHECK: 12:4014; CHECK-NEXT: [[TMP97:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)4015; CHECK-NEXT: [[TMP98:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_8t(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[TMP97]], i32 1)4016; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP98]]4017;4018entry:4019 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.triscv.vector.tuple_nxv4i8_8t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)4020 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_8t(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, i32 1)4021 ret <vscale x 1 x i32> %14022}4023 4024define <vscale x 1 x i32> @test_vluxseg8_mask_nxv1i32_nxv1i16(ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {4025; CHECK-LABEL: @test_vluxseg8_mask_nxv1i32_nxv1i16(4026; CHECK-NEXT: entry:4027; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 84028; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>4029; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]4030; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 04031; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]4032; CHECK: 4:4033; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()4034; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])4035; CHECK-NEXT: br label [[DOTSPLIT:%.*]]4036; CHECK: .split:4037; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]4038; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]4039; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]4040; CHECK: 8:4041; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]4042; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i644043; CHECK-NEXT: call void @__asan_loadN(i64 [[TMP10]], i64 32)4044; CHECK-NEXT: br label [[TMP11]]4045; CHECK: 11:4046; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 14047; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]4048; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]4049; CHECK: .split.split:4050; CHECK-NEXT: br label [[TMP12]]4051; CHECK: 12:4052; CHECK-NEXT: [[TMP97:%.*]] = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1, i64 5)4053; CHECK-NEXT: [[TMP98:%.*]] = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_8t(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[TMP97]], i32 1)4054; CHECK-NEXT: ret <vscale x 1 x i32> [[TMP98]]4055;4056entry:4057 %0 = tail call target("riscv.vector.tuple", <vscale x 4 x i8>, 8) @llvm.riscv.vluxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv4i1.nxv1i32(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) poison, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 1, i64 5)4058 %1 = call <vscale x 1 x i32> @llvm.riscv.tuple.extract.nxv1i32.triscv.vector.tuple_nxv4i8_8t(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %0, i32 1)4059 ret <vscale x 1 x i32> %14060}4061 4062 4063declare void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, <vscale x 4 x i8>, i64, i64)4064declare void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64)4065 4066define void @test_vsoxseg2_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {4067; CHECK-LABEL: @test_vsoxseg2_nxv1i32_nxv1i16(4068; CHECK-NEXT: entry:4069; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 84070; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>4071; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]4072; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 04073; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]4074; CHECK: 4:4075; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()4076; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])4077; CHECK-NEXT: br label [[DOTSPLIT:%.*]]4078; CHECK: .split:4079; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]4080; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]4081; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]4082; CHECK: 8:4083; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]4084; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i644085; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP10]], i64 8)4086; CHECK-NEXT: br label [[TMP11]]4087; CHECK: 11:4088; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 14089; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]4090; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]4091; CHECK: .split.split:4092; CHECK-NEXT: br label [[TMP12]]4093; CHECK: 12:4094; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)4095; CHECK-NEXT: ret void4096;4097entry:4098 tail call void @llvm.riscv.vsoxseg2.triscv.vector.tuple_nxv4i8_2t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)4099 ret void4100}4101 4102define void @test_vsoxseg2_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {4103; CHECK-LABEL: @test_vsoxseg2_mask_nxv1i32_nxv1i16(4104; CHECK-NEXT: entry:4105; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 84106; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>4107; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]4108; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 04109; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]4110; CHECK: 4:4111; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()4112; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])4113; CHECK-NEXT: br label [[DOTSPLIT:%.*]]4114; CHECK: .split:4115; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]4116; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]4117; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]4118; CHECK: 8:4119; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]4120; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i644121; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP10]], i64 8)4122; CHECK-NEXT: br label [[TMP11]]4123; CHECK: 11:4124; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 14125; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]4126; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]4127; CHECK: .split.split:4128; CHECK-NEXT: br label [[TMP12]]4129; CHECK: 12:4130; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)4131; CHECK-NEXT: ret void4132;4133entry:4134 tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)4135 ret void4136}4137 4138 4139declare void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, <vscale x 4 x i8>, i64, i64)4140declare void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64)4141 4142define void @test_vsoxseg3_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {4143; CHECK-LABEL: @test_vsoxseg3_nxv1i32_nxv1i16(4144; CHECK-NEXT: entry:4145; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 84146; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>4147; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]4148; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 04149; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]4150; CHECK: 4:4151; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()4152; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])4153; CHECK-NEXT: br label [[DOTSPLIT:%.*]]4154; CHECK: .split:4155; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]4156; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]4157; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]4158; CHECK: 8:4159; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]4160; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i644161; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP10]], i64 12)4162; CHECK-NEXT: br label [[TMP11]]4163; CHECK: 11:4164; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 14165; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]4166; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]4167; CHECK: .split.split:4168; CHECK-NEXT: br label [[TMP12]]4169; CHECK: 12:4170; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)4171; CHECK-NEXT: ret void4172;4173entry:4174 tail call void @llvm.riscv.vsoxseg3.triscv.vector.tuple_nxv4i8_3t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)4175 ret void4176}4177 4178define void @test_vsoxseg3_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {4179; CHECK-LABEL: @test_vsoxseg3_mask_nxv1i32_nxv1i16(4180; CHECK-NEXT: entry:4181; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 84182; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>4183; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]4184; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 04185; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]4186; CHECK: 4:4187; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()4188; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])4189; CHECK-NEXT: br label [[DOTSPLIT:%.*]]4190; CHECK: .split:4191; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]4192; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]4193; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]4194; CHECK: 8:4195; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]4196; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i644197; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP10]], i64 12)4198; CHECK-NEXT: br label [[TMP11]]4199; CHECK: 11:4200; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 14201; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]4202; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]4203; CHECK: .split.split:4204; CHECK-NEXT: br label [[TMP12]]4205; CHECK: 12:4206; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)4207; CHECK-NEXT: ret void4208;4209entry:4210 tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)4211 ret void4212}4213 4214 4215declare void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, <vscale x 4 x i8>, i64, i64)4216declare void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64)4217 4218define void @test_vsoxseg4_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {4219; CHECK-LABEL: @test_vsoxseg4_nxv1i32_nxv1i16(4220; CHECK-NEXT: entry:4221; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 84222; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>4223; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]4224; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 04225; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]4226; CHECK: 4:4227; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()4228; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])4229; CHECK-NEXT: br label [[DOTSPLIT:%.*]]4230; CHECK: .split:4231; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]4232; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]4233; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]4234; CHECK: 8:4235; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]4236; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i644237; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP10]], i64 16)4238; CHECK-NEXT: br label [[TMP11]]4239; CHECK: 11:4240; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 14241; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]4242; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]4243; CHECK: .split.split:4244; CHECK-NEXT: br label [[TMP12]]4245; CHECK: 12:4246; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)4247; CHECK-NEXT: ret void4248;4249entry:4250 tail call void @llvm.riscv.vsoxseg4.triscv.vector.tuple_nxv4i8_4t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)4251 ret void4252}4253 4254define void @test_vsoxseg4_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {4255; CHECK-LABEL: @test_vsoxseg4_mask_nxv1i32_nxv1i16(4256; CHECK-NEXT: entry:4257; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 84258; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>4259; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]4260; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 04261; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]4262; CHECK: 4:4263; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()4264; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])4265; CHECK-NEXT: br label [[DOTSPLIT:%.*]]4266; CHECK: .split:4267; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]4268; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]4269; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]4270; CHECK: 8:4271; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]4272; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i644273; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP10]], i64 16)4274; CHECK-NEXT: br label [[TMP11]]4275; CHECK: 11:4276; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 14277; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]4278; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]4279; CHECK: .split.split:4280; CHECK-NEXT: br label [[TMP12]]4281; CHECK: 12:4282; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)4283; CHECK-NEXT: ret void4284;4285entry:4286 tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)4287 ret void4288}4289 4290 4291declare void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, <vscale x 4 x i8>, i64, i64)4292declare void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64)4293 4294define void @test_vsoxseg5_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {4295; CHECK-LABEL: @test_vsoxseg5_nxv1i32_nxv1i16(4296; CHECK-NEXT: entry:4297; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 84298; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>4299; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]4300; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 04301; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]4302; CHECK: 4:4303; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()4304; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])4305; CHECK-NEXT: br label [[DOTSPLIT:%.*]]4306; CHECK: .split:4307; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]4308; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]4309; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]4310; CHECK: 8:4311; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]4312; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i644313; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP10]], i64 20)4314; CHECK-NEXT: br label [[TMP11]]4315; CHECK: 11:4316; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 14317; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]4318; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]4319; CHECK: .split.split:4320; CHECK-NEXT: br label [[TMP12]]4321; CHECK: 12:4322; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)4323; CHECK-NEXT: ret void4324;4325entry:4326 tail call void @llvm.riscv.vsoxseg5.triscv.vector.tuple_nxv4i8_5t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)4327 ret void4328}4329 4330define void @test_vsoxseg5_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {4331; CHECK-LABEL: @test_vsoxseg5_mask_nxv1i32_nxv1i16(4332; CHECK-NEXT: entry:4333; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 84334; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>4335; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]4336; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 04337; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]4338; CHECK: 4:4339; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()4340; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])4341; CHECK-NEXT: br label [[DOTSPLIT:%.*]]4342; CHECK: .split:4343; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]4344; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]4345; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]4346; CHECK: 8:4347; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]4348; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i644349; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP10]], i64 20)4350; CHECK-NEXT: br label [[TMP11]]4351; CHECK: 11:4352; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 14353; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]4354; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]4355; CHECK: .split.split:4356; CHECK-NEXT: br label [[TMP12]]4357; CHECK: 12:4358; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)4359; CHECK-NEXT: ret void4360;4361entry:4362 tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)4363 ret void4364}4365 4366 4367declare void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, <vscale x 4 x i8>, i64, i64)4368declare void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64)4369 4370define void @test_vsoxseg6_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {4371; CHECK-LABEL: @test_vsoxseg6_nxv1i32_nxv1i16(4372; CHECK-NEXT: entry:4373; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 84374; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>4375; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]4376; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 04377; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]4378; CHECK: 4:4379; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()4380; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])4381; CHECK-NEXT: br label [[DOTSPLIT:%.*]]4382; CHECK: .split:4383; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]4384; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]4385; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]4386; CHECK: 8:4387; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]4388; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i644389; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP10]], i64 24)4390; CHECK-NEXT: br label [[TMP11]]4391; CHECK: 11:4392; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 14393; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]4394; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]4395; CHECK: .split.split:4396; CHECK-NEXT: br label [[TMP12]]4397; CHECK: 12:4398; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)4399; CHECK-NEXT: ret void4400;4401entry:4402 tail call void @llvm.riscv.vsoxseg6.triscv.vector.tuple_nxv4i8_6t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)4403 ret void4404}4405 4406define void @test_vsoxseg6_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {4407; CHECK-LABEL: @test_vsoxseg6_mask_nxv1i32_nxv1i16(4408; CHECK-NEXT: entry:4409; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 84410; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>4411; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]4412; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 04413; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]4414; CHECK: 4:4415; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()4416; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])4417; CHECK-NEXT: br label [[DOTSPLIT:%.*]]4418; CHECK: .split:4419; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]4420; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]4421; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]4422; CHECK: 8:4423; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]4424; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i644425; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP10]], i64 24)4426; CHECK-NEXT: br label [[TMP11]]4427; CHECK: 11:4428; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 14429; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]4430; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]4431; CHECK: .split.split:4432; CHECK-NEXT: br label [[TMP12]]4433; CHECK: 12:4434; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)4435; CHECK-NEXT: ret void4436;4437entry:4438 tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)4439 ret void4440}4441 4442 4443declare void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, <vscale x 4 x i8>, i64, i64)4444declare void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64)4445 4446define void @test_vsoxseg7_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {4447; CHECK-LABEL: @test_vsoxseg7_nxv1i32_nxv1i16(4448; CHECK-NEXT: entry:4449; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 84450; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>4451; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]4452; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 04453; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]4454; CHECK: 4:4455; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()4456; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])4457; CHECK-NEXT: br label [[DOTSPLIT:%.*]]4458; CHECK: .split:4459; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]4460; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]4461; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]4462; CHECK: 8:4463; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]4464; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i644465; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP10]], i64 28)4466; CHECK-NEXT: br label [[TMP11]]4467; CHECK: 11:4468; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 14469; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]4470; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]4471; CHECK: .split.split:4472; CHECK-NEXT: br label [[TMP12]]4473; CHECK: 12:4474; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)4475; CHECK-NEXT: ret void4476;4477entry:4478 tail call void @llvm.riscv.vsoxseg7.triscv.vector.tuple_nxv4i8_7t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)4479 ret void4480}4481 4482define void @test_vsoxseg7_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {4483; CHECK-LABEL: @test_vsoxseg7_mask_nxv1i32_nxv1i16(4484; CHECK-NEXT: entry:4485; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 84486; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>4487; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]4488; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 04489; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]4490; CHECK: 4:4491; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()4492; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])4493; CHECK-NEXT: br label [[DOTSPLIT:%.*]]4494; CHECK: .split:4495; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]4496; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]4497; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]4498; CHECK: 8:4499; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]4500; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i644501; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP10]], i64 28)4502; CHECK-NEXT: br label [[TMP11]]4503; CHECK: 11:4504; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 14505; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]4506; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]4507; CHECK: .split.split:4508; CHECK-NEXT: br label [[TMP12]]4509; CHECK: 12:4510; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)4511; CHECK-NEXT: ret void4512;4513entry:4514 tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)4515 ret void4516}4517 4518 4519declare void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, <vscale x 4 x i8>, i64, i64)4520declare void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64)4521 4522define void @test_vsoxseg8_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {4523; CHECK-LABEL: @test_vsoxseg8_nxv1i32_nxv1i16(4524; CHECK-NEXT: entry:4525; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 84526; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>4527; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]4528; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 04529; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]4530; CHECK: 4:4531; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()4532; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])4533; CHECK-NEXT: br label [[DOTSPLIT:%.*]]4534; CHECK: .split:4535; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]4536; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]4537; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]4538; CHECK: 8:4539; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]4540; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i644541; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP10]], i64 32)4542; CHECK-NEXT: br label [[TMP11]]4543; CHECK: 11:4544; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 14545; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]4546; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]4547; CHECK: .split.split:4548; CHECK-NEXT: br label [[TMP12]]4549; CHECK: 12:4550; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)4551; CHECK-NEXT: ret void4552;4553entry:4554 tail call void @llvm.riscv.vsoxseg8.triscv.vector.tuple_nxv4i8_8t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)4555 ret void4556}4557 4558define void @test_vsoxseg8_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {4559; CHECK-LABEL: @test_vsoxseg8_mask_nxv1i32_nxv1i16(4560; CHECK-NEXT: entry:4561; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 84562; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>4563; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]4564; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 04565; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]4566; CHECK: 4:4567; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()4568; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])4569; CHECK-NEXT: br label [[DOTSPLIT:%.*]]4570; CHECK: .split:4571; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]4572; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]4573; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]4574; CHECK: 8:4575; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]4576; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i644577; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP10]], i64 32)4578; CHECK-NEXT: br label [[TMP11]]4579; CHECK: 11:4580; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 14581; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]4582; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]4583; CHECK: .split.split:4584; CHECK-NEXT: br label [[TMP12]]4585; CHECK: 12:4586; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)4587; CHECK-NEXT: ret void4588;4589entry:4590 tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)4591 ret void4592}4593 4594 4595declare void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, <vscale x 4 x i8>, i64, i64)4596declare void @llvm.riscv.vsuxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2), ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64)4597 4598define void @test_vsuxseg2_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {4599; CHECK-LABEL: @test_vsuxseg2_nxv1i32_nxv1i16(4600; CHECK-NEXT: entry:4601; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 84602; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>4603; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]4604; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 04605; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]4606; CHECK: 4:4607; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()4608; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])4609; CHECK-NEXT: br label [[DOTSPLIT:%.*]]4610; CHECK: .split:4611; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]4612; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]4613; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]4614; CHECK: 8:4615; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]4616; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i644617; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP10]], i64 8)4618; CHECK-NEXT: br label [[TMP11]]4619; CHECK: 11:4620; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 14621; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]4622; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]4623; CHECK: .split.split:4624; CHECK-NEXT: br label [[TMP12]]4625; CHECK: 12:4626; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)4627; CHECK-NEXT: ret void4628;4629entry:4630 tail call void @llvm.riscv.vsuxseg2.triscv.vector.tuple_nxv4i8_2t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)4631 ret void4632}4633 4634define void @test_vsuxseg2_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {4635; CHECK-LABEL: @test_vsuxseg2_mask_nxv1i32_nxv1i16(4636; CHECK-NEXT: entry:4637; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 84638; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>4639; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]4640; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 04641; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]4642; CHECK: 4:4643; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()4644; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])4645; CHECK-NEXT: br label [[DOTSPLIT:%.*]]4646; CHECK: .split:4647; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]4648; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]4649; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]4650; CHECK: 8:4651; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]4652; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i644653; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP10]], i64 8)4654; CHECK-NEXT: br label [[TMP11]]4655; CHECK: 11:4656; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 14657; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]4658; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]4659; CHECK: .split.split:4660; CHECK-NEXT: br label [[TMP12]]4661; CHECK: 12:4662; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)4663; CHECK-NEXT: ret void4664;4665entry:4666 tail call void @llvm.riscv.vsoxseg2.mask.triscv.vector.tuple_nxv4i8_2t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 2) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)4667 ret void4668}4669 4670 4671declare void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, <vscale x 4 x i8>, i64, i64)4672declare void @llvm.riscv.vsuxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3), ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64)4673 4674define void @test_vsuxseg3_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {4675; CHECK-LABEL: @test_vsuxseg3_nxv1i32_nxv1i16(4676; CHECK-NEXT: entry:4677; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 84678; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>4679; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]4680; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 04681; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]4682; CHECK: 4:4683; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()4684; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])4685; CHECK-NEXT: br label [[DOTSPLIT:%.*]]4686; CHECK: .split:4687; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]4688; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]4689; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]4690; CHECK: 8:4691; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]4692; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i644693; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP10]], i64 12)4694; CHECK-NEXT: br label [[TMP11]]4695; CHECK: 11:4696; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 14697; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]4698; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]4699; CHECK: .split.split:4700; CHECK-NEXT: br label [[TMP12]]4701; CHECK: 12:4702; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)4703; CHECK-NEXT: ret void4704;4705entry:4706 tail call void @llvm.riscv.vsuxseg3.triscv.vector.tuple_nxv4i8_3t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)4707 ret void4708}4709 4710define void @test_vsuxseg3_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {4711; CHECK-LABEL: @test_vsuxseg3_mask_nxv1i32_nxv1i16(4712; CHECK-NEXT: entry:4713; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 84714; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>4715; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]4716; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 04717; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]4718; CHECK: 4:4719; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()4720; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])4721; CHECK-NEXT: br label [[DOTSPLIT:%.*]]4722; CHECK: .split:4723; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]4724; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]4725; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]4726; CHECK: 8:4727; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]4728; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i644729; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP10]], i64 12)4730; CHECK-NEXT: br label [[TMP11]]4731; CHECK: 11:4732; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 14733; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]4734; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]4735; CHECK: .split.split:4736; CHECK-NEXT: br label [[TMP12]]4737; CHECK: 12:4738; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)4739; CHECK-NEXT: ret void4740;4741entry:4742 tail call void @llvm.riscv.vsoxseg3.mask.triscv.vector.tuple_nxv4i8_3t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 3) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)4743 ret void4744}4745 4746 4747declare void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, <vscale x 4 x i8>, i64, i64)4748declare void @llvm.riscv.vsuxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4), ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64)4749 4750define void @test_vsuxseg4_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {4751; CHECK-LABEL: @test_vsuxseg4_nxv1i32_nxv1i16(4752; CHECK-NEXT: entry:4753; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 84754; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>4755; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]4756; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 04757; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]4758; CHECK: 4:4759; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()4760; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])4761; CHECK-NEXT: br label [[DOTSPLIT:%.*]]4762; CHECK: .split:4763; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]4764; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]4765; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]4766; CHECK: 8:4767; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]4768; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i644769; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP10]], i64 16)4770; CHECK-NEXT: br label [[TMP11]]4771; CHECK: 11:4772; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 14773; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]4774; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]4775; CHECK: .split.split:4776; CHECK-NEXT: br label [[TMP12]]4777; CHECK: 12:4778; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)4779; CHECK-NEXT: ret void4780;4781entry:4782 tail call void @llvm.riscv.vsuxseg4.triscv.vector.tuple_nxv4i8_4t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)4783 ret void4784}4785 4786define void @test_vsuxseg4_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {4787; CHECK-LABEL: @test_vsuxseg4_mask_nxv1i32_nxv1i16(4788; CHECK-NEXT: entry:4789; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 84790; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>4791; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]4792; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 04793; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]4794; CHECK: 4:4795; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()4796; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])4797; CHECK-NEXT: br label [[DOTSPLIT:%.*]]4798; CHECK: .split:4799; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]4800; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]4801; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]4802; CHECK: 8:4803; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]4804; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i644805; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP10]], i64 16)4806; CHECK-NEXT: br label [[TMP11]]4807; CHECK: 11:4808; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 14809; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]4810; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]4811; CHECK: .split.split:4812; CHECK-NEXT: br label [[TMP12]]4813; CHECK: 12:4814; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)4815; CHECK-NEXT: ret void4816;4817entry:4818 tail call void @llvm.riscv.vsoxseg4.mask.triscv.vector.tuple_nxv4i8_4t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 4) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)4819 ret void4820}4821 4822 4823declare void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, <vscale x 4 x i8>, i64, i64)4824declare void @llvm.riscv.vsuxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5), ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64)4825 4826define void @test_vsuxseg5_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {4827; CHECK-LABEL: @test_vsuxseg5_nxv1i32_nxv1i16(4828; CHECK-NEXT: entry:4829; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 84830; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>4831; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]4832; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 04833; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]4834; CHECK: 4:4835; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()4836; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])4837; CHECK-NEXT: br label [[DOTSPLIT:%.*]]4838; CHECK: .split:4839; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]4840; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]4841; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]4842; CHECK: 8:4843; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]4844; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i644845; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP10]], i64 20)4846; CHECK-NEXT: br label [[TMP11]]4847; CHECK: 11:4848; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 14849; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]4850; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]4851; CHECK: .split.split:4852; CHECK-NEXT: br label [[TMP12]]4853; CHECK: 12:4854; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)4855; CHECK-NEXT: ret void4856;4857entry:4858 tail call void @llvm.riscv.vsuxseg5.triscv.vector.tuple_nxv4i8_5t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)4859 ret void4860}4861 4862define void @test_vsuxseg5_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {4863; CHECK-LABEL: @test_vsuxseg5_mask_nxv1i32_nxv1i16(4864; CHECK-NEXT: entry:4865; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 84866; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>4867; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]4868; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 04869; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]4870; CHECK: 4:4871; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()4872; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])4873; CHECK-NEXT: br label [[DOTSPLIT:%.*]]4874; CHECK: .split:4875; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]4876; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]4877; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]4878; CHECK: 8:4879; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]4880; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i644881; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP10]], i64 20)4882; CHECK-NEXT: br label [[TMP11]]4883; CHECK: 11:4884; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 14885; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]4886; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]4887; CHECK: .split.split:4888; CHECK-NEXT: br label [[TMP12]]4889; CHECK: 12:4890; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)4891; CHECK-NEXT: ret void4892;4893entry:4894 tail call void @llvm.riscv.vsoxseg5.mask.triscv.vector.tuple_nxv4i8_5t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 5) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)4895 ret void4896}4897 4898 4899declare void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, <vscale x 4 x i8>, i64, i64)4900declare void @llvm.riscv.vsuxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6), ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64)4901 4902define void @test_vsuxseg6_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {4903; CHECK-LABEL: @test_vsuxseg6_nxv1i32_nxv1i16(4904; CHECK-NEXT: entry:4905; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 84906; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>4907; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]4908; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 04909; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]4910; CHECK: 4:4911; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()4912; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])4913; CHECK-NEXT: br label [[DOTSPLIT:%.*]]4914; CHECK: .split:4915; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]4916; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]4917; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]4918; CHECK: 8:4919; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]4920; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i644921; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP10]], i64 24)4922; CHECK-NEXT: br label [[TMP11]]4923; CHECK: 11:4924; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 14925; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]4926; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]4927; CHECK: .split.split:4928; CHECK-NEXT: br label [[TMP12]]4929; CHECK: 12:4930; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)4931; CHECK-NEXT: ret void4932;4933entry:4934 tail call void @llvm.riscv.vsuxseg6.triscv.vector.tuple_nxv4i8_6t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)4935 ret void4936}4937 4938define void @test_vsuxseg6_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {4939; CHECK-LABEL: @test_vsuxseg6_mask_nxv1i32_nxv1i16(4940; CHECK-NEXT: entry:4941; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 84942; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>4943; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]4944; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 04945; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]4946; CHECK: 4:4947; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()4948; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])4949; CHECK-NEXT: br label [[DOTSPLIT:%.*]]4950; CHECK: .split:4951; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]4952; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]4953; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]4954; CHECK: 8:4955; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]4956; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i644957; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP10]], i64 24)4958; CHECK-NEXT: br label [[TMP11]]4959; CHECK: 11:4960; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 14961; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]4962; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]4963; CHECK: .split.split:4964; CHECK-NEXT: br label [[TMP12]]4965; CHECK: 12:4966; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)4967; CHECK-NEXT: ret void4968;4969entry:4970 tail call void @llvm.riscv.vsoxseg6.mask.triscv.vector.tuple_nxv4i8_6t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 6) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)4971 ret void4972}4973 4974 4975declare void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, <vscale x 4 x i8>, i64, i64)4976declare void @llvm.riscv.vsuxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7), ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64)4977 4978define void @test_vsuxseg7_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {4979; CHECK-LABEL: @test_vsuxseg7_nxv1i32_nxv1i16(4980; CHECK-NEXT: entry:4981; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 84982; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>4983; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]4984; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 04985; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]4986; CHECK: 4:4987; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()4988; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])4989; CHECK-NEXT: br label [[DOTSPLIT:%.*]]4990; CHECK: .split:4991; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]4992; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]4993; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]4994; CHECK: 8:4995; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]4996; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i644997; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP10]], i64 28)4998; CHECK-NEXT: br label [[TMP11]]4999; CHECK: 11:5000; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 15001; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]5002; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]5003; CHECK: .split.split:5004; CHECK-NEXT: br label [[TMP12]]5005; CHECK: 12:5006; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)5007; CHECK-NEXT: ret void5008;5009entry:5010 tail call void @llvm.riscv.vsuxseg7.triscv.vector.tuple_nxv4i8_7t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)5011 ret void5012}5013 5014define void @test_vsuxseg7_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {5015; CHECK-LABEL: @test_vsuxseg7_mask_nxv1i32_nxv1i16(5016; CHECK-NEXT: entry:5017; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 85018; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>5019; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]5020; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 05021; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]5022; CHECK: 4:5023; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()5024; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])5025; CHECK-NEXT: br label [[DOTSPLIT:%.*]]5026; CHECK: .split:5027; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]5028; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]5029; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]5030; CHECK: 8:5031; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]5032; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i645033; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP10]], i64 28)5034; CHECK-NEXT: br label [[TMP11]]5035; CHECK: 11:5036; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 15037; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]5038; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]5039; CHECK: .split.split:5040; CHECK-NEXT: br label [[TMP12]]5041; CHECK: 12:5042; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)5043; CHECK-NEXT: ret void5044;5045entry:5046 tail call void @llvm.riscv.vsoxseg7.mask.triscv.vector.tuple_nxv4i8_7t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 7) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)5047 ret void5048}5049 5050 5051declare void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.nxv4i8(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, <vscale x 4 x i8>, i64, i64)5052declare void @llvm.riscv.vsuxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv4i8.nxv4i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8), ptr, <vscale x 4 x i8>, <vscale x 4 x i1>, i64, i64)5053 5054define void @test_vsuxseg8_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl) sanitize_address {5055; CHECK-LABEL: @test_vsuxseg8_nxv1i32_nxv1i16(5056; CHECK-NEXT: entry:5057; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 85058; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>5059; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]5060; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 05061; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]5062; CHECK: 4:5063; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()5064; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])5065; CHECK-NEXT: br label [[DOTSPLIT:%.*]]5066; CHECK: .split:5067; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]5068; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> splat (i1 true), i64 [[IV]]5069; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]5070; CHECK: 8:5071; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]5072; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i645073; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP10]], i64 32)5074; CHECK-NEXT: br label [[TMP11]]5075; CHECK: 11:5076; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 15077; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]5078; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]5079; CHECK: .split.split:5080; CHECK-NEXT: br label [[TMP12]]5081; CHECK: 12:5082; CHECK-NEXT: tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], i64 [[VL]], i64 5)5083; CHECK-NEXT: ret void5084;5085entry:5086 tail call void @llvm.riscv.vsuxseg8.triscv.vector.tuple_nxv4i8_8t.nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, i64 5)5087 ret void5088}5089 5090define void @test_vsuxseg8_mask_nxv1i32_nxv1i16(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, i64 %vl, <vscale x 1 x i1> %mask) sanitize_address {5091; CHECK-LABEL: @test_vsuxseg8_mask_nxv1i32_nxv1i16(5092; CHECK-NEXT: entry:5093; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__asan_shadow_memory_dynamic_address, align 85094; CHECK-NEXT: [[TMP1:%.*]] = zext <vscale x 1 x i16> [[INDEX:%.*]] to <vscale x 1 x i64>5095; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[BASE:%.*]], <vscale x 1 x i64> [[TMP1]]5096; CHECK-NEXT: [[TMP3:%.*]] = icmp ne i64 [[VL:%.*]], 05097; CHECK-NEXT: br i1 [[TMP3]], label [[TMP4:%.*]], label [[TMP12:%.*]]5098; CHECK: 4:5099; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()5100; CHECK-NEXT: [[TMP6:%.*]] = call i64 @llvm.umin.i64(i64 [[VL]], i64 [[TMP5]])5101; CHECK-NEXT: br label [[DOTSPLIT:%.*]]5102; CHECK: .split:5103; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[TMP4]] ], [ [[IV_NEXT:%.*]], [[TMP11:%.*]] ]5104; CHECK-NEXT: [[TMP7:%.*]] = extractelement <vscale x 1 x i1> [[MASK:%.*]], i64 [[IV]]5105; CHECK-NEXT: br i1 [[TMP7]], label [[TMP8:%.*]], label [[TMP11]]5106; CHECK: 8:5107; CHECK-NEXT: [[TMP9:%.*]] = extractelement <vscale x 1 x ptr> [[TMP2]], i64 [[IV]]5108; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[TMP9]] to i645109; CHECK-NEXT: call void @__asan_storeN(i64 [[TMP10]], i64 32)5110; CHECK-NEXT: br label [[TMP11]]5111; CHECK: 11:5112; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 15113; CHECK-NEXT: [[IV_CHECK:%.*]] = icmp eq i64 [[IV_NEXT]], [[TMP6]]5114; CHECK-NEXT: br i1 [[IV_CHECK]], label [[DOTSPLIT_SPLIT:%.*]], label [[DOTSPLIT]]5115; CHECK: .split.split:5116; CHECK-NEXT: br label [[TMP12]]5117; CHECK: 12:5118; CHECK-NEXT: tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.p0.nxv1i16.nxv1i1.i64(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) [[VAL:%.*]], ptr [[BASE]], <vscale x 1 x i16> [[INDEX]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 5)5119; CHECK-NEXT: ret void5120;5121entry:5122 tail call void @llvm.riscv.vsoxseg8.mask.triscv.vector.tuple_nxv4i8_8t.nxv1i16.nxv1i1(target("riscv.vector.tuple", <vscale x 4 x i8>, 8) %val, ptr %base, <vscale x 1 x i16> %index, <vscale x 1 x i1> %mask, i64 %vl, i64 5)5123 ret void5124}5125 5126