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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt < %s -passes=asan -asan-instrumentation-with-call-threshold=100 -S | FileCheck %s3; RUN: opt < %s -passes=asan -asan-instrumentation-with-call-threshold=0 -S | FileCheck %s -check-prefix=CALLS4 5target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"6 7define void @load.v1i32(ptr %p) sanitize_address {8; CHECK-LABEL: @load.v1i32(9; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i6410; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 311; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP2]], 1759218604441612; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr13; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 114; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i8 [[TMP5]], 015; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP13:%.*]], !prof [[PROF1:![0-9]+]]16; CHECK: 7:17; CHECK-NEXT: [[TMP8:%.*]] = and i64 [[TMP1]], 718; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[TMP8]], 319; CHECK-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i820; CHECK-NEXT: [[TMP11:%.*]] = icmp sge i8 [[TMP10]], [[TMP5]]21; CHECK-NEXT: br i1 [[TMP11]], label [[TMP12:%.*]], label [[TMP13]]22; CHECK: 12:23; CHECK-NEXT: call void @__asan_report_load4(i64 [[TMP1]]) #[[ATTR4:[0-9]+]]24; CHECK-NEXT: unreachable25; CHECK: 13:26; CHECK-NEXT: [[TMP14:%.*]] = load <1 x i32>, ptr [[P]], align 427; CHECK-NEXT: ret void28;29; CALLS-LABEL: @load.v1i32(30; CALLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i6431; CALLS-NEXT: call void @__asan_load4(i64 [[TMP1]])32; CALLS-NEXT: [[TMP2:%.*]] = load <1 x i32>, ptr [[P]], align 433; CALLS-NEXT: ret void34;35 load <1 x i32>, ptr %p36 ret void37}38 39define void @load.v2i32(ptr %p) sanitize_address {40; CHECK-LABEL: @load.v2i32(41; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i6442; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 343; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP2]], 1759218604441644; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr45; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 146; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i8 [[TMP5]], 047; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP8:%.*]]48; CHECK: 7:49; CHECK-NEXT: call void @__asan_report_load8(i64 [[TMP1]]) #[[ATTR4]]50; CHECK-NEXT: unreachable51; CHECK: 8:52; CHECK-NEXT: [[TMP9:%.*]] = load <2 x i32>, ptr [[P]], align 853; CHECK-NEXT: ret void54;55; CALLS-LABEL: @load.v2i32(56; CALLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i6457; CALLS-NEXT: call void @__asan_load8(i64 [[TMP1]])58; CALLS-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr [[P]], align 859; CALLS-NEXT: ret void60;61 load <2 x i32>, ptr %p62 ret void63}64 65define void @load.v4i32(ptr %p) sanitize_address {66; CHECK-LABEL: @load.v4i32(67; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i6468; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 369; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP2]], 1759218604441670; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr71; CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 272; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i16 [[TMP5]], 073; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP8:%.*]]74; CHECK: 7:75; CHECK-NEXT: call void @__asan_report_load16(i64 [[TMP1]]) #[[ATTR4]]76; CHECK-NEXT: unreachable77; CHECK: 8:78; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i32>, ptr [[P]], align 1679; CHECK-NEXT: ret void80;81; CALLS-LABEL: @load.v4i32(82; CALLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i6483; CALLS-NEXT: call void @__asan_load16(i64 [[TMP1]])84; CALLS-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr [[P]], align 1685; CALLS-NEXT: ret void86;87 load <4 x i32>, ptr %p88 ret void89}90 91define void @load.v8i32(ptr %p) sanitize_address {92; CHECK-LABEL: @load.v8i32(93; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i6494; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 3195; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr96; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P]] to i6497; CHECK-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP4]], 398; CHECK-NEXT: [[TMP6:%.*]] = or i64 [[TMP5]], 1759218604441699; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr100; CHECK-NEXT: [[TMP8:%.*]] = load i8, ptr [[TMP7]], align 1101; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i8 [[TMP8]], 0102; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP15:%.*]], !prof [[PROF1]]103; CHECK: 10:104; CHECK-NEXT: [[TMP11:%.*]] = and i64 [[TMP4]], 7105; CHECK-NEXT: [[TMP12:%.*]] = trunc i64 [[TMP11]] to i8106; CHECK-NEXT: [[TMP13:%.*]] = icmp sge i8 [[TMP12]], [[TMP8]]107; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP15]]108; CHECK: 14:109; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP4]], i64 32) #[[ATTR4]]110; CHECK-NEXT: unreachable111; CHECK: 15:112; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[TMP3]] to i64113; CHECK-NEXT: [[TMP17:%.*]] = lshr i64 [[TMP16]], 3114; CHECK-NEXT: [[TMP18:%.*]] = or i64 [[TMP17]], 17592186044416115; CHECK-NEXT: [[TMP19:%.*]] = inttoptr i64 [[TMP18]] to ptr116; CHECK-NEXT: [[TMP20:%.*]] = load i8, ptr [[TMP19]], align 1117; CHECK-NEXT: [[TMP21:%.*]] = icmp ne i8 [[TMP20]], 0118; CHECK-NEXT: br i1 [[TMP21]], label [[TMP22:%.*]], label [[TMP27:%.*]], !prof [[PROF1]]119; CHECK: 22:120; CHECK-NEXT: [[TMP23:%.*]] = and i64 [[TMP16]], 7121; CHECK-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP23]] to i8122; CHECK-NEXT: [[TMP25:%.*]] = icmp sge i8 [[TMP24]], [[TMP20]]123; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP27]]124; CHECK: 26:125; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP16]], i64 32) #[[ATTR4]]126; CHECK-NEXT: unreachable127; CHECK: 27:128; CHECK-NEXT: [[TMP28:%.*]] = load <8 x i32>, ptr [[P]], align 32129; CHECK-NEXT: ret void130;131; CALLS-LABEL: @load.v8i32(132; CALLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64133; CALLS-NEXT: call void @__asan_loadN(i64 [[TMP1]], i64 32)134; CALLS-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr [[P]], align 32135; CALLS-NEXT: ret void136;137 load <8 x i32>, ptr %p138 ret void139}140 141define void @load.v16i32(ptr %p) sanitize_address {142; CHECK-LABEL: @load.v16i32(143; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64144; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 63145; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr146; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P]] to i64147; CHECK-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP4]], 3148; CHECK-NEXT: [[TMP6:%.*]] = or i64 [[TMP5]], 17592186044416149; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr150; CHECK-NEXT: [[TMP8:%.*]] = load i8, ptr [[TMP7]], align 1151; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i8 [[TMP8]], 0152; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP15:%.*]], !prof [[PROF1]]153; CHECK: 10:154; CHECK-NEXT: [[TMP11:%.*]] = and i64 [[TMP4]], 7155; CHECK-NEXT: [[TMP12:%.*]] = trunc i64 [[TMP11]] to i8156; CHECK-NEXT: [[TMP13:%.*]] = icmp sge i8 [[TMP12]], [[TMP8]]157; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP15]]158; CHECK: 14:159; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP4]], i64 64) #[[ATTR4]]160; CHECK-NEXT: unreachable161; CHECK: 15:162; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[TMP3]] to i64163; CHECK-NEXT: [[TMP17:%.*]] = lshr i64 [[TMP16]], 3164; CHECK-NEXT: [[TMP18:%.*]] = or i64 [[TMP17]], 17592186044416165; CHECK-NEXT: [[TMP19:%.*]] = inttoptr i64 [[TMP18]] to ptr166; CHECK-NEXT: [[TMP20:%.*]] = load i8, ptr [[TMP19]], align 1167; CHECK-NEXT: [[TMP21:%.*]] = icmp ne i8 [[TMP20]], 0168; CHECK-NEXT: br i1 [[TMP21]], label [[TMP22:%.*]], label [[TMP27:%.*]], !prof [[PROF1]]169; CHECK: 22:170; CHECK-NEXT: [[TMP23:%.*]] = and i64 [[TMP16]], 7171; CHECK-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP23]] to i8172; CHECK-NEXT: [[TMP25:%.*]] = icmp sge i8 [[TMP24]], [[TMP20]]173; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP27]]174; CHECK: 26:175; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP16]], i64 64) #[[ATTR4]]176; CHECK-NEXT: unreachable177; CHECK: 27:178; CHECK-NEXT: [[TMP28:%.*]] = load <16 x i32>, ptr [[P]], align 64179; CHECK-NEXT: ret void180;181; CALLS-LABEL: @load.v16i32(182; CALLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64183; CALLS-NEXT: call void @__asan_loadN(i64 [[TMP1]], i64 64)184; CALLS-NEXT: [[TMP2:%.*]] = load <16 x i32>, ptr [[P]], align 64185; CALLS-NEXT: ret void186;187 load <16 x i32>, ptr %p188 ret void189}190 191 192define void @store.v1i32(ptr %p) sanitize_address {193; CHECK-LABEL: @store.v1i32(194; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64195; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3196; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP2]], 17592186044416197; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr198; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1199; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i8 [[TMP5]], 0200; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]201; CHECK: 7:202; CHECK-NEXT: [[TMP8:%.*]] = and i64 [[TMP1]], 7203; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[TMP8]], 3204; CHECK-NEXT: [[TMP10:%.*]] = trunc i64 [[TMP9]] to i8205; CHECK-NEXT: [[TMP11:%.*]] = icmp sge i8 [[TMP10]], [[TMP5]]206; CHECK-NEXT: br i1 [[TMP11]], label [[TMP12:%.*]], label [[TMP13]]207; CHECK: 12:208; CHECK-NEXT: call void @__asan_report_store4(i64 [[TMP1]]) #[[ATTR4]]209; CHECK-NEXT: unreachable210; CHECK: 13:211; CHECK-NEXT: store <1 x i32> zeroinitializer, ptr [[P]], align 4212; CHECK-NEXT: ret void213;214; CALLS-LABEL: @store.v1i32(215; CALLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64216; CALLS-NEXT: call void @__asan_store4(i64 [[TMP1]])217; CALLS-NEXT: store <1 x i32> zeroinitializer, ptr [[P]], align 4218; CALLS-NEXT: ret void219;220 store <1 x i32> zeroinitializer, ptr %p221 ret void222}223 224define void @store.v2i32(ptr %p) sanitize_address {225; CHECK-LABEL: @store.v2i32(226; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64227; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3228; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP2]], 17592186044416229; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr230; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1231; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i8 [[TMP5]], 0232; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP8:%.*]]233; CHECK: 7:234; CHECK-NEXT: call void @__asan_report_store8(i64 [[TMP1]]) #[[ATTR4]]235; CHECK-NEXT: unreachable236; CHECK: 8:237; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr [[P]], align 8238; CHECK-NEXT: ret void239;240; CALLS-LABEL: @store.v2i32(241; CALLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64242; CALLS-NEXT: call void @__asan_store8(i64 [[TMP1]])243; CALLS-NEXT: store <2 x i32> zeroinitializer, ptr [[P]], align 8244; CALLS-NEXT: ret void245;246 store <2 x i32> zeroinitializer, ptr %p247 ret void248}249 250define void @store.v4i32(ptr %p) sanitize_address {251; CHECK-LABEL: @store.v4i32(252; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64253; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3254; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP2]], 17592186044416255; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr256; CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[TMP4]], align 2257; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i16 [[TMP5]], 0258; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP8:%.*]]259; CHECK: 7:260; CHECK-NEXT: call void @__asan_report_store16(i64 [[TMP1]]) #[[ATTR4]]261; CHECK-NEXT: unreachable262; CHECK: 8:263; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr [[P]], align 16264; CHECK-NEXT: ret void265;266; CALLS-LABEL: @store.v4i32(267; CALLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64268; CALLS-NEXT: call void @__asan_store16(i64 [[TMP1]])269; CALLS-NEXT: store <4 x i32> zeroinitializer, ptr [[P]], align 16270; CALLS-NEXT: ret void271;272 store <4 x i32> zeroinitializer, ptr %p273 ret void274}275 276define void @store.v8i32(ptr %p) sanitize_address {277; CHECK-LABEL: @store.v8i32(278; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64279; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 31280; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr281; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P]] to i64282; CHECK-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP4]], 3283; CHECK-NEXT: [[TMP6:%.*]] = or i64 [[TMP5]], 17592186044416284; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr285; CHECK-NEXT: [[TMP8:%.*]] = load i8, ptr [[TMP7]], align 1286; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i8 [[TMP8]], 0287; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP15:%.*]], !prof [[PROF1]]288; CHECK: 10:289; CHECK-NEXT: [[TMP11:%.*]] = and i64 [[TMP4]], 7290; CHECK-NEXT: [[TMP12:%.*]] = trunc i64 [[TMP11]] to i8291; CHECK-NEXT: [[TMP13:%.*]] = icmp sge i8 [[TMP12]], [[TMP8]]292; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP15]]293; CHECK: 14:294; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP4]], i64 32) #[[ATTR4]]295; CHECK-NEXT: unreachable296; CHECK: 15:297; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[TMP3]] to i64298; CHECK-NEXT: [[TMP17:%.*]] = lshr i64 [[TMP16]], 3299; CHECK-NEXT: [[TMP18:%.*]] = or i64 [[TMP17]], 17592186044416300; CHECK-NEXT: [[TMP19:%.*]] = inttoptr i64 [[TMP18]] to ptr301; CHECK-NEXT: [[TMP20:%.*]] = load i8, ptr [[TMP19]], align 1302; CHECK-NEXT: [[TMP21:%.*]] = icmp ne i8 [[TMP20]], 0303; CHECK-NEXT: br i1 [[TMP21]], label [[TMP22:%.*]], label [[TMP27:%.*]], !prof [[PROF1]]304; CHECK: 22:305; CHECK-NEXT: [[TMP23:%.*]] = and i64 [[TMP16]], 7306; CHECK-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP23]] to i8307; CHECK-NEXT: [[TMP25:%.*]] = icmp sge i8 [[TMP24]], [[TMP20]]308; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP27]]309; CHECK: 26:310; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP16]], i64 32) #[[ATTR4]]311; CHECK-NEXT: unreachable312; CHECK: 27:313; CHECK-NEXT: store <8 x i32> zeroinitializer, ptr [[P]], align 32314; CHECK-NEXT: ret void315;316; CALLS-LABEL: @store.v8i32(317; CALLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64318; CALLS-NEXT: call void @__asan_storeN(i64 [[TMP1]], i64 32)319; CALLS-NEXT: store <8 x i32> zeroinitializer, ptr [[P]], align 32320; CALLS-NEXT: ret void321;322 store <8 x i32> zeroinitializer, ptr %p323 ret void324}325 326define void @store.v16i32(ptr %p) sanitize_address {327; CHECK-LABEL: @store.v16i32(328; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64329; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 63330; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr331; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P]] to i64332; CHECK-NEXT: [[TMP5:%.*]] = lshr i64 [[TMP4]], 3333; CHECK-NEXT: [[TMP6:%.*]] = or i64 [[TMP5]], 17592186044416334; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr335; CHECK-NEXT: [[TMP8:%.*]] = load i8, ptr [[TMP7]], align 1336; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i8 [[TMP8]], 0337; CHECK-NEXT: br i1 [[TMP9]], label [[TMP10:%.*]], label [[TMP15:%.*]], !prof [[PROF1]]338; CHECK: 10:339; CHECK-NEXT: [[TMP11:%.*]] = and i64 [[TMP4]], 7340; CHECK-NEXT: [[TMP12:%.*]] = trunc i64 [[TMP11]] to i8341; CHECK-NEXT: [[TMP13:%.*]] = icmp sge i8 [[TMP12]], [[TMP8]]342; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP15]]343; CHECK: 14:344; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP4]], i64 64) #[[ATTR4]]345; CHECK-NEXT: unreachable346; CHECK: 15:347; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[TMP3]] to i64348; CHECK-NEXT: [[TMP17:%.*]] = lshr i64 [[TMP16]], 3349; CHECK-NEXT: [[TMP18:%.*]] = or i64 [[TMP17]], 17592186044416350; CHECK-NEXT: [[TMP19:%.*]] = inttoptr i64 [[TMP18]] to ptr351; CHECK-NEXT: [[TMP20:%.*]] = load i8, ptr [[TMP19]], align 1352; CHECK-NEXT: [[TMP21:%.*]] = icmp ne i8 [[TMP20]], 0353; CHECK-NEXT: br i1 [[TMP21]], label [[TMP22:%.*]], label [[TMP27:%.*]], !prof [[PROF1]]354; CHECK: 22:355; CHECK-NEXT: [[TMP23:%.*]] = and i64 [[TMP16]], 7356; CHECK-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP23]] to i8357; CHECK-NEXT: [[TMP25:%.*]] = icmp sge i8 [[TMP24]], [[TMP20]]358; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP27]]359; CHECK: 26:360; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP16]], i64 64) #[[ATTR4]]361; CHECK-NEXT: unreachable362; CHECK: 27:363; CHECK-NEXT: store <16 x i32> zeroinitializer, ptr [[P]], align 64364; CHECK-NEXT: ret void365;366; CALLS-LABEL: @store.v16i32(367; CALLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64368; CALLS-NEXT: call void @__asan_storeN(i64 [[TMP1]], i64 64)369; CALLS-NEXT: store <16 x i32> zeroinitializer, ptr [[P]], align 64370; CALLS-NEXT: ret void371;372 store <16 x i32> zeroinitializer, ptr %p373 ret void374}375 376define void @store.v2i32.align8(ptr %p) sanitize_address {377; CHECK-LABEL: @store.v2i32.align8(378; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64379; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 3380; CHECK-NEXT: [[TMP3:%.*]] = or i64 [[TMP2]], 17592186044416381; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr382; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr [[TMP4]], align 1383; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i8 [[TMP5]], 0384; CHECK-NEXT: br i1 [[TMP6]], label [[TMP7:%.*]], label [[TMP8:%.*]]385; CHECK: 7:386; CHECK-NEXT: call void @__asan_report_store8(i64 [[TMP1]]) #[[ATTR4]]387; CHECK-NEXT: unreachable388; CHECK: 8:389; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr [[P]], align 8390; CHECK-NEXT: ret void391;392; CALLS-LABEL: @store.v2i32.align8(393; CALLS-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P:%.*]] to i64394; CALLS-NEXT: call void @__asan_store8(i64 [[TMP1]])395; CALLS-NEXT: store <2 x i32> zeroinitializer, ptr [[P]], align 8396; CALLS-NEXT: ret void397;398 store <2 x i32> zeroinitializer, ptr %p, align 8399 ret void400}401 402define void @load.nxv1i32(ptr %p) sanitize_address {403; CHECK-LABEL: @load.nxv1i32(404; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()405; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 32406; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3407; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64408; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[TMP3]], 1409; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], [[TMP5]]410; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr411; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[P]] to i64412; CHECK-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP8]], 3413; CHECK-NEXT: [[TMP10:%.*]] = or i64 [[TMP9]], 17592186044416414; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr415; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr [[TMP11]], align 1416; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0417; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP19:%.*]], !prof [[PROF1]]418; CHECK: 14:419; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[TMP8]], 7420; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i8421; CHECK-NEXT: [[TMP17:%.*]] = icmp sge i8 [[TMP16]], [[TMP12]]422; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP19]]423; CHECK: 18:424; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP8]], i64 [[TMP3]]) #[[ATTR4]]425; CHECK-NEXT: unreachable426; CHECK: 19:427; CHECK-NEXT: [[TMP20:%.*]] = ptrtoint ptr [[TMP7]] to i64428; CHECK-NEXT: [[TMP21:%.*]] = lshr i64 [[TMP20]], 3429; CHECK-NEXT: [[TMP22:%.*]] = or i64 [[TMP21]], 17592186044416430; CHECK-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP22]] to ptr431; CHECK-NEXT: [[TMP24:%.*]] = load i8, ptr [[TMP23]], align 1432; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i8 [[TMP24]], 0433; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP31:%.*]], !prof [[PROF1]]434; CHECK: 26:435; CHECK-NEXT: [[TMP27:%.*]] = and i64 [[TMP20]], 7436; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i8437; CHECK-NEXT: [[TMP29:%.*]] = icmp sge i8 [[TMP28]], [[TMP24]]438; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP31]]439; CHECK: 30:440; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP20]], i64 [[TMP3]]) #[[ATTR4]]441; CHECK-NEXT: unreachable442; CHECK: 31:443; CHECK-NEXT: [[TMP32:%.*]] = load <vscale x 1 x i32>, ptr [[P]], align 4444; CHECK-NEXT: ret void445;446; CALLS-LABEL: @load.nxv1i32(447; CALLS-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()448; CALLS-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 32449; CALLS-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3450; CALLS-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64451; CALLS-NEXT: call void @__asan_loadN(i64 [[TMP4]], i64 [[TMP3]])452; CALLS-NEXT: [[TMP5:%.*]] = load <vscale x 1 x i32>, ptr [[P]], align 4453; CALLS-NEXT: ret void454;455 load <vscale x 1 x i32>, ptr %p456 ret void457}458 459define void @load.nxv2i32(ptr %p) sanitize_address {460; CHECK-LABEL: @load.nxv2i32(461; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()462; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 64463; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3464; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64465; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[TMP3]], 1466; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], [[TMP5]]467; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr468; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[P]] to i64469; CHECK-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP8]], 3470; CHECK-NEXT: [[TMP10:%.*]] = or i64 [[TMP9]], 17592186044416471; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr472; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr [[TMP11]], align 1473; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0474; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP19:%.*]], !prof [[PROF1]]475; CHECK: 14:476; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[TMP8]], 7477; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i8478; CHECK-NEXT: [[TMP17:%.*]] = icmp sge i8 [[TMP16]], [[TMP12]]479; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP19]]480; CHECK: 18:481; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP8]], i64 [[TMP3]]) #[[ATTR4]]482; CHECK-NEXT: unreachable483; CHECK: 19:484; CHECK-NEXT: [[TMP20:%.*]] = ptrtoint ptr [[TMP7]] to i64485; CHECK-NEXT: [[TMP21:%.*]] = lshr i64 [[TMP20]], 3486; CHECK-NEXT: [[TMP22:%.*]] = or i64 [[TMP21]], 17592186044416487; CHECK-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP22]] to ptr488; CHECK-NEXT: [[TMP24:%.*]] = load i8, ptr [[TMP23]], align 1489; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i8 [[TMP24]], 0490; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP31:%.*]], !prof [[PROF1]]491; CHECK: 26:492; CHECK-NEXT: [[TMP27:%.*]] = and i64 [[TMP20]], 7493; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i8494; CHECK-NEXT: [[TMP29:%.*]] = icmp sge i8 [[TMP28]], [[TMP24]]495; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP31]]496; CHECK: 30:497; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP20]], i64 [[TMP3]]) #[[ATTR4]]498; CHECK-NEXT: unreachable499; CHECK: 31:500; CHECK-NEXT: [[TMP32:%.*]] = load <vscale x 2 x i32>, ptr [[P]], align 8501; CHECK-NEXT: ret void502;503; CALLS-LABEL: @load.nxv2i32(504; CALLS-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()505; CALLS-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 64506; CALLS-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3507; CALLS-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64508; CALLS-NEXT: call void @__asan_loadN(i64 [[TMP4]], i64 [[TMP3]])509; CALLS-NEXT: [[TMP5:%.*]] = load <vscale x 2 x i32>, ptr [[P]], align 8510; CALLS-NEXT: ret void511;512 load <vscale x 2 x i32>, ptr %p513 ret void514}515 516define void @load.nxv4i32(ptr %p) sanitize_address {517; CHECK-LABEL: @load.nxv4i32(518; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()519; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 128520; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3521; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64522; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[TMP3]], 1523; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], [[TMP5]]524; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr525; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[P]] to i64526; CHECK-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP8]], 3527; CHECK-NEXT: [[TMP10:%.*]] = or i64 [[TMP9]], 17592186044416528; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr529; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr [[TMP11]], align 1530; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0531; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP19:%.*]], !prof [[PROF1]]532; CHECK: 14:533; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[TMP8]], 7534; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i8535; CHECK-NEXT: [[TMP17:%.*]] = icmp sge i8 [[TMP16]], [[TMP12]]536; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP19]]537; CHECK: 18:538; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP8]], i64 [[TMP3]]) #[[ATTR4]]539; CHECK-NEXT: unreachable540; CHECK: 19:541; CHECK-NEXT: [[TMP20:%.*]] = ptrtoint ptr [[TMP7]] to i64542; CHECK-NEXT: [[TMP21:%.*]] = lshr i64 [[TMP20]], 3543; CHECK-NEXT: [[TMP22:%.*]] = or i64 [[TMP21]], 17592186044416544; CHECK-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP22]] to ptr545; CHECK-NEXT: [[TMP24:%.*]] = load i8, ptr [[TMP23]], align 1546; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i8 [[TMP24]], 0547; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP31:%.*]], !prof [[PROF1]]548; CHECK: 26:549; CHECK-NEXT: [[TMP27:%.*]] = and i64 [[TMP20]], 7550; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i8551; CHECK-NEXT: [[TMP29:%.*]] = icmp sge i8 [[TMP28]], [[TMP24]]552; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP31]]553; CHECK: 30:554; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP20]], i64 [[TMP3]]) #[[ATTR4]]555; CHECK-NEXT: unreachable556; CHECK: 31:557; CHECK-NEXT: [[TMP32:%.*]] = load <vscale x 4 x i32>, ptr [[P]], align 16558; CHECK-NEXT: ret void559;560; CALLS-LABEL: @load.nxv4i32(561; CALLS-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()562; CALLS-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 128563; CALLS-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3564; CALLS-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64565; CALLS-NEXT: call void @__asan_loadN(i64 [[TMP4]], i64 [[TMP3]])566; CALLS-NEXT: [[TMP5:%.*]] = load <vscale x 4 x i32>, ptr [[P]], align 16567; CALLS-NEXT: ret void568;569 load <vscale x 4 x i32>, ptr %p570 ret void571}572 573define void @load.nxv8i32(ptr %p) sanitize_address {574; CHECK-LABEL: @load.nxv8i32(575; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()576; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 256577; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3578; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64579; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[TMP3]], 1580; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], [[TMP5]]581; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr582; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[P]] to i64583; CHECK-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP8]], 3584; CHECK-NEXT: [[TMP10:%.*]] = or i64 [[TMP9]], 17592186044416585; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr586; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr [[TMP11]], align 1587; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0588; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP19:%.*]], !prof [[PROF1]]589; CHECK: 14:590; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[TMP8]], 7591; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i8592; CHECK-NEXT: [[TMP17:%.*]] = icmp sge i8 [[TMP16]], [[TMP12]]593; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP19]]594; CHECK: 18:595; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP8]], i64 [[TMP3]]) #[[ATTR4]]596; CHECK-NEXT: unreachable597; CHECK: 19:598; CHECK-NEXT: [[TMP20:%.*]] = ptrtoint ptr [[TMP7]] to i64599; CHECK-NEXT: [[TMP21:%.*]] = lshr i64 [[TMP20]], 3600; CHECK-NEXT: [[TMP22:%.*]] = or i64 [[TMP21]], 17592186044416601; CHECK-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP22]] to ptr602; CHECK-NEXT: [[TMP24:%.*]] = load i8, ptr [[TMP23]], align 1603; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i8 [[TMP24]], 0604; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP31:%.*]], !prof [[PROF1]]605; CHECK: 26:606; CHECK-NEXT: [[TMP27:%.*]] = and i64 [[TMP20]], 7607; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i8608; CHECK-NEXT: [[TMP29:%.*]] = icmp sge i8 [[TMP28]], [[TMP24]]609; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP31]]610; CHECK: 30:611; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP20]], i64 [[TMP3]]) #[[ATTR4]]612; CHECK-NEXT: unreachable613; CHECK: 31:614; CHECK-NEXT: [[TMP32:%.*]] = load <vscale x 8 x i32>, ptr [[P]], align 32615; CHECK-NEXT: ret void616;617; CALLS-LABEL: @load.nxv8i32(618; CALLS-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()619; CALLS-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 256620; CALLS-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3621; CALLS-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64622; CALLS-NEXT: call void @__asan_loadN(i64 [[TMP4]], i64 [[TMP3]])623; CALLS-NEXT: [[TMP5:%.*]] = load <vscale x 8 x i32>, ptr [[P]], align 32624; CALLS-NEXT: ret void625;626 load <vscale x 8 x i32>, ptr %p627 ret void628}629 630define void @load.nxv16i32(ptr %p) sanitize_address {631; CHECK-LABEL: @load.nxv16i32(632; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()633; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 512634; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3635; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64636; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[TMP3]], 1637; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], [[TMP5]]638; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr639; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[P]] to i64640; CHECK-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP8]], 3641; CHECK-NEXT: [[TMP10:%.*]] = or i64 [[TMP9]], 17592186044416642; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr643; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr [[TMP11]], align 1644; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0645; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP19:%.*]], !prof [[PROF1]]646; CHECK: 14:647; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[TMP8]], 7648; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i8649; CHECK-NEXT: [[TMP17:%.*]] = icmp sge i8 [[TMP16]], [[TMP12]]650; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP19]]651; CHECK: 18:652; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP8]], i64 [[TMP3]]) #[[ATTR4]]653; CHECK-NEXT: unreachable654; CHECK: 19:655; CHECK-NEXT: [[TMP20:%.*]] = ptrtoint ptr [[TMP7]] to i64656; CHECK-NEXT: [[TMP21:%.*]] = lshr i64 [[TMP20]], 3657; CHECK-NEXT: [[TMP22:%.*]] = or i64 [[TMP21]], 17592186044416658; CHECK-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP22]] to ptr659; CHECK-NEXT: [[TMP24:%.*]] = load i8, ptr [[TMP23]], align 1660; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i8 [[TMP24]], 0661; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP31:%.*]], !prof [[PROF1]]662; CHECK: 26:663; CHECK-NEXT: [[TMP27:%.*]] = and i64 [[TMP20]], 7664; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i8665; CHECK-NEXT: [[TMP29:%.*]] = icmp sge i8 [[TMP28]], [[TMP24]]666; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP31]]667; CHECK: 30:668; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP20]], i64 [[TMP3]]) #[[ATTR4]]669; CHECK-NEXT: unreachable670; CHECK: 31:671; CHECK-NEXT: [[TMP32:%.*]] = load <vscale x 16 x i32>, ptr [[P]], align 64672; CHECK-NEXT: ret void673;674; CALLS-LABEL: @load.nxv16i32(675; CALLS-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()676; CALLS-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 512677; CALLS-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3678; CALLS-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64679; CALLS-NEXT: call void @__asan_loadN(i64 [[TMP4]], i64 [[TMP3]])680; CALLS-NEXT: [[TMP5:%.*]] = load <vscale x 16 x i32>, ptr [[P]], align 64681; CALLS-NEXT: ret void682;683 load <vscale x 16 x i32>, ptr %p684 ret void685}686 687 688define void @store.nxv1i32(ptr %p) sanitize_address {689; CHECK-LABEL: @store.nxv1i32(690; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()691; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 32692; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3693; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64694; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[TMP3]], 1695; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], [[TMP5]]696; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr697; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[P]] to i64698; CHECK-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP8]], 3699; CHECK-NEXT: [[TMP10:%.*]] = or i64 [[TMP9]], 17592186044416700; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr701; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr [[TMP11]], align 1702; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0703; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP19:%.*]], !prof [[PROF1]]704; CHECK: 14:705; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[TMP8]], 7706; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i8707; CHECK-NEXT: [[TMP17:%.*]] = icmp sge i8 [[TMP16]], [[TMP12]]708; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP19]]709; CHECK: 18:710; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP8]], i64 [[TMP3]]) #[[ATTR4]]711; CHECK-NEXT: unreachable712; CHECK: 19:713; CHECK-NEXT: [[TMP20:%.*]] = ptrtoint ptr [[TMP7]] to i64714; CHECK-NEXT: [[TMP21:%.*]] = lshr i64 [[TMP20]], 3715; CHECK-NEXT: [[TMP22:%.*]] = or i64 [[TMP21]], 17592186044416716; CHECK-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP22]] to ptr717; CHECK-NEXT: [[TMP24:%.*]] = load i8, ptr [[TMP23]], align 1718; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i8 [[TMP24]], 0719; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP31:%.*]], !prof [[PROF1]]720; CHECK: 26:721; CHECK-NEXT: [[TMP27:%.*]] = and i64 [[TMP20]], 7722; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i8723; CHECK-NEXT: [[TMP29:%.*]] = icmp sge i8 [[TMP28]], [[TMP24]]724; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP31]]725; CHECK: 30:726; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP20]], i64 [[TMP3]]) #[[ATTR4]]727; CHECK-NEXT: unreachable728; CHECK: 31:729; CHECK-NEXT: store <vscale x 1 x i32> zeroinitializer, ptr [[P]], align 4730; CHECK-NEXT: ret void731;732; CALLS-LABEL: @store.nxv1i32(733; CALLS-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()734; CALLS-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 32735; CALLS-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3736; CALLS-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64737; CALLS-NEXT: call void @__asan_storeN(i64 [[TMP4]], i64 [[TMP3]])738; CALLS-NEXT: store <vscale x 1 x i32> zeroinitializer, ptr [[P]], align 4739; CALLS-NEXT: ret void740;741 store <vscale x 1 x i32> zeroinitializer, ptr %p742 ret void743}744 745define void @store.nxv2i32(ptr %p) sanitize_address {746; CHECK-LABEL: @store.nxv2i32(747; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()748; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 64749; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3750; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64751; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[TMP3]], 1752; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], [[TMP5]]753; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr754; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[P]] to i64755; CHECK-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP8]], 3756; CHECK-NEXT: [[TMP10:%.*]] = or i64 [[TMP9]], 17592186044416757; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr758; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr [[TMP11]], align 1759; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0760; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP19:%.*]], !prof [[PROF1]]761; CHECK: 14:762; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[TMP8]], 7763; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i8764; CHECK-NEXT: [[TMP17:%.*]] = icmp sge i8 [[TMP16]], [[TMP12]]765; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP19]]766; CHECK: 18:767; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP8]], i64 [[TMP3]]) #[[ATTR4]]768; CHECK-NEXT: unreachable769; CHECK: 19:770; CHECK-NEXT: [[TMP20:%.*]] = ptrtoint ptr [[TMP7]] to i64771; CHECK-NEXT: [[TMP21:%.*]] = lshr i64 [[TMP20]], 3772; CHECK-NEXT: [[TMP22:%.*]] = or i64 [[TMP21]], 17592186044416773; CHECK-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP22]] to ptr774; CHECK-NEXT: [[TMP24:%.*]] = load i8, ptr [[TMP23]], align 1775; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i8 [[TMP24]], 0776; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP31:%.*]], !prof [[PROF1]]777; CHECK: 26:778; CHECK-NEXT: [[TMP27:%.*]] = and i64 [[TMP20]], 7779; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i8780; CHECK-NEXT: [[TMP29:%.*]] = icmp sge i8 [[TMP28]], [[TMP24]]781; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP31]]782; CHECK: 30:783; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP20]], i64 [[TMP3]]) #[[ATTR4]]784; CHECK-NEXT: unreachable785; CHECK: 31:786; CHECK-NEXT: store <vscale x 2 x i32> zeroinitializer, ptr [[P]], align 8787; CHECK-NEXT: ret void788;789; CALLS-LABEL: @store.nxv2i32(790; CALLS-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()791; CALLS-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 64792; CALLS-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3793; CALLS-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64794; CALLS-NEXT: call void @__asan_storeN(i64 [[TMP4]], i64 [[TMP3]])795; CALLS-NEXT: store <vscale x 2 x i32> zeroinitializer, ptr [[P]], align 8796; CALLS-NEXT: ret void797;798 store <vscale x 2 x i32> zeroinitializer, ptr %p799 ret void800}801 802define void @store.nxv4i32(ptr %p) sanitize_address {803; CHECK-LABEL: @store.nxv4i32(804; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()805; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 128806; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3807; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64808; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[TMP3]], 1809; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], [[TMP5]]810; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr811; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[P]] to i64812; CHECK-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP8]], 3813; CHECK-NEXT: [[TMP10:%.*]] = or i64 [[TMP9]], 17592186044416814; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr815; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr [[TMP11]], align 1816; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0817; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP19:%.*]], !prof [[PROF1]]818; CHECK: 14:819; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[TMP8]], 7820; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i8821; CHECK-NEXT: [[TMP17:%.*]] = icmp sge i8 [[TMP16]], [[TMP12]]822; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP19]]823; CHECK: 18:824; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP8]], i64 [[TMP3]]) #[[ATTR4]]825; CHECK-NEXT: unreachable826; CHECK: 19:827; CHECK-NEXT: [[TMP20:%.*]] = ptrtoint ptr [[TMP7]] to i64828; CHECK-NEXT: [[TMP21:%.*]] = lshr i64 [[TMP20]], 3829; CHECK-NEXT: [[TMP22:%.*]] = or i64 [[TMP21]], 17592186044416830; CHECK-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP22]] to ptr831; CHECK-NEXT: [[TMP24:%.*]] = load i8, ptr [[TMP23]], align 1832; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i8 [[TMP24]], 0833; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP31:%.*]], !prof [[PROF1]]834; CHECK: 26:835; CHECK-NEXT: [[TMP27:%.*]] = and i64 [[TMP20]], 7836; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i8837; CHECK-NEXT: [[TMP29:%.*]] = icmp sge i8 [[TMP28]], [[TMP24]]838; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP31]]839; CHECK: 30:840; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP20]], i64 [[TMP3]]) #[[ATTR4]]841; CHECK-NEXT: unreachable842; CHECK: 31:843; CHECK-NEXT: store <vscale x 4 x i32> zeroinitializer, ptr [[P]], align 16844; CHECK-NEXT: ret void845;846; CALLS-LABEL: @store.nxv4i32(847; CALLS-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()848; CALLS-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 128849; CALLS-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3850; CALLS-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64851; CALLS-NEXT: call void @__asan_storeN(i64 [[TMP4]], i64 [[TMP3]])852; CALLS-NEXT: store <vscale x 4 x i32> zeroinitializer, ptr [[P]], align 16853; CALLS-NEXT: ret void854;855 store <vscale x 4 x i32> zeroinitializer, ptr %p856 ret void857}858 859define void @store.nxv8i32(ptr %p) sanitize_address {860; CHECK-LABEL: @store.nxv8i32(861; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()862; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 256863; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3864; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64865; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[TMP3]], 1866; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], [[TMP5]]867; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr868; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[P]] to i64869; CHECK-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP8]], 3870; CHECK-NEXT: [[TMP10:%.*]] = or i64 [[TMP9]], 17592186044416871; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr872; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr [[TMP11]], align 1873; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0874; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP19:%.*]], !prof [[PROF1]]875; CHECK: 14:876; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[TMP8]], 7877; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i8878; CHECK-NEXT: [[TMP17:%.*]] = icmp sge i8 [[TMP16]], [[TMP12]]879; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP19]]880; CHECK: 18:881; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP8]], i64 [[TMP3]]) #[[ATTR4]]882; CHECK-NEXT: unreachable883; CHECK: 19:884; CHECK-NEXT: [[TMP20:%.*]] = ptrtoint ptr [[TMP7]] to i64885; CHECK-NEXT: [[TMP21:%.*]] = lshr i64 [[TMP20]], 3886; CHECK-NEXT: [[TMP22:%.*]] = or i64 [[TMP21]], 17592186044416887; CHECK-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP22]] to ptr888; CHECK-NEXT: [[TMP24:%.*]] = load i8, ptr [[TMP23]], align 1889; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i8 [[TMP24]], 0890; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP31:%.*]], !prof [[PROF1]]891; CHECK: 26:892; CHECK-NEXT: [[TMP27:%.*]] = and i64 [[TMP20]], 7893; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i8894; CHECK-NEXT: [[TMP29:%.*]] = icmp sge i8 [[TMP28]], [[TMP24]]895; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP31]]896; CHECK: 30:897; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP20]], i64 [[TMP3]]) #[[ATTR4]]898; CHECK-NEXT: unreachable899; CHECK: 31:900; CHECK-NEXT: store <vscale x 8 x i32> zeroinitializer, ptr [[P]], align 32901; CHECK-NEXT: ret void902;903; CALLS-LABEL: @store.nxv8i32(904; CALLS-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()905; CALLS-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 256906; CALLS-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3907; CALLS-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64908; CALLS-NEXT: call void @__asan_storeN(i64 [[TMP4]], i64 [[TMP3]])909; CALLS-NEXT: store <vscale x 8 x i32> zeroinitializer, ptr [[P]], align 32910; CALLS-NEXT: ret void911;912 store <vscale x 8 x i32> zeroinitializer, ptr %p913 ret void914}915 916define void @store.nxv16i32(ptr %p) sanitize_address {917; CHECK-LABEL: @store.nxv16i32(918; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()919; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 512920; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3921; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64922; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[TMP3]], 1923; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], [[TMP5]]924; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr925; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[P]] to i64926; CHECK-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP8]], 3927; CHECK-NEXT: [[TMP10:%.*]] = or i64 [[TMP9]], 17592186044416928; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr929; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr [[TMP11]], align 1930; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0931; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP19:%.*]], !prof [[PROF1]]932; CHECK: 14:933; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[TMP8]], 7934; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i8935; CHECK-NEXT: [[TMP17:%.*]] = icmp sge i8 [[TMP16]], [[TMP12]]936; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP19]]937; CHECK: 18:938; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP8]], i64 [[TMP3]]) #[[ATTR4]]939; CHECK-NEXT: unreachable940; CHECK: 19:941; CHECK-NEXT: [[TMP20:%.*]] = ptrtoint ptr [[TMP7]] to i64942; CHECK-NEXT: [[TMP21:%.*]] = lshr i64 [[TMP20]], 3943; CHECK-NEXT: [[TMP22:%.*]] = or i64 [[TMP21]], 17592186044416944; CHECK-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP22]] to ptr945; CHECK-NEXT: [[TMP24:%.*]] = load i8, ptr [[TMP23]], align 1946; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i8 [[TMP24]], 0947; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP31:%.*]], !prof [[PROF1]]948; CHECK: 26:949; CHECK-NEXT: [[TMP27:%.*]] = and i64 [[TMP20]], 7950; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i8951; CHECK-NEXT: [[TMP29:%.*]] = icmp sge i8 [[TMP28]], [[TMP24]]952; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP31]]953; CHECK: 30:954; CHECK-NEXT: call void @__asan_report_store_n(i64 [[TMP20]], i64 [[TMP3]]) #[[ATTR4]]955; CHECK-NEXT: unreachable956; CHECK: 31:957; CHECK-NEXT: store <vscale x 16 x i32> zeroinitializer, ptr [[P]], align 64958; CHECK-NEXT: ret void959;960; CALLS-LABEL: @store.nxv16i32(961; CALLS-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()962; CALLS-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 512963; CALLS-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3964; CALLS-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64965; CALLS-NEXT: call void @__asan_storeN(i64 [[TMP4]], i64 [[TMP3]])966; CALLS-NEXT: store <vscale x 16 x i32> zeroinitializer, ptr [[P]], align 64967; CALLS-NEXT: ret void968;969 store <vscale x 16 x i32> zeroinitializer, ptr %p970 ret void971}972 973declare void @clobber(ptr)974 975define <vscale x 2 x i32> @local_alloca() sanitize_address {976; CHECK-LABEL: @local_alloca(977; CHECK-NEXT: [[A:%.*]] = alloca <vscale x 2 x i32>, align 8978; CHECK-NEXT: call void @clobber(ptr [[A]])979; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()980; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 64981; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 3982; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i64983; CHECK-NEXT: [[TMP5:%.*]] = sub i64 [[TMP3]], 1984; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], [[TMP5]]985; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr986; CHECK-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[A]] to i64987; CHECK-NEXT: [[TMP9:%.*]] = lshr i64 [[TMP8]], 3988; CHECK-NEXT: [[TMP10:%.*]] = or i64 [[TMP9]], 17592186044416989; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr990; CHECK-NEXT: [[TMP12:%.*]] = load i8, ptr [[TMP11]], align 1991; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0992; CHECK-NEXT: br i1 [[TMP13]], label [[TMP14:%.*]], label [[TMP19:%.*]], !prof [[PROF1]]993; CHECK: 14:994; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[TMP8]], 7995; CHECK-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i8996; CHECK-NEXT: [[TMP17:%.*]] = icmp sge i8 [[TMP16]], [[TMP12]]997; CHECK-NEXT: br i1 [[TMP17]], label [[TMP18:%.*]], label [[TMP19]]998; CHECK: 18:999; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP8]], i64 [[TMP3]]) #[[ATTR4]]1000; CHECK-NEXT: unreachable1001; CHECK: 19:1002; CHECK-NEXT: [[TMP20:%.*]] = ptrtoint ptr [[TMP7]] to i641003; CHECK-NEXT: [[TMP21:%.*]] = lshr i64 [[TMP20]], 31004; CHECK-NEXT: [[TMP22:%.*]] = or i64 [[TMP21]], 175921860444161005; CHECK-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP22]] to ptr1006; CHECK-NEXT: [[TMP24:%.*]] = load i8, ptr [[TMP23]], align 11007; CHECK-NEXT: [[TMP25:%.*]] = icmp ne i8 [[TMP24]], 01008; CHECK-NEXT: br i1 [[TMP25]], label [[TMP26:%.*]], label [[TMP31:%.*]], !prof [[PROF1]]1009; CHECK: 26:1010; CHECK-NEXT: [[TMP27:%.*]] = and i64 [[TMP20]], 71011; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i81012; CHECK-NEXT: [[TMP29:%.*]] = icmp sge i8 [[TMP28]], [[TMP24]]1013; CHECK-NEXT: br i1 [[TMP29]], label [[TMP30:%.*]], label [[TMP31]]1014; CHECK: 30:1015; CHECK-NEXT: call void @__asan_report_load_n(i64 [[TMP20]], i64 [[TMP3]]) #[[ATTR4]]1016; CHECK-NEXT: unreachable1017; CHECK: 31:1018; CHECK-NEXT: [[RES:%.*]] = load <vscale x 2 x i32>, ptr [[A]], align 81019; CHECK-NEXT: ret <vscale x 2 x i32> [[RES]]1020;1021; CALLS-LABEL: @local_alloca(1022; CALLS-NEXT: [[A:%.*]] = alloca <vscale x 2 x i32>, align 81023; CALLS-NEXT: call void @clobber(ptr [[A]])1024; CALLS-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()1025; CALLS-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 641026; CALLS-NEXT: [[TMP3:%.*]] = lshr i64 [[TMP2]], 31027; CALLS-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i641028; CALLS-NEXT: call void @__asan_loadN(i64 [[TMP4]], i64 [[TMP3]])1029; CALLS-NEXT: [[RES:%.*]] = load <vscale x 2 x i32>, ptr [[A]], align 81030; CALLS-NEXT: ret <vscale x 2 x i32> [[RES]]1031;1032 %a = alloca <vscale x 2 x i32>1033 call void @clobber(ptr %a)1034 %res = load <vscale x 2 x i32>, ptr %a1035 ret <vscale x 2 x i32> %res1036}1037