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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 62; RUN: opt < %s -passes=dfsan -dfsan-track-origins=1 -dfsan-add-global-name-suffix=0 -S | FileCheck %s3;4; %i13 and %i15 have the same key in shadow cache. They should not reuse the same5; shadow because their blocks do not dominate each other. Origin tracking6; splt blocks. This test ensures DT is updated correctly, and cached shadows7; are not mis-used.8target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"9target triple = "x86_64-unknown-linux-gnu"10 11define void @cached_shadows(double %arg) {12; CHECK-LABEL: define void @cached_shadows(13; CHECK-SAME: double [[ARG:%.*]]) {14; CHECK-NEXT: [[BB:.*]]:15; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 416; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr @__dfsan_arg_tls, align 217; CHECK-NEXT: [[I:%.*]] = alloca double, align 818; CHECK-NEXT: [[I1:%.*]] = alloca double, align 819; CHECK-NEXT: [[I2:%.*]] = bitcast ptr [[I]] to ptr20; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[I]] to i6421; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 8796093022208022; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr23; CHECK-NEXT: store i64 0, ptr [[TMP4]], align 124; CHECK-NEXT: store volatile double 1.000000e+00, ptr [[I]], align 825; CHECK-NEXT: [[I3:%.*]] = bitcast ptr [[I1]] to ptr26; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[I1]] to i6427; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 8796093022208028; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr29; CHECK-NEXT: store i64 0, ptr [[TMP7]], align 130; CHECK-NEXT: store volatile double 2.000000e+00, ptr [[I1]], align 831; CHECK-NEXT: br label %[[BB4:.*]]32; CHECK: [[BB4]]:33; CHECK-NEXT: [[TMP8:%.*]] = phi i8 [ 0, %[[BB]] ], [ [[TMP76:%.*]], %[[BB16:.*]] ]34; CHECK-NEXT: [[TMP9:%.*]] = phi i32 [ 0, %[[BB]] ], [ [[TMP77:%.*]], %[[BB16]] ]35; CHECK-NEXT: [[I5:%.*]] = phi double [ 3.000000e+00, %[[BB]] ], [ [[I17:%.*]], %[[BB16]] ]36; CHECK-NEXT: [[TMP10:%.*]] = phi i8 [ 0, %[[BB]] ], [ [[TMP78:%.*]], %[[BB16]] ]37; CHECK-NEXT: [[TMP11:%.*]] = phi i32 [ 0, %[[BB]] ], [ [[TMP79:%.*]], %[[BB16]] ]38; CHECK-NEXT: [[I6:%.*]] = phi double [ 4.000000e+00, %[[BB]] ], [ [[I18:%.*]], %[[BB16]] ]39; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[I1]] to i6440; CHECK-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], 8796093022208041; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr42; CHECK-NEXT: [[TMP15:%.*]] = add i64 [[TMP13]], 1759218604441643; CHECK-NEXT: [[TMP16:%.*]] = inttoptr i64 [[TMP15]] to ptr44; CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 845; CHECK-NEXT: [[TMP18:%.*]] = load i64, ptr [[TMP14]], align 146; CHECK-NEXT: [[TMP19:%.*]] = shl i64 [[TMP18]], 3247; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr [[TMP16]], i64 148; CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 849; CHECK-NEXT: [[TMP22:%.*]] = lshr i64 [[TMP18]], 3250; CHECK-NEXT: [[TMP23:%.*]] = or i64 [[TMP18]], [[TMP22]]51; CHECK-NEXT: [[TMP24:%.*]] = lshr i64 [[TMP23]], 1652; CHECK-NEXT: [[TMP25:%.*]] = or i64 [[TMP23]], [[TMP24]]53; CHECK-NEXT: [[TMP26:%.*]] = lshr i64 [[TMP25]], 854; CHECK-NEXT: [[TMP27:%.*]] = or i64 [[TMP25]], [[TMP26]]55; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[TMP27]] to i856; CHECK-NEXT: [[TMP29:%.*]] = icmp ne i64 [[TMP19]], 057; CHECK-NEXT: [[TMP30:%.*]] = select i1 [[TMP29]], i32 [[TMP17]], i32 [[TMP21]]58; CHECK-NEXT: [[I7:%.*]] = load volatile double, ptr [[I1]], align 859; CHECK-NEXT: [[I8:%.*]] = fcmp une double [[I7]], 0.000000e+0060; CHECK-NEXT: [[TMP31:%.*]] = ptrtoint ptr [[I1]] to i6461; CHECK-NEXT: [[TMP32:%.*]] = xor i64 [[TMP31]], 8796093022208062; CHECK-NEXT: [[TMP33:%.*]] = inttoptr i64 [[TMP32]] to ptr63; CHECK-NEXT: [[TMP34:%.*]] = add i64 [[TMP32]], 1759218604441664; CHECK-NEXT: [[TMP35:%.*]] = inttoptr i64 [[TMP34]] to ptr65; CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP35]], align 866; CHECK-NEXT: [[TMP37:%.*]] = load i64, ptr [[TMP33]], align 167; CHECK-NEXT: [[TMP38:%.*]] = shl i64 [[TMP37]], 3268; CHECK-NEXT: [[TMP39:%.*]] = getelementptr i32, ptr [[TMP35]], i64 169; CHECK-NEXT: [[TMP40:%.*]] = load i32, ptr [[TMP39]], align 870; CHECK-NEXT: [[TMP41:%.*]] = lshr i64 [[TMP37]], 3271; CHECK-NEXT: [[TMP42:%.*]] = or i64 [[TMP37]], [[TMP41]]72; CHECK-NEXT: [[TMP43:%.*]] = lshr i64 [[TMP42]], 1673; CHECK-NEXT: [[TMP44:%.*]] = or i64 [[TMP42]], [[TMP43]]74; CHECK-NEXT: [[TMP45:%.*]] = lshr i64 [[TMP44]], 875; CHECK-NEXT: [[TMP46:%.*]] = or i64 [[TMP44]], [[TMP45]]76; CHECK-NEXT: [[TMP47:%.*]] = trunc i64 [[TMP46]] to i877; CHECK-NEXT: [[TMP48:%.*]] = icmp ne i64 [[TMP38]], 078; CHECK-NEXT: [[TMP49:%.*]] = select i1 [[TMP48]], i32 [[TMP36]], i32 [[TMP40]]79; CHECK-NEXT: [[I9:%.*]] = load volatile double, ptr [[I1]], align 880; CHECK-NEXT: br i1 [[I8]], label %[[BB10:.*]], label %[[BB14:.*]]81; CHECK: [[BB10]]:82; CHECK-NEXT: [[I11:%.*]] = fcmp une double [[I9]], 0.000000e+0083; CHECK-NEXT: br i1 [[I11]], label %[[BB12:.*]], label %[[BB16]]84; CHECK: [[BB12]]:85; CHECK-NEXT: [[TMP50:%.*]] = or i8 [[TMP10]], [[TMP1]]86; CHECK-NEXT: [[TMP51:%.*]] = icmp ne i8 [[TMP1]], 087; CHECK-NEXT: [[TMP52:%.*]] = select i1 [[TMP51]], i32 [[TMP0]], i32 [[TMP11]]88; CHECK-NEXT: [[I13:%.*]] = fsub double [[I6]], [[ARG]]89; CHECK-NEXT: br label %[[BB16]]90; CHECK: [[BB14]]:91; CHECK-NEXT: [[TMP53:%.*]] = ptrtoint ptr [[I]] to i6492; CHECK-NEXT: [[TMP54:%.*]] = xor i64 [[TMP53]], 8796093022208093; CHECK-NEXT: [[TMP55:%.*]] = inttoptr i64 [[TMP54]] to ptr94; CHECK-NEXT: [[TMP56:%.*]] = add i64 [[TMP54]], 1759218604441695; CHECK-NEXT: [[TMP57:%.*]] = inttoptr i64 [[TMP56]] to ptr96; CHECK-NEXT: [[TMP58:%.*]] = insertelement <8 x i8> poison, i8 [[TMP47]], i32 097; CHECK-NEXT: [[TMP59:%.*]] = insertelement <8 x i8> [[TMP58]], i8 [[TMP47]], i32 198; CHECK-NEXT: [[TMP60:%.*]] = insertelement <8 x i8> [[TMP59]], i8 [[TMP47]], i32 299; CHECK-NEXT: [[TMP61:%.*]] = insertelement <8 x i8> [[TMP60]], i8 [[TMP47]], i32 3100; CHECK-NEXT: [[TMP62:%.*]] = insertelement <8 x i8> [[TMP61]], i8 [[TMP47]], i32 4101; CHECK-NEXT: [[TMP63:%.*]] = insertelement <8 x i8> [[TMP62]], i8 [[TMP47]], i32 5102; CHECK-NEXT: [[TMP64:%.*]] = insertelement <8 x i8> [[TMP63]], i8 [[TMP47]], i32 6103; CHECK-NEXT: [[TMP65:%.*]] = insertelement <8 x i8> [[TMP64]], i8 [[TMP47]], i32 7104; CHECK-NEXT: [[TMP66:%.*]] = getelementptr <8 x i8>, ptr [[TMP55]], i32 0105; CHECK-NEXT: store <8 x i8> [[TMP65]], ptr [[TMP66]], align 1106; CHECK-NEXT: [[_DFSCMP:%.*]] = icmp ne i8 [[TMP47]], 0107; CHECK-NEXT: br i1 [[_DFSCMP]], label %[[BB67:.*]], label %[[BB72:.*]], !prof [[PROF1:![0-9]+]]108; CHECK: [[BB67]]:109; CHECK-NEXT: [[TMP68:%.*]] = call i32 @__dfsan_chain_origin(i32 [[TMP49]])110; CHECK-NEXT: [[TMP69:%.*]] = zext i32 [[TMP68]] to i64111; CHECK-NEXT: [[TMP70:%.*]] = shl i64 [[TMP69]], 32112; CHECK-NEXT: [[TMP71:%.*]] = or i64 [[TMP69]], [[TMP70]]113; CHECK-NEXT: store i64 [[TMP71]], ptr [[TMP57]], align 8114; CHECK-NEXT: br label %[[BB72]]115; CHECK: [[BB72]]:116; CHECK-NEXT: store volatile double [[I9]], ptr [[I]], align 8117; CHECK-NEXT: [[TMP73:%.*]] = or i8 [[TMP10]], [[TMP1]]118; CHECK-NEXT: [[TMP74:%.*]] = icmp ne i8 [[TMP1]], 0119; CHECK-NEXT: [[TMP75:%.*]] = select i1 [[TMP74]], i32 [[TMP0]], i32 [[TMP11]]120; CHECK-NEXT: [[I15:%.*]] = fadd double [[I6]], [[ARG]]121; CHECK-NEXT: br label %[[BB16]]122; CHECK: [[BB16]]:123; CHECK-NEXT: [[TMP76]] = phi i8 [ [[TMP10]], %[[BB12]] ], [ [[TMP8]], %[[BB10]] ], [ [[TMP10]], %[[BB72]] ]124; CHECK-NEXT: [[TMP77]] = phi i32 [ [[TMP11]], %[[BB12]] ], [ [[TMP9]], %[[BB10]] ], [ [[TMP11]], %[[BB72]] ]125; CHECK-NEXT: [[I17]] = phi double [ [[I6]], %[[BB12]] ], [ [[I5]], %[[BB10]] ], [ [[I6]], %[[BB72]] ]126; CHECK-NEXT: [[TMP78]] = phi i8 [ [[TMP50]], %[[BB12]] ], [ [[TMP10]], %[[BB10]] ], [ [[TMP73]], %[[BB72]] ]127; CHECK-NEXT: [[TMP79]] = phi i32 [ [[TMP52]], %[[BB12]] ], [ [[TMP11]], %[[BB10]] ], [ [[TMP75]], %[[BB72]] ]128; CHECK-NEXT: [[I18]] = phi double [ [[I13]], %[[BB12]] ], [ [[I6]], %[[BB10]] ], [ [[I15]], %[[BB72]] ]129; CHECK-NEXT: [[I19:%.*]] = fcmp olt double [[I17]], 9.900000e+01130; CHECK-NEXT: br i1 [[I19]], label %[[BB4]], label %[[BB20:.*]]131; CHECK: [[BB20]]:132; CHECK-NEXT: ret void133;134bb:135 %i = alloca double, align 8136 %i1 = alloca double, align 8137 %i2 = bitcast ptr %i to ptr138 store volatile double 1.000000e+00, ptr %i, align 8139 %i3 = bitcast ptr %i1 to ptr140 store volatile double 2.000000e+00, ptr %i1, align 8141 br label %bb4142 143bb4: ; preds = %bb16, %bb144 %i5 = phi double [ 3.000000e+00, %bb ], [ %i17, %bb16 ]145 %i6 = phi double [ 4.000000e+00, %bb ], [ %i18, %bb16 ]146 %i7 = load volatile double, ptr %i1, align 8147 %i8 = fcmp une double %i7, 0.000000e+00148 %i9 = load volatile double, ptr %i1, align 8149 br i1 %i8, label %bb10, label %bb14150 151bb10: ; preds = %bb4152 %i11 = fcmp une double %i9, 0.000000e+00153 br i1 %i11, label %bb12, label %bb16154 155bb12: ; preds = %bb10156 %i13 = fsub double %i6, %arg157 br label %bb16158 159bb14: ; preds = %bb4160 store volatile double %i9, ptr %i, align 8161 %i15 = fadd double %i6, %arg162 br label %bb16163 164bb16: ; preds = %bb14, %bb12, %bb10165 %i17 = phi double [ %i6, %bb12 ], [ %i5, %bb10 ], [ %i6, %bb14 ]166 %i18 = phi double [ %i13, %bb12 ], [ %i6, %bb10 ], [ %i15, %bb14 ]167 %i19 = fcmp olt double %i17, 9.900000e+01168 br i1 %i19, label %bb4, label %bb20169 170bb20: ; preds = %bb16171 ret void172}173;.174; CHECK: [[PROF1]] = !{!"branch_weights", i32 1, i32 1048575}175;.176