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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 62; RUN: opt < %s -passes=dfsan -dfsan-track-origins=1 -dfsan-add-global-name-suffix=0 -S | FileCheck %s3target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"4target triple = "x86_64-unknown-linux-gnu"5 6define float @unop(float %f) {7; CHECK-LABEL: define float @unop(8; CHECK-SAME: float [[F:%.*]]) {9; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 410; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr @__dfsan_arg_tls, align 211; CHECK-NEXT: [[R:%.*]] = fneg float [[F]]12; CHECK-NEXT: store i8 [[TMP2]], ptr @__dfsan_retval_tls, align 213; CHECK-NEXT: store i32 [[TMP1]], ptr @__dfsan_retval_origin_tls, align 414; CHECK-NEXT: ret float [[R]]15;16 %r = fneg float %f17 ret float %r18}19 20define i1 @binop(i1 %a, i1 %b) {21; CHECK-LABEL: define i1 @binop(22; CHECK-SAME: i1 [[A:%.*]], i1 [[B:%.*]]) {23; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 424; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 425; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 226; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr @__dfsan_arg_tls, align 227; CHECK-NEXT: [[TMP5:%.*]] = or i8 [[TMP4]], [[TMP3]]28; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i8 [[TMP3]], 029; CHECK-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i32 [[TMP1]], i32 [[TMP2]]30; CHECK-NEXT: [[R:%.*]] = add i1 [[A]], [[B]]31; CHECK-NEXT: store i8 [[TMP5]], ptr @__dfsan_retval_tls, align 232; CHECK-NEXT: store i32 [[TMP7]], ptr @__dfsan_retval_origin_tls, align 433; CHECK-NEXT: ret i1 [[R]]34;35 %r = add i1 %a, %b36 ret i1 %r37}38 39define i8 @castop(ptr %p) {40; CHECK-LABEL: define i8 @castop(41; CHECK-SAME: ptr [[P:%.*]]) {42; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 443; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr @__dfsan_arg_tls, align 244; CHECK-NEXT: [[R:%.*]] = ptrtoint ptr [[P]] to i845; CHECK-NEXT: store i8 [[TMP2]], ptr @__dfsan_retval_tls, align 246; CHECK-NEXT: store i32 [[TMP1]], ptr @__dfsan_retval_origin_tls, align 447; CHECK-NEXT: ret i8 [[R]]48;49 %r = ptrtoint ptr %p to i850 ret i8 %r51}52 53define i1 @cmpop(i1 %a, i1 %b) {54; CHECK-LABEL: define i1 @cmpop(55; CHECK-SAME: i1 [[A:%.*]], i1 [[B:%.*]]) {56; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 457; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 458; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 259; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr @__dfsan_arg_tls, align 260; CHECK-NEXT: [[TMP5:%.*]] = or i8 [[TMP4]], [[TMP3]]61; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i8 [[TMP3]], 062; CHECK-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i32 [[TMP1]], i32 [[TMP2]]63; CHECK-NEXT: [[R:%.*]] = icmp eq i1 [[A]], [[B]]64; CHECK-NEXT: store i8 [[TMP5]], ptr @__dfsan_retval_tls, align 265; CHECK-NEXT: store i32 [[TMP7]], ptr @__dfsan_retval_origin_tls, align 466; CHECK-NEXT: ret i1 [[R]]67;68 %r = icmp eq i1 %a, %b69 ret i1 %r70}71 72define ptr @gepop(ptr %p, i32 %a, i32 %b, i32 %c) {73; CHECK-LABEL: define ptr @gepop(74; CHECK-SAME: ptr [[P:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]]) {75; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 3), align 476; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 2), align 477; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 478; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 479; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 6), align 280; CHECK-NEXT: [[TMP6:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 4), align 281; CHECK-NEXT: [[TMP7:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 282; CHECK-NEXT: [[TMP8:%.*]] = load i8, ptr @__dfsan_arg_tls, align 283; CHECK-NEXT: [[TMP9:%.*]] = or i8 [[TMP8]], [[TMP7]]84; CHECK-NEXT: [[TMP10:%.*]] = or i8 [[TMP9]], [[TMP6]]85; CHECK-NEXT: [[TMP11:%.*]] = or i8 [[TMP10]], [[TMP5]]86; CHECK-NEXT: [[TMP12:%.*]] = icmp ne i8 [[TMP7]], 087; CHECK-NEXT: [[TMP13:%.*]] = select i1 [[TMP12]], i32 [[TMP3]], i32 [[TMP4]]88; CHECK-NEXT: [[TMP14:%.*]] = icmp ne i8 [[TMP6]], 089; CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i32 [[TMP2]], i32 [[TMP13]]90; CHECK-NEXT: [[TMP16:%.*]] = icmp ne i8 [[TMP5]], 091; CHECK-NEXT: [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP1]], i32 [[TMP15]]92; CHECK-NEXT: [[E:%.*]] = getelementptr [10 x [20 x i32]], ptr [[P]], i32 [[A]], i32 [[B]], i32 [[C]]93; CHECK-NEXT: store i8 [[TMP11]], ptr @__dfsan_retval_tls, align 294; CHECK-NEXT: store i32 [[TMP17]], ptr @__dfsan_retval_origin_tls, align 495; CHECK-NEXT: ret ptr [[E]]96;97 %e = getelementptr [10 x [20 x i32]], ptr %p, i32 %a, i32 %b, i32 %c98 ret ptr %e99}100 101define i32 @eeop(<4 x i32> %a, i32 %b) {102; CHECK-LABEL: define i32 @eeop(103; CHECK-SAME: <4 x i32> [[A:%.*]], i32 [[B:%.*]]) {104; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4105; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4106; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2107; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2108; CHECK-NEXT: [[TMP5:%.*]] = or i8 [[TMP4]], [[TMP3]]109; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i8 [[TMP3]], 0110; CHECK-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i32 [[TMP1]], i32 [[TMP2]]111; CHECK-NEXT: [[E:%.*]] = extractelement <4 x i32> [[A]], i32 [[B]]112; CHECK-NEXT: store i8 [[TMP5]], ptr @__dfsan_retval_tls, align 2113; CHECK-NEXT: store i32 [[TMP7]], ptr @__dfsan_retval_origin_tls, align 4114; CHECK-NEXT: ret i32 [[E]]115;116 %e = extractelement <4 x i32> %a, i32 %b117 ret i32 %e118}119 120define <4 x i32> @ieop(<4 x i32> %p, i32 %a, i32 %b) {121; CHECK-LABEL: define <4 x i32> @ieop(122; CHECK-SAME: <4 x i32> [[P:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) {123; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 2), align 4124; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4125; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4126; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 4), align 2127; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2128; CHECK-NEXT: [[TMP6:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2129; CHECK-NEXT: [[TMP7:%.*]] = or i8 [[TMP6]], [[TMP5]]130; CHECK-NEXT: [[TMP8:%.*]] = or i8 [[TMP7]], [[TMP4]]131; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i8 [[TMP5]], 0132; CHECK-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], i32 [[TMP2]], i32 [[TMP3]]133; CHECK-NEXT: [[TMP11:%.*]] = icmp ne i8 [[TMP4]], 0134; CHECK-NEXT: [[TMP12:%.*]] = select i1 [[TMP11]], i32 [[TMP1]], i32 [[TMP10]]135; CHECK-NEXT: [[E:%.*]] = insertelement <4 x i32> [[P]], i32 [[A]], i32 [[B]]136; CHECK-NEXT: store i8 [[TMP8]], ptr @__dfsan_retval_tls, align 2137; CHECK-NEXT: store i32 [[TMP12]], ptr @__dfsan_retval_origin_tls, align 4138; CHECK-NEXT: ret <4 x i32> [[E]]139;140 %e = insertelement <4 x i32> %p, i32 %a, i32 %b141 ret <4 x i32> %e142}143 144define <4 x i32> @svop(<4 x i32> %a, <4 x i32> %b) {145; CHECK-LABEL: define <4 x i32> @svop(146; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) {147; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4148; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4149; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2150; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2151; CHECK-NEXT: [[TMP5:%.*]] = or i8 [[TMP4]], [[TMP3]]152; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i8 [[TMP3]], 0153; CHECK-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i32 [[TMP1]], i32 [[TMP2]]154; CHECK-NEXT: [[E:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> [[B]], <4 x i32> <i32 0, i32 4, i32 1, i32 5>155; CHECK-NEXT: store i8 [[TMP5]], ptr @__dfsan_retval_tls, align 2156; CHECK-NEXT: store i32 [[TMP7]], ptr @__dfsan_retval_origin_tls, align 4157; CHECK-NEXT: ret <4 x i32> [[E]]158;159 %e = shufflevector <4 x i32> %a, <4 x i32> %b, <4 x i32> <i32 0, i32 4, i32 1, i32 5>160 ret <4 x i32> %e161}162 163define i32 @evop({i32, float} %a) {164; CHECK-LABEL: define i32 @evop(165; CHECK-SAME: { i32, float } [[A:%.*]]) {166; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4167; CHECK-NEXT: [[TMP2:%.*]] = load { i8, i8 }, ptr @__dfsan_arg_tls, align 2168; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i8, i8 } [[TMP2]], 0169; CHECK-NEXT: [[E:%.*]] = extractvalue { i32, float } [[A]], 0170; CHECK-NEXT: store i8 [[TMP3]], ptr @__dfsan_retval_tls, align 2171; CHECK-NEXT: store i32 [[TMP1]], ptr @__dfsan_retval_origin_tls, align 4172; CHECK-NEXT: ret i32 [[E]]173;174 %e = extractvalue {i32, float} %a, 0175 ret i32 %e176}177 178; COMM: TODO simplify the expression 4 to179; COMM: 6, if shadow-tls-alignment is updated to match shadow180define {i32, {float, float}} @ivop({i32, {float, float}} %a, {float, float} %b) {181; CHECK-LABEL: define { i32, { float, float } } @ivop(182; CHECK-SAME: { i32, { float, float } } [[A:%.*]], { float, float } [[B:%.*]]) {183; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4184; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4185; CHECK-NEXT: [[TMP3:%.*]] = load { i8, i8 }, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 4), align 2186; CHECK-NEXT: [[TMP4:%.*]] = load { i8, { i8, i8 } }, ptr @__dfsan_arg_tls, align 2187; CHECK-NEXT: [[TMP5:%.*]] = insertvalue { i8, { i8, i8 } } [[TMP4]], { i8, i8 } [[TMP3]], 1188; CHECK-NEXT: [[TMP6:%.*]] = extractvalue { i8, i8 } [[TMP3]], 0189; CHECK-NEXT: [[TMP7:%.*]] = extractvalue { i8, i8 } [[TMP3]], 1190; CHECK-NEXT: [[TMP8:%.*]] = or i8 [[TMP6]], [[TMP7]]191; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i8 [[TMP8]], 0192; CHECK-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], i32 [[TMP1]], i32 [[TMP2]]193; CHECK-NEXT: [[E:%.*]] = insertvalue { i32, { float, float } } [[A]], { float, float } [[B]], 1194; CHECK-NEXT: store { i8, { i8, i8 } } [[TMP5]], ptr @__dfsan_retval_tls, align 2195; CHECK-NEXT: store i32 [[TMP10]], ptr @__dfsan_retval_origin_tls, align 4196; CHECK-NEXT: ret { i32, { float, float } } [[E]]197;198 %e = insertvalue {i32, {float, float}} %a, {float, float} %b, 1199 ret {i32, {float, float}} %e200}201