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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 62; RUN: opt < %s -passes=dfsan -dfsan-add-global-name-suffix=0 -S | FileCheck %s3target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"4target triple = "x86_64-unknown-linux-gnu"5 6define <4 x i4> @pass_vector(<4 x i4> %v) {7; CHECK-LABEL: define <4 x i4> @pass_vector(8; CHECK-SAME: <4 x i4> [[V:%.*]]) {9; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr @__dfsan_arg_tls, align 210; CHECK-NEXT: store i8 [[TMP1]], ptr @__dfsan_retval_tls, align 211; CHECK-NEXT: ret <4 x i4> [[V]]12;13 ret <4 x i4> %v14}15 16define void @load_update_store_vector(ptr %p) {17; CHECK-LABEL: define void @load_update_store_vector(18; CHECK-SAME: ptr [[P:%.*]]) {19; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr @__dfsan_arg_tls, align 220; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[P]] to i6421; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 8796093022208022; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr23; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[TMP4]], i64 124; CHECK-NEXT: [[TMP6:%.*]] = load i8, ptr [[TMP4]], align 125; CHECK-NEXT: [[TMP7:%.*]] = load i8, ptr [[TMP5]], align 126; CHECK-NEXT: [[TMP8:%.*]] = or i8 [[TMP6]], [[TMP7]]27; CHECK-NEXT: [[TMP9:%.*]] = or i8 [[TMP8]], [[TMP1]]28; CHECK-NEXT: [[V:%.*]] = load <4 x i4>, ptr [[P]], align 229; CHECK-NEXT: [[E2:%.*]] = extractelement <4 x i4> [[V]], i32 230; CHECK-NEXT: [[V1:%.*]] = insertelement <4 x i4> [[V]], i4 [[E2]], i32 031; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[P]] to i6432; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 8796093022208033; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr34; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[TMP12]], i32 035; CHECK-NEXT: store i8 [[TMP9]], ptr [[TMP13]], align 136; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[TMP12]], i32 137; CHECK-NEXT: store i8 [[TMP9]], ptr [[TMP14]], align 138; CHECK-NEXT: store <4 x i4> [[V1]], ptr [[P]], align 239; CHECK-NEXT: ret void40;41 %v = load <4 x i4>, ptr %p42 %e2 = extractelement <4 x i4> %v, i32 243 %v1 = insertelement <4 x i4> %v, i4 %e2, i32 044 store <4 x i4> %v1, ptr %p45 ret void46}47 48define <4 x i1> @icmp_vector(<4 x i8> %a, <4 x i8> %b) {49; CHECK-LABEL: define <4 x i1> @icmp_vector(50; CHECK-SAME: <4 x i8> [[A:%.*]], <4 x i8> [[B:%.*]]) {51; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 252; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr @__dfsan_arg_tls, align 253; CHECK-NEXT: [[TMP3:%.*]] = or i8 [[TMP2]], [[TMP1]]54; CHECK-NEXT: [[R:%.*]] = icmp eq <4 x i8> [[A]], [[B]]55; CHECK-NEXT: store i8 [[TMP3]], ptr @__dfsan_retval_tls, align 256; CHECK-NEXT: ret <4 x i1> [[R]]57;58 %r = icmp eq <4 x i8> %a, %b59 ret <4 x i1> %r60}61 62define <2 x i32> @const_vector() {63; CHECK-LABEL: define <2 x i32> @const_vector() {64; CHECK-NEXT: store i8 0, ptr @__dfsan_retval_tls, align 265; CHECK-NEXT: ret <2 x i32> <i32 42, i32 11>66;67 ret <2 x i32> < i32 42, i32 11 >68}69 70define <4 x i4> @call_vector(<4 x i4> %v) {71; CHECK-LABEL: define <4 x i4> @call_vector(72; CHECK-SAME: <4 x i4> [[V:%.*]]) {73; CHECK-NEXT: [[TMP1:%.*]] = load i8, ptr @__dfsan_arg_tls, align 274; CHECK-NEXT: store i8 [[TMP1]], ptr @__dfsan_arg_tls, align 275; CHECK-NEXT: [[R:%.*]] = call <4 x i4> @pass_vector(<4 x i4> [[V]])76; CHECK-NEXT: [[_DFSRET:%.*]] = load i8, ptr @__dfsan_retval_tls, align 277; CHECK-NEXT: store i8 [[_DFSRET]], ptr @__dfsan_retval_tls, align 278; CHECK-NEXT: ret <4 x i4> [[R]]79;80 %r = call <4 x i4> @pass_vector(<4 x i4> %v)81 ret <4 x i4> %r82}83