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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 22; Test that alloca instrumentation with old API levels does not use short granules.3;4; RUN: opt < %s -passes=hwasan -S | FileCheck %s5 6target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"7target triple = "aarch64--linux-android"8 9declare void @use32(ptr)10 11define void @test_alloca() sanitize_hwaddress {12; CHECK-LABEL: define void @test_alloca13; CHECK-SAME: () #[[ATTR0:[0-9]+]] {14; CHECK-NEXT: [[TMP1:%.*]] = call ptr @llvm.thread.pointer.p0()15; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 4816; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr [[TMP2]], align 817; CHECK-NEXT: [[TMP4:%.*]] = ashr i64 [[TMP3]], 318; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.read_register.i64(metadata [[META1:![0-9]+]])19; CHECK-NEXT: [[TMP6:%.*]] = call ptr @llvm.frameaddress.p0(i32 0)20; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[TMP6]] to i6421; CHECK-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 4422; CHECK-NEXT: [[TMP9:%.*]] = or i64 [[TMP5]], [[TMP8]]23; CHECK-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP3]] to ptr24; CHECK-NEXT: store i64 [[TMP9]], ptr [[TMP10]], align 825; CHECK-NEXT: [[TMP11:%.*]] = ashr i64 [[TMP3]], 5626; CHECK-NEXT: [[TMP12:%.*]] = shl nuw nsw i64 [[TMP11]], 1227; CHECK-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], -128; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 829; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], [[TMP13]]30; CHECK-NEXT: store i64 [[TMP15]], ptr [[TMP2]], align 831; CHECK-NEXT: [[TMP16:%.*]] = or i64 [[TMP3]], 429496729532; CHECK-NEXT: [[HWASAN_SHADOW:%.*]] = add i64 [[TMP16]], 133; CHECK-NEXT: [[TMP17:%.*]] = inttoptr i64 [[HWASAN_SHADOW]] to ptr34; CHECK-NEXT: [[HWASAN_UAR_TAG:%.*]] = lshr i64 [[TMP7]], 5635; CHECK-NEXT: [[X:%.*]] = alloca { i32, [12 x i8] }, align 1636; CHECK-NEXT: [[TMP18:%.*]] = xor i64 [[TMP4]], 037; CHECK-NEXT: [[TMP19:%.*]] = ptrtoint ptr [[X]] to i6438; CHECK-NEXT: [[TMP20:%.*]] = and i64 [[TMP19]], 7205759403792793539; CHECK-NEXT: [[TMP21:%.*]] = shl i64 [[TMP18]], 5640; CHECK-NEXT: [[TMP22:%.*]] = or i64 [[TMP20]], [[TMP21]]41; CHECK-NEXT: [[X_HWASAN:%.*]] = inttoptr i64 [[TMP22]] to ptr42; CHECK-NEXT: [[TMP23:%.*]] = trunc i64 [[TMP18]] to i843; CHECK-NEXT: [[TMP24:%.*]] = ptrtoint ptr [[X]] to i6444; CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], 7205759403792793545; CHECK-NEXT: [[TMP26:%.*]] = lshr i64 [[TMP25]], 446; CHECK-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP26]]47; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP27]], i8 [[TMP23]], i64 1, i1 false)48; CHECK-NEXT: call void @use32(ptr nonnull [[X_HWASAN]])49; CHECK-NEXT: [[TMP28:%.*]] = trunc i64 [[HWASAN_UAR_TAG]] to i850; CHECK-NEXT: [[TMP29:%.*]] = ptrtoint ptr [[X]] to i6451; CHECK-NEXT: [[TMP30:%.*]] = and i64 [[TMP29]], 7205759403792793552; CHECK-NEXT: [[TMP31:%.*]] = lshr i64 [[TMP30]], 453; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i8, ptr [[TMP17]], i64 [[TMP31]]54; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP32]], i8 [[TMP28]], i64 1, i1 false)55; CHECK-NEXT: ret void56;57 %x = alloca i32, align 458 call void @use32(ptr nonnull %x)59 ret void60}61