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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: opt < %s -passes=msan -S | FileCheck %s3;4; Suboptimally handled by visitInstruction: llvm.aarch64.neon.5; - fcvtas, fcvtau6; - fcvtms, fcvtmu7; - fcvtns, fcvtnu8; - fcvtps, fcvtpu9; - fcvtzs, fcvtzu10;11; Forked from llvm/test/CodeGen/AArch64/arm64-cvt.ll12 13target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"14target triple = "aarch64--linux-android9001"15 16define i32 @fcvtas_1w1s(float %A) nounwind #0 {17; CHECK-LABEL: define i32 @fcvtas_1w1s(18; CHECK-SAME: float [[A:%.*]]) #[[ATTR0:[0-9]+]] {19; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 820; CHECK-NEXT: call void @llvm.donothing()21; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 022; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i3223; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.aarch64.neon.fcvtas.i32.f32(float [[A]])24; CHECK-NEXT: store i32 [[TMP4]], ptr @__msan_retval_tls, align 825; CHECK-NEXT: ret i32 [[TMP3]]26;27 %tmpvar3 = call i32 @llvm.aarch64.neon.fcvtas.i32.f32(float %A)28 ret i32 %tmpvar329}30 31define i64 @fcvtas_1x1s(float %A) nounwind #0 {32; CHECK-LABEL: define i64 @fcvtas_1x1s(33; CHECK-SAME: float [[A:%.*]]) #[[ATTR0]] {34; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 835; CHECK-NEXT: call void @llvm.donothing()36; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 037; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i6438; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.fcvtas.i64.f32(float [[A]])39; CHECK-NEXT: store i64 [[TMP4]], ptr @__msan_retval_tls, align 840; CHECK-NEXT: ret i64 [[TMP3]]41;42 %tmpvar3 = call i64 @llvm.aarch64.neon.fcvtas.i64.f32(float %A)43 ret i64 %tmpvar344}45 46define i32 @fcvtas_1w1d(double %A) nounwind #0 {47; CHECK-LABEL: define i32 @fcvtas_1w1d(48; CHECK-SAME: double [[A:%.*]]) #[[ATTR0]] {49; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 850; CHECK-NEXT: call void @llvm.donothing()51; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 052; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i3253; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.aarch64.neon.fcvtas.i32.f64(double [[A]])54; CHECK-NEXT: store i32 [[TMP4]], ptr @__msan_retval_tls, align 855; CHECK-NEXT: ret i32 [[TMP3]]56;57 %tmpvar3 = call i32 @llvm.aarch64.neon.fcvtas.i32.f64(double %A)58 ret i32 %tmpvar359}60 61define i64 @fcvtas_1x1d(double %A) nounwind #0 {62; CHECK-LABEL: define i64 @fcvtas_1x1d(63; CHECK-SAME: double [[A:%.*]]) #[[ATTR0]] {64; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 865; CHECK-NEXT: call void @llvm.donothing()66; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 067; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i6468; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.fcvtas.i64.f64(double [[A]])69; CHECK-NEXT: store i64 [[TMP4]], ptr @__msan_retval_tls, align 870; CHECK-NEXT: ret i64 [[TMP3]]71;72 %tmpvar3 = call i64 @llvm.aarch64.neon.fcvtas.i64.f64(double %A)73 ret i64 %tmpvar374}75 76declare i32 @llvm.aarch64.neon.fcvtas.i32.f32(float) nounwind readnone77declare i64 @llvm.aarch64.neon.fcvtas.i64.f32(float) nounwind readnone78declare i32 @llvm.aarch64.neon.fcvtas.i32.f64(double) nounwind readnone79declare i64 @llvm.aarch64.neon.fcvtas.i64.f64(double) nounwind readnone80 81define i32 @fcvtau_1w1s(float %A) nounwind #0 {82; CHECK-LABEL: define i32 @fcvtau_1w1s(83; CHECK-SAME: float [[A:%.*]]) #[[ATTR0]] {84; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 885; CHECK-NEXT: call void @llvm.donothing()86; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 087; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i3288; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.aarch64.neon.fcvtau.i32.f32(float [[A]])89; CHECK-NEXT: store i32 [[TMP4]], ptr @__msan_retval_tls, align 890; CHECK-NEXT: ret i32 [[TMP3]]91;92 %tmpvar3 = call i32 @llvm.aarch64.neon.fcvtau.i32.f32(float %A)93 ret i32 %tmpvar394}95 96define i64 @fcvtau_1x1s(float %A) nounwind #0 {97; CHECK-LABEL: define i64 @fcvtau_1x1s(98; CHECK-SAME: float [[A:%.*]]) #[[ATTR0]] {99; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8100; CHECK-NEXT: call void @llvm.donothing()101; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0102; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i64103; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.fcvtau.i64.f32(float [[A]])104; CHECK-NEXT: store i64 [[TMP4]], ptr @__msan_retval_tls, align 8105; CHECK-NEXT: ret i64 [[TMP3]]106;107 %tmpvar3 = call i64 @llvm.aarch64.neon.fcvtau.i64.f32(float %A)108 ret i64 %tmpvar3109}110 111define i32 @fcvtau_1w1d(double %A) nounwind #0 {112; CHECK-LABEL: define i32 @fcvtau_1w1d(113; CHECK-SAME: double [[A:%.*]]) #[[ATTR0]] {114; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8115; CHECK-NEXT: call void @llvm.donothing()116; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0117; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i32118; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.aarch64.neon.fcvtau.i32.f64(double [[A]])119; CHECK-NEXT: store i32 [[TMP4]], ptr @__msan_retval_tls, align 8120; CHECK-NEXT: ret i32 [[TMP3]]121;122 %tmpvar3 = call i32 @llvm.aarch64.neon.fcvtau.i32.f64(double %A)123 ret i32 %tmpvar3124}125 126define i64 @fcvtau_1x1d(double %A) nounwind #0 {127; CHECK-LABEL: define i64 @fcvtau_1x1d(128; CHECK-SAME: double [[A:%.*]]) #[[ATTR0]] {129; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8130; CHECK-NEXT: call void @llvm.donothing()131; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0132; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i64133; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.fcvtau.i64.f64(double [[A]])134; CHECK-NEXT: store i64 [[TMP4]], ptr @__msan_retval_tls, align 8135; CHECK-NEXT: ret i64 [[TMP3]]136;137 %tmpvar3 = call i64 @llvm.aarch64.neon.fcvtau.i64.f64(double %A)138 ret i64 %tmpvar3139}140 141declare i32 @llvm.aarch64.neon.fcvtau.i32.f32(float) nounwind readnone142declare i64 @llvm.aarch64.neon.fcvtau.i64.f32(float) nounwind readnone143declare i32 @llvm.aarch64.neon.fcvtau.i32.f64(double) nounwind readnone144declare i64 @llvm.aarch64.neon.fcvtau.i64.f64(double) nounwind readnone145 146define i32 @fcvtms_1w1s(float %A) nounwind #0 {147; CHECK-LABEL: define i32 @fcvtms_1w1s(148; CHECK-SAME: float [[A:%.*]]) #[[ATTR0]] {149; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8150; CHECK-NEXT: call void @llvm.donothing()151; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0152; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i32153; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.aarch64.neon.fcvtms.i32.f32(float [[A]])154; CHECK-NEXT: store i32 [[TMP4]], ptr @__msan_retval_tls, align 8155; CHECK-NEXT: ret i32 [[TMP3]]156;157 %tmpvar3 = call i32 @llvm.aarch64.neon.fcvtms.i32.f32(float %A)158 ret i32 %tmpvar3159}160 161define i64 @fcvtms_1x1s(float %A) nounwind #0 {162; CHECK-LABEL: define i64 @fcvtms_1x1s(163; CHECK-SAME: float [[A:%.*]]) #[[ATTR0]] {164; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8165; CHECK-NEXT: call void @llvm.donothing()166; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0167; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i64168; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.fcvtms.i64.f32(float [[A]])169; CHECK-NEXT: store i64 [[TMP4]], ptr @__msan_retval_tls, align 8170; CHECK-NEXT: ret i64 [[TMP3]]171;172 %tmpvar3 = call i64 @llvm.aarch64.neon.fcvtms.i64.f32(float %A)173 ret i64 %tmpvar3174}175 176define i32 @fcvtms_1w1d(double %A) nounwind #0 {177; CHECK-LABEL: define i32 @fcvtms_1w1d(178; CHECK-SAME: double [[A:%.*]]) #[[ATTR0]] {179; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8180; CHECK-NEXT: call void @llvm.donothing()181; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0182; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i32183; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.aarch64.neon.fcvtms.i32.f64(double [[A]])184; CHECK-NEXT: store i32 [[TMP4]], ptr @__msan_retval_tls, align 8185; CHECK-NEXT: ret i32 [[TMP3]]186;187 %tmpvar3 = call i32 @llvm.aarch64.neon.fcvtms.i32.f64(double %A)188 ret i32 %tmpvar3189}190 191define i64 @fcvtms_1x1d(double %A) nounwind #0 {192; CHECK-LABEL: define i64 @fcvtms_1x1d(193; CHECK-SAME: double [[A:%.*]]) #[[ATTR0]] {194; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8195; CHECK-NEXT: call void @llvm.donothing()196; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0197; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i64198; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.fcvtms.i64.f64(double [[A]])199; CHECK-NEXT: store i64 [[TMP4]], ptr @__msan_retval_tls, align 8200; CHECK-NEXT: ret i64 [[TMP3]]201;202 %tmpvar3 = call i64 @llvm.aarch64.neon.fcvtms.i64.f64(double %A)203 ret i64 %tmpvar3204}205 206declare i32 @llvm.aarch64.neon.fcvtms.i32.f32(float) nounwind readnone207declare i64 @llvm.aarch64.neon.fcvtms.i64.f32(float) nounwind readnone208declare i32 @llvm.aarch64.neon.fcvtms.i32.f64(double) nounwind readnone209declare i64 @llvm.aarch64.neon.fcvtms.i64.f64(double) nounwind readnone210 211define i32 @fcvtmu_1w1s(float %A) nounwind #0 {212; CHECK-LABEL: define i32 @fcvtmu_1w1s(213; CHECK-SAME: float [[A:%.*]]) #[[ATTR0]] {214; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8215; CHECK-NEXT: call void @llvm.donothing()216; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0217; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i32218; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.aarch64.neon.fcvtmu.i32.f32(float [[A]])219; CHECK-NEXT: store i32 [[TMP4]], ptr @__msan_retval_tls, align 8220; CHECK-NEXT: ret i32 [[TMP3]]221;222 %tmpvar3 = call i32 @llvm.aarch64.neon.fcvtmu.i32.f32(float %A)223 ret i32 %tmpvar3224}225 226define i64 @fcvtmu_1x1s(float %A) nounwind #0 {227; CHECK-LABEL: define i64 @fcvtmu_1x1s(228; CHECK-SAME: float [[A:%.*]]) #[[ATTR0]] {229; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8230; CHECK-NEXT: call void @llvm.donothing()231; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0232; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i64233; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.fcvtmu.i64.f32(float [[A]])234; CHECK-NEXT: store i64 [[TMP4]], ptr @__msan_retval_tls, align 8235; CHECK-NEXT: ret i64 [[TMP3]]236;237 %tmpvar3 = call i64 @llvm.aarch64.neon.fcvtmu.i64.f32(float %A)238 ret i64 %tmpvar3239}240 241define i32 @fcvtmu_1w1d(double %A) nounwind #0 {242; CHECK-LABEL: define i32 @fcvtmu_1w1d(243; CHECK-SAME: double [[A:%.*]]) #[[ATTR0]] {244; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8245; CHECK-NEXT: call void @llvm.donothing()246; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0247; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i32248; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.aarch64.neon.fcvtmu.i32.f64(double [[A]])249; CHECK-NEXT: store i32 [[TMP4]], ptr @__msan_retval_tls, align 8250; CHECK-NEXT: ret i32 [[TMP3]]251;252 %tmpvar3 = call i32 @llvm.aarch64.neon.fcvtmu.i32.f64(double %A)253 ret i32 %tmpvar3254}255 256define i64 @fcvtmu_1x1d(double %A) nounwind #0 {257; CHECK-LABEL: define i64 @fcvtmu_1x1d(258; CHECK-SAME: double [[A:%.*]]) #[[ATTR0]] {259; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8260; CHECK-NEXT: call void @llvm.donothing()261; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0262; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i64263; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.fcvtmu.i64.f64(double [[A]])264; CHECK-NEXT: store i64 [[TMP4]], ptr @__msan_retval_tls, align 8265; CHECK-NEXT: ret i64 [[TMP3]]266;267 %tmpvar3 = call i64 @llvm.aarch64.neon.fcvtmu.i64.f64(double %A)268 ret i64 %tmpvar3269}270 271declare i32 @llvm.aarch64.neon.fcvtmu.i32.f32(float) nounwind readnone272declare i64 @llvm.aarch64.neon.fcvtmu.i64.f32(float) nounwind readnone273declare i32 @llvm.aarch64.neon.fcvtmu.i32.f64(double) nounwind readnone274declare i64 @llvm.aarch64.neon.fcvtmu.i64.f64(double) nounwind readnone275 276define i32 @fcvtns_1w1s(float %A) nounwind #0 {277; CHECK-LABEL: define i32 @fcvtns_1w1s(278; CHECK-SAME: float [[A:%.*]]) #[[ATTR0]] {279; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8280; CHECK-NEXT: call void @llvm.donothing()281; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0282; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i32283; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.aarch64.neon.fcvtns.i32.f32(float [[A]])284; CHECK-NEXT: store i32 [[TMP4]], ptr @__msan_retval_tls, align 8285; CHECK-NEXT: ret i32 [[TMP3]]286;287 %tmpvar3 = call i32 @llvm.aarch64.neon.fcvtns.i32.f32(float %A)288 ret i32 %tmpvar3289}290 291define i64 @fcvtns_1x1s(float %A) nounwind #0 {292; CHECK-LABEL: define i64 @fcvtns_1x1s(293; CHECK-SAME: float [[A:%.*]]) #[[ATTR0]] {294; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8295; CHECK-NEXT: call void @llvm.donothing()296; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0297; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i64298; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.fcvtns.i64.f32(float [[A]])299; CHECK-NEXT: store i64 [[TMP4]], ptr @__msan_retval_tls, align 8300; CHECK-NEXT: ret i64 [[TMP3]]301;302 %tmpvar3 = call i64 @llvm.aarch64.neon.fcvtns.i64.f32(float %A)303 ret i64 %tmpvar3304}305 306define i32 @fcvtns_1w1d(double %A) nounwind #0 {307; CHECK-LABEL: define i32 @fcvtns_1w1d(308; CHECK-SAME: double [[A:%.*]]) #[[ATTR0]] {309; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8310; CHECK-NEXT: call void @llvm.donothing()311; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0312; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i32313; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.aarch64.neon.fcvtns.i32.f64(double [[A]])314; CHECK-NEXT: store i32 [[TMP4]], ptr @__msan_retval_tls, align 8315; CHECK-NEXT: ret i32 [[TMP3]]316;317 %tmpvar3 = call i32 @llvm.aarch64.neon.fcvtns.i32.f64(double %A)318 ret i32 %tmpvar3319}320 321define i64 @fcvtns_1x1d(double %A) nounwind #0 {322; CHECK-LABEL: define i64 @fcvtns_1x1d(323; CHECK-SAME: double [[A:%.*]]) #[[ATTR0]] {324; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8325; CHECK-NEXT: call void @llvm.donothing()326; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0327; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i64328; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.fcvtns.i64.f64(double [[A]])329; CHECK-NEXT: store i64 [[TMP4]], ptr @__msan_retval_tls, align 8330; CHECK-NEXT: ret i64 [[TMP3]]331;332 %tmpvar3 = call i64 @llvm.aarch64.neon.fcvtns.i64.f64(double %A)333 ret i64 %tmpvar3334}335 336declare i32 @llvm.aarch64.neon.fcvtns.i32.f32(float) nounwind readnone337declare i64 @llvm.aarch64.neon.fcvtns.i64.f32(float) nounwind readnone338declare i32 @llvm.aarch64.neon.fcvtns.i32.f64(double) nounwind readnone339declare i64 @llvm.aarch64.neon.fcvtns.i64.f64(double) nounwind readnone340 341define i32 @fcvtnu_1w1s(float %A) nounwind #0 {342; CHECK-LABEL: define i32 @fcvtnu_1w1s(343; CHECK-SAME: float [[A:%.*]]) #[[ATTR0]] {344; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8345; CHECK-NEXT: call void @llvm.donothing()346; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0347; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i32348; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.aarch64.neon.fcvtnu.i32.f32(float [[A]])349; CHECK-NEXT: store i32 [[TMP4]], ptr @__msan_retval_tls, align 8350; CHECK-NEXT: ret i32 [[TMP3]]351;352 %tmpvar3 = call i32 @llvm.aarch64.neon.fcvtnu.i32.f32(float %A)353 ret i32 %tmpvar3354}355 356define i64 @fcvtnu_1x1s(float %A) nounwind #0 {357; CHECK-LABEL: define i64 @fcvtnu_1x1s(358; CHECK-SAME: float [[A:%.*]]) #[[ATTR0]] {359; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8360; CHECK-NEXT: call void @llvm.donothing()361; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0362; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i64363; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.fcvtnu.i64.f32(float [[A]])364; CHECK-NEXT: store i64 [[TMP4]], ptr @__msan_retval_tls, align 8365; CHECK-NEXT: ret i64 [[TMP3]]366;367 %tmpvar3 = call i64 @llvm.aarch64.neon.fcvtnu.i64.f32(float %A)368 ret i64 %tmpvar3369}370 371define i32 @fcvtnu_1w1d(double %A) nounwind #0 {372; CHECK-LABEL: define i32 @fcvtnu_1w1d(373; CHECK-SAME: double [[A:%.*]]) #[[ATTR0]] {374; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8375; CHECK-NEXT: call void @llvm.donothing()376; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0377; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i32378; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.aarch64.neon.fcvtnu.i32.f64(double [[A]])379; CHECK-NEXT: store i32 [[TMP4]], ptr @__msan_retval_tls, align 8380; CHECK-NEXT: ret i32 [[TMP3]]381;382 %tmpvar3 = call i32 @llvm.aarch64.neon.fcvtnu.i32.f64(double %A)383 ret i32 %tmpvar3384}385 386define i64 @fcvtnu_1x1d(double %A) nounwind #0 {387; CHECK-LABEL: define i64 @fcvtnu_1x1d(388; CHECK-SAME: double [[A:%.*]]) #[[ATTR0]] {389; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8390; CHECK-NEXT: call void @llvm.donothing()391; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0392; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i64393; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.fcvtnu.i64.f64(double [[A]])394; CHECK-NEXT: store i64 [[TMP4]], ptr @__msan_retval_tls, align 8395; CHECK-NEXT: ret i64 [[TMP3]]396;397 %tmpvar3 = call i64 @llvm.aarch64.neon.fcvtnu.i64.f64(double %A)398 ret i64 %tmpvar3399}400 401declare i32 @llvm.aarch64.neon.fcvtnu.i32.f32(float) nounwind readnone402declare i64 @llvm.aarch64.neon.fcvtnu.i64.f32(float) nounwind readnone403declare i32 @llvm.aarch64.neon.fcvtnu.i32.f64(double) nounwind readnone404declare i64 @llvm.aarch64.neon.fcvtnu.i64.f64(double) nounwind readnone405 406define i32 @fcvtps_1w1s(float %A) nounwind #0 {407; CHECK-LABEL: define i32 @fcvtps_1w1s(408; CHECK-SAME: float [[A:%.*]]) #[[ATTR0]] {409; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8410; CHECK-NEXT: call void @llvm.donothing()411; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0412; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i32413; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.aarch64.neon.fcvtps.i32.f32(float [[A]])414; CHECK-NEXT: store i32 [[TMP4]], ptr @__msan_retval_tls, align 8415; CHECK-NEXT: ret i32 [[TMP3]]416;417 %tmpvar3 = call i32 @llvm.aarch64.neon.fcvtps.i32.f32(float %A)418 ret i32 %tmpvar3419}420 421define i64 @fcvtps_1x1s(float %A) nounwind #0 {422; CHECK-LABEL: define i64 @fcvtps_1x1s(423; CHECK-SAME: float [[A:%.*]]) #[[ATTR0]] {424; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8425; CHECK-NEXT: call void @llvm.donothing()426; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0427; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i64428; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.fcvtps.i64.f32(float [[A]])429; CHECK-NEXT: store i64 [[TMP4]], ptr @__msan_retval_tls, align 8430; CHECK-NEXT: ret i64 [[TMP3]]431;432 %tmpvar3 = call i64 @llvm.aarch64.neon.fcvtps.i64.f32(float %A)433 ret i64 %tmpvar3434}435 436define i32 @fcvtps_1w1d(double %A) nounwind #0 {437; CHECK-LABEL: define i32 @fcvtps_1w1d(438; CHECK-SAME: double [[A:%.*]]) #[[ATTR0]] {439; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8440; CHECK-NEXT: call void @llvm.donothing()441; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0442; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i32443; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.aarch64.neon.fcvtps.i32.f64(double [[A]])444; CHECK-NEXT: store i32 [[TMP4]], ptr @__msan_retval_tls, align 8445; CHECK-NEXT: ret i32 [[TMP3]]446;447 %tmpvar3 = call i32 @llvm.aarch64.neon.fcvtps.i32.f64(double %A)448 ret i32 %tmpvar3449}450 451define i64 @fcvtps_1x1d(double %A) nounwind #0 {452; CHECK-LABEL: define i64 @fcvtps_1x1d(453; CHECK-SAME: double [[A:%.*]]) #[[ATTR0]] {454; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8455; CHECK-NEXT: call void @llvm.donothing()456; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0457; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i64458; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.fcvtps.i64.f64(double [[A]])459; CHECK-NEXT: store i64 [[TMP4]], ptr @__msan_retval_tls, align 8460; CHECK-NEXT: ret i64 [[TMP3]]461;462 %tmpvar3 = call i64 @llvm.aarch64.neon.fcvtps.i64.f64(double %A)463 ret i64 %tmpvar3464}465 466declare i32 @llvm.aarch64.neon.fcvtps.i32.f32(float) nounwind readnone467declare i64 @llvm.aarch64.neon.fcvtps.i64.f32(float) nounwind readnone468declare i32 @llvm.aarch64.neon.fcvtps.i32.f64(double) nounwind readnone469declare i64 @llvm.aarch64.neon.fcvtps.i64.f64(double) nounwind readnone470 471define i32 @fcvtpu_1w1s(float %A) nounwind #0 {472; CHECK-LABEL: define i32 @fcvtpu_1w1s(473; CHECK-SAME: float [[A:%.*]]) #[[ATTR0]] {474; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8475; CHECK-NEXT: call void @llvm.donothing()476; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0477; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i32478; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.aarch64.neon.fcvtpu.i32.f32(float [[A]])479; CHECK-NEXT: store i32 [[TMP4]], ptr @__msan_retval_tls, align 8480; CHECK-NEXT: ret i32 [[TMP3]]481;482 %tmpvar3 = call i32 @llvm.aarch64.neon.fcvtpu.i32.f32(float %A)483 ret i32 %tmpvar3484}485 486define i64 @fcvtpu_1x1s(float %A) nounwind #0 {487; CHECK-LABEL: define i64 @fcvtpu_1x1s(488; CHECK-SAME: float [[A:%.*]]) #[[ATTR0]] {489; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8490; CHECK-NEXT: call void @llvm.donothing()491; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0492; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i64493; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.fcvtpu.i64.f32(float [[A]])494; CHECK-NEXT: store i64 [[TMP4]], ptr @__msan_retval_tls, align 8495; CHECK-NEXT: ret i64 [[TMP3]]496;497 %tmpvar3 = call i64 @llvm.aarch64.neon.fcvtpu.i64.f32(float %A)498 ret i64 %tmpvar3499}500 501define i32 @fcvtpu_1w1d(double %A) nounwind #0 {502; CHECK-LABEL: define i32 @fcvtpu_1w1d(503; CHECK-SAME: double [[A:%.*]]) #[[ATTR0]] {504; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8505; CHECK-NEXT: call void @llvm.donothing()506; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0507; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i32508; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.aarch64.neon.fcvtpu.i32.f64(double [[A]])509; CHECK-NEXT: store i32 [[TMP4]], ptr @__msan_retval_tls, align 8510; CHECK-NEXT: ret i32 [[TMP3]]511;512 %tmpvar3 = call i32 @llvm.aarch64.neon.fcvtpu.i32.f64(double %A)513 ret i32 %tmpvar3514}515 516define i64 @fcvtpu_1x1d(double %A) nounwind #0 {517; CHECK-LABEL: define i64 @fcvtpu_1x1d(518; CHECK-SAME: double [[A:%.*]]) #[[ATTR0]] {519; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8520; CHECK-NEXT: call void @llvm.donothing()521; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0522; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i64523; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.fcvtpu.i64.f64(double [[A]])524; CHECK-NEXT: store i64 [[TMP4]], ptr @__msan_retval_tls, align 8525; CHECK-NEXT: ret i64 [[TMP3]]526;527 %tmpvar3 = call i64 @llvm.aarch64.neon.fcvtpu.i64.f64(double %A)528 ret i64 %tmpvar3529}530 531declare i32 @llvm.aarch64.neon.fcvtpu.i32.f32(float) nounwind readnone532declare i64 @llvm.aarch64.neon.fcvtpu.i64.f32(float) nounwind readnone533declare i32 @llvm.aarch64.neon.fcvtpu.i32.f64(double) nounwind readnone534declare i64 @llvm.aarch64.neon.fcvtpu.i64.f64(double) nounwind readnone535 536define i32 @fcvtzs_1w1s(float %A) nounwind #0 {537; CHECK-LABEL: define i32 @fcvtzs_1w1s(538; CHECK-SAME: float [[A:%.*]]) #[[ATTR0]] {539; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8540; CHECK-NEXT: call void @llvm.donothing()541; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0542; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i32543; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float [[A]])544; CHECK-NEXT: store i32 [[TMP4]], ptr @__msan_retval_tls, align 8545; CHECK-NEXT: ret i32 [[TMP3]]546;547 %tmpvar3 = call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %A)548 ret i32 %tmpvar3549}550 551define i64 @fcvtzs_1x1s(float %A) nounwind #0 {552; CHECK-LABEL: define i64 @fcvtzs_1x1s(553; CHECK-SAME: float [[A:%.*]]) #[[ATTR0]] {554; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8555; CHECK-NEXT: call void @llvm.donothing()556; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0557; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i64558; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.fcvtzs.i64.f32(float [[A]])559; CHECK-NEXT: store i64 [[TMP4]], ptr @__msan_retval_tls, align 8560; CHECK-NEXT: ret i64 [[TMP3]]561;562 %tmpvar3 = call i64 @llvm.aarch64.neon.fcvtzs.i64.f32(float %A)563 ret i64 %tmpvar3564}565 566define i32 @fcvtzs_1w1d(double %A) nounwind #0 {567; CHECK-LABEL: define i32 @fcvtzs_1w1d(568; CHECK-SAME: double [[A:%.*]]) #[[ATTR0]] {569; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8570; CHECK-NEXT: call void @llvm.donothing()571; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0572; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i32573; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.aarch64.neon.fcvtzs.i32.f64(double [[A]])574; CHECK-NEXT: store i32 [[TMP4]], ptr @__msan_retval_tls, align 8575; CHECK-NEXT: ret i32 [[TMP3]]576;577 %tmpvar3 = call i32 @llvm.aarch64.neon.fcvtzs.i32.f64(double %A)578 ret i32 %tmpvar3579}580 581define i64 @fcvtzs_1x1d(double %A) nounwind #0 {582; CHECK-LABEL: define i64 @fcvtzs_1x1d(583; CHECK-SAME: double [[A:%.*]]) #[[ATTR0]] {584; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8585; CHECK-NEXT: call void @llvm.donothing()586; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0587; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i64588; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.fcvtzs.i64.f64(double [[A]])589; CHECK-NEXT: store i64 [[TMP4]], ptr @__msan_retval_tls, align 8590; CHECK-NEXT: ret i64 [[TMP3]]591;592 %tmpvar3 = call i64 @llvm.aarch64.neon.fcvtzs.i64.f64(double %A)593 ret i64 %tmpvar3594}595 596declare i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float) nounwind readnone597declare i64 @llvm.aarch64.neon.fcvtzs.i64.f32(float) nounwind readnone598declare i32 @llvm.aarch64.neon.fcvtzs.i32.f64(double) nounwind readnone599declare i64 @llvm.aarch64.neon.fcvtzs.i64.f64(double) nounwind readnone600 601define i32 @fcvtzu_1w1s(float %A) nounwind #0 {602; CHECK-LABEL: define i32 @fcvtzu_1w1s(603; CHECK-SAME: float [[A:%.*]]) #[[ATTR0]] {604; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8605; CHECK-NEXT: call void @llvm.donothing()606; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0607; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i32608; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.aarch64.neon.fcvtzu.i32.f32(float [[A]])609; CHECK-NEXT: store i32 [[TMP4]], ptr @__msan_retval_tls, align 8610; CHECK-NEXT: ret i32 [[TMP3]]611;612 %tmpvar3 = call i32 @llvm.aarch64.neon.fcvtzu.i32.f32(float %A)613 ret i32 %tmpvar3614}615 616define i64 @fcvtzu_1x1s(float %A) nounwind #0 {617; CHECK-LABEL: define i64 @fcvtzu_1x1s(618; CHECK-SAME: float [[A:%.*]]) #[[ATTR0]] {619; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 8620; CHECK-NEXT: call void @llvm.donothing()621; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 0622; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i64623; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.fcvtzu.i64.f32(float [[A]])624; CHECK-NEXT: store i64 [[TMP4]], ptr @__msan_retval_tls, align 8625; CHECK-NEXT: ret i64 [[TMP3]]626;627 %tmpvar3 = call i64 @llvm.aarch64.neon.fcvtzu.i64.f32(float %A)628 ret i64 %tmpvar3629}630 631define i32 @fcvtzu_1w1d(double %A) nounwind #0 {632; CHECK-LABEL: define i32 @fcvtzu_1w1d(633; CHECK-SAME: double [[A:%.*]]) #[[ATTR0]] {634; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8635; CHECK-NEXT: call void @llvm.donothing()636; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0637; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i32638; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.aarch64.neon.fcvtzu.i32.f64(double [[A]])639; CHECK-NEXT: store i32 [[TMP4]], ptr @__msan_retval_tls, align 8640; CHECK-NEXT: ret i32 [[TMP3]]641;642 %tmpvar3 = call i32 @llvm.aarch64.neon.fcvtzu.i32.f64(double %A)643 ret i32 %tmpvar3644}645 646define i64 @fcvtzu_1x1d(double %A) nounwind #0 {647; CHECK-LABEL: define i64 @fcvtzu_1x1d(648; CHECK-SAME: double [[A:%.*]]) #[[ATTR0]] {649; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8650; CHECK-NEXT: call void @llvm.donothing()651; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0652; CHECK-NEXT: [[TMP4:%.*]] = sext i1 [[_MSCMP]] to i64653; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.fcvtzu.i64.f64(double [[A]])654; CHECK-NEXT: store i64 [[TMP4]], ptr @__msan_retval_tls, align 8655; CHECK-NEXT: ret i64 [[TMP3]]656;657 %tmpvar3 = call i64 @llvm.aarch64.neon.fcvtzu.i64.f64(double %A)658 ret i64 %tmpvar3659}660 661declare i32 @llvm.aarch64.neon.fcvtzu.i32.f32(float) nounwind readnone662declare i64 @llvm.aarch64.neon.fcvtzu.i64.f32(float) nounwind readnone663declare i32 @llvm.aarch64.neon.fcvtzu.i32.f64(double) nounwind readnone664declare i64 @llvm.aarch64.neon.fcvtzu.i64.f64(double) nounwind readnone665 666attributes #0 = { sanitize_memory }667