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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: opt < %s -passes=msan -S | FileCheck %s3;4; Forked from llvm/test/CodeGen/AArch64/arm64-fminv.ll5 6target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"7target triple = "aarch64--linux-android9001"8 9define float @test_fminv_v2f32(<2 x float> %in) #0 {10; CHECK-LABEL: define float @test_fminv_v2f32(11; CHECK-SAME: <2 x float> [[IN:%.*]]) #[[ATTR0:[0-9]+]] {12; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 813; CHECK-NEXT: call void @llvm.donothing()14; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> [[TMP1]])15; CHECK-NEXT: [[MIN:%.*]] = call float @llvm.aarch64.neon.fminv.f32.v2f32(<2 x float> [[IN]])16; CHECK-NEXT: store i32 [[TMP2]], ptr @__msan_retval_tls, align 817; CHECK-NEXT: ret float [[MIN]]18;19 %min = call float @llvm.aarch64.neon.fminv.f32.v2f32(<2 x float> %in)20 ret float %min21}22 23define float @test_fminv_v4f32(<4 x float> %in) #0 {24; CHECK-LABEL: define float @test_fminv_v4f32(25; CHECK-SAME: <4 x float> [[IN:%.*]]) #[[ATTR0]] {26; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 827; CHECK-NEXT: call void @llvm.donothing()28; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP1]])29; CHECK-NEXT: [[MIN:%.*]] = call float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float> [[IN]])30; CHECK-NEXT: store i32 [[TMP2]], ptr @__msan_retval_tls, align 831; CHECK-NEXT: ret float [[MIN]]32;33 %min = call float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float> %in)34 ret float %min35}36 37define double @test_fminv_v2f64(<2 x double> %in) #0 {38; CHECK-LABEL: define double @test_fminv_v2f64(39; CHECK-SAME: <2 x double> [[IN:%.*]]) #[[ATTR0]] {40; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 841; CHECK-NEXT: call void @llvm.donothing()42; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> [[TMP1]])43; CHECK-NEXT: [[MIN:%.*]] = call double @llvm.aarch64.neon.fminv.f64.v2f64(<2 x double> [[IN]])44; CHECK-NEXT: store i64 [[TMP2]], ptr @__msan_retval_tls, align 845; CHECK-NEXT: ret double [[MIN]]46;47 %min = call double @llvm.aarch64.neon.fminv.f64.v2f64(<2 x double> %in)48 ret double %min49}50 51declare float @llvm.aarch64.neon.fminv.f32.v2f32(<2 x float>)52declare float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float>)53declare double @llvm.aarch64.neon.fminv.f64.v2f64(<2 x double>)54 55define float @test_fmaxv_v2f32(<2 x float> %in) #0 {56; CHECK-LABEL: define float @test_fmaxv_v2f32(57; CHECK-SAME: <2 x float> [[IN:%.*]]) #[[ATTR0]] {58; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 859; CHECK-NEXT: call void @llvm.donothing()60; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> [[TMP1]])61; CHECK-NEXT: [[MAX:%.*]] = call float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float> [[IN]])62; CHECK-NEXT: store i32 [[TMP2]], ptr @__msan_retval_tls, align 863; CHECK-NEXT: ret float [[MAX]]64;65 %max = call float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float> %in)66 ret float %max67}68 69define float @test_fmaxv_v4f32(<4 x float> %in) #0 {70; CHECK-LABEL: define float @test_fmaxv_v4f32(71; CHECK-SAME: <4 x float> [[IN:%.*]]) #[[ATTR0]] {72; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 873; CHECK-NEXT: call void @llvm.donothing()74; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP1]])75; CHECK-NEXT: [[MAX:%.*]] = call float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float> [[IN]])76; CHECK-NEXT: store i32 [[TMP2]], ptr @__msan_retval_tls, align 877; CHECK-NEXT: ret float [[MAX]]78;79 %max = call float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float> %in)80 ret float %max81}82 83define double @test_fmaxv_v2f64(<2 x double> %shareholder_value) #0 {84; CHECK-LABEL: define double @test_fmaxv_v2f64(85; CHECK-SAME: <2 x double> [[SHAREHOLDER_VALUE:%.*]]) #[[ATTR0]] {86; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 887; CHECK-NEXT: call void @llvm.donothing()88; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> [[TMP1]])89; CHECK-NEXT: [[MAX:%.*]] = call double @llvm.aarch64.neon.fmaxv.f64.v2f64(<2 x double> [[SHAREHOLDER_VALUE]])90; CHECK-NEXT: store i64 [[TMP2]], ptr @__msan_retval_tls, align 891; CHECK-NEXT: ret double [[MAX]]92;93 %max_sv = call double @llvm.aarch64.neon.fmaxv.f64.v2f64(<2 x double> %shareholder_value)94 ret double %max_sv95}96 97declare float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float>)98declare float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float>)99declare double @llvm.aarch64.neon.fmaxv.f64.v2f64(<2 x double>)100 101define float @test_fminnmv_v2f32(<2 x float> %in) #0 {102; CHECK-LABEL: define float @test_fminnmv_v2f32(103; CHECK-SAME: <2 x float> [[IN:%.*]]) #[[ATTR0]] {104; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8105; CHECK-NEXT: call void @llvm.donothing()106; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> [[TMP1]])107; CHECK-NEXT: [[MINNM:%.*]] = call float @llvm.aarch64.neon.fminnmv.f32.v2f32(<2 x float> [[IN]])108; CHECK-NEXT: store i32 [[TMP2]], ptr @__msan_retval_tls, align 8109; CHECK-NEXT: ret float [[MINNM]]110;111 %minnm = call float @llvm.aarch64.neon.fminnmv.f32.v2f32(<2 x float> %in)112 ret float %minnm113}114 115define float @test_fminnmv_v4f32(<4 x float> %in) #0 {116; CHECK-LABEL: define float @test_fminnmv_v4f32(117; CHECK-SAME: <4 x float> [[IN:%.*]]) #[[ATTR0]] {118; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8119; CHECK-NEXT: call void @llvm.donothing()120; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP1]])121; CHECK-NEXT: [[MINNM:%.*]] = call float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float> [[IN]])122; CHECK-NEXT: store i32 [[TMP2]], ptr @__msan_retval_tls, align 8123; CHECK-NEXT: ret float [[MINNM]]124;125 %minnm = call float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float> %in)126 ret float %minnm127}128 129define double @test_fminnmv_v2f64(<2 x double> %in) #0 {130; CHECK-LABEL: define double @test_fminnmv_v2f64(131; CHECK-SAME: <2 x double> [[IN:%.*]]) #[[ATTR0]] {132; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8133; CHECK-NEXT: call void @llvm.donothing()134; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> [[TMP1]])135; CHECK-NEXT: [[MINNM:%.*]] = call double @llvm.aarch64.neon.fminnmv.f64.v2f64(<2 x double> [[IN]])136; CHECK-NEXT: store i64 [[TMP2]], ptr @__msan_retval_tls, align 8137; CHECK-NEXT: ret double [[MINNM]]138;139 %minnm = call double @llvm.aarch64.neon.fminnmv.f64.v2f64(<2 x double> %in)140 ret double %minnm141}142 143declare float @llvm.aarch64.neon.fminnmv.f32.v2f32(<2 x float>)144declare float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float>)145declare double @llvm.aarch64.neon.fminnmv.f64.v2f64(<2 x double>)146 147define float @test_fmaxnmv_v2f32(<2 x float> %in) #0 {148; CHECK-LABEL: define float @test_fmaxnmv_v2f32(149; CHECK-SAME: <2 x float> [[IN:%.*]]) #[[ATTR0]] {150; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8151; CHECK-NEXT: call void @llvm.donothing()152; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> [[TMP1]])153; CHECK-NEXT: [[MAXNM:%.*]] = call float @llvm.aarch64.neon.fmaxnmv.f32.v2f32(<2 x float> [[IN]])154; CHECK-NEXT: store i32 [[TMP2]], ptr @__msan_retval_tls, align 8155; CHECK-NEXT: ret float [[MAXNM]]156;157 %maxnm = call float @llvm.aarch64.neon.fmaxnmv.f32.v2f32(<2 x float> %in)158 ret float %maxnm159}160 161define float @test_fmaxnmv_v4f32(<4 x float> %in) #0 {162; CHECK-LABEL: define float @test_fmaxnmv_v4f32(163; CHECK-SAME: <4 x float> [[IN:%.*]]) #[[ATTR0]] {164; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8165; CHECK-NEXT: call void @llvm.donothing()166; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP1]])167; CHECK-NEXT: [[MAXNM:%.*]] = call float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float> [[IN]])168; CHECK-NEXT: store i32 [[TMP2]], ptr @__msan_retval_tls, align 8169; CHECK-NEXT: ret float [[MAXNM]]170;171 %maxnm = call float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float> %in)172 ret float %maxnm173}174 175define double @test_fmaxnmv_v2f64(<2 x double> %in) #0 {176; CHECK-LABEL: define double @test_fmaxnmv_v2f64(177; CHECK-SAME: <2 x double> [[IN:%.*]]) #[[ATTR0]] {178; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8179; CHECK-NEXT: call void @llvm.donothing()180; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> [[TMP1]])181; CHECK-NEXT: [[MAXNM:%.*]] = call double @llvm.aarch64.neon.fmaxnmv.f64.v2f64(<2 x double> [[IN]])182; CHECK-NEXT: store i64 [[TMP2]], ptr @__msan_retval_tls, align 8183; CHECK-NEXT: ret double [[MAXNM]]184;185 %maxnm = call double @llvm.aarch64.neon.fmaxnmv.f64.v2f64(<2 x double> %in)186 ret double %maxnm187}188 189declare float @llvm.aarch64.neon.fmaxnmv.f32.v2f32(<2 x float>)190declare float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float>)191declare double @llvm.aarch64.neon.fmaxnmv.f64.v2f64(<2 x double>)192 193attributes #0 = { sanitize_memory }194