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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt < %s -passes=msan -S | FileCheck %s3;4; Forked from llvm/test/CodeGen/AArch64/arm64-uminv.ll5 6target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"7target triple = "aarch64--linux-android9001"8 9define signext i8 @test_vminv_s8(<8 x i8> %a1) #0 {10; CHECK-LABEL: define signext i8 @test_vminv_s8(11; CHECK-SAME: <8 x i8> [[A1:%.*]]) #[[ATTR0:[0-9]+]] {12; CHECK-NEXT: [[ENTRY:.*:]]13; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i8>, ptr @__msan_param_tls, align 814; CHECK-NEXT: call void @llvm.donothing()15; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> [[TMP0]])16; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[TMP1]] to i3217; CHECK-NEXT: [[VMINV_I:%.*]] = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> [[A1]])18; CHECK-NEXT: [[_MSPROP:%.*]] = trunc i32 [[TMP2]] to i819; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[VMINV_I]] to i820; CHECK-NEXT: store i8 [[_MSPROP]], ptr @__msan_retval_tls, align 821; CHECK-NEXT: ret i8 [[TMP4]]22;23entry:24 %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> %a1)25 %0 = trunc i32 %vminv.i to i826 ret i8 %027}28 29define signext i16 @test_vminv_s16(<4 x i16> %a1) #0 {30; CHECK-LABEL: define signext i16 @test_vminv_s16(31; CHECK-SAME: <4 x i16> [[A1:%.*]]) #[[ATTR0]] {32; CHECK-NEXT: [[ENTRY:.*:]]33; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr @__msan_param_tls, align 834; CHECK-NEXT: call void @llvm.donothing()35; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP0]])36; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[TMP1]] to i3237; CHECK-NEXT: [[VMINV_I:%.*]] = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> [[A1]])38; CHECK-NEXT: [[_MSPROP:%.*]] = trunc i32 [[TMP2]] to i1639; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[VMINV_I]] to i1640; CHECK-NEXT: store i16 [[_MSPROP]], ptr @__msan_retval_tls, align 841; CHECK-NEXT: ret i16 [[TMP4]]42;43entry:44 %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> %a1)45 %0 = trunc i32 %vminv.i to i1646 ret i16 %047}48 49define i32 @test_vminv_s32(<2 x i32> %a1) #0 {50; CHECK-LABEL: define i32 @test_vminv_s32(51; CHECK-SAME: <2 x i32> [[A1:%.*]]) #[[ATTR0]] {52; CHECK-NEXT: [[ENTRY:.*:]]53; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 854; CHECK-NEXT: call void @llvm.donothing()55; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> [[TMP0]])56; CHECK-NEXT: [[VMINV_I:%.*]] = tail call i32 @llvm.aarch64.neon.sminv.i32.v2i32(<2 x i32> [[A1]])57; CHECK-NEXT: store i32 [[TMP1]], ptr @__msan_retval_tls, align 858; CHECK-NEXT: ret i32 [[VMINV_I]]59;60entry:61 %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v2i32(<2 x i32> %a1)62 ret i32 %vminv.i63}64 65define signext i8 @test_vminvq_s8(<16 x i8> %a1) #0 {66; CHECK-LABEL: define signext i8 @test_vminvq_s8(67; CHECK-SAME: <16 x i8> [[A1:%.*]]) #[[ATTR0]] {68; CHECK-NEXT: [[ENTRY:.*:]]69; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @__msan_param_tls, align 870; CHECK-NEXT: call void @llvm.donothing()71; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> [[TMP0]])72; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[TMP1]] to i3273; CHECK-NEXT: [[VMINV_I:%.*]] = tail call i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8> [[A1]])74; CHECK-NEXT: [[_MSPROP:%.*]] = trunc i32 [[TMP2]] to i875; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[VMINV_I]] to i876; CHECK-NEXT: store i8 [[_MSPROP]], ptr @__msan_retval_tls, align 877; CHECK-NEXT: ret i8 [[TMP4]]78;79entry:80 %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8> %a1)81 %0 = trunc i32 %vminv.i to i882 ret i8 %083}84 85define signext i16 @test_vminvq_s16(<8 x i16> %a1) #0 {86; CHECK-LABEL: define signext i16 @test_vminvq_s16(87; CHECK-SAME: <8 x i16> [[A1:%.*]]) #[[ATTR0]] {88; CHECK-NEXT: [[ENTRY:.*:]]89; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 890; CHECK-NEXT: call void @llvm.donothing()91; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> [[TMP0]])92; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[TMP1]] to i3293; CHECK-NEXT: [[VMINV_I:%.*]] = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> [[A1]])94; CHECK-NEXT: [[_MSPROP:%.*]] = trunc i32 [[TMP2]] to i1695; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[VMINV_I]] to i1696; CHECK-NEXT: store i16 [[_MSPROP]], ptr @__msan_retval_tls, align 897; CHECK-NEXT: ret i16 [[TMP4]]98;99entry:100 %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> %a1)101 %0 = trunc i32 %vminv.i to i16102 ret i16 %0103}104 105define i32 @test_vminvq_s32(<4 x i32> %a1) #0 {106; CHECK-LABEL: define i32 @test_vminvq_s32(107; CHECK-SAME: <4 x i32> [[A1:%.*]]) #[[ATTR0]] {108; CHECK-NEXT: [[ENTRY:.*:]]109; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8110; CHECK-NEXT: call void @llvm.donothing()111; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP0]])112; CHECK-NEXT: [[VMINV_I:%.*]] = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32> [[A1]])113; CHECK-NEXT: store i32 [[TMP1]], ptr @__msan_retval_tls, align 8114; CHECK-NEXT: ret i32 [[VMINV_I]]115;116entry:117 %vminv.i = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32> %a1)118 ret i32 %vminv.i119}120 121define <8 x i8> @test_vminv_s8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) #0 {122; CHECK-LABEL: define <8 x i8> @test_vminv_s8_used_by_laneop(123; CHECK-SAME: <8 x i8> [[A1:%.*]], <8 x i8> [[A2:%.*]]) #[[ATTR0]] {124; CHECK-NEXT: [[ENTRY:.*:]]125; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8126; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr @__msan_param_tls, align 8127; CHECK-NEXT: call void @llvm.donothing()128; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> [[TMP0]])129; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i32130; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> [[A2]])131; CHECK-NEXT: [[_MSPROP1:%.*]] = trunc i32 [[TMP3]] to i8132; CHECK-NEXT: [[TMP6:%.*]] = trunc i32 [[TMP5]] to i8133; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <8 x i8> [[TMP1]], i8 [[_MSPROP1]], i32 3134; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i8> [[A1]], i8 [[TMP6]], i32 3135; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8136; CHECK-NEXT: ret <8 x i8> [[TMP7]]137;138entry:139 %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8> %a2)140 %1 = trunc i32 %0 to i8141 %2 = insertelement <8 x i8> %a1, i8 %1, i32 3142 ret <8 x i8> %2143}144 145define <4 x i16> @test_vminv_s16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) #0 {146; CHECK-LABEL: define <4 x i16> @test_vminv_s16_used_by_laneop(147; CHECK-SAME: <4 x i16> [[A1:%.*]], <4 x i16> [[A2:%.*]]) #[[ATTR0]] {148; CHECK-NEXT: [[ENTRY:.*:]]149; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8150; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @__msan_param_tls, align 8151; CHECK-NEXT: call void @llvm.donothing()152; CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP0]])153; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[TMP2]] to i32154; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> [[A2]])155; CHECK-NEXT: [[_MSPROP1:%.*]] = trunc i32 [[TMP3]] to i16156; CHECK-NEXT: [[TMP6:%.*]] = trunc i32 [[TMP5]] to i16157; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <4 x i16> [[TMP1]], i16 [[_MSPROP1]], i32 3158; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i16> [[A1]], i16 [[TMP6]], i32 3159; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8160; CHECK-NEXT: ret <4 x i16> [[TMP7]]161;162entry:163 %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16> %a2)164 %1 = trunc i32 %0 to i16165 %2 = insertelement <4 x i16> %a1, i16 %1, i32 3166 ret <4 x i16> %2167}168 169define <2 x i32> @test_vminv_s32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) #0 {170; CHECK-LABEL: define <2 x i32> @test_vminv_s32_used_by_laneop(171; CHECK-SAME: <2 x i32> [[A1:%.*]], <2 x i32> [[A2:%.*]]) #[[ATTR0]] {172; CHECK-NEXT: [[ENTRY:.*:]]173; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8174; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8175; CHECK-NEXT: call void @llvm.donothing()176; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> [[TMP0]])177; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.sminv.i32.v2i32(<2 x i32> [[A2]])178; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[TMP2]], i32 1179; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> [[A1]], i32 [[TMP5]], i32 1180; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8181; CHECK-NEXT: ret <2 x i32> [[TMP6]]182;183entry:184 %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v2i32(<2 x i32> %a2)185 %1 = insertelement <2 x i32> %a1, i32 %0, i32 1186 ret <2 x i32> %1187}188 189define <16 x i8> @test_vminvq_s8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) #0 {190; CHECK-LABEL: define <16 x i8> @test_vminvq_s8_used_by_laneop(191; CHECK-SAME: <16 x i8> [[A1:%.*]], <16 x i8> [[A2:%.*]]) #[[ATTR0]] {192; CHECK-NEXT: [[ENTRY:.*:]]193; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8194; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @__msan_param_tls, align 8195; CHECK-NEXT: call void @llvm.donothing()196; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> [[TMP0]])197; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i32198; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8> [[A2]])199; CHECK-NEXT: [[_MSPROP1:%.*]] = trunc i32 [[TMP3]] to i8200; CHECK-NEXT: [[TMP6:%.*]] = trunc i32 [[TMP5]] to i8201; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <16 x i8> [[TMP1]], i8 [[_MSPROP1]], i32 3202; CHECK-NEXT: [[TMP7:%.*]] = insertelement <16 x i8> [[A1]], i8 [[TMP6]], i32 3203; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8204; CHECK-NEXT: ret <16 x i8> [[TMP7]]205;206entry:207 %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8> %a2)208 %1 = trunc i32 %0 to i8209 %2 = insertelement <16 x i8> %a1, i8 %1, i32 3210 ret <16 x i8> %2211}212 213define <8 x i16> @test_vminvq_s16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) #0 {214; CHECK-LABEL: define <8 x i16> @test_vminvq_s16_used_by_laneop(215; CHECK-SAME: <8 x i16> [[A1:%.*]], <8 x i16> [[A2:%.*]]) #[[ATTR0]] {216; CHECK-NEXT: [[ENTRY:.*:]]217; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8218; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8219; CHECK-NEXT: call void @llvm.donothing()220; CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> [[TMP0]])221; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[TMP2]] to i32222; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> [[A2]])223; CHECK-NEXT: [[_MSPROP1:%.*]] = trunc i32 [[TMP3]] to i16224; CHECK-NEXT: [[TMP6:%.*]] = trunc i32 [[TMP5]] to i16225; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <8 x i16> [[TMP1]], i16 [[_MSPROP1]], i32 3226; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i16> [[A1]], i16 [[TMP6]], i32 3227; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8228; CHECK-NEXT: ret <8 x i16> [[TMP7]]229;230entry:231 %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16> %a2)232 %1 = trunc i32 %0 to i16233 %2 = insertelement <8 x i16> %a1, i16 %1, i32 3234 ret <8 x i16> %2235}236 237define <4 x i32> @test_vminvq_s32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) #0 {238; CHECK-LABEL: define <4 x i32> @test_vminvq_s32_used_by_laneop(239; CHECK-SAME: <4 x i32> [[A1:%.*]], <4 x i32> [[A2:%.*]]) #[[ATTR0]] {240; CHECK-NEXT: [[ENTRY:.*:]]241; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8242; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8243; CHECK-NEXT: call void @llvm.donothing()244; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP0]])245; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32> [[A2]])246; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[TMP2]], i32 3247; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[A1]], i32 [[TMP5]], i32 3248; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8249; CHECK-NEXT: ret <4 x i32> [[TMP6]]250;251entry:252 %0 = tail call i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32> %a2)253 %1 = insertelement <4 x i32> %a1, i32 %0, i32 3254 ret <4 x i32> %1255}256 257declare i32 @llvm.aarch64.neon.sminv.i32.v4i32(<4 x i32>)258declare i32 @llvm.aarch64.neon.sminv.i32.v8i16(<8 x i16>)259declare i32 @llvm.aarch64.neon.sminv.i32.v16i8(<16 x i8>)260declare i32 @llvm.aarch64.neon.sminv.i32.v2i32(<2 x i32>)261declare i32 @llvm.aarch64.neon.sminv.i32.v4i16(<4 x i16>)262declare i32 @llvm.aarch64.neon.sminv.i32.v8i8(<8 x i8>)263 264attributes #0 = { sanitize_memory }265