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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 22; Test memory sanitizer instrumentation for Arm NEON VST instructions, with3; origin tracking. These tests are deliberately shorter than neon_vst.ll, due4; to the verbosity of the output.5;6; RUN: opt < %s -passes=msan -msan-track-origins=2 -S | FileCheck %s7;8; Forked from llvm/test/CodeGen/AArch64/arm64-st1.ll9 10target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"11target triple = "aarch64--linux-android9001"12 13; -----------------------------------------------------------------------------------------------------------------------------------------------14 15define void @st2_16b(<16 x i8> %A, <16 x i8> %B, ptr %P) nounwind sanitize_memory {16;17;18; CHECK-LABEL: define void @st2_16b19; CHECK-SAME: (<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], ptr [[P:%.*]]) #[[ATTR0:[0-9]+]] {20; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 821; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_origin_tls, i64 32), align 422; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i8>, ptr @__msan_param_tls, align 823; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr @__msan_param_origin_tls, align 424; CHECK-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 825; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_origin_tls, i64 16), align 426; CHECK-NEXT: call void @llvm.donothing()27; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[P]] to i6428; CHECK-NEXT: [[TMP8:%.*]] = xor i64 [[TMP7]], 19351404648857629; CHECK-NEXT: [[TMP9:%.*]] = inttoptr i64 [[TMP8]] to ptr30; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[TMP8]], 3518437208883231; CHECK-NEXT: [[TMP11:%.*]] = and i64 [[TMP10]], -432; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr33; CHECK-NEXT: call void @llvm.aarch64.neon.st2.v16i8.p0(<16 x i8> [[TMP3]], <16 x i8> [[TMP5]], ptr [[TMP9]])34; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[TMP5]] to i12835; CHECK-NEXT: [[TMP14:%.*]] = icmp ne i128 [[TMP13]], 036; CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i32 [[TMP6]], i32 [[TMP4]]37; CHECK-NEXT: store i32 [[TMP15]], ptr [[TMP12]], align 438; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[TMP12]], i32 139; CHECK-NEXT: store i32 [[TMP15]], ptr [[TMP16]], align 440; CHECK-NEXT: [[TMP17:%.*]] = getelementptr i32, ptr [[TMP12]], i32 241; CHECK-NEXT: store i32 [[TMP15]], ptr [[TMP17]], align 442; CHECK-NEXT: [[TMP18:%.*]] = getelementptr i32, ptr [[TMP12]], i32 343; CHECK-NEXT: store i32 [[TMP15]], ptr [[TMP18]], align 444; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i32, ptr [[TMP12]], i32 445; CHECK-NEXT: store i32 [[TMP15]], ptr [[TMP19]], align 446; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr [[TMP12]], i32 547; CHECK-NEXT: store i32 [[TMP15]], ptr [[TMP20]], align 448; CHECK-NEXT: [[TMP21:%.*]] = getelementptr i32, ptr [[TMP12]], i32 649; CHECK-NEXT: store i32 [[TMP15]], ptr [[TMP21]], align 450; CHECK-NEXT: [[TMP22:%.*]] = getelementptr i32, ptr [[TMP12]], i32 751; CHECK-NEXT: store i32 [[TMP15]], ptr [[TMP22]], align 452; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 053; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP23:%.*]], label [[TMP24:%.*]], !prof [[PROF1:![0-9]+]]54; CHECK: 23:55; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 [[TMP2]]) #[[ATTR4:[0-9]+]]56; CHECK-NEXT: unreachable57; CHECK: 24:58; CHECK-NEXT: call void @llvm.aarch64.neon.st2.v16i8.p0(<16 x i8> [[A]], <16 x i8> [[B]], ptr [[P]])59; CHECK-NEXT: ret void60;61 call void @llvm.aarch64.neon.st2.v16i8.p0(<16 x i8> %A, <16 x i8> %B, ptr %P)62 ret void63}64 65define void @st3_16b(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, ptr %P) nounwind sanitize_memory {66;67;68; CHECK-LABEL: define void @st3_16b69; CHECK-SAME: (<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i8> [[C:%.*]], ptr [[P:%.*]]) #[[ATTR0]] {70; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 871; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_origin_tls, i64 48), align 472; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i8>, ptr @__msan_param_tls, align 873; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr @__msan_param_origin_tls, align 474; CHECK-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 875; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_origin_tls, i64 16), align 476; CHECK-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 877; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_origin_tls, i64 32), align 478; CHECK-NEXT: call void @llvm.donothing()79; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[P]] to i6480; CHECK-NEXT: [[TMP10:%.*]] = xor i64 [[TMP9]], 19351404648857681; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr82; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[TMP10]], 3518437208883283; CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], -484; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr85; CHECK-NEXT: call void @llvm.aarch64.neon.st3.v16i8.p0(<16 x i8> [[TMP3]], <16 x i8> [[TMP5]], <16 x i8> [[TMP7]], ptr [[TMP11]])86; CHECK-NEXT: [[TMP15:%.*]] = bitcast <16 x i8> [[TMP5]] to i12887; CHECK-NEXT: [[TMP16:%.*]] = icmp ne i128 [[TMP15]], 088; CHECK-NEXT: [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP6]], i32 [[TMP4]]89; CHECK-NEXT: [[TMP18:%.*]] = bitcast <16 x i8> [[TMP7]] to i12890; CHECK-NEXT: [[TMP19:%.*]] = icmp ne i128 [[TMP18]], 091; CHECK-NEXT: [[TMP20:%.*]] = select i1 [[TMP19]], i32 [[TMP8]], i32 [[TMP17]]92; CHECK-NEXT: store i32 [[TMP20]], ptr [[TMP14]], align 493; CHECK-NEXT: [[TMP21:%.*]] = getelementptr i32, ptr [[TMP14]], i32 194; CHECK-NEXT: store i32 [[TMP20]], ptr [[TMP21]], align 495; CHECK-NEXT: [[TMP22:%.*]] = getelementptr i32, ptr [[TMP14]], i32 296; CHECK-NEXT: store i32 [[TMP20]], ptr [[TMP22]], align 497; CHECK-NEXT: [[TMP23:%.*]] = getelementptr i32, ptr [[TMP14]], i32 398; CHECK-NEXT: store i32 [[TMP20]], ptr [[TMP23]], align 499; CHECK-NEXT: [[TMP24:%.*]] = getelementptr i32, ptr [[TMP14]], i32 4100; CHECK-NEXT: store i32 [[TMP20]], ptr [[TMP24]], align 4101; CHECK-NEXT: [[TMP25:%.*]] = getelementptr i32, ptr [[TMP14]], i32 5102; CHECK-NEXT: store i32 [[TMP20]], ptr [[TMP25]], align 4103; CHECK-NEXT: [[TMP26:%.*]] = getelementptr i32, ptr [[TMP14]], i32 6104; CHECK-NEXT: store i32 [[TMP20]], ptr [[TMP26]], align 4105; CHECK-NEXT: [[TMP27:%.*]] = getelementptr i32, ptr [[TMP14]], i32 7106; CHECK-NEXT: store i32 [[TMP20]], ptr [[TMP27]], align 4107; CHECK-NEXT: [[TMP28:%.*]] = getelementptr i32, ptr [[TMP14]], i32 8108; CHECK-NEXT: store i32 [[TMP20]], ptr [[TMP28]], align 4109; CHECK-NEXT: [[TMP29:%.*]] = getelementptr i32, ptr [[TMP14]], i32 9110; CHECK-NEXT: store i32 [[TMP20]], ptr [[TMP29]], align 4111; CHECK-NEXT: [[TMP30:%.*]] = getelementptr i32, ptr [[TMP14]], i32 10112; CHECK-NEXT: store i32 [[TMP20]], ptr [[TMP30]], align 4113; CHECK-NEXT: [[TMP31:%.*]] = getelementptr i32, ptr [[TMP14]], i32 11114; CHECK-NEXT: store i32 [[TMP20]], ptr [[TMP31]], align 4115; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0116; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP32:%.*]], label [[TMP33:%.*]], !prof [[PROF1]]117; CHECK: 32:118; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 [[TMP2]]) #[[ATTR4]]119; CHECK-NEXT: unreachable120; CHECK: 33:121; CHECK-NEXT: call void @llvm.aarch64.neon.st3.v16i8.p0(<16 x i8> [[A]], <16 x i8> [[B]], <16 x i8> [[C]], ptr [[P]])122; CHECK-NEXT: ret void123;124 call void @llvm.aarch64.neon.st3.v16i8.p0(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, ptr %P)125 ret void126}127 128define void @st4_16b(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, ptr %P) nounwind sanitize_memory {129;130;131; CHECK-LABEL: define void @st4_16b132; CHECK-SAME: (<16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i8> [[C:%.*]], <16 x i8> [[D:%.*]], ptr [[P:%.*]]) #[[ATTR0]] {133; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 8134; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_origin_tls, i64 64), align 4135; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i8>, ptr @__msan_param_tls, align 8136; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4137; CHECK-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8138; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_origin_tls, i64 16), align 4139; CHECK-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8140; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_origin_tls, i64 32), align 4141; CHECK-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 8142; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_origin_tls, i64 48), align 4143; CHECK-NEXT: call void @llvm.donothing()144; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[P]] to i64145; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 193514046488576146; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr147; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[TMP12]], 35184372088832148; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[TMP14]], -4149; CHECK-NEXT: [[TMP16:%.*]] = inttoptr i64 [[TMP15]] to ptr150; CHECK-NEXT: call void @llvm.aarch64.neon.st4.v16i8.p0(<16 x i8> [[TMP3]], <16 x i8> [[TMP5]], <16 x i8> [[TMP7]], <16 x i8> [[TMP9]], ptr [[TMP13]])151; CHECK-NEXT: [[TMP17:%.*]] = bitcast <16 x i8> [[TMP5]] to i128152; CHECK-NEXT: [[TMP18:%.*]] = icmp ne i128 [[TMP17]], 0153; CHECK-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP6]], i32 [[TMP4]]154; CHECK-NEXT: [[TMP20:%.*]] = bitcast <16 x i8> [[TMP7]] to i128155; CHECK-NEXT: [[TMP21:%.*]] = icmp ne i128 [[TMP20]], 0156; CHECK-NEXT: [[TMP22:%.*]] = select i1 [[TMP21]], i32 [[TMP8]], i32 [[TMP19]]157; CHECK-NEXT: [[TMP23:%.*]] = bitcast <16 x i8> [[TMP9]] to i128158; CHECK-NEXT: [[TMP24:%.*]] = icmp ne i128 [[TMP23]], 0159; CHECK-NEXT: [[TMP25:%.*]] = select i1 [[TMP24]], i32 [[TMP10]], i32 [[TMP22]]160; CHECK-NEXT: store i32 [[TMP25]], ptr [[TMP16]], align 4161; CHECK-NEXT: [[TMP26:%.*]] = getelementptr i32, ptr [[TMP16]], i32 1162; CHECK-NEXT: store i32 [[TMP25]], ptr [[TMP26]], align 4163; CHECK-NEXT: [[TMP27:%.*]] = getelementptr i32, ptr [[TMP16]], i32 2164; CHECK-NEXT: store i32 [[TMP25]], ptr [[TMP27]], align 4165; CHECK-NEXT: [[TMP28:%.*]] = getelementptr i32, ptr [[TMP16]], i32 3166; CHECK-NEXT: store i32 [[TMP25]], ptr [[TMP28]], align 4167; CHECK-NEXT: [[TMP29:%.*]] = getelementptr i32, ptr [[TMP16]], i32 4168; CHECK-NEXT: store i32 [[TMP25]], ptr [[TMP29]], align 4169; CHECK-NEXT: [[TMP30:%.*]] = getelementptr i32, ptr [[TMP16]], i32 5170; CHECK-NEXT: store i32 [[TMP25]], ptr [[TMP30]], align 4171; CHECK-NEXT: [[TMP31:%.*]] = getelementptr i32, ptr [[TMP16]], i32 6172; CHECK-NEXT: store i32 [[TMP25]], ptr [[TMP31]], align 4173; CHECK-NEXT: [[TMP32:%.*]] = getelementptr i32, ptr [[TMP16]], i32 7174; CHECK-NEXT: store i32 [[TMP25]], ptr [[TMP32]], align 4175; CHECK-NEXT: [[TMP33:%.*]] = getelementptr i32, ptr [[TMP16]], i32 8176; CHECK-NEXT: store i32 [[TMP25]], ptr [[TMP33]], align 4177; CHECK-NEXT: [[TMP34:%.*]] = getelementptr i32, ptr [[TMP16]], i32 9178; CHECK-NEXT: store i32 [[TMP25]], ptr [[TMP34]], align 4179; CHECK-NEXT: [[TMP35:%.*]] = getelementptr i32, ptr [[TMP16]], i32 10180; CHECK-NEXT: store i32 [[TMP25]], ptr [[TMP35]], align 4181; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i32, ptr [[TMP16]], i32 11182; CHECK-NEXT: store i32 [[TMP25]], ptr [[TMP36]], align 4183; CHECK-NEXT: [[TMP37:%.*]] = getelementptr i32, ptr [[TMP16]], i32 12184; CHECK-NEXT: store i32 [[TMP25]], ptr [[TMP37]], align 4185; CHECK-NEXT: [[TMP38:%.*]] = getelementptr i32, ptr [[TMP16]], i32 13186; CHECK-NEXT: store i32 [[TMP25]], ptr [[TMP38]], align 4187; CHECK-NEXT: [[TMP39:%.*]] = getelementptr i32, ptr [[TMP16]], i32 14188; CHECK-NEXT: store i32 [[TMP25]], ptr [[TMP39]], align 4189; CHECK-NEXT: [[TMP40:%.*]] = getelementptr i32, ptr [[TMP16]], i32 15190; CHECK-NEXT: store i32 [[TMP25]], ptr [[TMP40]], align 4191; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0192; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP41:%.*]], label [[TMP42:%.*]], !prof [[PROF1]]193; CHECK: 41:194; CHECK-NEXT: call void @__msan_warning_with_origin_noreturn(i32 [[TMP2]]) #[[ATTR4]]195; CHECK-NEXT: unreachable196; CHECK: 42:197; CHECK-NEXT: call void @llvm.aarch64.neon.st4.v16i8.p0(<16 x i8> [[A]], <16 x i8> [[B]], <16 x i8> [[C]], <16 x i8> [[D]], ptr [[P]])198; CHECK-NEXT: ret void199;200 call void @llvm.aarch64.neon.st4.v16i8.p0(<16 x i8> %A, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, ptr %P)201 ret void202}203 204declare void @llvm.aarch64.neon.st2.v16i8.p0(<16 x i8>, <16 x i8>, ptr) nounwind sanitize_memory readonly205declare void @llvm.aarch64.neon.st3.v16i8.p0(<16 x i8>, <16 x i8>, <16 x i8>, ptr) nounwind sanitize_memory readonly206declare void @llvm.aarch64.neon.st4.v16i8.p0(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, ptr) nounwind sanitize_memory readonly207