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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt < %s -passes=msan -S | FileCheck %s3;4; Forked from llvm/test/CodeGen/AArch64/arm64-umaxv.ll5 6target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"7target triple = "aarch64--linux-android9001"8 9define i32 @vmax_u8x8(<8 x i8> %a) nounwind ssp #0 {10; CHECK-LABEL: define i32 @vmax_u8x8(11; CHECK-SAME: <8 x i8> [[A:%.*]]) #[[ATTR0:[0-9]+]] {12; CHECK-NEXT: [[ENTRY:.*:]]13; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i8>, ptr @__msan_param_tls, align 814; CHECK-NEXT: call void @llvm.donothing()15; CHECK-NEXT: [[TMP7:%.*]] = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> [[TMP3]])16; CHECK-NEXT: [[VMAXV_I:%.*]] = zext i8 [[TMP7]] to i3217; CHECK-NEXT: [[VMAXV_I1:%.*]] = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> [[A]]) #[[ATTR3:[0-9]+]]18; CHECK-NEXT: [[TMP:%.*]] = trunc i32 [[VMAXV_I]] to i819; CHECK-NEXT: [[TMP8:%.*]] = trunc i32 [[VMAXV_I1]] to i820; CHECK-NEXT: [[TMP9:%.*]] = xor i8 [[TMP8]], 021; CHECK-NEXT: [[TMP4:%.*]] = or i8 [[TMP]], 022; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 023; CHECK-NEXT: [[TMP6:%.*]] = xor i8 [[TMP4]], -124; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[TMP6]], [[TMP9]]25; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i8 [[TMP1]], 026; CHECK-NEXT: [[_MSPROP_ICMP:%.*]] = and i1 [[TMP5]], [[TMP2]]27; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i8 [[TMP8]], 028; CHECK-NEXT: br i1 [[_MSPROP_ICMP]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1:![0-9]+]]29; CHECK: [[BB9]]:30; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5:[0-9]+]]31; CHECK-NEXT: unreachable32; CHECK: [[BB10]]:33; CHECK-NEXT: br i1 [[TOBOOL]], label %[[RETURN:.*]], label %[[IF_THEN:.*]]34; CHECK: [[IF_THEN]]:35; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 836; CHECK-NEXT: [[CALL1:%.*]] = tail call i32 @bar() #[[ATTR3]]37; CHECK-NEXT: [[_MSRET:%.*]] = load i32, ptr @__msan_retval_tls, align 838; CHECK-NEXT: br label %[[RETURN]]39; CHECK: [[RETURN]]:40; CHECK-NEXT: [[_MSPHI_S:%.*]] = phi i32 [ [[_MSRET]], %[[IF_THEN]] ], [ 0, %[[BB10]] ]41; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ [[CALL1]], %[[IF_THEN]] ], [ 0, %[[BB10]] ]42; CHECK-NEXT: store i32 [[_MSPHI_S]], ptr @__msan_retval_tls, align 843; CHECK-NEXT: ret i32 [[RETVAL_0]]44;45entry:46 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a) nounwind47 %tmp = trunc i32 %vmaxv.i to i848 %tobool = icmp eq i8 %tmp, 049 br i1 %tobool, label %return, label %if.then50 51if.then:52 %call1 = tail call i32 @bar() nounwind53 br label %return54 55return:56 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]57 ret i32 %retval.058}59 60declare i32 @bar(...)61 62define i32 @vmax_u4x16(<4 x i16> %a) nounwind ssp #0 {63; CHECK-LABEL: define i32 @vmax_u4x16(64; CHECK-SAME: <4 x i16> [[A:%.*]]) #[[ATTR0]] {65; CHECK-NEXT: [[ENTRY:.*:]]66; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i16>, ptr @__msan_param_tls, align 867; CHECK-NEXT: call void @llvm.donothing()68; CHECK-NEXT: [[TMP7:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP3]])69; CHECK-NEXT: [[VMAXV_I:%.*]] = zext i16 [[TMP7]] to i3270; CHECK-NEXT: [[VMAXV_I1:%.*]] = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> [[A]]) #[[ATTR3]]71; CHECK-NEXT: [[TMP:%.*]] = trunc i32 [[VMAXV_I]] to i1672; CHECK-NEXT: [[TMP8:%.*]] = trunc i32 [[VMAXV_I1]] to i1673; CHECK-NEXT: [[TMP9:%.*]] = xor i16 [[TMP8]], 074; CHECK-NEXT: [[TMP4:%.*]] = or i16 [[TMP]], 075; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i16 [[TMP4]], 076; CHECK-NEXT: [[TMP6:%.*]] = xor i16 [[TMP4]], -177; CHECK-NEXT: [[TMP1:%.*]] = and i16 [[TMP6]], [[TMP9]]78; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i16 [[TMP1]], 079; CHECK-NEXT: [[_MSPROP_ICMP:%.*]] = and i1 [[TMP5]], [[TMP2]]80; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i16 [[TMP8]], 081; CHECK-NEXT: br i1 [[_MSPROP_ICMP]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]82; CHECK: [[BB9]]:83; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]84; CHECK-NEXT: unreachable85; CHECK: [[BB10]]:86; CHECK-NEXT: br i1 [[TOBOOL]], label %[[RETURN:.*]], label %[[IF_THEN:.*]]87; CHECK: [[IF_THEN]]:88; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 889; CHECK-NEXT: [[CALL1:%.*]] = tail call i32 @bar() #[[ATTR3]]90; CHECK-NEXT: [[_MSRET:%.*]] = load i32, ptr @__msan_retval_tls, align 891; CHECK-NEXT: br label %[[RETURN]]92; CHECK: [[RETURN]]:93; CHECK-NEXT: [[_MSPHI_S:%.*]] = phi i32 [ [[_MSRET]], %[[IF_THEN]] ], [ 0, %[[BB10]] ]94; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ [[CALL1]], %[[IF_THEN]] ], [ 0, %[[BB10]] ]95; CHECK-NEXT: store i32 [[_MSPHI_S]], ptr @__msan_retval_tls, align 896; CHECK-NEXT: ret i32 [[RETVAL_0]]97;98entry:99 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> %a) nounwind100 %tmp = trunc i32 %vmaxv.i to i16101 %tobool = icmp eq i16 %tmp, 0102 br i1 %tobool, label %return, label %if.then103 104if.then:105 %call1 = tail call i32 @bar() nounwind106 br label %return107 108return:109 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]110 ret i32 %retval.0111}112 113define i32 @vmax_u8x16(<8 x i16> %a) nounwind ssp #0 {114; CHECK-LABEL: define i32 @vmax_u8x16(115; CHECK-SAME: <8 x i16> [[A:%.*]]) #[[ATTR0]] {116; CHECK-NEXT: [[ENTRY:.*:]]117; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8118; CHECK-NEXT: call void @llvm.donothing()119; CHECK-NEXT: [[TMP7:%.*]] = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> [[TMP3]])120; CHECK-NEXT: [[VMAXV_I:%.*]] = zext i16 [[TMP7]] to i32121; CHECK-NEXT: [[VMAXV_I1:%.*]] = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16> [[A]]) #[[ATTR3]]122; CHECK-NEXT: [[TMP:%.*]] = trunc i32 [[VMAXV_I]] to i16123; CHECK-NEXT: [[TMP8:%.*]] = trunc i32 [[VMAXV_I1]] to i16124; CHECK-NEXT: [[TMP9:%.*]] = xor i16 [[TMP8]], 0125; CHECK-NEXT: [[TMP4:%.*]] = or i16 [[TMP]], 0126; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i16 [[TMP4]], 0127; CHECK-NEXT: [[TMP6:%.*]] = xor i16 [[TMP4]], -1128; CHECK-NEXT: [[TMP1:%.*]] = and i16 [[TMP6]], [[TMP9]]129; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i16 [[TMP1]], 0130; CHECK-NEXT: [[_MSPROP_ICMP:%.*]] = and i1 [[TMP5]], [[TMP2]]131; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i16 [[TMP8]], 0132; CHECK-NEXT: br i1 [[_MSPROP_ICMP]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]133; CHECK: [[BB9]]:134; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]135; CHECK-NEXT: unreachable136; CHECK: [[BB10]]:137; CHECK-NEXT: br i1 [[TOBOOL]], label %[[RETURN:.*]], label %[[IF_THEN:.*]]138; CHECK: [[IF_THEN]]:139; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8140; CHECK-NEXT: [[CALL1:%.*]] = tail call i32 @bar() #[[ATTR3]]141; CHECK-NEXT: [[_MSRET:%.*]] = load i32, ptr @__msan_retval_tls, align 8142; CHECK-NEXT: br label %[[RETURN]]143; CHECK: [[RETURN]]:144; CHECK-NEXT: [[_MSPHI_S:%.*]] = phi i32 [ [[_MSRET]], %[[IF_THEN]] ], [ 0, %[[BB10]] ]145; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ [[CALL1]], %[[IF_THEN]] ], [ 0, %[[BB10]] ]146; CHECK-NEXT: store i32 [[_MSPHI_S]], ptr @__msan_retval_tls, align 8147; CHECK-NEXT: ret i32 [[RETVAL_0]]148;149entry:150 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16> %a) nounwind151 %tmp = trunc i32 %vmaxv.i to i16152 %tobool = icmp eq i16 %tmp, 0153 br i1 %tobool, label %return, label %if.then154 155if.then:156 %call1 = tail call i32 @bar() nounwind157 br label %return158 159return:160 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]161 ret i32 %retval.0162}163 164define i32 @vmax_u16x8(<16 x i8> %a) nounwind ssp #0 {165; CHECK-LABEL: define i32 @vmax_u16x8(166; CHECK-SAME: <16 x i8> [[A:%.*]]) #[[ATTR0]] {167; CHECK-NEXT: [[ENTRY:.*:]]168; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i8>, ptr @__msan_param_tls, align 8169; CHECK-NEXT: call void @llvm.donothing()170; CHECK-NEXT: [[TMP7:%.*]] = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> [[TMP3]])171; CHECK-NEXT: [[VMAXV_I:%.*]] = zext i8 [[TMP7]] to i32172; CHECK-NEXT: [[VMAXV_I1:%.*]] = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> [[A]]) #[[ATTR3]]173; CHECK-NEXT: [[TMP:%.*]] = trunc i32 [[VMAXV_I]] to i8174; CHECK-NEXT: [[TMP8:%.*]] = trunc i32 [[VMAXV_I1]] to i8175; CHECK-NEXT: [[TMP9:%.*]] = xor i8 [[TMP8]], 0176; CHECK-NEXT: [[TMP4:%.*]] = or i8 [[TMP]], 0177; CHECK-NEXT: [[TMP5:%.*]] = icmp ne i8 [[TMP4]], 0178; CHECK-NEXT: [[TMP6:%.*]] = xor i8 [[TMP4]], -1179; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[TMP6]], [[TMP9]]180; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i8 [[TMP1]], 0181; CHECK-NEXT: [[_MSPROP_ICMP:%.*]] = and i1 [[TMP5]], [[TMP2]]182; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i8 [[TMP8]], 0183; CHECK-NEXT: br i1 [[_MSPROP_ICMP]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]184; CHECK: [[BB9]]:185; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]186; CHECK-NEXT: unreachable187; CHECK: [[BB10]]:188; CHECK-NEXT: br i1 [[TOBOOL]], label %[[RETURN:.*]], label %[[IF_THEN:.*]]189; CHECK: [[IF_THEN]]:190; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8191; CHECK-NEXT: [[CALL1:%.*]] = tail call i32 @bar() #[[ATTR3]]192; CHECK-NEXT: [[_MSRET:%.*]] = load i32, ptr @__msan_retval_tls, align 8193; CHECK-NEXT: br label %[[RETURN]]194; CHECK: [[RETURN]]:195; CHECK-NEXT: [[_MSPHI_S:%.*]] = phi i32 [ [[_MSRET]], %[[IF_THEN]] ], [ 0, %[[BB10]] ]196; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ [[CALL1]], %[[IF_THEN]] ], [ 0, %[[BB10]] ]197; CHECK-NEXT: store i32 [[_MSPHI_S]], ptr @__msan_retval_tls, align 8198; CHECK-NEXT: ret i32 [[RETVAL_0]]199;200entry:201 %vmaxv.i = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %a) nounwind202 %tmp = trunc i32 %vmaxv.i to i8203 %tobool = icmp eq i8 %tmp, 0204 br i1 %tobool, label %return, label %if.then205 206if.then:207 %call1 = tail call i32 @bar() nounwind208 br label %return209 210return:211 %retval.0 = phi i32 [ %call1, %if.then ], [ 0, %entry ]212 ret i32 %retval.0213}214 215define <8 x i8> @test_vmaxv_u8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) #0 {216; CHECK-LABEL: define <8 x i8> @test_vmaxv_u8_used_by_laneop(217; CHECK-SAME: <8 x i8> [[A1:%.*]], <8 x i8> [[A2:%.*]]) #[[ATTR1:[0-9]+]] {218; CHECK-NEXT: [[ENTRY:.*:]]219; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8220; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr @__msan_param_tls, align 8221; CHECK-NEXT: call void @llvm.donothing()222; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> [[TMP0]])223; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i32224; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> [[A2]])225; CHECK-NEXT: [[_MSPROP1:%.*]] = trunc i32 [[TMP3]] to i8226; CHECK-NEXT: [[TMP6:%.*]] = trunc i32 [[TMP5]] to i8227; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <8 x i8> [[TMP1]], i8 [[_MSPROP1]], i32 3228; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i8> [[A1]], i8 [[TMP6]], i32 3229; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8230; CHECK-NEXT: ret <8 x i8> [[TMP7]]231;232entry:233 %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8> %a2)234 %1 = trunc i32 %0 to i8235 %2 = insertelement <8 x i8> %a1, i8 %1, i32 3236 ret <8 x i8> %2237}238 239define <4 x i16> @test_vmaxv_u16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) #0 {240; CHECK-LABEL: define <4 x i16> @test_vmaxv_u16_used_by_laneop(241; CHECK-SAME: <4 x i16> [[A1:%.*]], <4 x i16> [[A2:%.*]]) #[[ATTR1]] {242; CHECK-NEXT: [[ENTRY:.*:]]243; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8244; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @__msan_param_tls, align 8245; CHECK-NEXT: call void @llvm.donothing()246; CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP0]])247; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[TMP2]] to i32248; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> [[A2]])249; CHECK-NEXT: [[_MSPROP1:%.*]] = trunc i32 [[TMP3]] to i16250; CHECK-NEXT: [[TMP6:%.*]] = trunc i32 [[TMP5]] to i16251; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <4 x i16> [[TMP1]], i16 [[_MSPROP1]], i32 3252; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i16> [[A1]], i16 [[TMP6]], i32 3253; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8254; CHECK-NEXT: ret <4 x i16> [[TMP7]]255;256entry:257 %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16> %a2)258 %1 = trunc i32 %0 to i16259 %2 = insertelement <4 x i16> %a1, i16 %1, i32 3260 ret <4 x i16> %2261}262 263define <2 x i32> @test_vmaxv_u32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) #0 {264; CHECK-LABEL: define <2 x i32> @test_vmaxv_u32_used_by_laneop(265; CHECK-SAME: <2 x i32> [[A1:%.*]], <2 x i32> [[A2:%.*]]) #[[ATTR1]] {266; CHECK-NEXT: [[ENTRY:.*:]]267; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8268; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8269; CHECK-NEXT: call void @llvm.donothing()270; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> [[TMP0]])271; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.umaxv.i32.v2i32(<2 x i32> [[A2]])272; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[TMP2]], i32 1273; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> [[A1]], i32 [[TMP5]], i32 1274; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8275; CHECK-NEXT: ret <2 x i32> [[TMP6]]276;277entry:278 %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v2i32(<2 x i32> %a2)279 %1 = insertelement <2 x i32> %a1, i32 %0, i32 1280 ret <2 x i32> %1281}282 283define <16 x i8> @test_vmaxvq_u8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) #0 {284; CHECK-LABEL: define <16 x i8> @test_vmaxvq_u8_used_by_laneop(285; CHECK-SAME: <16 x i8> [[A1:%.*]], <16 x i8> [[A2:%.*]]) #[[ATTR1]] {286; CHECK-NEXT: [[ENTRY:.*:]]287; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8288; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @__msan_param_tls, align 8289; CHECK-NEXT: call void @llvm.donothing()290; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> [[TMP0]])291; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i32292; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> [[A2]])293; CHECK-NEXT: [[_MSPROP1:%.*]] = trunc i32 [[TMP3]] to i8294; CHECK-NEXT: [[TMP6:%.*]] = trunc i32 [[TMP5]] to i8295; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <16 x i8> [[TMP1]], i8 [[_MSPROP1]], i32 3296; CHECK-NEXT: [[TMP7:%.*]] = insertelement <16 x i8> [[A1]], i8 [[TMP6]], i32 3297; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8298; CHECK-NEXT: ret <16 x i8> [[TMP7]]299;300entry:301 %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8> %a2)302 %1 = trunc i32 %0 to i8303 %2 = insertelement <16 x i8> %a1, i8 %1, i32 3304 ret <16 x i8> %2305}306 307define <8 x i16> @test_vmaxvq_u16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) #0 {308; CHECK-LABEL: define <8 x i16> @test_vmaxvq_u16_used_by_laneop(309; CHECK-SAME: <8 x i16> [[A1:%.*]], <8 x i16> [[A2:%.*]]) #[[ATTR1]] {310; CHECK-NEXT: [[ENTRY:.*:]]311; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8312; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8313; CHECK-NEXT: call void @llvm.donothing()314; CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> [[TMP0]])315; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[TMP2]] to i32316; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16> [[A2]])317; CHECK-NEXT: [[_MSPROP1:%.*]] = trunc i32 [[TMP3]] to i16318; CHECK-NEXT: [[TMP6:%.*]] = trunc i32 [[TMP5]] to i16319; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <8 x i16> [[TMP1]], i16 [[_MSPROP1]], i32 3320; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i16> [[A1]], i16 [[TMP6]], i32 3321; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8322; CHECK-NEXT: ret <8 x i16> [[TMP7]]323;324entry:325 %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16> %a2)326 %1 = trunc i32 %0 to i16327 %2 = insertelement <8 x i16> %a1, i16 %1, i32 3328 ret <8 x i16> %2329}330 331define <4 x i32> @test_vmaxvq_u32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) #0 {332; CHECK-LABEL: define <4 x i32> @test_vmaxvq_u32_used_by_laneop(333; CHECK-SAME: <4 x i32> [[A1:%.*]], <4 x i32> [[A2:%.*]]) #[[ATTR1]] {334; CHECK-NEXT: [[ENTRY:.*:]]335; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8336; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8337; CHECK-NEXT: call void @llvm.donothing()338; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP0]])339; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32> [[A2]])340; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[TMP2]], i32 3341; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[A1]], i32 [[TMP5]], i32 3342; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8343; CHECK-NEXT: ret <4 x i32> [[TMP6]]344;345entry:346 %0 = tail call i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32> %a2)347 %1 = insertelement <4 x i32> %a1, i32 %0, i32 3348 ret <4 x i32> %1349}350 351declare i32 @llvm.aarch64.neon.umaxv.i32.v16i8(<16 x i8>) nounwind readnone352declare i32 @llvm.aarch64.neon.umaxv.i32.v8i16(<8 x i16>) nounwind readnone353declare i32 @llvm.aarch64.neon.umaxv.i32.v4i16(<4 x i16>) nounwind readnone354declare i32 @llvm.aarch64.neon.umaxv.i32.v8i8(<8 x i8>) nounwind readnone355declare i32 @llvm.aarch64.neon.umaxv.i32.v2i32(<2 x i32>) nounwind readnone356declare i32 @llvm.aarch64.neon.umaxv.i32.v4i32(<4 x i32>) nounwind readnone357 358attributes #0 = { sanitize_memory }359;.360; CHECK: [[PROF1]] = !{!"branch_weights", i32 1, i32 1048575}361;.362