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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: opt < %s -passes=msan -S | FileCheck %s3;4; Handled heuristically but incorrectly:5; - llvm.aarch64.neon.{addp, faddp}6;7; Unknown instructions handled by visitInstruction:8; - Incorrectly: llvm.aarch64.neon.{addhn, raddhn}9; - Suboptimally: llvm.aarch64.neon.{saddlp, uaddlp}10;11; Forked from llvm/test/CodeGen/AArch64/arm64-vadd.ll12 13target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"14target triple = "aarch64--linux-android9001"15 16define <8 x i8> @addhn8b(ptr %A, ptr %B) nounwind #0 {17; CHECK-LABEL: define <8 x i8> @addhn8b(18; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {19; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 820; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 821; CHECK-NEXT: call void @llvm.donothing()22; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 023; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP17:%.*]], label [[TMP4:%.*]], !prof [[PROF1:![0-9]+]]24; CHECK: 3:25; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4:[0-9]+]]26; CHECK-NEXT: unreachable27; CHECK: 4:28; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i16>, ptr [[A]], align 1629; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i6430; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 19351404648857631; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr32; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 1633; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 034; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]35; CHECK: 8:36; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]37; CHECK-NEXT: unreachable38; CHECK: 9:39; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i16>, ptr [[B]], align 1640; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i6441; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 19351404648857642; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr43; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 1644; CHECK-NEXT: [[TMP13:%.*]] = bitcast <8 x i16> [[_MSLD]] to i12845; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP13]], 046; CHECK-NEXT: [[TMP14:%.*]] = bitcast <8 x i16> [[_MSLD1]] to i12847; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP14]], 048; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP3]], [[_MSCMP4]]49; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP15:%.*]], label [[TMP16:%.*]], !prof [[PROF1]]50; CHECK: 15:51; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]52; CHECK-NEXT: unreachable53; CHECK: 16:54; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.addhn.v8i8(<8 x i16> [[TMPVAR1]], <8 x i16> [[TMPVAR2]])55; CHECK-NEXT: store <8 x i8> zeroinitializer, ptr @__msan_retval_tls, align 856; CHECK-NEXT: ret <8 x i8> [[TMP3]]57;58 %tmpvar1 = load <8 x i16>, ptr %A59 %tmpvar2 = load <8 x i16>, ptr %B60 %tmpvar3 = call <8 x i8> @llvm.aarch64.neon.addhn.v8i8(<8 x i16> %tmpvar1, <8 x i16> %tmpvar2)61 ret <8 x i8> %tmpvar362}63 64define <4 x i16> @addhn4h(ptr %A, ptr %B) nounwind #0 {65; CHECK-LABEL: define <4 x i16> @addhn4h(66; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {67; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 868; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 869; CHECK-NEXT: call void @llvm.donothing()70; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 071; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP17:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]72; CHECK: 3:73; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]74; CHECK-NEXT: unreachable75; CHECK: 4:76; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i32>, ptr [[A]], align 1677; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i6478; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 19351404648857679; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr80; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 1681; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 082; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]83; CHECK: 8:84; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]85; CHECK-NEXT: unreachable86; CHECK: 9:87; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i32>, ptr [[B]], align 1688; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i6489; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 19351404648857690; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr91; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 1692; CHECK-NEXT: [[TMP13:%.*]] = bitcast <4 x i32> [[_MSLD]] to i12893; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP13]], 094; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i32> [[_MSLD1]] to i12895; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP14]], 096; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP3]], [[_MSCMP4]]97; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP15:%.*]], label [[TMP16:%.*]], !prof [[PROF1]]98; CHECK: 15:99; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]100; CHECK-NEXT: unreachable101; CHECK: 16:102; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.addhn.v4i16(<4 x i32> [[TMPVAR1]], <4 x i32> [[TMPVAR2]])103; CHECK-NEXT: store <4 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8104; CHECK-NEXT: ret <4 x i16> [[TMP3]]105;106 %tmpvar1 = load <4 x i32>, ptr %A107 %tmpvar2 = load <4 x i32>, ptr %B108 %tmpvar3 = call <4 x i16> @llvm.aarch64.neon.addhn.v4i16(<4 x i32> %tmpvar1, <4 x i32> %tmpvar2)109 ret <4 x i16> %tmpvar3110}111 112define <2 x i32> @addhn2s(ptr %A, ptr %B) nounwind #0 {113; CHECK-LABEL: define <2 x i32> @addhn2s(114; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {115; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8116; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8117; CHECK-NEXT: call void @llvm.donothing()118; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0119; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP17:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]120; CHECK: 3:121; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]122; CHECK-NEXT: unreachable123; CHECK: 4:124; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i64>, ptr [[A]], align 16125; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64126; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576127; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr128; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 16129; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0130; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]131; CHECK: 8:132; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]133; CHECK-NEXT: unreachable134; CHECK: 9:135; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x i64>, ptr [[B]], align 16136; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64137; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576138; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr139; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 16140; CHECK-NEXT: [[TMP13:%.*]] = bitcast <2 x i64> [[_MSLD]] to i128141; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP13]], 0142; CHECK-NEXT: [[TMP14:%.*]] = bitcast <2 x i64> [[_MSLD1]] to i128143; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP14]], 0144; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP3]], [[_MSCMP4]]145; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP15:%.*]], label [[TMP16:%.*]], !prof [[PROF1]]146; CHECK: 15:147; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]148; CHECK-NEXT: unreachable149; CHECK: 16:150; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.addhn.v2i32(<2 x i64> [[TMPVAR1]], <2 x i64> [[TMPVAR2]])151; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8152; CHECK-NEXT: ret <2 x i32> [[TMP3]]153;154 %tmpvar1 = load <2 x i64>, ptr %A155 %tmpvar2 = load <2 x i64>, ptr %B156 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.addhn.v2i32(<2 x i64> %tmpvar1, <2 x i64> %tmpvar2)157 ret <2 x i32> %tmpvar3158}159 160define <16 x i8> @addhn2_16b(<8 x i16> %a, <8 x i16> %b) nounwind #0 {161; CHECK-LABEL: define <16 x i8> @addhn2_16b(162; CHECK-SAME: <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]]) #[[ATTR0]] {163; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8164; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8165; CHECK-NEXT: call void @llvm.donothing()166; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP1]] to i128167; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0168; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP2]] to i128169; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 0170; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]171; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]172; CHECK: 5:173; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]174; CHECK-NEXT: unreachable175; CHECK: 6:176; CHECK-NEXT: [[VADDHN2_I:%.*]] = tail call <8 x i8> @llvm.aarch64.neon.addhn.v8i8(<8 x i16> [[A]], <8 x i16> [[B]]) #[[ATTR3:[0-9]+]]177; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i16> [[TMP1]] to i128178; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 0179; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i16> [[TMP2]] to i128180; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP8]], 0181; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]182; CHECK-NEXT: br i1 [[_MSOR4]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]183; CHECK: 9:184; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]185; CHECK-NEXT: unreachable186; CHECK: 10:187; CHECK-NEXT: [[VADDHN_HIGH2_I:%.*]] = tail call <8 x i8> @llvm.aarch64.neon.addhn.v8i8(<8 x i16> [[A]], <8 x i16> [[B]]) #[[ATTR3]]188; CHECK-NEXT: [[RES:%.*]] = shufflevector <8 x i8> [[VADDHN2_I]], <8 x i8> [[VADDHN_HIGH2_I]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>189; CHECK-NEXT: store <16 x i8> zeroinitializer, ptr @__msan_retval_tls, align 8190; CHECK-NEXT: ret <16 x i8> [[RES]]191;192 %vaddhn2.i = tail call <8 x i8> @llvm.aarch64.neon.addhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwind193 %vaddhn_high2.i = tail call <8 x i8> @llvm.aarch64.neon.addhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwind194 %res = shufflevector <8 x i8> %vaddhn2.i, <8 x i8> %vaddhn_high2.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>195 ret <16 x i8> %res196}197 198define <8 x i16> @addhn2_8h(<4 x i32> %a, <4 x i32> %b) nounwind #0 {199; CHECK-LABEL: define <8 x i16> @addhn2_8h(200; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) #[[ATTR0]] {201; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8202; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8203; CHECK-NEXT: call void @llvm.donothing()204; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to i128205; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0206; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i128207; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 0208; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]209; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]210; CHECK: 5:211; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]212; CHECK-NEXT: unreachable213; CHECK: 6:214; CHECK-NEXT: [[VADDHN2_I:%.*]] = tail call <4 x i16> @llvm.aarch64.neon.addhn.v4i16(<4 x i32> [[A]], <4 x i32> [[B]]) #[[ATTR3]]215; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP1]] to i128216; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 0217; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i32> [[TMP2]] to i128218; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP8]], 0219; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]220; CHECK-NEXT: br i1 [[_MSOR4]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]221; CHECK: 9:222; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]223; CHECK-NEXT: unreachable224; CHECK: 10:225; CHECK-NEXT: [[VADDHN_HIGH3_I:%.*]] = tail call <4 x i16> @llvm.aarch64.neon.addhn.v4i16(<4 x i32> [[A]], <4 x i32> [[B]]) #[[ATTR3]]226; CHECK-NEXT: [[RES:%.*]] = shufflevector <4 x i16> [[VADDHN2_I]], <4 x i16> [[VADDHN_HIGH3_I]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>227; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8228; CHECK-NEXT: ret <8 x i16> [[RES]]229;230 %vaddhn2.i = tail call <4 x i16> @llvm.aarch64.neon.addhn.v4i16(<4 x i32> %a, <4 x i32> %b) nounwind231 %vaddhn_high3.i = tail call <4 x i16> @llvm.aarch64.neon.addhn.v4i16(<4 x i32> %a, <4 x i32> %b) nounwind232 %res = shufflevector <4 x i16> %vaddhn2.i, <4 x i16> %vaddhn_high3.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>233 ret <8 x i16> %res234}235 236define <4 x i32> @addhn2_4s(<2 x i64> %a, <2 x i64> %b) nounwind #0 {237; CHECK-LABEL: define <4 x i32> @addhn2_4s(238; CHECK-SAME: <2 x i64> [[A:%.*]], <2 x i64> [[B:%.*]]) #[[ATTR0]] {239; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8240; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8241; CHECK-NEXT: call void @llvm.donothing()242; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP1]] to i128243; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0244; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i128245; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 0246; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]247; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]248; CHECK: 5:249; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]250; CHECK-NEXT: unreachable251; CHECK: 6:252; CHECK-NEXT: [[VADDHN2_I:%.*]] = tail call <2 x i32> @llvm.aarch64.neon.addhn.v2i32(<2 x i64> [[A]], <2 x i64> [[B]]) #[[ATTR3]]253; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP1]] to i128254; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 0255; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x i64> [[TMP2]] to i128256; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP8]], 0257; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]258; CHECK-NEXT: br i1 [[_MSOR4]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]259; CHECK: 9:260; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]261; CHECK-NEXT: unreachable262; CHECK: 10:263; CHECK-NEXT: [[VADDHN_HIGH3_I:%.*]] = tail call <2 x i32> @llvm.aarch64.neon.addhn.v2i32(<2 x i64> [[A]], <2 x i64> [[B]]) #[[ATTR3]]264; CHECK-NEXT: [[RES:%.*]] = shufflevector <2 x i32> [[VADDHN2_I]], <2 x i32> [[VADDHN_HIGH3_I]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>265; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8266; CHECK-NEXT: ret <4 x i32> [[RES]]267;268 %vaddhn2.i = tail call <2 x i32> @llvm.aarch64.neon.addhn.v2i32(<2 x i64> %a, <2 x i64> %b) nounwind269 %vaddhn_high3.i = tail call <2 x i32> @llvm.aarch64.neon.addhn.v2i32(<2 x i64> %a, <2 x i64> %b) nounwind270 %res = shufflevector <2 x i32> %vaddhn2.i, <2 x i32> %vaddhn_high3.i, <4 x i32> <i32 0, i32 1, i32 2, i32 3>271 ret <4 x i32> %res272}273 274declare <2 x i32> @llvm.aarch64.neon.addhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone275declare <4 x i16> @llvm.aarch64.neon.addhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone276declare <8 x i8> @llvm.aarch64.neon.addhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone277 278 279define <8 x i8> @raddhn8b(ptr %A, ptr %B) nounwind #0 {280; CHECK-LABEL: define <8 x i8> @raddhn8b(281; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {282; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8283; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8284; CHECK-NEXT: call void @llvm.donothing()285; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0286; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP17:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]287; CHECK: 3:288; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]289; CHECK-NEXT: unreachable290; CHECK: 4:291; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i16>, ptr [[A]], align 16292; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64293; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576294; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr295; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 16296; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0297; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]298; CHECK: 8:299; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]300; CHECK-NEXT: unreachable301; CHECK: 9:302; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i16>, ptr [[B]], align 16303; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64304; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576305; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr306; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 16307; CHECK-NEXT: [[TMP13:%.*]] = bitcast <8 x i16> [[_MSLD]] to i128308; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP13]], 0309; CHECK-NEXT: [[TMP14:%.*]] = bitcast <8 x i16> [[_MSLD1]] to i128310; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP14]], 0311; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP3]], [[_MSCMP4]]312; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP15:%.*]], label [[TMP16:%.*]], !prof [[PROF1]]313; CHECK: 15:314; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]315; CHECK-NEXT: unreachable316; CHECK: 16:317; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16> [[TMPVAR1]], <8 x i16> [[TMPVAR2]])318; CHECK-NEXT: store <8 x i8> zeroinitializer, ptr @__msan_retval_tls, align 8319; CHECK-NEXT: ret <8 x i8> [[TMP3]]320;321 %tmpvar1 = load <8 x i16>, ptr %A322 %tmpvar2 = load <8 x i16>, ptr %B323 %tmpvar3 = call <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16> %tmpvar1, <8 x i16> %tmpvar2)324 ret <8 x i8> %tmpvar3325}326 327define <4 x i16> @raddhn4h(ptr %A, ptr %B) nounwind #0 {328; CHECK-LABEL: define <4 x i16> @raddhn4h(329; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {330; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8331; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8332; CHECK-NEXT: call void @llvm.donothing()333; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0334; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP17:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]335; CHECK: 3:336; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]337; CHECK-NEXT: unreachable338; CHECK: 4:339; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i32>, ptr [[A]], align 16340; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64341; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576342; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr343; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 16344; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0345; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]346; CHECK: 8:347; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]348; CHECK-NEXT: unreachable349; CHECK: 9:350; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i32>, ptr [[B]], align 16351; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64352; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576353; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr354; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 16355; CHECK-NEXT: [[TMP13:%.*]] = bitcast <4 x i32> [[_MSLD]] to i128356; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP13]], 0357; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i32> [[_MSLD1]] to i128358; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP14]], 0359; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP3]], [[_MSCMP4]]360; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP15:%.*]], label [[TMP16:%.*]], !prof [[PROF1]]361; CHECK: 15:362; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]363; CHECK-NEXT: unreachable364; CHECK: 16:365; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> [[TMPVAR1]], <4 x i32> [[TMPVAR2]])366; CHECK-NEXT: store <4 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8367; CHECK-NEXT: ret <4 x i16> [[TMP3]]368;369 %tmpvar1 = load <4 x i32>, ptr %A370 %tmpvar2 = load <4 x i32>, ptr %B371 %tmpvar3 = call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> %tmpvar1, <4 x i32> %tmpvar2)372 ret <4 x i16> %tmpvar3373}374 375define <2 x i32> @raddhn2s(ptr %A, ptr %B) nounwind #0 {376; CHECK-LABEL: define <2 x i32> @raddhn2s(377; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {378; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8379; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8380; CHECK-NEXT: call void @llvm.donothing()381; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0382; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP17:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]383; CHECK: 3:384; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]385; CHECK-NEXT: unreachable386; CHECK: 4:387; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i64>, ptr [[A]], align 16388; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64389; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576390; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr391; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 16392; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0393; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]394; CHECK: 8:395; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]396; CHECK-NEXT: unreachable397; CHECK: 9:398; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x i64>, ptr [[B]], align 16399; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64400; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576401; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr402; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 16403; CHECK-NEXT: [[TMP13:%.*]] = bitcast <2 x i64> [[_MSLD]] to i128404; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP13]], 0405; CHECK-NEXT: [[TMP14:%.*]] = bitcast <2 x i64> [[_MSLD1]] to i128406; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP14]], 0407; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP3]], [[_MSCMP4]]408; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP15:%.*]], label [[TMP16:%.*]], !prof [[PROF1]]409; CHECK: 15:410; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]411; CHECK-NEXT: unreachable412; CHECK: 16:413; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64> [[TMPVAR1]], <2 x i64> [[TMPVAR2]])414; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8415; CHECK-NEXT: ret <2 x i32> [[TMP3]]416;417 %tmpvar1 = load <2 x i64>, ptr %A418 %tmpvar2 = load <2 x i64>, ptr %B419 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64> %tmpvar1, <2 x i64> %tmpvar2)420 ret <2 x i32> %tmpvar3421}422 423define <16 x i8> @raddhn2_16b(<8 x i16> %a, <8 x i16> %b) nounwind #0 {424; CHECK-LABEL: define <16 x i8> @raddhn2_16b(425; CHECK-SAME: <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]]) #[[ATTR0]] {426; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8427; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8428; CHECK-NEXT: call void @llvm.donothing()429; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP1]] to i128430; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0431; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP2]] to i128432; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 0433; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]434; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]435; CHECK: 5:436; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]437; CHECK-NEXT: unreachable438; CHECK: 6:439; CHECK-NEXT: [[VRADDHN2_I:%.*]] = tail call <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16> [[A]], <8 x i16> [[B]]) #[[ATTR3]]440; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i16> [[TMP1]] to i128441; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 0442; CHECK-NEXT: [[TMP8:%.*]] = bitcast <8 x i16> [[TMP2]] to i128443; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP8]], 0444; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]445; CHECK-NEXT: br i1 [[_MSOR4]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]446; CHECK: 9:447; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]448; CHECK-NEXT: unreachable449; CHECK: 10:450; CHECK-NEXT: [[VRADDHN_HIGH2_I:%.*]] = tail call <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16> [[A]], <8 x i16> [[B]]) #[[ATTR3]]451; CHECK-NEXT: [[RES:%.*]] = shufflevector <8 x i8> [[VRADDHN2_I]], <8 x i8> [[VRADDHN_HIGH2_I]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>452; CHECK-NEXT: store <16 x i8> zeroinitializer, ptr @__msan_retval_tls, align 8453; CHECK-NEXT: ret <16 x i8> [[RES]]454;455 %vraddhn2.i = tail call <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwind456 %vraddhn_high2.i = tail call <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16> %a, <8 x i16> %b) nounwind457 %res = shufflevector <8 x i8> %vraddhn2.i, <8 x i8> %vraddhn_high2.i, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>458 ret <16 x i8> %res459}460 461define <8 x i16> @raddhn2_8h(<4 x i32> %a, <4 x i32> %b) nounwind #0 {462; CHECK-LABEL: define <8 x i16> @raddhn2_8h(463; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) #[[ATTR0]] {464; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8465; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8466; CHECK-NEXT: call void @llvm.donothing()467; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to i128468; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0469; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP2]] to i128470; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 0471; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]472; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]473; CHECK: 5:474; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]475; CHECK-NEXT: unreachable476; CHECK: 6:477; CHECK-NEXT: [[VRADDHN2_I:%.*]] = tail call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> [[A]], <4 x i32> [[B]]) #[[ATTR3]]478; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i32> [[TMP1]] to i128479; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 0480; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i32> [[TMP2]] to i128481; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP8]], 0482; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]483; CHECK-NEXT: br i1 [[_MSOR4]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]484; CHECK: 9:485; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]486; CHECK-NEXT: unreachable487; CHECK: 10:488; CHECK-NEXT: [[VRADDHN_HIGH3_I:%.*]] = tail call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> [[A]], <4 x i32> [[B]]) #[[ATTR3]]489; CHECK-NEXT: [[RES:%.*]] = shufflevector <4 x i16> [[VRADDHN2_I]], <4 x i16> [[VRADDHN_HIGH3_I]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>490; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 8491; CHECK-NEXT: ret <8 x i16> [[RES]]492;493 %vraddhn2.i = tail call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> %a, <4 x i32> %b) nounwind494 %vraddhn_high3.i = tail call <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32> %a, <4 x i32> %b) nounwind495 %res = shufflevector <4 x i16> %vraddhn2.i, <4 x i16> %vraddhn_high3.i, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>496 ret <8 x i16> %res497}498 499define <4 x i32> @raddhn2_4s(<2 x i64> %a, <2 x i64> %b) nounwind #0 {500; CHECK-LABEL: define <4 x i32> @raddhn2_4s(501; CHECK-SAME: <2 x i64> [[A:%.*]], <2 x i64> [[B:%.*]]) #[[ATTR0]] {502; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8503; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8504; CHECK-NEXT: call void @llvm.donothing()505; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i64> [[TMP1]] to i128506; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP3]], 0507; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i64> [[TMP2]] to i128508; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i128 [[TMP4]], 0509; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]510; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]511; CHECK: 5:512; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]513; CHECK-NEXT: unreachable514; CHECK: 6:515; CHECK-NEXT: [[VRADDHN2_I:%.*]] = tail call <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64> [[A]], <2 x i64> [[B]]) #[[ATTR3]]516; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i64> [[TMP1]] to i128517; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i128 [[TMP7]], 0518; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x i64> [[TMP2]] to i128519; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP8]], 0520; CHECK-NEXT: [[_MSOR4:%.*]] = or i1 [[_MSCMP2]], [[_MSCMP3]]521; CHECK-NEXT: br i1 [[_MSOR4]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]522; CHECK: 9:523; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]524; CHECK-NEXT: unreachable525; CHECK: 10:526; CHECK-NEXT: [[VRADDHN_HIGH3_I:%.*]] = tail call <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64> [[A]], <2 x i64> [[B]]) #[[ATTR3]]527; CHECK-NEXT: [[RES:%.*]] = shufflevector <2 x i32> [[VRADDHN2_I]], <2 x i32> [[VRADDHN_HIGH3_I]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>528; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8529; CHECK-NEXT: ret <4 x i32> [[RES]]530;531 %vraddhn2.i = tail call <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64> %a, <2 x i64> %b) nounwind532 %vraddhn_high3.i = tail call <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64> %a, <2 x i64> %b) nounwind533 %res = shufflevector <2 x i32> %vraddhn2.i, <2 x i32> %vraddhn_high3.i, <4 x i32> <i32 0, i32 1, i32 2, i32 3>534 ret <4 x i32> %res535}536 537declare <2 x i32> @llvm.aarch64.neon.raddhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone538declare <4 x i16> @llvm.aarch64.neon.raddhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone539declare <8 x i8> @llvm.aarch64.neon.raddhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone540 541define <8 x i16> @saddl8h(ptr %A, ptr %B) nounwind #0 {542; CHECK-LABEL: define <8 x i16> @saddl8h(543; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {544; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8545; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8546; CHECK-NEXT: call void @llvm.donothing()547; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0548; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]549; CHECK: 3:550; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]551; CHECK-NEXT: unreachable552; CHECK: 4:553; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i8>, ptr [[A]], align 8554; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64555; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576556; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr557; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 8558; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP2]], 0559; CHECK-NEXT: br i1 [[_MSCMP4]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]560; CHECK: 8:561; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]562; CHECK-NEXT: unreachable563; CHECK: 9:564; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i8>, ptr [[B]], align 8565; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64566; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576567; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr568; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP12]], align 8569; CHECK-NEXT: [[_MSPROP:%.*]] = sext <8 x i8> [[_MSLD]] to <8 x i16>570; CHECK-NEXT: [[TMPVAR3:%.*]] = sext <8 x i8> [[TMPVAR1]] to <8 x i16>571; CHECK-NEXT: [[_MSPROP2:%.*]] = sext <8 x i8> [[_MSLD1]] to <8 x i16>572; CHECK-NEXT: [[TMPVAR4:%.*]] = sext <8 x i8> [[TMPVAR2]] to <8 x i16>573; CHECK-NEXT: [[_MSPROP3:%.*]] = or <8 x i16> [[_MSPROP]], [[_MSPROP2]]574; CHECK-NEXT: [[TMPVAR5:%.*]] = add <8 x i16> [[TMPVAR3]], [[TMPVAR4]]575; CHECK-NEXT: store <8 x i16> [[_MSPROP3]], ptr @__msan_retval_tls, align 8576; CHECK-NEXT: ret <8 x i16> [[TMPVAR5]]577;578 %tmpvar1 = load <8 x i8>, ptr %A579 %tmpvar2 = load <8 x i8>, ptr %B580 %tmpvar3 = sext <8 x i8> %tmpvar1 to <8 x i16>581 %tmpvar4 = sext <8 x i8> %tmpvar2 to <8 x i16>582 %tmpvar5 = add <8 x i16> %tmpvar3, %tmpvar4583 ret <8 x i16> %tmpvar5584}585 586define <4 x i32> @saddl4s(ptr %A, ptr %B) nounwind #0 {587; CHECK-LABEL: define <4 x i32> @saddl4s(588; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {589; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8590; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8591; CHECK-NEXT: call void @llvm.donothing()592; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0593; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]594; CHECK: 3:595; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]596; CHECK-NEXT: unreachable597; CHECK: 4:598; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i16>, ptr [[A]], align 8599; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64600; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576601; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr602; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 8603; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP2]], 0604; CHECK-NEXT: br i1 [[_MSCMP4]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]605; CHECK: 8:606; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]607; CHECK-NEXT: unreachable608; CHECK: 9:609; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i16>, ptr [[B]], align 8610; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64611; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576612; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr613; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 8614; CHECK-NEXT: [[_MSPROP:%.*]] = sext <4 x i16> [[_MSLD]] to <4 x i32>615; CHECK-NEXT: [[TMPVAR3:%.*]] = sext <4 x i16> [[TMPVAR1]] to <4 x i32>616; CHECK-NEXT: [[_MSPROP2:%.*]] = sext <4 x i16> [[_MSLD1]] to <4 x i32>617; CHECK-NEXT: [[TMPVAR4:%.*]] = sext <4 x i16> [[TMPVAR2]] to <4 x i32>618; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i32> [[_MSPROP]], [[_MSPROP2]]619; CHECK-NEXT: [[TMPVAR5:%.*]] = add <4 x i32> [[TMPVAR3]], [[TMPVAR4]]620; CHECK-NEXT: store <4 x i32> [[_MSPROP3]], ptr @__msan_retval_tls, align 8621; CHECK-NEXT: ret <4 x i32> [[TMPVAR5]]622;623 %tmpvar1 = load <4 x i16>, ptr %A624 %tmpvar2 = load <4 x i16>, ptr %B625 %tmpvar3 = sext <4 x i16> %tmpvar1 to <4 x i32>626 %tmpvar4 = sext <4 x i16> %tmpvar2 to <4 x i32>627 %tmpvar5 = add <4 x i32> %tmpvar3, %tmpvar4628 ret <4 x i32> %tmpvar5629}630 631define <2 x i64> @saddl2d(ptr %A, ptr %B) nounwind #0 {632; CHECK-LABEL: define <2 x i64> @saddl2d(633; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {634; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8635; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8636; CHECK-NEXT: call void @llvm.donothing()637; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0638; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]639; CHECK: 3:640; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]641; CHECK-NEXT: unreachable642; CHECK: 4:643; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i32>, ptr [[A]], align 8644; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64645; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576646; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr647; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 8648; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP2]], 0649; CHECK-NEXT: br i1 [[_MSCMP4]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]650; CHECK: 8:651; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]652; CHECK-NEXT: unreachable653; CHECK: 9:654; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x i32>, ptr [[B]], align 8655; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64656; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576657; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr658; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 8659; CHECK-NEXT: [[_MSPROP:%.*]] = sext <2 x i32> [[_MSLD]] to <2 x i64>660; CHECK-NEXT: [[TMPVAR3:%.*]] = sext <2 x i32> [[TMPVAR1]] to <2 x i64>661; CHECK-NEXT: [[_MSPROP2:%.*]] = sext <2 x i32> [[_MSLD1]] to <2 x i64>662; CHECK-NEXT: [[TMPVAR4:%.*]] = sext <2 x i32> [[TMPVAR2]] to <2 x i64>663; CHECK-NEXT: [[_MSPROP3:%.*]] = or <2 x i64> [[_MSPROP]], [[_MSPROP2]]664; CHECK-NEXT: [[TMPVAR5:%.*]] = add <2 x i64> [[TMPVAR3]], [[TMPVAR4]]665; CHECK-NEXT: store <2 x i64> [[_MSPROP3]], ptr @__msan_retval_tls, align 8666; CHECK-NEXT: ret <2 x i64> [[TMPVAR5]]667;668 %tmpvar1 = load <2 x i32>, ptr %A669 %tmpvar2 = load <2 x i32>, ptr %B670 %tmpvar3 = sext <2 x i32> %tmpvar1 to <2 x i64>671 %tmpvar4 = sext <2 x i32> %tmpvar2 to <2 x i64>672 %tmpvar5 = add <2 x i64> %tmpvar3, %tmpvar4673 ret <2 x i64> %tmpvar5674}675 676define <8 x i16> @saddl2_8h(<16 x i8> %a, <16 x i8> %b, <2 x i64> %param1, <2 x i64> %param2) nounwind #0 {677; CHECK-LABEL: define <8 x i16> @saddl2_8h(678; CHECK-SAME: <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <2 x i64> [[PARAM1:%.*]], <2 x i64> [[PARAM2:%.*]]) #[[ATTR0]] {679; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @__msan_param_tls, align 8680; CHECK-NEXT: [[TMP7:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8681; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8682; CHECK-NEXT: [[TMP8:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 8683; CHECK-NEXT: call void @llvm.donothing()684; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>685; CHECK-NEXT: [[TMP:%.*]] = bitcast <16 x i8> [[A]] to <2 x i64>686; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i64> [[TMP3]], <2 x i64> [[TMP7]], <1 x i32> <i32 1>687; CHECK-NEXT: [[SHUFFLE_I_I_I:%.*]] = shufflevector <2 x i64> [[TMP]], <2 x i64> [[PARAM1]], <1 x i32> <i32 1>688; CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>689; CHECK-NEXT: [[TMPVAR1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I_I]] to <8 x i8>690; CHECK-NEXT: [[_MSPROP1:%.*]] = sext <8 x i8> [[TMP4]] to <8 x i16>691; CHECK-NEXT: [[VMOVL_I_I_I:%.*]] = sext <8 x i8> [[TMPVAR1]] to <8 x i16>692; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64>693; CHECK-NEXT: [[TMPVAR2:%.*]] = bitcast <16 x i8> [[B]] to <2 x i64>694; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <2 x i64> [[TMP5]], <2 x i64> [[TMP8]], <1 x i32> <i32 1>695; CHECK-NEXT: [[SHUFFLE_I_I4_I:%.*]] = shufflevector <2 x i64> [[TMPVAR2]], <2 x i64> [[PARAM2]], <1 x i32> <i32 1>696; CHECK-NEXT: [[TMP6:%.*]] = bitcast <1 x i64> [[_MSPROP2]] to <8 x i8>697; CHECK-NEXT: [[TMPVAR3:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I4_I]] to <8 x i8>698; CHECK-NEXT: [[_MSPROP3:%.*]] = sext <8 x i8> [[TMP6]] to <8 x i16>699; CHECK-NEXT: [[VMOVL_I_I5_I:%.*]] = sext <8 x i8> [[TMPVAR3]] to <8 x i16>700; CHECK-NEXT: [[_MSPROP4:%.*]] = or <8 x i16> [[_MSPROP1]], [[_MSPROP3]]701; CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i16> [[VMOVL_I_I_I]], [[VMOVL_I_I5_I]]702; CHECK-NEXT: store <8 x i16> [[_MSPROP4]], ptr @__msan_retval_tls, align 8703; CHECK-NEXT: ret <8 x i16> [[ADD_I]]704;705 %tmpvar = bitcast <16 x i8> %a to <2 x i64>706 %shuffle.i.i.i = shufflevector <2 x i64> %tmpvar, <2 x i64> %param1, <1 x i32> <i32 1>707 %tmpvar1 = bitcast <1 x i64> %shuffle.i.i.i to <8 x i8>708 %vmovl.i.i.i = sext <8 x i8> %tmpvar1 to <8 x i16>709 %tmpvar2 = bitcast <16 x i8> %b to <2 x i64>710 %shuffle.i.i4.i = shufflevector <2 x i64> %tmpvar2, <2 x i64> %param2, <1 x i32> <i32 1>711 %tmpvar3 = bitcast <1 x i64> %shuffle.i.i4.i to <8 x i8>712 %vmovl.i.i5.i = sext <8 x i8> %tmpvar3 to <8 x i16>713 %add.i = add <8 x i16> %vmovl.i.i.i, %vmovl.i.i5.i714 ret <8 x i16> %add.i715}716 717define <4 x i32> @saddl2_4s(<8 x i16> %a, <8 x i16> %b, <2 x i64> %param1, <2 x i64> %param2) nounwind #0 {718; CHECK-LABEL: define <4 x i32> @saddl2_4s(719; CHECK-SAME: <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <2 x i64> [[PARAM1:%.*]], <2 x i64> [[PARAM2:%.*]]) #[[ATTR0]] {720; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8721; CHECK-NEXT: [[TMP7:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8722; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8723; CHECK-NEXT: [[TMP8:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 8724; CHECK-NEXT: call void @llvm.donothing()725; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP1]] to <2 x i64>726; CHECK-NEXT: [[TMP:%.*]] = bitcast <8 x i16> [[A]] to <2 x i64>727; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i64> [[TMP3]], <2 x i64> [[TMP7]], <1 x i32> <i32 1>728; CHECK-NEXT: [[SHUFFLE_I_I_I:%.*]] = shufflevector <2 x i64> [[TMP]], <2 x i64> [[PARAM1]], <1 x i32> <i32 1>729; CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>730; CHECK-NEXT: [[TMPVAR1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I_I]] to <4 x i16>731; CHECK-NEXT: [[_MSPROP1:%.*]] = sext <4 x i16> [[TMP4]] to <4 x i32>732; CHECK-NEXT: [[VMOVL_I_I_I:%.*]] = sext <4 x i16> [[TMPVAR1]] to <4 x i32>733; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP2]] to <2 x i64>734; CHECK-NEXT: [[TMPVAR2:%.*]] = bitcast <8 x i16> [[B]] to <2 x i64>735; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <2 x i64> [[TMP5]], <2 x i64> [[TMP8]], <1 x i32> <i32 1>736; CHECK-NEXT: [[SHUFFLE_I_I4_I:%.*]] = shufflevector <2 x i64> [[TMPVAR2]], <2 x i64> [[PARAM2]], <1 x i32> <i32 1>737; CHECK-NEXT: [[TMP6:%.*]] = bitcast <1 x i64> [[_MSPROP2]] to <4 x i16>738; CHECK-NEXT: [[TMPVAR3:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I4_I]] to <4 x i16>739; CHECK-NEXT: [[_MSPROP3:%.*]] = sext <4 x i16> [[TMP6]] to <4 x i32>740; CHECK-NEXT: [[VMOVL_I_I5_I:%.*]] = sext <4 x i16> [[TMPVAR3]] to <4 x i32>741; CHECK-NEXT: [[_MSPROP4:%.*]] = or <4 x i32> [[_MSPROP1]], [[_MSPROP3]]742; CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i32> [[VMOVL_I_I_I]], [[VMOVL_I_I5_I]]743; CHECK-NEXT: store <4 x i32> [[_MSPROP4]], ptr @__msan_retval_tls, align 8744; CHECK-NEXT: ret <4 x i32> [[ADD_I]]745;746 %tmpvar = bitcast <8 x i16> %a to <2 x i64>747 %shuffle.i.i.i = shufflevector <2 x i64> %tmpvar, <2 x i64> %param1, <1 x i32> <i32 1>748 %tmpvar1 = bitcast <1 x i64> %shuffle.i.i.i to <4 x i16>749 %vmovl.i.i.i = sext <4 x i16> %tmpvar1 to <4 x i32>750 %tmpvar2 = bitcast <8 x i16> %b to <2 x i64>751 %shuffle.i.i4.i = shufflevector <2 x i64> %tmpvar2, <2 x i64> %param2, <1 x i32> <i32 1>752 %tmpvar3 = bitcast <1 x i64> %shuffle.i.i4.i to <4 x i16>753 %vmovl.i.i5.i = sext <4 x i16> %tmpvar3 to <4 x i32>754 %add.i = add <4 x i32> %vmovl.i.i.i, %vmovl.i.i5.i755 ret <4 x i32> %add.i756}757 758define <2 x i64> @saddl2_2d(<4 x i32> %a, <4 x i32> %b, <2 x i64> %param1, <2 x i64> %param2) nounwind #0 {759; CHECK-LABEL: define <2 x i64> @saddl2_2d(760; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <2 x i64> [[PARAM1:%.*]], <2 x i64> [[PARAM2:%.*]]) #[[ATTR0]] {761; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8762; CHECK-NEXT: [[TMP7:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8763; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8764; CHECK-NEXT: [[TMP8:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 8765; CHECK-NEXT: call void @llvm.donothing()766; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to <2 x i64>767; CHECK-NEXT: [[TMP:%.*]] = bitcast <4 x i32> [[A]] to <2 x i64>768; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i64> [[TMP3]], <2 x i64> [[TMP7]], <1 x i32> <i32 1>769; CHECK-NEXT: [[SHUFFLE_I_I_I:%.*]] = shufflevector <2 x i64> [[TMP]], <2 x i64> [[PARAM1]], <1 x i32> <i32 1>770; CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <2 x i32>771; CHECK-NEXT: [[TMPVAR1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I_I]] to <2 x i32>772; CHECK-NEXT: [[_MSPROP1:%.*]] = sext <2 x i32> [[TMP4]] to <2 x i64>773; CHECK-NEXT: [[VMOVL_I_I_I:%.*]] = sext <2 x i32> [[TMPVAR1]] to <2 x i64>774; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to <2 x i64>775; CHECK-NEXT: [[TMPVAR2:%.*]] = bitcast <4 x i32> [[B]] to <2 x i64>776; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <2 x i64> [[TMP5]], <2 x i64> [[TMP8]], <1 x i32> <i32 1>777; CHECK-NEXT: [[SHUFFLE_I_I4_I:%.*]] = shufflevector <2 x i64> [[TMPVAR2]], <2 x i64> [[PARAM2]], <1 x i32> <i32 1>778; CHECK-NEXT: [[TMP6:%.*]] = bitcast <1 x i64> [[_MSPROP2]] to <2 x i32>779; CHECK-NEXT: [[TMPVAR3:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I4_I]] to <2 x i32>780; CHECK-NEXT: [[_MSPROP3:%.*]] = sext <2 x i32> [[TMP6]] to <2 x i64>781; CHECK-NEXT: [[VMOVL_I_I5_I:%.*]] = sext <2 x i32> [[TMPVAR3]] to <2 x i64>782; CHECK-NEXT: [[_MSPROP4:%.*]] = or <2 x i64> [[_MSPROP1]], [[_MSPROP3]]783; CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i64> [[VMOVL_I_I_I]], [[VMOVL_I_I5_I]]784; CHECK-NEXT: store <2 x i64> [[_MSPROP4]], ptr @__msan_retval_tls, align 8785; CHECK-NEXT: ret <2 x i64> [[ADD_I]]786;787 %tmpvar = bitcast <4 x i32> %a to <2 x i64>788 %shuffle.i.i.i = shufflevector <2 x i64> %tmpvar, <2 x i64> %param1, <1 x i32> <i32 1>789 %tmpvar1 = bitcast <1 x i64> %shuffle.i.i.i to <2 x i32>790 %vmovl.i.i.i = sext <2 x i32> %tmpvar1 to <2 x i64>791 %tmpvar2 = bitcast <4 x i32> %b to <2 x i64>792 %shuffle.i.i4.i = shufflevector <2 x i64> %tmpvar2, <2 x i64> %param2, <1 x i32> <i32 1>793 %tmpvar3 = bitcast <1 x i64> %shuffle.i.i4.i to <2 x i32>794 %vmovl.i.i5.i = sext <2 x i32> %tmpvar3 to <2 x i64>795 %add.i = add <2 x i64> %vmovl.i.i.i, %vmovl.i.i5.i796 ret <2 x i64> %add.i797}798 799define <8 x i16> @uaddl8h(ptr %A, ptr %B) nounwind #0 {800; CHECK-LABEL: define <8 x i16> @uaddl8h(801; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {802; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8803; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8804; CHECK-NEXT: call void @llvm.donothing()805; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0806; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]807; CHECK: 3:808; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]809; CHECK-NEXT: unreachable810; CHECK: 4:811; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i8>, ptr [[A]], align 8812; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64813; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576814; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr815; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 8816; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP2]], 0817; CHECK-NEXT: br i1 [[_MSCMP4]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]818; CHECK: 8:819; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]820; CHECK-NEXT: unreachable821; CHECK: 9:822; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i8>, ptr [[B]], align 8823; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64824; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576825; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr826; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP12]], align 8827; CHECK-NEXT: [[_MSPROP:%.*]] = zext <8 x i8> [[_MSLD]] to <8 x i16>828; CHECK-NEXT: [[TMPVAR3:%.*]] = zext <8 x i8> [[TMPVAR1]] to <8 x i16>829; CHECK-NEXT: [[_MSPROP2:%.*]] = zext <8 x i8> [[_MSLD1]] to <8 x i16>830; CHECK-NEXT: [[TMPVAR4:%.*]] = zext <8 x i8> [[TMPVAR2]] to <8 x i16>831; CHECK-NEXT: [[_MSPROP3:%.*]] = or <8 x i16> [[_MSPROP]], [[_MSPROP2]]832; CHECK-NEXT: [[TMPVAR5:%.*]] = add <8 x i16> [[TMPVAR3]], [[TMPVAR4]]833; CHECK-NEXT: store <8 x i16> [[_MSPROP3]], ptr @__msan_retval_tls, align 8834; CHECK-NEXT: ret <8 x i16> [[TMPVAR5]]835;836 %tmpvar1 = load <8 x i8>, ptr %A837 %tmpvar2 = load <8 x i8>, ptr %B838 %tmpvar3 = zext <8 x i8> %tmpvar1 to <8 x i16>839 %tmpvar4 = zext <8 x i8> %tmpvar2 to <8 x i16>840 %tmpvar5 = add <8 x i16> %tmpvar3, %tmpvar4841 ret <8 x i16> %tmpvar5842}843 844define <4 x i32> @uaddl4s(ptr %A, ptr %B) nounwind #0 {845; CHECK-LABEL: define <4 x i32> @uaddl4s(846; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {847; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8848; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8849; CHECK-NEXT: call void @llvm.donothing()850; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0851; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]852; CHECK: 3:853; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]854; CHECK-NEXT: unreachable855; CHECK: 4:856; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i16>, ptr [[A]], align 8857; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64858; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576859; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr860; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 8861; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP2]], 0862; CHECK-NEXT: br i1 [[_MSCMP4]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]863; CHECK: 8:864; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]865; CHECK-NEXT: unreachable866; CHECK: 9:867; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i16>, ptr [[B]], align 8868; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64869; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576870; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr871; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 8872; CHECK-NEXT: [[_MSPROP:%.*]] = zext <4 x i16> [[_MSLD]] to <4 x i32>873; CHECK-NEXT: [[TMPVAR3:%.*]] = zext <4 x i16> [[TMPVAR1]] to <4 x i32>874; CHECK-NEXT: [[_MSPROP2:%.*]] = zext <4 x i16> [[_MSLD1]] to <4 x i32>875; CHECK-NEXT: [[TMPVAR4:%.*]] = zext <4 x i16> [[TMPVAR2]] to <4 x i32>876; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i32> [[_MSPROP]], [[_MSPROP2]]877; CHECK-NEXT: [[TMPVAR5:%.*]] = add <4 x i32> [[TMPVAR3]], [[TMPVAR4]]878; CHECK-NEXT: store <4 x i32> [[_MSPROP3]], ptr @__msan_retval_tls, align 8879; CHECK-NEXT: ret <4 x i32> [[TMPVAR5]]880;881 %tmpvar1 = load <4 x i16>, ptr %A882 %tmpvar2 = load <4 x i16>, ptr %B883 %tmpvar3 = zext <4 x i16> %tmpvar1 to <4 x i32>884 %tmpvar4 = zext <4 x i16> %tmpvar2 to <4 x i32>885 %tmpvar5 = add <4 x i32> %tmpvar3, %tmpvar4886 ret <4 x i32> %tmpvar5887}888 889define <2 x i64> @uaddl2d(ptr %A, ptr %B) nounwind #0 {890; CHECK-LABEL: define <2 x i64> @uaddl2d(891; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {892; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8893; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8894; CHECK-NEXT: call void @llvm.donothing()895; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0896; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]897; CHECK: 3:898; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]899; CHECK-NEXT: unreachable900; CHECK: 4:901; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i32>, ptr [[A]], align 8902; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64903; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576904; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr905; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 8906; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP2]], 0907; CHECK-NEXT: br i1 [[_MSCMP4]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]908; CHECK: 8:909; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]910; CHECK-NEXT: unreachable911; CHECK: 9:912; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x i32>, ptr [[B]], align 8913; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64914; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576915; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr916; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 8917; CHECK-NEXT: [[_MSPROP:%.*]] = zext <2 x i32> [[_MSLD]] to <2 x i64>918; CHECK-NEXT: [[TMPVAR3:%.*]] = zext <2 x i32> [[TMPVAR1]] to <2 x i64>919; CHECK-NEXT: [[_MSPROP2:%.*]] = zext <2 x i32> [[_MSLD1]] to <2 x i64>920; CHECK-NEXT: [[TMPVAR4:%.*]] = zext <2 x i32> [[TMPVAR2]] to <2 x i64>921; CHECK-NEXT: [[_MSPROP3:%.*]] = or <2 x i64> [[_MSPROP]], [[_MSPROP2]]922; CHECK-NEXT: [[TMPVAR5:%.*]] = add <2 x i64> [[TMPVAR3]], [[TMPVAR4]]923; CHECK-NEXT: store <2 x i64> [[_MSPROP3]], ptr @__msan_retval_tls, align 8924; CHECK-NEXT: ret <2 x i64> [[TMPVAR5]]925;926 %tmpvar1 = load <2 x i32>, ptr %A927 %tmpvar2 = load <2 x i32>, ptr %B928 %tmpvar3 = zext <2 x i32> %tmpvar1 to <2 x i64>929 %tmpvar4 = zext <2 x i32> %tmpvar2 to <2 x i64>930 %tmpvar5 = add <2 x i64> %tmpvar3, %tmpvar4931 ret <2 x i64> %tmpvar5932}933 934 935define <8 x i16> @uaddl2_8h(<16 x i8> %a, <16 x i8> %b, <2 x i64> %param1, <2 x i64> %param2) nounwind #0 {936; CHECK-LABEL: define <8 x i16> @uaddl2_8h(937; CHECK-SAME: <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]], <2 x i64> [[PARAM1:%.*]], <2 x i64> [[PARAM2:%.*]]) #[[ATTR0]] {938; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @__msan_param_tls, align 8939; CHECK-NEXT: [[TMP7:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8940; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8941; CHECK-NEXT: [[TMP8:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 8942; CHECK-NEXT: call void @llvm.donothing()943; CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64>944; CHECK-NEXT: [[TMP:%.*]] = bitcast <16 x i8> [[A]] to <2 x i64>945; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i64> [[TMP3]], <2 x i64> [[TMP7]], <1 x i32> <i32 1>946; CHECK-NEXT: [[SHUFFLE_I_I_I:%.*]] = shufflevector <2 x i64> [[TMP]], <2 x i64> [[PARAM1]], <1 x i32> <i32 1>947; CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>948; CHECK-NEXT: [[TMPVAR1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I_I]] to <8 x i8>949; CHECK-NEXT: [[_MSPROP1:%.*]] = zext <8 x i8> [[TMP4]] to <8 x i16>950; CHECK-NEXT: [[VMOVL_I_I_I:%.*]] = zext <8 x i8> [[TMPVAR1]] to <8 x i16>951; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64>952; CHECK-NEXT: [[TMPVAR2:%.*]] = bitcast <16 x i8> [[B]] to <2 x i64>953; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <2 x i64> [[TMP5]], <2 x i64> [[TMP8]], <1 x i32> <i32 1>954; CHECK-NEXT: [[SHUFFLE_I_I4_I:%.*]] = shufflevector <2 x i64> [[TMPVAR2]], <2 x i64> [[PARAM2]], <1 x i32> <i32 1>955; CHECK-NEXT: [[TMP6:%.*]] = bitcast <1 x i64> [[_MSPROP2]] to <8 x i8>956; CHECK-NEXT: [[TMPVAR3:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I4_I]] to <8 x i8>957; CHECK-NEXT: [[_MSPROP3:%.*]] = zext <8 x i8> [[TMP6]] to <8 x i16>958; CHECK-NEXT: [[VMOVL_I_I5_I:%.*]] = zext <8 x i8> [[TMPVAR3]] to <8 x i16>959; CHECK-NEXT: [[_MSPROP4:%.*]] = or <8 x i16> [[_MSPROP1]], [[_MSPROP3]]960; CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i16> [[VMOVL_I_I_I]], [[VMOVL_I_I5_I]]961; CHECK-NEXT: store <8 x i16> [[_MSPROP4]], ptr @__msan_retval_tls, align 8962; CHECK-NEXT: ret <8 x i16> [[ADD_I]]963;964 %tmpvar = bitcast <16 x i8> %a to <2 x i64>965 %shuffle.i.i.i = shufflevector <2 x i64> %tmpvar, <2 x i64> %param1, <1 x i32> <i32 1>966 %tmpvar1 = bitcast <1 x i64> %shuffle.i.i.i to <8 x i8>967 %vmovl.i.i.i = zext <8 x i8> %tmpvar1 to <8 x i16>968 %tmpvar2 = bitcast <16 x i8> %b to <2 x i64>969 %shuffle.i.i4.i = shufflevector <2 x i64> %tmpvar2, <2 x i64> %param2, <1 x i32> <i32 1>970 %tmpvar3 = bitcast <1 x i64> %shuffle.i.i4.i to <8 x i8>971 %vmovl.i.i5.i = zext <8 x i8> %tmpvar3 to <8 x i16>972 %add.i = add <8 x i16> %vmovl.i.i.i, %vmovl.i.i5.i973 ret <8 x i16> %add.i974}975 976define <4 x i32> @uaddl2_4s(<8 x i16> %a, <8 x i16> %b, <2 x i64> %param1, <2 x i64> %param2) nounwind #0 {977; CHECK-LABEL: define <4 x i32> @uaddl2_4s(978; CHECK-SAME: <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <2 x i64> [[PARAM1:%.*]], <2 x i64> [[PARAM2:%.*]]) #[[ATTR0]] {979; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8980; CHECK-NEXT: [[TMP7:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 8981; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8982; CHECK-NEXT: [[TMP8:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 8983; CHECK-NEXT: call void @llvm.donothing()984; CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i16> [[TMP1]] to <2 x i64>985; CHECK-NEXT: [[TMP:%.*]] = bitcast <8 x i16> [[A]] to <2 x i64>986; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i64> [[TMP3]], <2 x i64> [[TMP7]], <1 x i32> <i32 1>987; CHECK-NEXT: [[SHUFFLE_I_I_I:%.*]] = shufflevector <2 x i64> [[TMP]], <2 x i64> [[PARAM1]], <1 x i32> <i32 1>988; CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>989; CHECK-NEXT: [[TMPVAR1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I_I]] to <4 x i16>990; CHECK-NEXT: [[_MSPROP1:%.*]] = zext <4 x i16> [[TMP4]] to <4 x i32>991; CHECK-NEXT: [[VMOVL_I_I_I:%.*]] = zext <4 x i16> [[TMPVAR1]] to <4 x i32>992; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP2]] to <2 x i64>993; CHECK-NEXT: [[TMPVAR2:%.*]] = bitcast <8 x i16> [[B]] to <2 x i64>994; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <2 x i64> [[TMP5]], <2 x i64> [[TMP8]], <1 x i32> <i32 1>995; CHECK-NEXT: [[SHUFFLE_I_I4_I:%.*]] = shufflevector <2 x i64> [[TMPVAR2]], <2 x i64> [[PARAM2]], <1 x i32> <i32 1>996; CHECK-NEXT: [[TMP6:%.*]] = bitcast <1 x i64> [[_MSPROP2]] to <4 x i16>997; CHECK-NEXT: [[TMPVAR3:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I4_I]] to <4 x i16>998; CHECK-NEXT: [[_MSPROP3:%.*]] = zext <4 x i16> [[TMP6]] to <4 x i32>999; CHECK-NEXT: [[VMOVL_I_I5_I:%.*]] = zext <4 x i16> [[TMPVAR3]] to <4 x i32>1000; CHECK-NEXT: [[_MSPROP4:%.*]] = or <4 x i32> [[_MSPROP1]], [[_MSPROP3]]1001; CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i32> [[VMOVL_I_I_I]], [[VMOVL_I_I5_I]]1002; CHECK-NEXT: store <4 x i32> [[_MSPROP4]], ptr @__msan_retval_tls, align 81003; CHECK-NEXT: ret <4 x i32> [[ADD_I]]1004;1005 %tmpvar = bitcast <8 x i16> %a to <2 x i64>1006 %shuffle.i.i.i = shufflevector <2 x i64> %tmpvar, <2 x i64> %param1, <1 x i32> <i32 1>1007 %tmpvar1 = bitcast <1 x i64> %shuffle.i.i.i to <4 x i16>1008 %vmovl.i.i.i = zext <4 x i16> %tmpvar1 to <4 x i32>1009 %tmpvar2 = bitcast <8 x i16> %b to <2 x i64>1010 %shuffle.i.i4.i = shufflevector <2 x i64> %tmpvar2, <2 x i64> %param2, <1 x i32> <i32 1>1011 %tmpvar3 = bitcast <1 x i64> %shuffle.i.i4.i to <4 x i16>1012 %vmovl.i.i5.i = zext <4 x i16> %tmpvar3 to <4 x i32>1013 %add.i = add <4 x i32> %vmovl.i.i.i, %vmovl.i.i5.i1014 ret <4 x i32> %add.i1015}1016 1017define <2 x i64> @uaddl2_2d(<4 x i32> %a, <4 x i32> %b, <2 x i64> %param1, <2 x i64> %param2) nounwind #0 {1018; CHECK-LABEL: define <2 x i64> @uaddl2_2d(1019; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <2 x i64> [[PARAM1:%.*]], <2 x i64> [[PARAM2:%.*]]) #[[ATTR0]] {1020; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81021; CHECK-NEXT: [[TMP7:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 81022; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81023; CHECK-NEXT: [[TMP8:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 48), align 81024; CHECK-NEXT: call void @llvm.donothing()1025; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i32> [[TMP1]] to <2 x i64>1026; CHECK-NEXT: [[TMP:%.*]] = bitcast <4 x i32> [[A]] to <2 x i64>1027; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i64> [[TMP3]], <2 x i64> [[TMP7]], <1 x i32> <i32 1>1028; CHECK-NEXT: [[SHUFFLE_I_I_I:%.*]] = shufflevector <2 x i64> [[TMP]], <2 x i64> [[PARAM1]], <1 x i32> <i32 1>1029; CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <2 x i32>1030; CHECK-NEXT: [[TMPVAR1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I_I]] to <2 x i32>1031; CHECK-NEXT: [[_MSPROP1:%.*]] = zext <2 x i32> [[TMP4]] to <2 x i64>1032; CHECK-NEXT: [[VMOVL_I_I_I:%.*]] = zext <2 x i32> [[TMPVAR1]] to <2 x i64>1033; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP2]] to <2 x i64>1034; CHECK-NEXT: [[TMPVAR2:%.*]] = bitcast <4 x i32> [[B]] to <2 x i64>1035; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <2 x i64> [[TMP5]], <2 x i64> [[TMP8]], <1 x i32> <i32 1>1036; CHECK-NEXT: [[SHUFFLE_I_I4_I:%.*]] = shufflevector <2 x i64> [[TMPVAR2]], <2 x i64> [[PARAM2]], <1 x i32> <i32 1>1037; CHECK-NEXT: [[TMP6:%.*]] = bitcast <1 x i64> [[_MSPROP2]] to <2 x i32>1038; CHECK-NEXT: [[TMPVAR3:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I4_I]] to <2 x i32>1039; CHECK-NEXT: [[_MSPROP3:%.*]] = zext <2 x i32> [[TMP6]] to <2 x i64>1040; CHECK-NEXT: [[VMOVL_I_I5_I:%.*]] = zext <2 x i32> [[TMPVAR3]] to <2 x i64>1041; CHECK-NEXT: [[_MSPROP4:%.*]] = or <2 x i64> [[_MSPROP1]], [[_MSPROP3]]1042; CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i64> [[VMOVL_I_I_I]], [[VMOVL_I_I5_I]]1043; CHECK-NEXT: store <2 x i64> [[_MSPROP4]], ptr @__msan_retval_tls, align 81044; CHECK-NEXT: ret <2 x i64> [[ADD_I]]1045;1046 %tmpvar = bitcast <4 x i32> %a to <2 x i64>1047 %shuffle.i.i.i = shufflevector <2 x i64> %tmpvar, <2 x i64> %param1, <1 x i32> <i32 1>1048 %tmpvar1 = bitcast <1 x i64> %shuffle.i.i.i to <2 x i32>1049 %vmovl.i.i.i = zext <2 x i32> %tmpvar1 to <2 x i64>1050 %tmpvar2 = bitcast <4 x i32> %b to <2 x i64>1051 %shuffle.i.i4.i = shufflevector <2 x i64> %tmpvar2, <2 x i64> %param2, <1 x i32> <i32 1>1052 %tmpvar3 = bitcast <1 x i64> %shuffle.i.i4.i to <2 x i32>1053 %vmovl.i.i5.i = zext <2 x i32> %tmpvar3 to <2 x i64>1054 %add.i = add <2 x i64> %vmovl.i.i.i, %vmovl.i.i5.i1055 ret <2 x i64> %add.i1056}1057 1058define <8 x i16> @uaddw8h(ptr %A, ptr %B) nounwind #0 {1059; CHECK-LABEL: define <8 x i16> @uaddw8h(1060; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1061; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81062; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81063; CHECK-NEXT: call void @llvm.donothing()1064; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01065; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]1066; CHECK: 3:1067; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1068; CHECK-NEXT: unreachable1069; CHECK: 4:1070; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i16>, ptr [[A]], align 161071; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641072; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761073; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1074; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 161075; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 01076; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1077; CHECK: 8:1078; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1079; CHECK-NEXT: unreachable1080; CHECK: 9:1081; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i8>, ptr [[B]], align 81082; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641083; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761084; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1085; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP12]], align 81086; CHECK-NEXT: [[_MSPROP:%.*]] = zext <8 x i8> [[_MSLD1]] to <8 x i16>1087; CHECK-NEXT: [[TMPVAR3:%.*]] = zext <8 x i8> [[TMPVAR2]] to <8 x i16>1088; CHECK-NEXT: [[_MSPROP2:%.*]] = or <8 x i16> [[_MSLD]], [[_MSPROP]]1089; CHECK-NEXT: [[TMP4:%.*]] = add <8 x i16> [[TMPVAR1]], [[TMPVAR3]]1090; CHECK-NEXT: store <8 x i16> [[_MSPROP2]], ptr @__msan_retval_tls, align 81091; CHECK-NEXT: ret <8 x i16> [[TMP4]]1092;1093 %tmpvar1 = load <8 x i16>, ptr %A1094 %tmpvar2 = load <8 x i8>, ptr %B1095 %tmpvar3 = zext <8 x i8> %tmpvar2 to <8 x i16>1096 %tmpvar4 = add <8 x i16> %tmpvar1, %tmpvar31097 ret <8 x i16> %tmpvar41098}1099 1100define <4 x i32> @uaddw4s(ptr %A, ptr %B) nounwind #0 {1101; CHECK-LABEL: define <4 x i32> @uaddw4s(1102; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1103; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81104; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81105; CHECK-NEXT: call void @llvm.donothing()1106; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01107; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]1108; CHECK: 3:1109; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1110; CHECK-NEXT: unreachable1111; CHECK: 4:1112; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i32>, ptr [[A]], align 161113; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641114; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761115; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1116; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 161117; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 01118; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1119; CHECK: 8:1120; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1121; CHECK-NEXT: unreachable1122; CHECK: 9:1123; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i16>, ptr [[B]], align 81124; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641125; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761126; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1127; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 81128; CHECK-NEXT: [[_MSPROP:%.*]] = zext <4 x i16> [[_MSLD1]] to <4 x i32>1129; CHECK-NEXT: [[TMPVAR3:%.*]] = zext <4 x i16> [[TMPVAR2]] to <4 x i32>1130; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i32> [[_MSLD]], [[_MSPROP]]1131; CHECK-NEXT: [[TMP4:%.*]] = add <4 x i32> [[TMPVAR1]], [[TMPVAR3]]1132; CHECK-NEXT: store <4 x i32> [[_MSPROP2]], ptr @__msan_retval_tls, align 81133; CHECK-NEXT: ret <4 x i32> [[TMP4]]1134;1135 %tmpvar1 = load <4 x i32>, ptr %A1136 %tmpvar2 = load <4 x i16>, ptr %B1137 %tmpvar3 = zext <4 x i16> %tmpvar2 to <4 x i32>1138 %tmpvar4 = add <4 x i32> %tmpvar1, %tmpvar31139 ret <4 x i32> %tmpvar41140}1141 1142define <2 x i64> @uaddw2d(ptr %A, ptr %B) nounwind #0 {1143; CHECK-LABEL: define <2 x i64> @uaddw2d(1144; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1145; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81146; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81147; CHECK-NEXT: call void @llvm.donothing()1148; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01149; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]1150; CHECK: 3:1151; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1152; CHECK-NEXT: unreachable1153; CHECK: 4:1154; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i64>, ptr [[A]], align 161155; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641156; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761157; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1158; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 161159; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 01160; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1161; CHECK: 8:1162; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1163; CHECK-NEXT: unreachable1164; CHECK: 9:1165; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x i32>, ptr [[B]], align 81166; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641167; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761168; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1169; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 81170; CHECK-NEXT: [[_MSPROP:%.*]] = zext <2 x i32> [[_MSLD1]] to <2 x i64>1171; CHECK-NEXT: [[TMPVAR3:%.*]] = zext <2 x i32> [[TMPVAR2]] to <2 x i64>1172; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i64> [[_MSLD]], [[_MSPROP]]1173; CHECK-NEXT: [[TMP4:%.*]] = add <2 x i64> [[TMPVAR1]], [[TMPVAR3]]1174; CHECK-NEXT: store <2 x i64> [[_MSPROP2]], ptr @__msan_retval_tls, align 81175; CHECK-NEXT: ret <2 x i64> [[TMP4]]1176;1177 %tmpvar1 = load <2 x i64>, ptr %A1178 %tmpvar2 = load <2 x i32>, ptr %B1179 %tmpvar3 = zext <2 x i32> %tmpvar2 to <2 x i64>1180 %tmpvar4 = add <2 x i64> %tmpvar1, %tmpvar31181 ret <2 x i64> %tmpvar41182}1183 1184define <8 x i16> @uaddw2_8h(ptr %A, ptr %B, <16 x i8> %param1) nounwind #0 {1185; CHECK-LABEL: define <8 x i16> @uaddw2_8h(1186; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], <16 x i8> [[PARAM1:%.*]]) #[[ATTR0]] {1187; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81188; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81189; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81190; CHECK-NEXT: call void @llvm.donothing()1191; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01192; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP4:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]1193; CHECK: 4:1194; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1195; CHECK-NEXT: unreachable1196; CHECK: 5:1197; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i16>, ptr [[A]], align 161198; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641199; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761200; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1201; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 161202; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP2]], 01203; CHECK-NEXT: br i1 [[_MSCMP4]], label [[TMP9:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]1204; CHECK: 9:1205; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1206; CHECK-NEXT: unreachable1207; CHECK: 10:1208; CHECK-NEXT: [[TMPVAR2:%.*]] = load <16 x i8>, ptr [[B]], align 161209; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641210; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761211; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1212; CHECK-NEXT: [[_MSLD1:%.*]] = load <16 x i8>, ptr [[TMP12]], align 161213; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <16 x i8> [[_MSLD1]], <16 x i8> [[TMP3]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1214; CHECK-NEXT: [[HIGH2:%.*]] = shufflevector <16 x i8> [[TMPVAR2]], <16 x i8> [[PARAM1]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1215; CHECK-NEXT: [[_MSPROP2:%.*]] = zext <8 x i8> [[_MSPROP]] to <8 x i16>1216; CHECK-NEXT: [[EXT2:%.*]] = zext <8 x i8> [[HIGH2]] to <8 x i16>1217; CHECK-NEXT: [[_MSPROP3:%.*]] = or <8 x i16> [[_MSLD]], [[_MSPROP2]]1218; CHECK-NEXT: [[RES:%.*]] = add <8 x i16> [[TMPVAR1]], [[EXT2]]1219; CHECK-NEXT: store <8 x i16> [[_MSPROP3]], ptr @__msan_retval_tls, align 81220; CHECK-NEXT: ret <8 x i16> [[RES]]1221;1222 %tmpvar1 = load <8 x i16>, ptr %A1223 1224 %tmpvar2 = load <16 x i8>, ptr %B1225 %high2 = shufflevector <16 x i8> %tmpvar2, <16 x i8> %param1, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1226 %ext2 = zext <8 x i8> %high2 to <8 x i16>1227 1228 %res = add <8 x i16> %tmpvar1, %ext21229 ret <8 x i16> %res1230}1231 1232define <4 x i32> @uaddw2_4s(ptr %A, ptr %B, <8 x i16> %param1) nounwind #0 {1233; CHECK-LABEL: define <4 x i32> @uaddw2_4s(1234; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], <8 x i16> [[PARAM1:%.*]]) #[[ATTR0]] {1235; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81236; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81237; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81238; CHECK-NEXT: call void @llvm.donothing()1239; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01240; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP4:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]1241; CHECK: 4:1242; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1243; CHECK-NEXT: unreachable1244; CHECK: 5:1245; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i32>, ptr [[A]], align 161246; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641247; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761248; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1249; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 161250; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP2]], 01251; CHECK-NEXT: br i1 [[_MSCMP4]], label [[TMP9:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]1252; CHECK: 9:1253; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1254; CHECK-NEXT: unreachable1255; CHECK: 10:1256; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i16>, ptr [[B]], align 161257; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641258; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761259; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1260; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 161261; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i16> [[_MSLD1]], <8 x i16> [[TMP3]], <4 x i32> <i32 4, i32 5, i32 6, i32 7>1262; CHECK-NEXT: [[HIGH2:%.*]] = shufflevector <8 x i16> [[TMPVAR2]], <8 x i16> [[PARAM1]], <4 x i32> <i32 4, i32 5, i32 6, i32 7>1263; CHECK-NEXT: [[_MSPROP2:%.*]] = zext <4 x i16> [[_MSPROP]] to <4 x i32>1264; CHECK-NEXT: [[EXT2:%.*]] = zext <4 x i16> [[HIGH2]] to <4 x i32>1265; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i32> [[_MSLD]], [[_MSPROP2]]1266; CHECK-NEXT: [[RES:%.*]] = add <4 x i32> [[TMPVAR1]], [[EXT2]]1267; CHECK-NEXT: store <4 x i32> [[_MSPROP3]], ptr @__msan_retval_tls, align 81268; CHECK-NEXT: ret <4 x i32> [[RES]]1269;1270 %tmpvar1 = load <4 x i32>, ptr %A1271 1272 %tmpvar2 = load <8 x i16>, ptr %B1273 %high2 = shufflevector <8 x i16> %tmpvar2, <8 x i16> %param1, <4 x i32> <i32 4, i32 5, i32 6, i32 7>1274 %ext2 = zext <4 x i16> %high2 to <4 x i32>1275 1276 %res = add <4 x i32> %tmpvar1, %ext21277 ret <4 x i32> %res1278}1279 1280define <2 x i64> @uaddw2_2d(ptr %A, ptr %B, <4 x i32> %param1) nounwind #0 {1281; CHECK-LABEL: define <2 x i64> @uaddw2_2d(1282; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], <4 x i32> [[PARAM1:%.*]]) #[[ATTR0]] {1283; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81284; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81285; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81286; CHECK-NEXT: call void @llvm.donothing()1287; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01288; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP4:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]1289; CHECK: 4:1290; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1291; CHECK-NEXT: unreachable1292; CHECK: 5:1293; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i64>, ptr [[A]], align 161294; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641295; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761296; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1297; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 161298; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP2]], 01299; CHECK-NEXT: br i1 [[_MSCMP4]], label [[TMP9:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]1300; CHECK: 9:1301; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1302; CHECK-NEXT: unreachable1303; CHECK: 10:1304; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i32>, ptr [[B]], align 161305; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641306; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761307; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1308; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 161309; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i32> [[_MSLD1]], <4 x i32> [[TMP3]], <2 x i32> <i32 2, i32 3>1310; CHECK-NEXT: [[HIGH2:%.*]] = shufflevector <4 x i32> [[TMPVAR2]], <4 x i32> [[PARAM1]], <2 x i32> <i32 2, i32 3>1311; CHECK-NEXT: [[_MSPROP2:%.*]] = zext <2 x i32> [[_MSPROP]] to <2 x i64>1312; CHECK-NEXT: [[EXT2:%.*]] = zext <2 x i32> [[HIGH2]] to <2 x i64>1313; CHECK-NEXT: [[_MSPROP3:%.*]] = or <2 x i64> [[_MSLD]], [[_MSPROP2]]1314; CHECK-NEXT: [[RES:%.*]] = add <2 x i64> [[TMPVAR1]], [[EXT2]]1315; CHECK-NEXT: store <2 x i64> [[_MSPROP3]], ptr @__msan_retval_tls, align 81316; CHECK-NEXT: ret <2 x i64> [[RES]]1317;1318 %tmpvar1 = load <2 x i64>, ptr %A1319 1320 %tmpvar2 = load <4 x i32>, ptr %B1321 %high2 = shufflevector <4 x i32> %tmpvar2, <4 x i32> %param1, <2 x i32> <i32 2, i32 3>1322 %ext2 = zext <2 x i32> %high2 to <2 x i64>1323 1324 %res = add <2 x i64> %tmpvar1, %ext21325 ret <2 x i64> %res1326}1327 1328define <8 x i16> @saddw8h(ptr %A, ptr %B) nounwind #0 {1329; CHECK-LABEL: define <8 x i16> @saddw8h(1330; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1331; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81332; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81333; CHECK-NEXT: call void @llvm.donothing()1334; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01335; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]1336; CHECK: 3:1337; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1338; CHECK-NEXT: unreachable1339; CHECK: 4:1340; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i16>, ptr [[A]], align 161341; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641342; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761343; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1344; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 161345; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 01346; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1347; CHECK: 8:1348; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1349; CHECK-NEXT: unreachable1350; CHECK: 9:1351; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i8>, ptr [[B]], align 81352; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641353; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761354; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1355; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP12]], align 81356; CHECK-NEXT: [[_MSPROP:%.*]] = sext <8 x i8> [[_MSLD1]] to <8 x i16>1357; CHECK-NEXT: [[TMPVAR3:%.*]] = sext <8 x i8> [[TMPVAR2]] to <8 x i16>1358; CHECK-NEXT: [[_MSPROP2:%.*]] = or <8 x i16> [[_MSLD]], [[_MSPROP]]1359; CHECK-NEXT: [[TMP4:%.*]] = add <8 x i16> [[TMPVAR1]], [[TMPVAR3]]1360; CHECK-NEXT: store <8 x i16> [[_MSPROP2]], ptr @__msan_retval_tls, align 81361; CHECK-NEXT: ret <8 x i16> [[TMP4]]1362;1363 %tmpvar1 = load <8 x i16>, ptr %A1364 %tmpvar2 = load <8 x i8>, ptr %B1365 %tmpvar3 = sext <8 x i8> %tmpvar2 to <8 x i16>1366 %tmpvar4 = add <8 x i16> %tmpvar1, %tmpvar31367 ret <8 x i16> %tmpvar41368}1369 1370define <4 x i32> @saddw4s(ptr %A, ptr %B) nounwind #0 {1371; CHECK-LABEL: define <4 x i32> @saddw4s(1372; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1373; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81374; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81375; CHECK-NEXT: call void @llvm.donothing()1376; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01377; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]1378; CHECK: 3:1379; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1380; CHECK-NEXT: unreachable1381; CHECK: 4:1382; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i32>, ptr [[A]], align 161383; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641384; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761385; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1386; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 161387; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 01388; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1389; CHECK: 8:1390; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1391; CHECK-NEXT: unreachable1392; CHECK: 9:1393; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i16>, ptr [[B]], align 81394; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641395; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761396; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1397; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 81398; CHECK-NEXT: [[_MSPROP:%.*]] = sext <4 x i16> [[_MSLD1]] to <4 x i32>1399; CHECK-NEXT: [[TMPVAR3:%.*]] = sext <4 x i16> [[TMPVAR2]] to <4 x i32>1400; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i32> [[_MSLD]], [[_MSPROP]]1401; CHECK-NEXT: [[TMP4:%.*]] = add <4 x i32> [[TMPVAR1]], [[TMPVAR3]]1402; CHECK-NEXT: store <4 x i32> [[_MSPROP2]], ptr @__msan_retval_tls, align 81403; CHECK-NEXT: ret <4 x i32> [[TMP4]]1404;1405 %tmpvar1 = load <4 x i32>, ptr %A1406 %tmpvar2 = load <4 x i16>, ptr %B1407 %tmpvar3 = sext <4 x i16> %tmpvar2 to <4 x i32>1408 %tmpvar4 = add <4 x i32> %tmpvar1, %tmpvar31409 ret <4 x i32> %tmpvar41410}1411 1412define <2 x i64> @saddw2d(ptr %A, ptr %B) nounwind #0 {1413; CHECK-LABEL: define <2 x i64> @saddw2d(1414; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1415; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81416; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81417; CHECK-NEXT: call void @llvm.donothing()1418; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01419; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]1420; CHECK: 3:1421; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1422; CHECK-NEXT: unreachable1423; CHECK: 4:1424; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i64>, ptr [[A]], align 161425; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641426; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761427; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1428; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 161429; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 01430; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1431; CHECK: 8:1432; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1433; CHECK-NEXT: unreachable1434; CHECK: 9:1435; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x i32>, ptr [[B]], align 81436; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641437; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761438; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1439; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 81440; CHECK-NEXT: [[_MSPROP:%.*]] = sext <2 x i32> [[_MSLD1]] to <2 x i64>1441; CHECK-NEXT: [[TMPVAR3:%.*]] = sext <2 x i32> [[TMPVAR2]] to <2 x i64>1442; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i64> [[_MSLD]], [[_MSPROP]]1443; CHECK-NEXT: [[TMP4:%.*]] = add <2 x i64> [[TMPVAR1]], [[TMPVAR3]]1444; CHECK-NEXT: store <2 x i64> [[_MSPROP2]], ptr @__msan_retval_tls, align 81445; CHECK-NEXT: ret <2 x i64> [[TMP4]]1446;1447 %tmpvar1 = load <2 x i64>, ptr %A1448 %tmpvar2 = load <2 x i32>, ptr %B1449 %tmpvar3 = sext <2 x i32> %tmpvar2 to <2 x i64>1450 %tmpvar4 = add <2 x i64> %tmpvar1, %tmpvar31451 ret <2 x i64> %tmpvar41452}1453 1454define <8 x i16> @saddw2_8h(ptr %A, ptr %B, <16 x i8> %param1) nounwind #0 {1455; CHECK-LABEL: define <8 x i16> @saddw2_8h(1456; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], <16 x i8> [[PARAM1:%.*]]) #[[ATTR0]] {1457; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81458; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81459; CHECK-NEXT: [[TMP3:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81460; CHECK-NEXT: call void @llvm.donothing()1461; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01462; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP4:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]1463; CHECK: 4:1464; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1465; CHECK-NEXT: unreachable1466; CHECK: 5:1467; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i16>, ptr [[A]], align 161468; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641469; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761470; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1471; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 161472; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP2]], 01473; CHECK-NEXT: br i1 [[_MSCMP4]], label [[TMP9:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]1474; CHECK: 9:1475; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1476; CHECK-NEXT: unreachable1477; CHECK: 10:1478; CHECK-NEXT: [[TMPVAR2:%.*]] = load <16 x i8>, ptr [[B]], align 161479; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641480; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761481; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1482; CHECK-NEXT: [[_MSLD1:%.*]] = load <16 x i8>, ptr [[TMP12]], align 161483; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <16 x i8> [[_MSLD1]], <16 x i8> [[TMP3]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1484; CHECK-NEXT: [[HIGH2:%.*]] = shufflevector <16 x i8> [[TMPVAR2]], <16 x i8> [[PARAM1]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1485; CHECK-NEXT: [[_MSPROP2:%.*]] = sext <8 x i8> [[_MSPROP]] to <8 x i16>1486; CHECK-NEXT: [[EXT2:%.*]] = sext <8 x i8> [[HIGH2]] to <8 x i16>1487; CHECK-NEXT: [[_MSPROP3:%.*]] = or <8 x i16> [[_MSLD]], [[_MSPROP2]]1488; CHECK-NEXT: [[RES:%.*]] = add <8 x i16> [[TMPVAR1]], [[EXT2]]1489; CHECK-NEXT: store <8 x i16> [[_MSPROP3]], ptr @__msan_retval_tls, align 81490; CHECK-NEXT: ret <8 x i16> [[RES]]1491;1492 %tmpvar1 = load <8 x i16>, ptr %A1493 1494 %tmpvar2 = load <16 x i8>, ptr %B1495 %high2 = shufflevector <16 x i8> %tmpvar2, <16 x i8> %param1, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>1496 %ext2 = sext <8 x i8> %high2 to <8 x i16>1497 1498 %res = add <8 x i16> %tmpvar1, %ext21499 ret <8 x i16> %res1500}1501 1502define <4 x i32> @saddw2_4s(ptr %A, ptr %B, <8 x i16> %param1) nounwind #0 {1503; CHECK-LABEL: define <4 x i32> @saddw2_4s(1504; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], <8 x i16> [[PARAM1:%.*]]) #[[ATTR0]] {1505; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81506; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81507; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81508; CHECK-NEXT: call void @llvm.donothing()1509; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01510; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP4:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]1511; CHECK: 4:1512; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1513; CHECK-NEXT: unreachable1514; CHECK: 5:1515; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i32>, ptr [[A]], align 161516; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641517; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761518; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1519; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 161520; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP2]], 01521; CHECK-NEXT: br i1 [[_MSCMP4]], label [[TMP9:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]1522; CHECK: 9:1523; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1524; CHECK-NEXT: unreachable1525; CHECK: 10:1526; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i16>, ptr [[B]], align 161527; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641528; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761529; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1530; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 161531; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i16> [[_MSLD1]], <8 x i16> [[TMP3]], <4 x i32> <i32 4, i32 5, i32 6, i32 7>1532; CHECK-NEXT: [[HIGH2:%.*]] = shufflevector <8 x i16> [[TMPVAR2]], <8 x i16> [[PARAM1]], <4 x i32> <i32 4, i32 5, i32 6, i32 7>1533; CHECK-NEXT: [[_MSPROP2:%.*]] = sext <4 x i16> [[_MSPROP]] to <4 x i32>1534; CHECK-NEXT: [[EXT2:%.*]] = sext <4 x i16> [[HIGH2]] to <4 x i32>1535; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i32> [[_MSLD]], [[_MSPROP2]]1536; CHECK-NEXT: [[RES:%.*]] = add <4 x i32> [[TMPVAR1]], [[EXT2]]1537; CHECK-NEXT: store <4 x i32> [[_MSPROP3]], ptr @__msan_retval_tls, align 81538; CHECK-NEXT: ret <4 x i32> [[RES]]1539;1540 %tmpvar1 = load <4 x i32>, ptr %A1541 1542 %tmpvar2 = load <8 x i16>, ptr %B1543 %high2 = shufflevector <8 x i16> %tmpvar2, <8 x i16> %param1, <4 x i32> <i32 4, i32 5, i32 6, i32 7>1544 %ext2 = sext <4 x i16> %high2 to <4 x i32>1545 1546 %res = add <4 x i32> %tmpvar1, %ext21547 ret <4 x i32> %res1548}1549 1550define <2 x i64> @saddw2_2d(ptr %A, ptr %B, <4 x i32> %param1) nounwind #0 {1551; CHECK-LABEL: define <2 x i64> @saddw2_2d(1552; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], <4 x i32> [[PARAM1:%.*]]) #[[ATTR0]] {1553; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81554; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81555; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81556; CHECK-NEXT: call void @llvm.donothing()1557; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01558; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP4:%.*]], label [[TMP8:%.*]], !prof [[PROF1]]1559; CHECK: 4:1560; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1561; CHECK-NEXT: unreachable1562; CHECK: 5:1563; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i64>, ptr [[A]], align 161564; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641565; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761566; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1567; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 161568; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP2]], 01569; CHECK-NEXT: br i1 [[_MSCMP4]], label [[TMP9:%.*]], label [[TMP13:%.*]], !prof [[PROF1]]1570; CHECK: 9:1571; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1572; CHECK-NEXT: unreachable1573; CHECK: 10:1574; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i32>, ptr [[B]], align 161575; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641576; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761577; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1578; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 161579; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i32> [[_MSLD1]], <4 x i32> [[TMP3]], <2 x i32> <i32 2, i32 3>1580; CHECK-NEXT: [[HIGH2:%.*]] = shufflevector <4 x i32> [[TMPVAR2]], <4 x i32> [[PARAM1]], <2 x i32> <i32 2, i32 3>1581; CHECK-NEXT: [[_MSPROP2:%.*]] = sext <2 x i32> [[_MSPROP]] to <2 x i64>1582; CHECK-NEXT: [[EXT2:%.*]] = sext <2 x i32> [[HIGH2]] to <2 x i64>1583; CHECK-NEXT: [[_MSPROP3:%.*]] = or <2 x i64> [[_MSLD]], [[_MSPROP2]]1584; CHECK-NEXT: [[RES:%.*]] = add <2 x i64> [[TMPVAR1]], [[EXT2]]1585; CHECK-NEXT: store <2 x i64> [[_MSPROP3]], ptr @__msan_retval_tls, align 81586; CHECK-NEXT: ret <2 x i64> [[RES]]1587;1588 %tmpvar1 = load <2 x i64>, ptr %A1589 1590 %tmpvar2 = load <4 x i32>, ptr %B1591 %high2 = shufflevector <4 x i32> %tmpvar2, <4 x i32> %param1, <2 x i32> <i32 2, i32 3>1592 %ext2 = sext <2 x i32> %high2 to <2 x i64>1593 1594 %res = add <2 x i64> %tmpvar1, %ext21595 ret <2 x i64> %res1596}1597 1598define <4 x i16> @saddlp4h(ptr %A) nounwind #0 {1599; CHECK-LABEL: define <4 x i16> @saddlp4h(1600; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {1601; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81602; CHECK-NEXT: call void @llvm.donothing()1603; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01604; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]1605; CHECK: 2:1606; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1607; CHECK-NEXT: unreachable1608; CHECK: 3:1609; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i8>, ptr [[A]], align 81610; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i641611; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885761612; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr1613; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP6]], align 81614; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <8 x i8> [[_MSLD]], <8 x i8> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>1615; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <8 x i8> [[_MSLD]], <8 x i8> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>1616; CHECK-NEXT: [[TMP9:%.*]] = or <4 x i8> [[TMP7]], [[TMP8]]1617; CHECK-NEXT: [[TMP10:%.*]] = zext <4 x i8> [[TMP9]] to <4 x i16>1618; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.saddlp.v4i16.v8i8(<8 x i8> [[TMPVAR1]])1619; CHECK-NEXT: store <4 x i16> [[TMP10]], ptr @__msan_retval_tls, align 81620; CHECK-NEXT: ret <4 x i16> [[TMP3]]1621;1622 %tmpvar1 = load <8 x i8>, ptr %A1623 %tmpvar3 = call <4 x i16> @llvm.aarch64.neon.saddlp.v4i16.v8i8(<8 x i8> %tmpvar1)1624 ret <4 x i16> %tmpvar31625}1626 1627define <2 x i32> @saddlp2s(ptr %A) nounwind #0 {1628; CHECK-LABEL: define <2 x i32> @saddlp2s(1629; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {1630; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81631; CHECK-NEXT: call void @llvm.donothing()1632; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01633; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]1634; CHECK: 2:1635; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1636; CHECK-NEXT: unreachable1637; CHECK: 3:1638; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i16>, ptr [[A]], align 81639; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i641640; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885761641; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr1642; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP6]], align 81643; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i16> [[_MSLD]], <4 x i16> poison, <2 x i32> <i32 0, i32 2>1644; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i16> [[_MSLD]], <4 x i16> poison, <2 x i32> <i32 1, i32 3>1645; CHECK-NEXT: [[TMP9:%.*]] = or <2 x i16> [[TMP7]], [[TMP8]]1646; CHECK-NEXT: [[TMP10:%.*]] = zext <2 x i16> [[TMP9]] to <2 x i32>1647; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.saddlp.v2i32.v4i16(<4 x i16> [[TMPVAR1]])1648; CHECK-NEXT: store <2 x i32> [[TMP10]], ptr @__msan_retval_tls, align 81649; CHECK-NEXT: ret <2 x i32> [[TMP3]]1650;1651 %tmpvar1 = load <4 x i16>, ptr %A1652 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.saddlp.v2i32.v4i16(<4 x i16> %tmpvar1)1653 ret <2 x i32> %tmpvar31654}1655 1656define <1 x i64> @saddlp1d(ptr %A) nounwind #0 {1657; CHECK-LABEL: define <1 x i64> @saddlp1d(1658; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {1659; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81660; CHECK-NEXT: call void @llvm.donothing()1661; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01662; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]1663; CHECK: 2:1664; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1665; CHECK-NEXT: unreachable1666; CHECK: 3:1667; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i32>, ptr [[A]], align 81668; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i641669; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885761670; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr1671; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP6]], align 81672; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x i32> [[_MSLD]], <2 x i32> poison, <1 x i32> zeroinitializer1673; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x i32> [[_MSLD]], <2 x i32> poison, <1 x i32> <i32 1>1674; CHECK-NEXT: [[TMP9:%.*]] = or <1 x i32> [[TMP7]], [[TMP8]]1675; CHECK-NEXT: [[TMP10:%.*]] = zext <1 x i32> [[TMP9]] to <1 x i64>1676; CHECK-NEXT: [[TMP3:%.*]] = call <1 x i64> @llvm.aarch64.neon.saddlp.v1i64.v2i32(<2 x i32> [[TMPVAR1]])1677; CHECK-NEXT: store <1 x i64> [[TMP10]], ptr @__msan_retval_tls, align 81678; CHECK-NEXT: ret <1 x i64> [[TMP3]]1679;1680 %tmpvar1 = load <2 x i32>, ptr %A1681 %tmpvar3 = call <1 x i64> @llvm.aarch64.neon.saddlp.v1i64.v2i32(<2 x i32> %tmpvar1)1682 ret <1 x i64> %tmpvar31683}1684 1685define <8 x i16> @saddlp8h(ptr %A) nounwind #0 {1686; CHECK-LABEL: define <8 x i16> @saddlp8h(1687; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {1688; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81689; CHECK-NEXT: call void @llvm.donothing()1690; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01691; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]1692; CHECK: 2:1693; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1694; CHECK-NEXT: unreachable1695; CHECK: 3:1696; CHECK-NEXT: [[TMPVAR1:%.*]] = load <16 x i8>, ptr [[A]], align 161697; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i641698; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885761699; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr1700; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP6]], align 161701; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <16 x i8> [[_MSLD]], <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>1702; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <16 x i8> [[_MSLD]], <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>1703; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i8> [[TMP7]], [[TMP8]]1704; CHECK-NEXT: [[TMP10:%.*]] = zext <8 x i8> [[TMP9]] to <8 x i16>1705; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i16> @llvm.aarch64.neon.saddlp.v8i16.v16i8(<16 x i8> [[TMPVAR1]])1706; CHECK-NEXT: store <8 x i16> [[TMP10]], ptr @__msan_retval_tls, align 81707; CHECK-NEXT: ret <8 x i16> [[TMP3]]1708;1709 %tmpvar1 = load <16 x i8>, ptr %A1710 %tmpvar3 = call <8 x i16> @llvm.aarch64.neon.saddlp.v8i16.v16i8(<16 x i8> %tmpvar1)1711 ret <8 x i16> %tmpvar31712}1713 1714define <4 x i32> @saddlp4s(ptr %A) nounwind #0 {1715; CHECK-LABEL: define <4 x i32> @saddlp4s(1716; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {1717; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81718; CHECK-NEXT: call void @llvm.donothing()1719; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01720; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]1721; CHECK: 2:1722; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1723; CHECK-NEXT: unreachable1724; CHECK: 3:1725; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i16>, ptr [[A]], align 161726; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i641727; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885761728; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr1729; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP6]], align 161730; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <8 x i16> [[_MSLD]], <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>1731; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <8 x i16> [[_MSLD]], <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>1732; CHECK-NEXT: [[TMP9:%.*]] = or <4 x i16> [[TMP7]], [[TMP8]]1733; CHECK-NEXT: [[TMP10:%.*]] = zext <4 x i16> [[TMP9]] to <4 x i32>1734; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.saddlp.v4i32.v8i16(<8 x i16> [[TMPVAR1]])1735; CHECK-NEXT: store <4 x i32> [[TMP10]], ptr @__msan_retval_tls, align 81736; CHECK-NEXT: ret <4 x i32> [[TMP3]]1737;1738 %tmpvar1 = load <8 x i16>, ptr %A1739 %tmpvar3 = call <4 x i32> @llvm.aarch64.neon.saddlp.v4i32.v8i16(<8 x i16> %tmpvar1)1740 ret <4 x i32> %tmpvar31741}1742 1743define <2 x i64> @saddlp2d(ptr %A) nounwind #0 {1744; CHECK-LABEL: define <2 x i64> @saddlp2d(1745; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {1746; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81747; CHECK-NEXT: call void @llvm.donothing()1748; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01749; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]1750; CHECK: 2:1751; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1752; CHECK-NEXT: unreachable1753; CHECK: 3:1754; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i32>, ptr [[A]], align 161755; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i641756; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885761757; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr1758; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP6]], align 161759; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> poison, <2 x i32> <i32 0, i32 2>1760; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> poison, <2 x i32> <i32 1, i32 3>1761; CHECK-NEXT: [[TMP9:%.*]] = or <2 x i32> [[TMP7]], [[TMP8]]1762; CHECK-NEXT: [[TMP10:%.*]] = zext <2 x i32> [[TMP9]] to <2 x i64>1763; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.saddlp.v2i64.v4i32(<4 x i32> [[TMPVAR1]])1764; CHECK-NEXT: store <2 x i64> [[TMP10]], ptr @__msan_retval_tls, align 81765; CHECK-NEXT: ret <2 x i64> [[TMP3]]1766;1767 %tmpvar1 = load <4 x i32>, ptr %A1768 %tmpvar3 = call <2 x i64> @llvm.aarch64.neon.saddlp.v2i64.v4i32(<4 x i32> %tmpvar1)1769 ret <2 x i64> %tmpvar31770}1771 1772declare <4 x i16> @llvm.aarch64.neon.saddlp.v4i16.v8i8(<8 x i8>) nounwind readnone1773declare <2 x i32> @llvm.aarch64.neon.saddlp.v2i32.v4i16(<4 x i16>) nounwind readnone1774declare <1 x i64> @llvm.aarch64.neon.saddlp.v1i64.v2i32(<2 x i32>) nounwind readnone1775 1776declare <8 x i16> @llvm.aarch64.neon.saddlp.v8i16.v16i8(<16 x i8>) nounwind readnone1777declare <4 x i32> @llvm.aarch64.neon.saddlp.v4i32.v8i16(<8 x i16>) nounwind readnone1778declare <2 x i64> @llvm.aarch64.neon.saddlp.v2i64.v4i32(<4 x i32>) nounwind readnone1779 1780define <4 x i16> @uaddlp4h(ptr %A) nounwind #0 {1781; CHECK-LABEL: define <4 x i16> @uaddlp4h(1782; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {1783; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81784; CHECK-NEXT: call void @llvm.donothing()1785; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01786; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]1787; CHECK: 2:1788; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1789; CHECK-NEXT: unreachable1790; CHECK: 3:1791; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i8>, ptr [[A]], align 81792; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i641793; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885761794; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr1795; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP6]], align 81796; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <8 x i8> [[_MSLD]], <8 x i8> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>1797; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <8 x i8> [[_MSLD]], <8 x i8> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>1798; CHECK-NEXT: [[TMP9:%.*]] = or <4 x i8> [[TMP7]], [[TMP8]]1799; CHECK-NEXT: [[TMP10:%.*]] = zext <4 x i8> [[TMP9]] to <4 x i16>1800; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.uaddlp.v4i16.v8i8(<8 x i8> [[TMPVAR1]])1801; CHECK-NEXT: store <4 x i16> [[TMP10]], ptr @__msan_retval_tls, align 81802; CHECK-NEXT: ret <4 x i16> [[TMP3]]1803;1804 %tmpvar1 = load <8 x i8>, ptr %A1805 %tmpvar3 = call <4 x i16> @llvm.aarch64.neon.uaddlp.v4i16.v8i8(<8 x i8> %tmpvar1)1806 ret <4 x i16> %tmpvar31807}1808 1809define <2 x i32> @uaddlp2s(ptr %A) nounwind #0 {1810; CHECK-LABEL: define <2 x i32> @uaddlp2s(1811; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {1812; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81813; CHECK-NEXT: call void @llvm.donothing()1814; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01815; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]1816; CHECK: 2:1817; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1818; CHECK-NEXT: unreachable1819; CHECK: 3:1820; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i16>, ptr [[A]], align 81821; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i641822; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885761823; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr1824; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP6]], align 81825; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i16> [[_MSLD]], <4 x i16> poison, <2 x i32> <i32 0, i32 2>1826; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i16> [[_MSLD]], <4 x i16> poison, <2 x i32> <i32 1, i32 3>1827; CHECK-NEXT: [[TMP9:%.*]] = or <2 x i16> [[TMP7]], [[TMP8]]1828; CHECK-NEXT: [[TMP10:%.*]] = zext <2 x i16> [[TMP9]] to <2 x i32>1829; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.uaddlp.v2i32.v4i16(<4 x i16> [[TMPVAR1]])1830; CHECK-NEXT: store <2 x i32> [[TMP10]], ptr @__msan_retval_tls, align 81831; CHECK-NEXT: ret <2 x i32> [[TMP3]]1832;1833 %tmpvar1 = load <4 x i16>, ptr %A1834 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.uaddlp.v2i32.v4i16(<4 x i16> %tmpvar1)1835 ret <2 x i32> %tmpvar31836}1837 1838define <1 x i64> @uaddlp1d(ptr %A) nounwind #0 {1839; CHECK-LABEL: define <1 x i64> @uaddlp1d(1840; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {1841; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81842; CHECK-NEXT: call void @llvm.donothing()1843; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01844; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]1845; CHECK: 2:1846; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1847; CHECK-NEXT: unreachable1848; CHECK: 3:1849; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i32>, ptr [[A]], align 81850; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i641851; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885761852; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr1853; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP6]], align 81854; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <2 x i32> [[_MSLD]], <2 x i32> poison, <1 x i32> zeroinitializer1855; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <2 x i32> [[_MSLD]], <2 x i32> poison, <1 x i32> <i32 1>1856; CHECK-NEXT: [[TMP9:%.*]] = or <1 x i32> [[TMP7]], [[TMP8]]1857; CHECK-NEXT: [[TMP10:%.*]] = zext <1 x i32> [[TMP9]] to <1 x i64>1858; CHECK-NEXT: [[TMP3:%.*]] = call <1 x i64> @llvm.aarch64.neon.uaddlp.v1i64.v2i32(<2 x i32> [[TMPVAR1]])1859; CHECK-NEXT: store <1 x i64> [[TMP10]], ptr @__msan_retval_tls, align 81860; CHECK-NEXT: ret <1 x i64> [[TMP3]]1861;1862 %tmpvar1 = load <2 x i32>, ptr %A1863 %tmpvar3 = call <1 x i64> @llvm.aarch64.neon.uaddlp.v1i64.v2i32(<2 x i32> %tmpvar1)1864 ret <1 x i64> %tmpvar31865}1866 1867define <8 x i16> @uaddlp8h(ptr %A) nounwind #0 {1868; CHECK-LABEL: define <8 x i16> @uaddlp8h(1869; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {1870; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81871; CHECK-NEXT: call void @llvm.donothing()1872; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01873; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]1874; CHECK: 2:1875; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1876; CHECK-NEXT: unreachable1877; CHECK: 3:1878; CHECK-NEXT: [[TMPVAR1:%.*]] = load <16 x i8>, ptr [[A]], align 161879; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i641880; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885761881; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr1882; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP6]], align 161883; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <16 x i8> [[_MSLD]], <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>1884; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <16 x i8> [[_MSLD]], <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>1885; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i8> [[TMP7]], [[TMP8]]1886; CHECK-NEXT: [[TMP10:%.*]] = zext <8 x i8> [[TMP9]] to <8 x i16>1887; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i16> @llvm.aarch64.neon.uaddlp.v8i16.v16i8(<16 x i8> [[TMPVAR1]])1888; CHECK-NEXT: store <8 x i16> [[TMP10]], ptr @__msan_retval_tls, align 81889; CHECK-NEXT: ret <8 x i16> [[TMP3]]1890;1891 %tmpvar1 = load <16 x i8>, ptr %A1892 %tmpvar3 = call <8 x i16> @llvm.aarch64.neon.uaddlp.v8i16.v16i8(<16 x i8> %tmpvar1)1893 ret <8 x i16> %tmpvar31894}1895 1896define <4 x i32> @uaddlp4s(ptr %A) nounwind #0 {1897; CHECK-LABEL: define <4 x i32> @uaddlp4s(1898; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {1899; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81900; CHECK-NEXT: call void @llvm.donothing()1901; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01902; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]1903; CHECK: 2:1904; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1905; CHECK-NEXT: unreachable1906; CHECK: 3:1907; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i16>, ptr [[A]], align 161908; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i641909; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885761910; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr1911; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP6]], align 161912; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <8 x i16> [[_MSLD]], <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>1913; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <8 x i16> [[_MSLD]], <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>1914; CHECK-NEXT: [[TMP9:%.*]] = or <4 x i16> [[TMP7]], [[TMP8]]1915; CHECK-NEXT: [[TMP10:%.*]] = zext <4 x i16> [[TMP9]] to <4 x i32>1916; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.uaddlp.v4i32.v8i16(<8 x i16> [[TMPVAR1]])1917; CHECK-NEXT: store <4 x i32> [[TMP10]], ptr @__msan_retval_tls, align 81918; CHECK-NEXT: ret <4 x i32> [[TMP3]]1919;1920 %tmpvar1 = load <8 x i16>, ptr %A1921 %tmpvar3 = call <4 x i32> @llvm.aarch64.neon.uaddlp.v4i32.v8i16(<8 x i16> %tmpvar1)1922 ret <4 x i32> %tmpvar31923}1924 1925define <2 x i64> @uaddlp2d(ptr %A) nounwind #0 {1926; CHECK-LABEL: define <2 x i64> @uaddlp2d(1927; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {1928; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81929; CHECK-NEXT: call void @llvm.donothing()1930; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01931; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]1932; CHECK: 2:1933; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1934; CHECK-NEXT: unreachable1935; CHECK: 3:1936; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i32>, ptr [[A]], align 161937; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i641938; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885761939; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr1940; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP6]], align 161941; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> poison, <2 x i32> <i32 0, i32 2>1942; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> poison, <2 x i32> <i32 1, i32 3>1943; CHECK-NEXT: [[TMP9:%.*]] = or <2 x i32> [[TMP7]], [[TMP8]]1944; CHECK-NEXT: [[TMP10:%.*]] = zext <2 x i32> [[TMP9]] to <2 x i64>1945; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.uaddlp.v2i64.v4i32(<4 x i32> [[TMPVAR1]])1946; CHECK-NEXT: store <2 x i64> [[TMP10]], ptr @__msan_retval_tls, align 81947; CHECK-NEXT: ret <2 x i64> [[TMP3]]1948;1949 %tmpvar1 = load <4 x i32>, ptr %A1950 %tmpvar3 = call <2 x i64> @llvm.aarch64.neon.uaddlp.v2i64.v4i32(<4 x i32> %tmpvar1)1951 ret <2 x i64> %tmpvar31952}1953 1954declare <4 x i16> @llvm.aarch64.neon.uaddlp.v4i16.v8i8(<8 x i8>) nounwind readnone1955declare <2 x i32> @llvm.aarch64.neon.uaddlp.v2i32.v4i16(<4 x i16>) nounwind readnone1956declare <1 x i64> @llvm.aarch64.neon.uaddlp.v1i64.v2i32(<2 x i32>) nounwind readnone1957 1958declare <8 x i16> @llvm.aarch64.neon.uaddlp.v8i16.v16i8(<16 x i8>) nounwind readnone1959declare <4 x i32> @llvm.aarch64.neon.uaddlp.v4i32.v8i16(<8 x i16>) nounwind readnone1960declare <2 x i64> @llvm.aarch64.neon.uaddlp.v2i64.v4i32(<4 x i32>) nounwind readnone1961 1962define <4 x i16> @sadalp4h(ptr %A, ptr %B) nounwind #0 {1963; CHECK-LABEL: define <4 x i16> @sadalp4h(1964; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1965; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81966; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81967; CHECK-NEXT: call void @llvm.donothing()1968; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01969; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP16:%.*]], !prof [[PROF1]]1970; CHECK: 3:1971; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1972; CHECK-NEXT: unreachable1973; CHECK: 4:1974; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i8>, ptr [[A]], align 81975; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641976; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761977; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1978; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 81979; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <8 x i8> [[_MSLD]], <8 x i8> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>1980; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <8 x i8> [[_MSLD]], <8 x i8> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>1981; CHECK-NEXT: [[TMP10:%.*]] = or <4 x i8> [[TMP8]], [[TMP9]]1982; CHECK-NEXT: [[TMP11:%.*]] = zext <4 x i8> [[TMP10]] to <4 x i16>1983; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i16> @llvm.aarch64.neon.saddlp.v4i16.v8i8(<8 x i8> [[TMPVAR1]])1984; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 01985; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP12:%.*]], label [[TMP17:%.*]], !prof [[PROF1]]1986; CHECK: 12:1987; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]1988; CHECK-NEXT: unreachable1989; CHECK: 13:1990; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i16>, ptr [[B]], align 81991; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[B]] to i641992; CHECK-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], 1935140464885761993; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to ptr1994; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP15]], align 81995; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[TMP11]], [[_MSLD1]]1996; CHECK-NEXT: [[TMPVAR5:%.*]] = add <4 x i16> [[TMPVAR3]], [[TMP4]]1997; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 81998; CHECK-NEXT: ret <4 x i16> [[TMPVAR5]]1999;2000 %tmpvar1 = load <8 x i8>, ptr %A2001 %tmpvar3 = call <4 x i16> @llvm.aarch64.neon.saddlp.v4i16.v8i8(<8 x i8> %tmpvar1)2002 %tmpvar4 = load <4 x i16>, ptr %B2003 %tmpvar5 = add <4 x i16> %tmpvar3, %tmpvar42004 ret <4 x i16> %tmpvar52005}2006 2007define <2 x i32> @sadalp2s(ptr %A, ptr %B) nounwind #0 {2008; CHECK-LABEL: define <2 x i32> @sadalp2s(2009; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2010; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82011; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82012; CHECK-NEXT: call void @llvm.donothing()2013; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02014; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP16:%.*]], !prof [[PROF1]]2015; CHECK: 3:2016; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2017; CHECK-NEXT: unreachable2018; CHECK: 4:2019; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i16>, ptr [[A]], align 82020; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642021; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762022; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2023; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 82024; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i16> [[_MSLD]], <4 x i16> poison, <2 x i32> <i32 0, i32 2>2025; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <4 x i16> [[_MSLD]], <4 x i16> poison, <2 x i32> <i32 1, i32 3>2026; CHECK-NEXT: [[TMP10:%.*]] = or <2 x i16> [[TMP8]], [[TMP9]]2027; CHECK-NEXT: [[TMP11:%.*]] = zext <2 x i16> [[TMP10]] to <2 x i32>2028; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i32> @llvm.aarch64.neon.saddlp.v2i32.v4i16(<4 x i16> [[TMPVAR1]])2029; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 02030; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP12:%.*]], label [[TMP17:%.*]], !prof [[PROF1]]2031; CHECK: 12:2032; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2033; CHECK-NEXT: unreachable2034; CHECK: 13:2035; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i32>, ptr [[B]], align 82036; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[B]] to i642037; CHECK-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], 1935140464885762038; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to ptr2039; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP15]], align 82040; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[TMP11]], [[_MSLD1]]2041; CHECK-NEXT: [[TMPVAR5:%.*]] = add <2 x i32> [[TMPVAR3]], [[TMP4]]2042; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 82043; CHECK-NEXT: ret <2 x i32> [[TMPVAR5]]2044;2045 %tmpvar1 = load <4 x i16>, ptr %A2046 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.saddlp.v2i32.v4i16(<4 x i16> %tmpvar1)2047 %tmpvar4 = load <2 x i32>, ptr %B2048 %tmpvar5 = add <2 x i32> %tmpvar3, %tmpvar42049 ret <2 x i32> %tmpvar52050}2051 2052define <8 x i16> @sadalp8h(ptr %A, ptr %B) nounwind #0 {2053; CHECK-LABEL: define <8 x i16> @sadalp8h(2054; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2055; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82056; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82057; CHECK-NEXT: call void @llvm.donothing()2058; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02059; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP16:%.*]], !prof [[PROF1]]2060; CHECK: 3:2061; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2062; CHECK-NEXT: unreachable2063; CHECK: 4:2064; CHECK-NEXT: [[TMPVAR1:%.*]] = load <16 x i8>, ptr [[A]], align 162065; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642066; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762067; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2068; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP7]], align 162069; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <16 x i8> [[_MSLD]], <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>2070; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <16 x i8> [[_MSLD]], <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>2071; CHECK-NEXT: [[TMP10:%.*]] = or <8 x i8> [[TMP8]], [[TMP9]]2072; CHECK-NEXT: [[TMP11:%.*]] = zext <8 x i8> [[TMP10]] to <8 x i16>2073; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i16> @llvm.aarch64.neon.saddlp.v8i16.v16i8(<16 x i8> [[TMPVAR1]])2074; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 02075; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP12:%.*]], label [[TMP17:%.*]], !prof [[PROF1]]2076; CHECK: 12:2077; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2078; CHECK-NEXT: unreachable2079; CHECK: 13:2080; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i16>, ptr [[B]], align 162081; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[B]] to i642082; CHECK-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], 1935140464885762083; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to ptr2084; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP15]], align 162085; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP11]], [[_MSLD1]]2086; CHECK-NEXT: [[TMPVAR5:%.*]] = add <8 x i16> [[TMPVAR3]], [[TMP4]]2087; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 82088; CHECK-NEXT: ret <8 x i16> [[TMPVAR5]]2089;2090 %tmpvar1 = load <16 x i8>, ptr %A2091 %tmpvar3 = call <8 x i16> @llvm.aarch64.neon.saddlp.v8i16.v16i8(<16 x i8> %tmpvar1)2092 %tmpvar4 = load <8 x i16>, ptr %B2093 %tmpvar5 = add <8 x i16> %tmpvar3, %tmpvar42094 ret <8 x i16> %tmpvar52095}2096 2097define <4 x i32> @sadalp4s(ptr %A, ptr %B) nounwind #0 {2098; CHECK-LABEL: define <4 x i32> @sadalp4s(2099; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2100; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82101; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82102; CHECK-NEXT: call void @llvm.donothing()2103; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02104; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP16:%.*]], !prof [[PROF1]]2105; CHECK: 3:2106; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2107; CHECK-NEXT: unreachable2108; CHECK: 4:2109; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i16>, ptr [[A]], align 162110; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642111; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762112; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2113; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 162114; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <8 x i16> [[_MSLD]], <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>2115; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <8 x i16> [[_MSLD]], <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>2116; CHECK-NEXT: [[TMP10:%.*]] = or <4 x i16> [[TMP8]], [[TMP9]]2117; CHECK-NEXT: [[TMP11:%.*]] = zext <4 x i16> [[TMP10]] to <4 x i32>2118; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i32> @llvm.aarch64.neon.saddlp.v4i32.v8i16(<8 x i16> [[TMPVAR1]])2119; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 02120; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP12:%.*]], label [[TMP17:%.*]], !prof [[PROF1]]2121; CHECK: 12:2122; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2123; CHECK-NEXT: unreachable2124; CHECK: 13:2125; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr [[B]], align 162126; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[B]] to i642127; CHECK-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], 1935140464885762128; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to ptr2129; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP15]], align 162130; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP11]], [[_MSLD1]]2131; CHECK-NEXT: [[TMPVAR5:%.*]] = add <4 x i32> [[TMPVAR3]], [[TMP4]]2132; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 82133; CHECK-NEXT: ret <4 x i32> [[TMPVAR5]]2134;2135 %tmpvar1 = load <8 x i16>, ptr %A2136 %tmpvar3 = call <4 x i32> @llvm.aarch64.neon.saddlp.v4i32.v8i16(<8 x i16> %tmpvar1)2137 %tmpvar4 = load <4 x i32>, ptr %B2138 %tmpvar5 = add <4 x i32> %tmpvar3, %tmpvar42139 ret <4 x i32> %tmpvar52140}2141 2142define <2 x i64> @sadalp2d(ptr %A, ptr %B) nounwind #0 {2143; CHECK-LABEL: define <2 x i64> @sadalp2d(2144; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2145; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82146; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82147; CHECK-NEXT: call void @llvm.donothing()2148; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02149; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP16:%.*]], !prof [[PROF1]]2150; CHECK: 3:2151; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2152; CHECK-NEXT: unreachable2153; CHECK: 4:2154; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i32>, ptr [[A]], align 162155; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642156; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762157; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2158; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 162159; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> poison, <2 x i32> <i32 0, i32 2>2160; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> poison, <2 x i32> <i32 1, i32 3>2161; CHECK-NEXT: [[TMP10:%.*]] = or <2 x i32> [[TMP8]], [[TMP9]]2162; CHECK-NEXT: [[TMP11:%.*]] = zext <2 x i32> [[TMP10]] to <2 x i64>2163; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i64> @llvm.aarch64.neon.saddlp.v2i64.v4i32(<4 x i32> [[TMPVAR1]])2164; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 02165; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP12:%.*]], label [[TMP17:%.*]], !prof [[PROF1]]2166; CHECK: 12:2167; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2168; CHECK-NEXT: unreachable2169; CHECK: 13:2170; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr [[B]], align 162171; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[B]] to i642172; CHECK-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], 1935140464885762173; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to ptr2174; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP15]], align 162175; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP11]], [[_MSLD1]]2176; CHECK-NEXT: [[TMPVAR5:%.*]] = add <2 x i64> [[TMPVAR3]], [[TMP4]]2177; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 82178; CHECK-NEXT: ret <2 x i64> [[TMPVAR5]]2179;2180 %tmpvar1 = load <4 x i32>, ptr %A2181 %tmpvar3 = call <2 x i64> @llvm.aarch64.neon.saddlp.v2i64.v4i32(<4 x i32> %tmpvar1)2182 %tmpvar4 = load <2 x i64>, ptr %B2183 %tmpvar5 = add <2 x i64> %tmpvar3, %tmpvar42184 ret <2 x i64> %tmpvar52185}2186 2187define <4 x i16> @uadalp4h(ptr %A, ptr %B) nounwind #0 {2188; CHECK-LABEL: define <4 x i16> @uadalp4h(2189; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2190; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82191; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82192; CHECK-NEXT: call void @llvm.donothing()2193; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02194; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP16:%.*]], !prof [[PROF1]]2195; CHECK: 3:2196; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2197; CHECK-NEXT: unreachable2198; CHECK: 4:2199; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i8>, ptr [[A]], align 82200; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642201; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762202; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2203; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 82204; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <8 x i8> [[_MSLD]], <8 x i8> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>2205; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <8 x i8> [[_MSLD]], <8 x i8> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>2206; CHECK-NEXT: [[TMP10:%.*]] = or <4 x i8> [[TMP8]], [[TMP9]]2207; CHECK-NEXT: [[TMP11:%.*]] = zext <4 x i8> [[TMP10]] to <4 x i16>2208; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i16> @llvm.aarch64.neon.uaddlp.v4i16.v8i8(<8 x i8> [[TMPVAR1]])2209; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 02210; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP12:%.*]], label [[TMP17:%.*]], !prof [[PROF1]]2211; CHECK: 12:2212; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2213; CHECK-NEXT: unreachable2214; CHECK: 13:2215; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i16>, ptr [[B]], align 82216; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[B]] to i642217; CHECK-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], 1935140464885762218; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to ptr2219; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP15]], align 82220; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[TMP11]], [[_MSLD1]]2221; CHECK-NEXT: [[TMPVAR5:%.*]] = add <4 x i16> [[TMPVAR3]], [[TMP4]]2222; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 82223; CHECK-NEXT: ret <4 x i16> [[TMPVAR5]]2224;2225 %tmpvar1 = load <8 x i8>, ptr %A2226 %tmpvar3 = call <4 x i16> @llvm.aarch64.neon.uaddlp.v4i16.v8i8(<8 x i8> %tmpvar1)2227 %tmpvar4 = load <4 x i16>, ptr %B2228 %tmpvar5 = add <4 x i16> %tmpvar3, %tmpvar42229 ret <4 x i16> %tmpvar52230}2231 2232define <2 x i32> @uadalp2s(ptr %A, ptr %B) nounwind #0 {2233; CHECK-LABEL: define <2 x i32> @uadalp2s(2234; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2235; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82236; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82237; CHECK-NEXT: call void @llvm.donothing()2238; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02239; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP16:%.*]], !prof [[PROF1]]2240; CHECK: 3:2241; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2242; CHECK-NEXT: unreachable2243; CHECK: 4:2244; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i16>, ptr [[A]], align 82245; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642246; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762247; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2248; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 82249; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i16> [[_MSLD]], <4 x i16> poison, <2 x i32> <i32 0, i32 2>2250; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <4 x i16> [[_MSLD]], <4 x i16> poison, <2 x i32> <i32 1, i32 3>2251; CHECK-NEXT: [[TMP10:%.*]] = or <2 x i16> [[TMP8]], [[TMP9]]2252; CHECK-NEXT: [[TMP11:%.*]] = zext <2 x i16> [[TMP10]] to <2 x i32>2253; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i32> @llvm.aarch64.neon.uaddlp.v2i32.v4i16(<4 x i16> [[TMPVAR1]])2254; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 02255; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP12:%.*]], label [[TMP17:%.*]], !prof [[PROF1]]2256; CHECK: 12:2257; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2258; CHECK-NEXT: unreachable2259; CHECK: 13:2260; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i32>, ptr [[B]], align 82261; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[B]] to i642262; CHECK-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], 1935140464885762263; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to ptr2264; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP15]], align 82265; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[TMP11]], [[_MSLD1]]2266; CHECK-NEXT: [[TMPVAR5:%.*]] = add <2 x i32> [[TMPVAR3]], [[TMP4]]2267; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 82268; CHECK-NEXT: ret <2 x i32> [[TMPVAR5]]2269;2270 %tmpvar1 = load <4 x i16>, ptr %A2271 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.uaddlp.v2i32.v4i16(<4 x i16> %tmpvar1)2272 %tmpvar4 = load <2 x i32>, ptr %B2273 %tmpvar5 = add <2 x i32> %tmpvar3, %tmpvar42274 ret <2 x i32> %tmpvar52275}2276 2277define <8 x i16> @uadalp8h(ptr %A, ptr %B) nounwind #0 {2278; CHECK-LABEL: define <8 x i16> @uadalp8h(2279; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2280; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82281; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82282; CHECK-NEXT: call void @llvm.donothing()2283; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02284; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP16:%.*]], !prof [[PROF1]]2285; CHECK: 3:2286; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2287; CHECK-NEXT: unreachable2288; CHECK: 4:2289; CHECK-NEXT: [[TMPVAR1:%.*]] = load <16 x i8>, ptr [[A]], align 162290; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642291; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762292; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2293; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP7]], align 162294; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <16 x i8> [[_MSLD]], <16 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>2295; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <16 x i8> [[_MSLD]], <16 x i8> poison, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>2296; CHECK-NEXT: [[TMP10:%.*]] = or <8 x i8> [[TMP8]], [[TMP9]]2297; CHECK-NEXT: [[TMP11:%.*]] = zext <8 x i8> [[TMP10]] to <8 x i16>2298; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i16> @llvm.aarch64.neon.uaddlp.v8i16.v16i8(<16 x i8> [[TMPVAR1]])2299; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 02300; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP12:%.*]], label [[TMP17:%.*]], !prof [[PROF1]]2301; CHECK: 12:2302; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2303; CHECK-NEXT: unreachable2304; CHECK: 13:2305; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i16>, ptr [[B]], align 162306; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[B]] to i642307; CHECK-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], 1935140464885762308; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to ptr2309; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP15]], align 162310; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP11]], [[_MSLD1]]2311; CHECK-NEXT: [[TMPVAR5:%.*]] = add <8 x i16> [[TMPVAR3]], [[TMP4]]2312; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 82313; CHECK-NEXT: ret <8 x i16> [[TMPVAR5]]2314;2315 %tmpvar1 = load <16 x i8>, ptr %A2316 %tmpvar3 = call <8 x i16> @llvm.aarch64.neon.uaddlp.v8i16.v16i8(<16 x i8> %tmpvar1)2317 %tmpvar4 = load <8 x i16>, ptr %B2318 %tmpvar5 = add <8 x i16> %tmpvar3, %tmpvar42319 ret <8 x i16> %tmpvar52320}2321 2322define <4 x i32> @uadalp4s(ptr %A, ptr %B) nounwind #0 {2323; CHECK-LABEL: define <4 x i32> @uadalp4s(2324; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2325; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82326; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82327; CHECK-NEXT: call void @llvm.donothing()2328; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02329; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP16:%.*]], !prof [[PROF1]]2330; CHECK: 3:2331; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2332; CHECK-NEXT: unreachable2333; CHECK: 4:2334; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i16>, ptr [[A]], align 162335; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642336; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762337; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2338; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 162339; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <8 x i16> [[_MSLD]], <8 x i16> poison, <4 x i32> <i32 0, i32 2, i32 4, i32 6>2340; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <8 x i16> [[_MSLD]], <8 x i16> poison, <4 x i32> <i32 1, i32 3, i32 5, i32 7>2341; CHECK-NEXT: [[TMP10:%.*]] = or <4 x i16> [[TMP8]], [[TMP9]]2342; CHECK-NEXT: [[TMP11:%.*]] = zext <4 x i16> [[TMP10]] to <4 x i32>2343; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i32> @llvm.aarch64.neon.uaddlp.v4i32.v8i16(<8 x i16> [[TMPVAR1]])2344; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 02345; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP12:%.*]], label [[TMP17:%.*]], !prof [[PROF1]]2346; CHECK: 12:2347; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2348; CHECK-NEXT: unreachable2349; CHECK: 13:2350; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr [[B]], align 162351; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[B]] to i642352; CHECK-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], 1935140464885762353; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to ptr2354; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP15]], align 162355; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP11]], [[_MSLD1]]2356; CHECK-NEXT: [[TMPVAR5:%.*]] = add <4 x i32> [[TMPVAR3]], [[TMP4]]2357; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 82358; CHECK-NEXT: ret <4 x i32> [[TMPVAR5]]2359;2360 %tmpvar1 = load <8 x i16>, ptr %A2361 %tmpvar3 = call <4 x i32> @llvm.aarch64.neon.uaddlp.v4i32.v8i16(<8 x i16> %tmpvar1)2362 %tmpvar4 = load <4 x i32>, ptr %B2363 %tmpvar5 = add <4 x i32> %tmpvar3, %tmpvar42364 ret <4 x i32> %tmpvar52365}2366 2367define <2 x i64> @uadalp2d(ptr %A, ptr %B) nounwind #0 {2368; CHECK-LABEL: define <2 x i64> @uadalp2d(2369; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2370; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82371; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82372; CHECK-NEXT: call void @llvm.donothing()2373; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02374; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP16:%.*]], !prof [[PROF1]]2375; CHECK: 3:2376; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2377; CHECK-NEXT: unreachable2378; CHECK: 4:2379; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i32>, ptr [[A]], align 162380; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642381; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762382; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2383; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 162384; CHECK-NEXT: [[TMP8:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> poison, <2 x i32> <i32 0, i32 2>2385; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> poison, <2 x i32> <i32 1, i32 3>2386; CHECK-NEXT: [[TMP10:%.*]] = or <2 x i32> [[TMP8]], [[TMP9]]2387; CHECK-NEXT: [[TMP11:%.*]] = zext <2 x i32> [[TMP10]] to <2 x i64>2388; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i64> @llvm.aarch64.neon.uaddlp.v2i64.v4i32(<4 x i32> [[TMPVAR1]])2389; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 02390; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP12:%.*]], label [[TMP17:%.*]], !prof [[PROF1]]2391; CHECK: 12:2392; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2393; CHECK-NEXT: unreachable2394; CHECK: 13:2395; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr [[B]], align 162396; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[B]] to i642397; CHECK-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], 1935140464885762398; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to ptr2399; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP15]], align 162400; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP11]], [[_MSLD1]]2401; CHECK-NEXT: [[TMPVAR5:%.*]] = add <2 x i64> [[TMPVAR3]], [[TMP4]]2402; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 82403; CHECK-NEXT: ret <2 x i64> [[TMPVAR5]]2404;2405 %tmpvar1 = load <4 x i32>, ptr %A2406 %tmpvar3 = call <2 x i64> @llvm.aarch64.neon.uaddlp.v2i64.v4i32(<4 x i32> %tmpvar1)2407 %tmpvar4 = load <2 x i64>, ptr %B2408 %tmpvar5 = add <2 x i64> %tmpvar3, %tmpvar42409 ret <2 x i64> %tmpvar52410}2411 2412define <8 x i8> @addp_8b(ptr %A, ptr %B) nounwind #0 {2413; CHECK-LABEL: define <8 x i8> @addp_8b(2414; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2415; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82416; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82417; CHECK-NEXT: call void @llvm.donothing()2418; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02419; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP15:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]2420; CHECK: 3:2421; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2422; CHECK-NEXT: unreachable2423; CHECK: 4:2424; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i8>, ptr [[A]], align 82425; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642426; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762427; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2428; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 82429; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 02430; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2431; CHECK: 8:2432; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2433; CHECK-NEXT: unreachable2434; CHECK: 9:2435; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i8>, ptr [[B]], align 82436; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642437; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762438; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2439; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP12]], align 82440; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <8 x i8> [[_MSLD]], <8 x i8> [[_MSLD1]], <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>2441; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <8 x i8> [[_MSLD]], <8 x i8> [[_MSLD1]], <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>2442; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i8> [[TMP13]], [[TMP14]]2443; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.addp.v8i8(<8 x i8> [[TMPVAR1]], <8 x i8> [[TMPVAR2]])2444; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 82445; CHECK-NEXT: ret <8 x i8> [[TMP3]]2446;2447 %tmpvar1 = load <8 x i8>, ptr %A2448 %tmpvar2 = load <8 x i8>, ptr %B2449 %tmpvar3 = call <8 x i8> @llvm.aarch64.neon.addp.v8i8(<8 x i8> %tmpvar1, <8 x i8> %tmpvar2)2450 ret <8 x i8> %tmpvar32451}2452 2453define <16 x i8> @addp_16b(ptr %A, ptr %B) nounwind #0 {2454; CHECK-LABEL: define <16 x i8> @addp_16b(2455; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2456; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82457; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82458; CHECK-NEXT: call void @llvm.donothing()2459; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02460; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP15:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]2461; CHECK: 3:2462; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2463; CHECK-NEXT: unreachable2464; CHECK: 4:2465; CHECK-NEXT: [[TMPVAR1:%.*]] = load <16 x i8>, ptr [[A]], align 162466; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642467; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762468; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2469; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP7]], align 162470; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 02471; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2472; CHECK: 8:2473; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2474; CHECK-NEXT: unreachable2475; CHECK: 9:2476; CHECK-NEXT: [[TMPVAR2:%.*]] = load <16 x i8>, ptr [[B]], align 162477; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642478; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762479; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2480; CHECK-NEXT: [[_MSLD1:%.*]] = load <16 x i8>, ptr [[TMP12]], align 162481; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <16 x i8> [[_MSLD]], <16 x i8> [[_MSLD1]], <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>2482; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <16 x i8> [[_MSLD]], <16 x i8> [[_MSLD1]], <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>2483; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP13]], [[TMP14]]2484; CHECK-NEXT: [[TMP3:%.*]] = call <16 x i8> @llvm.aarch64.neon.addp.v16i8(<16 x i8> [[TMPVAR1]], <16 x i8> [[TMPVAR2]])2485; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 82486; CHECK-NEXT: ret <16 x i8> [[TMP3]]2487;2488 %tmpvar1 = load <16 x i8>, ptr %A2489 %tmpvar2 = load <16 x i8>, ptr %B2490 %tmpvar3 = call <16 x i8> @llvm.aarch64.neon.addp.v16i8(<16 x i8> %tmpvar1, <16 x i8> %tmpvar2)2491 ret <16 x i8> %tmpvar32492}2493 2494define <4 x i16> @addp_4h(ptr %A, ptr %B) nounwind #0 {2495; CHECK-LABEL: define <4 x i16> @addp_4h(2496; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2497; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82498; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82499; CHECK-NEXT: call void @llvm.donothing()2500; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02501; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP15:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]2502; CHECK: 3:2503; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2504; CHECK-NEXT: unreachable2505; CHECK: 4:2506; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i16>, ptr [[A]], align 82507; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642508; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762509; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2510; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 82511; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 02512; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2513; CHECK: 8:2514; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2515; CHECK-NEXT: unreachable2516; CHECK: 9:2517; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i16>, ptr [[B]], align 82518; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642519; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762520; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2521; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 82522; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <4 x i16> [[_MSLD]], <4 x i16> [[_MSLD1]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>2523; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x i16> [[_MSLD]], <4 x i16> [[_MSLD1]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>2524; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[TMP13]], [[TMP14]]2525; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.addp.v4i16(<4 x i16> [[TMPVAR1]], <4 x i16> [[TMPVAR2]])2526; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 82527; CHECK-NEXT: ret <4 x i16> [[TMP3]]2528;2529 %tmpvar1 = load <4 x i16>, ptr %A2530 %tmpvar2 = load <4 x i16>, ptr %B2531 %tmpvar3 = call <4 x i16> @llvm.aarch64.neon.addp.v4i16(<4 x i16> %tmpvar1, <4 x i16> %tmpvar2)2532 ret <4 x i16> %tmpvar32533}2534 2535define <8 x i16> @addp_8h(ptr %A, ptr %B) nounwind #0 {2536; CHECK-LABEL: define <8 x i16> @addp_8h(2537; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2538; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82539; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82540; CHECK-NEXT: call void @llvm.donothing()2541; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02542; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP15:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]2543; CHECK: 3:2544; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2545; CHECK-NEXT: unreachable2546; CHECK: 4:2547; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i16>, ptr [[A]], align 162548; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642549; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762550; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2551; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 162552; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 02553; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2554; CHECK: 8:2555; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2556; CHECK-NEXT: unreachable2557; CHECK: 9:2558; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i16>, ptr [[B]], align 162559; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642560; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762561; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2562; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 162563; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <8 x i16> [[_MSLD]], <8 x i16> [[_MSLD1]], <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>2564; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <8 x i16> [[_MSLD]], <8 x i16> [[_MSLD1]], <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>2565; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP13]], [[TMP14]]2566; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i16> @llvm.aarch64.neon.addp.v8i16(<8 x i16> [[TMPVAR1]], <8 x i16> [[TMPVAR2]])2567; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 82568; CHECK-NEXT: ret <8 x i16> [[TMP3]]2569;2570 %tmpvar1 = load <8 x i16>, ptr %A2571 %tmpvar2 = load <8 x i16>, ptr %B2572 %tmpvar3 = call <8 x i16> @llvm.aarch64.neon.addp.v8i16(<8 x i16> %tmpvar1, <8 x i16> %tmpvar2)2573 ret <8 x i16> %tmpvar32574}2575 2576define <2 x i32> @addp_2s(ptr %A, ptr %B) nounwind #0 {2577; CHECK-LABEL: define <2 x i32> @addp_2s(2578; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2579; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82580; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82581; CHECK-NEXT: call void @llvm.donothing()2582; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02583; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP15:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]2584; CHECK: 3:2585; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2586; CHECK-NEXT: unreachable2587; CHECK: 4:2588; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i32>, ptr [[A]], align 82589; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642590; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762591; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2592; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 82593; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 02594; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2595; CHECK: 8:2596; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2597; CHECK-NEXT: unreachable2598; CHECK: 9:2599; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x i32>, ptr [[B]], align 82600; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642601; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762602; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2603; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 82604; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <2 x i32> [[_MSLD]], <2 x i32> [[_MSLD1]], <2 x i32> <i32 0, i32 2>2605; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <2 x i32> [[_MSLD]], <2 x i32> [[_MSLD1]], <2 x i32> <i32 1, i32 3>2606; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[TMP13]], [[TMP14]]2607; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.addp.v2i32(<2 x i32> [[TMPVAR1]], <2 x i32> [[TMPVAR2]])2608; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 82609; CHECK-NEXT: ret <2 x i32> [[TMP3]]2610;2611 %tmpvar1 = load <2 x i32>, ptr %A2612 %tmpvar2 = load <2 x i32>, ptr %B2613 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.addp.v2i32(<2 x i32> %tmpvar1, <2 x i32> %tmpvar2)2614 ret <2 x i32> %tmpvar32615}2616 2617define <4 x i32> @addp_4s(ptr %A, ptr %B) nounwind #0 {2618; CHECK-LABEL: define <4 x i32> @addp_4s(2619; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2620; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82621; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82622; CHECK-NEXT: call void @llvm.donothing()2623; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02624; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP15:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]2625; CHECK: 3:2626; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2627; CHECK-NEXT: unreachable2628; CHECK: 4:2629; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i32>, ptr [[A]], align 162630; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642631; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762632; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2633; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 162634; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 02635; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2636; CHECK: 8:2637; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2638; CHECK-NEXT: unreachable2639; CHECK: 9:2640; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i32>, ptr [[B]], align 162641; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642642; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762643; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2644; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 162645; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> [[_MSLD1]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>2646; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> [[_MSLD1]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>2647; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP13]], [[TMP14]]2648; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.addp.v4i32(<4 x i32> [[TMPVAR1]], <4 x i32> [[TMPVAR2]])2649; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 82650; CHECK-NEXT: ret <4 x i32> [[TMP3]]2651;2652 %tmpvar1 = load <4 x i32>, ptr %A2653 %tmpvar2 = load <4 x i32>, ptr %B2654 %tmpvar3 = call <4 x i32> @llvm.aarch64.neon.addp.v4i32(<4 x i32> %tmpvar1, <4 x i32> %tmpvar2)2655 ret <4 x i32> %tmpvar32656}2657 2658define <2 x i64> @addp_2d(ptr %A, ptr %B) nounwind #0 {2659; CHECK-LABEL: define <2 x i64> @addp_2d(2660; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2661; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82662; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82663; CHECK-NEXT: call void @llvm.donothing()2664; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02665; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP15:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]2666; CHECK: 3:2667; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2668; CHECK-NEXT: unreachable2669; CHECK: 4:2670; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i64>, ptr [[A]], align 162671; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642672; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762673; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2674; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 162675; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 02676; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2677; CHECK: 8:2678; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2679; CHECK-NEXT: unreachable2680; CHECK: 9:2681; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x i64>, ptr [[B]], align 162682; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642683; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762684; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2685; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 162686; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <2 x i64> [[_MSLD]], <2 x i64> [[_MSLD1]], <2 x i32> <i32 0, i32 2>2687; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <2 x i64> [[_MSLD]], <2 x i64> [[_MSLD1]], <2 x i32> <i32 1, i32 3>2688; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP13]], [[TMP14]]2689; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> [[TMPVAR1]], <2 x i64> [[TMPVAR2]])2690; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 82691; CHECK-NEXT: ret <2 x i64> [[TMP3]]2692;2693 %tmpvar1 = load <2 x i64>, ptr %A2694 %tmpvar2 = load <2 x i64>, ptr %B2695 %tmpvar3 = call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> %tmpvar1, <2 x i64> %tmpvar2)2696 ret <2 x i64> %tmpvar32697}2698 2699declare <8 x i8> @llvm.aarch64.neon.addp.v8i8(<8 x i8>, <8 x i8>) nounwind readnone2700declare <16 x i8> @llvm.aarch64.neon.addp.v16i8(<16 x i8>, <16 x i8>) nounwind readnone2701declare <4 x i16> @llvm.aarch64.neon.addp.v4i16(<4 x i16>, <4 x i16>) nounwind readnone2702declare <8 x i16> @llvm.aarch64.neon.addp.v8i16(<8 x i16>, <8 x i16>) nounwind readnone2703declare <2 x i32> @llvm.aarch64.neon.addp.v2i32(<2 x i32>, <2 x i32>) nounwind readnone2704declare <4 x i32> @llvm.aarch64.neon.addp.v4i32(<4 x i32>, <4 x i32>) nounwind readnone2705declare <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64>, <2 x i64>) nounwind readnone2706 2707define <2 x float> @faddp_2s(ptr %A, ptr %B) nounwind #0 {2708; CHECK-LABEL: define <2 x float> @faddp_2s(2709; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2710; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82711; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82712; CHECK-NEXT: call void @llvm.donothing()2713; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02714; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP15:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]2715; CHECK: 3:2716; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2717; CHECK-NEXT: unreachable2718; CHECK: 4:2719; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x float>, ptr [[A]], align 82720; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642721; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762722; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2723; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 82724; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 02725; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2726; CHECK: 8:2727; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2728; CHECK-NEXT: unreachable2729; CHECK: 9:2730; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x float>, ptr [[B]], align 82731; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642732; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762733; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2734; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 82735; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <2 x i32> [[_MSLD]], <2 x i32> [[_MSLD1]], <2 x i32> <i32 0, i32 2>2736; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <2 x i32> [[_MSLD]], <2 x i32> [[_MSLD1]], <2 x i32> <i32 1, i32 3>2737; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[TMP13]], [[TMP14]]2738; CHECK-NEXT: [[TMP3:%.*]] = call <2 x float> @llvm.aarch64.neon.faddp.v2f32(<2 x float> [[TMPVAR1]], <2 x float> [[TMPVAR2]])2739; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 82740; CHECK-NEXT: ret <2 x float> [[TMP3]]2741;2742 %tmpvar1 = load <2 x float>, ptr %A2743 %tmpvar2 = load <2 x float>, ptr %B2744 %tmpvar3 = call <2 x float> @llvm.aarch64.neon.faddp.v2f32(<2 x float> %tmpvar1, <2 x float> %tmpvar2)2745 ret <2 x float> %tmpvar32746}2747 2748define <4 x float> @faddp_4s(ptr %A, ptr %B) nounwind #0 {2749; CHECK-LABEL: define <4 x float> @faddp_4s(2750; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2751; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82752; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82753; CHECK-NEXT: call void @llvm.donothing()2754; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02755; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP15:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]2756; CHECK: 3:2757; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2758; CHECK-NEXT: unreachable2759; CHECK: 4:2760; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x float>, ptr [[A]], align 162761; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642762; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762763; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2764; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 162765; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 02766; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2767; CHECK: 8:2768; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2769; CHECK-NEXT: unreachable2770; CHECK: 9:2771; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x float>, ptr [[B]], align 162772; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642773; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762774; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2775; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 162776; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> [[_MSLD1]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>2777; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> [[_MSLD1]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>2778; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP13]], [[TMP14]]2779; CHECK-NEXT: [[TMP3:%.*]] = call <4 x float> @llvm.aarch64.neon.faddp.v4f32(<4 x float> [[TMPVAR1]], <4 x float> [[TMPVAR2]])2780; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 82781; CHECK-NEXT: ret <4 x float> [[TMP3]]2782;2783 %tmpvar1 = load <4 x float>, ptr %A2784 %tmpvar2 = load <4 x float>, ptr %B2785 %tmpvar3 = call <4 x float> @llvm.aarch64.neon.faddp.v4f32(<4 x float> %tmpvar1, <4 x float> %tmpvar2)2786 ret <4 x float> %tmpvar32787}2788 2789define <2 x double> @faddp_2d(ptr %A, ptr %B) nounwind #0 {2790; CHECK-LABEL: define <2 x double> @faddp_2d(2791; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2792; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82793; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82794; CHECK-NEXT: call void @llvm.donothing()2795; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02796; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP15:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]2797; CHECK: 3:2798; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2799; CHECK-NEXT: unreachable2800; CHECK: 4:2801; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x double>, ptr [[A]], align 162802; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642803; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762804; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2805; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 162806; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 02807; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2808; CHECK: 8:2809; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]2810; CHECK-NEXT: unreachable2811; CHECK: 9:2812; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x double>, ptr [[B]], align 162813; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642814; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762815; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2816; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 162817; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <2 x i64> [[_MSLD]], <2 x i64> [[_MSLD1]], <2 x i32> <i32 0, i32 2>2818; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <2 x i64> [[_MSLD]], <2 x i64> [[_MSLD1]], <2 x i32> <i32 1, i32 3>2819; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP13]], [[TMP14]]2820; CHECK-NEXT: [[TMP3:%.*]] = call <2 x double> @llvm.aarch64.neon.faddp.v2f64(<2 x double> [[TMPVAR1]], <2 x double> [[TMPVAR2]])2821; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 82822; CHECK-NEXT: ret <2 x double> [[TMP3]]2823;2824 %tmpvar1 = load <2 x double>, ptr %A2825 %tmpvar2 = load <2 x double>, ptr %B2826 %tmpvar3 = call <2 x double> @llvm.aarch64.neon.faddp.v2f64(<2 x double> %tmpvar1, <2 x double> %tmpvar2)2827 ret <2 x double> %tmpvar32828}2829 2830declare <2 x float> @llvm.aarch64.neon.faddp.v2f32(<2 x float>, <2 x float>) nounwind readnone2831declare <4 x float> @llvm.aarch64.neon.faddp.v4f32(<4 x float>, <4 x float>) nounwind readnone2832declare <2 x double> @llvm.aarch64.neon.faddp.v2f64(<2 x double>, <2 x double>) nounwind readnone2833 2834define <2 x i64> @uaddl_duprhs(<4 x i32> %lhs, i32 %rhs, <2 x i32> %param1, <4 x i32> %param2) #0 {2835; CHECK-LABEL: define <2 x i64> @uaddl_duprhs(2836; CHECK-SAME: <4 x i32> [[LHS:%.*]], i32 [[RHS:%.*]], <2 x i32> [[PARAM1:%.*]], <4 x i32> [[PARAM2:%.*]]) #[[ATTR2:[0-9]+]] {2837; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 82838; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82839; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 82840; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82841; CHECK-NEXT: call void @llvm.donothing()2842; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP1]], i32 02843; CHECK-NEXT: [[RHSVEC_TMP:%.*]] = insertelement <2 x i32> [[PARAM1]], i32 [[RHS]], i32 02844; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <2 x i32> [[_MSPROP]], i32 [[TMP1]], i32 12845; CHECK-NEXT: [[RHSVEC:%.*]] = insertelement <2 x i32> [[RHSVEC_TMP]], i32 [[RHS]], i32 12846; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> [[TMP4]], <2 x i32> <i32 0, i32 1>2847; CHECK-NEXT: [[LHS_HIGH:%.*]] = shufflevector <4 x i32> [[LHS]], <4 x i32> [[PARAM2]], <2 x i32> <i32 0, i32 1>2848; CHECK-NEXT: [[_MSPROP3:%.*]] = zext <2 x i32> [[_MSPROP2]] to <2 x i64>2849; CHECK-NEXT: [[LHS_EXT:%.*]] = zext <2 x i32> [[LHS_HIGH]] to <2 x i64>2850; CHECK-NEXT: [[_MSPROP4:%.*]] = zext <2 x i32> [[_MSPROP1]] to <2 x i64>2851; CHECK-NEXT: [[RHS_EXT:%.*]] = zext <2 x i32> [[RHSVEC]] to <2 x i64>2852; CHECK-NEXT: [[_MSPROP5:%.*]] = or <2 x i64> [[_MSPROP3]], [[_MSPROP4]]2853; CHECK-NEXT: [[RES:%.*]] = add <2 x i64> [[LHS_EXT]], [[RHS_EXT]]2854; CHECK-NEXT: store <2 x i64> [[_MSPROP5]], ptr @__msan_retval_tls, align 82855; CHECK-NEXT: ret <2 x i64> [[RES]]2856;2857 %rhsvec.tmp = insertelement <2 x i32> %param1, i32 %rhs, i32 02858 %rhsvec = insertelement <2 x i32> %rhsvec.tmp, i32 %rhs, i32 12859 2860 %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> %param2, <2 x i32> <i32 0, i32 1>2861 2862 %lhs.ext = zext <2 x i32> %lhs.high to <2 x i64>2863 %rhs.ext = zext <2 x i32> %rhsvec to <2 x i64>2864 2865 %res = add <2 x i64> %lhs.ext, %rhs.ext2866 ret <2 x i64> %res2867}2868 2869define <2 x i64> @uaddl2_duprhs(<4 x i32> %lhs, i32 %rhs, <2 x i32> %param1, <4 x i32> %param2) #0 {2870; CHECK-LABEL: define <2 x i64> @uaddl2_duprhs(2871; CHECK-SAME: <4 x i32> [[LHS:%.*]], i32 [[RHS:%.*]], <2 x i32> [[PARAM1:%.*]], <4 x i32> [[PARAM2:%.*]]) #[[ATTR2]] {2872; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 82873; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82874; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 82875; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82876; CHECK-NEXT: call void @llvm.donothing()2877; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP1]], i32 02878; CHECK-NEXT: [[RHSVEC_TMP:%.*]] = insertelement <2 x i32> [[PARAM1]], i32 [[RHS]], i32 02879; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <2 x i32> [[_MSPROP]], i32 [[TMP1]], i32 12880; CHECK-NEXT: [[RHSVEC:%.*]] = insertelement <2 x i32> [[RHSVEC_TMP]], i32 [[RHS]], i32 12881; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> [[TMP4]], <2 x i32> <i32 2, i32 3>2882; CHECK-NEXT: [[LHS_HIGH:%.*]] = shufflevector <4 x i32> [[LHS]], <4 x i32> [[PARAM2]], <2 x i32> <i32 2, i32 3>2883; CHECK-NEXT: [[_MSPROP3:%.*]] = zext <2 x i32> [[_MSPROP2]] to <2 x i64>2884; CHECK-NEXT: [[LHS_EXT:%.*]] = zext <2 x i32> [[LHS_HIGH]] to <2 x i64>2885; CHECK-NEXT: [[_MSPROP4:%.*]] = zext <2 x i32> [[_MSPROP1]] to <2 x i64>2886; CHECK-NEXT: [[RHS_EXT:%.*]] = zext <2 x i32> [[RHSVEC]] to <2 x i64>2887; CHECK-NEXT: [[_MSPROP5:%.*]] = or <2 x i64> [[_MSPROP3]], [[_MSPROP4]]2888; CHECK-NEXT: [[RES:%.*]] = add <2 x i64> [[LHS_EXT]], [[RHS_EXT]]2889; CHECK-NEXT: store <2 x i64> [[_MSPROP5]], ptr @__msan_retval_tls, align 82890; CHECK-NEXT: ret <2 x i64> [[RES]]2891;2892 %rhsvec.tmp = insertelement <2 x i32> %param1, i32 %rhs, i32 02893 %rhsvec = insertelement <2 x i32> %rhsvec.tmp, i32 %rhs, i32 12894 2895 %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> %param2, <2 x i32> <i32 2, i32 3>2896 2897 %lhs.ext = zext <2 x i32> %lhs.high to <2 x i64>2898 %rhs.ext = zext <2 x i32> %rhsvec to <2 x i64>2899 2900 %res = add <2 x i64> %lhs.ext, %rhs.ext2901 ret <2 x i64> %res2902}2903 2904define <2 x i64> @saddl_duplhs(i32 %lhs, <4 x i32> %rhs, <2 x i32> %param1, <4 x i32> %param2) #0 {2905; CHECK-LABEL: define <2 x i64> @saddl_duplhs(2906; CHECK-SAME: i32 [[LHS:%.*]], <4 x i32> [[RHS:%.*]], <2 x i32> [[PARAM1:%.*]], <4 x i32> [[PARAM2:%.*]]) #[[ATTR2]] {2907; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 82908; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 82909; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82910; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82911; CHECK-NEXT: call void @llvm.donothing()2912; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP1]], i32 02913; CHECK-NEXT: [[LHSVEC_TMP:%.*]] = insertelement <2 x i32> [[PARAM1]], i32 [[LHS]], i32 02914; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <2 x i32> [[_MSPROP]], i32 [[TMP1]], i32 12915; CHECK-NEXT: [[LHSVEC:%.*]] = insertelement <2 x i32> [[LHSVEC_TMP]], i32 [[LHS]], i32 12916; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> [[TMP4]], <2 x i32> <i32 0, i32 1>2917; CHECK-NEXT: [[RHS_HIGH:%.*]] = shufflevector <4 x i32> [[RHS]], <4 x i32> [[PARAM2]], <2 x i32> <i32 0, i32 1>2918; CHECK-NEXT: [[_MSPROP3:%.*]] = sext <2 x i32> [[_MSPROP1]] to <2 x i64>2919; CHECK-NEXT: [[LHS_EXT:%.*]] = sext <2 x i32> [[LHSVEC]] to <2 x i64>2920; CHECK-NEXT: [[_MSPROP4:%.*]] = sext <2 x i32> [[_MSPROP2]] to <2 x i64>2921; CHECK-NEXT: [[RHS_EXT:%.*]] = sext <2 x i32> [[RHS_HIGH]] to <2 x i64>2922; CHECK-NEXT: [[_MSPROP5:%.*]] = or <2 x i64> [[_MSPROP3]], [[_MSPROP4]]2923; CHECK-NEXT: [[RES:%.*]] = add <2 x i64> [[LHS_EXT]], [[RHS_EXT]]2924; CHECK-NEXT: store <2 x i64> [[_MSPROP5]], ptr @__msan_retval_tls, align 82925; CHECK-NEXT: ret <2 x i64> [[RES]]2926;2927 %lhsvec.tmp = insertelement <2 x i32> %param1, i32 %lhs, i32 02928 %lhsvec = insertelement <2 x i32> %lhsvec.tmp, i32 %lhs, i32 12929 2930 %rhs.high = shufflevector <4 x i32> %rhs, <4 x i32> %param2, <2 x i32> <i32 0, i32 1>2931 2932 %lhs.ext = sext <2 x i32> %lhsvec to <2 x i64>2933 %rhs.ext = sext <2 x i32> %rhs.high to <2 x i64>2934 2935 %res = add <2 x i64> %lhs.ext, %rhs.ext2936 ret <2 x i64> %res2937}2938 2939define <2 x i64> @saddl2_duplhs(i32 %lhs, <4 x i32> %rhs, <2 x i32> %param1, <4 x i32> %param2) #0 {2940; CHECK-LABEL: define <2 x i64> @saddl2_duplhs(2941; CHECK-SAME: i32 [[LHS:%.*]], <4 x i32> [[RHS:%.*]], <2 x i32> [[PARAM1:%.*]], <4 x i32> [[PARAM2:%.*]]) #[[ATTR2]] {2942; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 82943; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 82944; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82945; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82946; CHECK-NEXT: call void @llvm.donothing()2947; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP1]], i32 02948; CHECK-NEXT: [[LHSVEC_TMP:%.*]] = insertelement <2 x i32> [[PARAM1]], i32 [[LHS]], i32 02949; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <2 x i32> [[_MSPROP]], i32 [[TMP1]], i32 12950; CHECK-NEXT: [[LHSVEC:%.*]] = insertelement <2 x i32> [[LHSVEC_TMP]], i32 [[LHS]], i32 12951; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> [[TMP4]], <2 x i32> <i32 2, i32 3>2952; CHECK-NEXT: [[RHS_HIGH:%.*]] = shufflevector <4 x i32> [[RHS]], <4 x i32> [[PARAM2]], <2 x i32> <i32 2, i32 3>2953; CHECK-NEXT: [[_MSPROP3:%.*]] = sext <2 x i32> [[_MSPROP1]] to <2 x i64>2954; CHECK-NEXT: [[LHS_EXT:%.*]] = sext <2 x i32> [[LHSVEC]] to <2 x i64>2955; CHECK-NEXT: [[_MSPROP4:%.*]] = sext <2 x i32> [[_MSPROP2]] to <2 x i64>2956; CHECK-NEXT: [[RHS_EXT:%.*]] = sext <2 x i32> [[RHS_HIGH]] to <2 x i64>2957; CHECK-NEXT: [[_MSPROP5:%.*]] = or <2 x i64> [[_MSPROP3]], [[_MSPROP4]]2958; CHECK-NEXT: [[RES:%.*]] = add <2 x i64> [[LHS_EXT]], [[RHS_EXT]]2959; CHECK-NEXT: store <2 x i64> [[_MSPROP5]], ptr @__msan_retval_tls, align 82960; CHECK-NEXT: ret <2 x i64> [[RES]]2961;2962 %lhsvec.tmp = insertelement <2 x i32> %param1, i32 %lhs, i32 02963 %lhsvec = insertelement <2 x i32> %lhsvec.tmp, i32 %lhs, i32 12964 2965 %rhs.high = shufflevector <4 x i32> %rhs, <4 x i32> %param2, <2 x i32> <i32 2, i32 3>2966 2967 %lhs.ext = sext <2 x i32> %lhsvec to <2 x i64>2968 %rhs.ext = sext <2 x i32> %rhs.high to <2 x i64>2969 2970 %res = add <2 x i64> %lhs.ext, %rhs.ext2971 ret <2 x i64> %res2972}2973 2974define <2 x i64> @usubl_duprhs(<4 x i32> %lhs, i32 %rhs, <2 x i32> %param1, <4 x i32> %param2) #0 {2975; CHECK-LABEL: define <2 x i64> @usubl_duprhs(2976; CHECK-SAME: <4 x i32> [[LHS:%.*]], i32 [[RHS:%.*]], <2 x i32> [[PARAM1:%.*]], <4 x i32> [[PARAM2:%.*]]) #[[ATTR2]] {2977; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 82978; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82979; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 82980; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 82981; CHECK-NEXT: call void @llvm.donothing()2982; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP1]], i32 02983; CHECK-NEXT: [[RHSVEC_TMP:%.*]] = insertelement <2 x i32> [[PARAM1]], i32 [[RHS]], i32 02984; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <2 x i32> [[_MSPROP]], i32 [[TMP1]], i32 12985; CHECK-NEXT: [[RHSVEC:%.*]] = insertelement <2 x i32> [[RHSVEC_TMP]], i32 [[RHS]], i32 12986; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> [[TMP4]], <2 x i32> <i32 0, i32 1>2987; CHECK-NEXT: [[LHS_HIGH:%.*]] = shufflevector <4 x i32> [[LHS]], <4 x i32> [[PARAM2]], <2 x i32> <i32 0, i32 1>2988; CHECK-NEXT: [[_MSPROP3:%.*]] = zext <2 x i32> [[_MSPROP2]] to <2 x i64>2989; CHECK-NEXT: [[LHS_EXT:%.*]] = zext <2 x i32> [[LHS_HIGH]] to <2 x i64>2990; CHECK-NEXT: [[_MSPROP4:%.*]] = zext <2 x i32> [[_MSPROP1]] to <2 x i64>2991; CHECK-NEXT: [[RHS_EXT:%.*]] = zext <2 x i32> [[RHSVEC]] to <2 x i64>2992; CHECK-NEXT: [[_MSPROP5:%.*]] = or <2 x i64> [[_MSPROP3]], [[_MSPROP4]]2993; CHECK-NEXT: [[RES:%.*]] = sub <2 x i64> [[LHS_EXT]], [[RHS_EXT]]2994; CHECK-NEXT: store <2 x i64> [[_MSPROP5]], ptr @__msan_retval_tls, align 82995; CHECK-NEXT: ret <2 x i64> [[RES]]2996;2997 %rhsvec.tmp = insertelement <2 x i32> %param1, i32 %rhs, i32 02998 %rhsvec = insertelement <2 x i32> %rhsvec.tmp, i32 %rhs, i32 12999 3000 %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> %param2, <2 x i32> <i32 0, i32 1>3001 3002 %lhs.ext = zext <2 x i32> %lhs.high to <2 x i64>3003 %rhs.ext = zext <2 x i32> %rhsvec to <2 x i64>3004 3005 %res = sub <2 x i64> %lhs.ext, %rhs.ext3006 ret <2 x i64> %res3007}3008 3009define <2 x i64> @usubl2_duprhs(<4 x i32> %lhs, i32 %rhs, <2 x i32> %param1, <4 x i32> %param2) #0 {3010; CHECK-LABEL: define <2 x i64> @usubl2_duprhs(3011; CHECK-SAME: <4 x i32> [[LHS:%.*]], i32 [[RHS:%.*]], <2 x i32> [[PARAM1:%.*]], <4 x i32> [[PARAM2:%.*]]) #[[ATTR2]] {3012; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 83013; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83014; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 83015; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 83016; CHECK-NEXT: call void @llvm.donothing()3017; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP1]], i32 03018; CHECK-NEXT: [[RHSVEC_TMP:%.*]] = insertelement <2 x i32> [[PARAM1]], i32 [[RHS]], i32 03019; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <2 x i32> [[_MSPROP]], i32 [[TMP1]], i32 13020; CHECK-NEXT: [[RHSVEC:%.*]] = insertelement <2 x i32> [[RHSVEC_TMP]], i32 [[RHS]], i32 13021; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> [[TMP4]], <2 x i32> <i32 2, i32 3>3022; CHECK-NEXT: [[LHS_HIGH:%.*]] = shufflevector <4 x i32> [[LHS]], <4 x i32> [[PARAM2]], <2 x i32> <i32 2, i32 3>3023; CHECK-NEXT: [[_MSPROP3:%.*]] = zext <2 x i32> [[_MSPROP2]] to <2 x i64>3024; CHECK-NEXT: [[LHS_EXT:%.*]] = zext <2 x i32> [[LHS_HIGH]] to <2 x i64>3025; CHECK-NEXT: [[_MSPROP4:%.*]] = zext <2 x i32> [[_MSPROP1]] to <2 x i64>3026; CHECK-NEXT: [[RHS_EXT:%.*]] = zext <2 x i32> [[RHSVEC]] to <2 x i64>3027; CHECK-NEXT: [[_MSPROP5:%.*]] = or <2 x i64> [[_MSPROP3]], [[_MSPROP4]]3028; CHECK-NEXT: [[RES:%.*]] = sub <2 x i64> [[LHS_EXT]], [[RHS_EXT]]3029; CHECK-NEXT: store <2 x i64> [[_MSPROP5]], ptr @__msan_retval_tls, align 83030; CHECK-NEXT: ret <2 x i64> [[RES]]3031;3032 %rhsvec.tmp = insertelement <2 x i32> %param1, i32 %rhs, i32 03033 %rhsvec = insertelement <2 x i32> %rhsvec.tmp, i32 %rhs, i32 13034 3035 %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> %param2, <2 x i32> <i32 2, i32 3>3036 3037 %lhs.ext = zext <2 x i32> %lhs.high to <2 x i64>3038 %rhs.ext = zext <2 x i32> %rhsvec to <2 x i64>3039 3040 %res = sub <2 x i64> %lhs.ext, %rhs.ext3041 ret <2 x i64> %res3042}3043 3044define <2 x i64> @ssubl_duplhs(i32 %lhs, <4 x i32> %rhs, <2 x i32> %param1, <4 x i32> %param2) #0 {3045; CHECK-LABEL: define <2 x i64> @ssubl_duplhs(3046; CHECK-SAME: i32 [[LHS:%.*]], <4 x i32> [[RHS:%.*]], <2 x i32> [[PARAM1:%.*]], <4 x i32> [[PARAM2:%.*]]) #[[ATTR2]] {3047; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 83048; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 83049; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83050; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 83051; CHECK-NEXT: call void @llvm.donothing()3052; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP1]], i32 03053; CHECK-NEXT: [[LHSVEC_TMP:%.*]] = insertelement <2 x i32> [[PARAM1]], i32 [[LHS]], i32 03054; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <2 x i32> [[_MSPROP]], i32 [[TMP1]], i32 13055; CHECK-NEXT: [[LHSVEC:%.*]] = insertelement <2 x i32> [[LHSVEC_TMP]], i32 [[LHS]], i32 13056; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> [[TMP4]], <2 x i32> <i32 0, i32 1>3057; CHECK-NEXT: [[RHS_HIGH:%.*]] = shufflevector <4 x i32> [[RHS]], <4 x i32> [[PARAM2]], <2 x i32> <i32 0, i32 1>3058; CHECK-NEXT: [[_MSPROP3:%.*]] = sext <2 x i32> [[_MSPROP1]] to <2 x i64>3059; CHECK-NEXT: [[LHS_EXT:%.*]] = sext <2 x i32> [[LHSVEC]] to <2 x i64>3060; CHECK-NEXT: [[_MSPROP4:%.*]] = sext <2 x i32> [[_MSPROP2]] to <2 x i64>3061; CHECK-NEXT: [[RHS_EXT:%.*]] = sext <2 x i32> [[RHS_HIGH]] to <2 x i64>3062; CHECK-NEXT: [[_MSPROP5:%.*]] = or <2 x i64> [[_MSPROP3]], [[_MSPROP4]]3063; CHECK-NEXT: [[RES:%.*]] = sub <2 x i64> [[LHS_EXT]], [[RHS_EXT]]3064; CHECK-NEXT: store <2 x i64> [[_MSPROP5]], ptr @__msan_retval_tls, align 83065; CHECK-NEXT: ret <2 x i64> [[RES]]3066;3067 %lhsvec.tmp = insertelement <2 x i32> %param1, i32 %lhs, i32 03068 %lhsvec = insertelement <2 x i32> %lhsvec.tmp, i32 %lhs, i32 13069 3070 %rhs.high = shufflevector <4 x i32> %rhs, <4 x i32> %param2, <2 x i32> <i32 0, i32 1>3071 3072 %lhs.ext = sext <2 x i32> %lhsvec to <2 x i64>3073 %rhs.ext = sext <2 x i32> %rhs.high to <2 x i64>3074 3075 %res = sub <2 x i64> %lhs.ext, %rhs.ext3076 ret <2 x i64> %res3077}3078 3079define <2 x i64> @ssubl2_duplhs(i32 %lhs, <4 x i32> %rhs, <2 x i32> %param1, <4 x i32> %param2) #0 {3080; CHECK-LABEL: define <2 x i64> @ssubl2_duplhs(3081; CHECK-SAME: i32 [[LHS:%.*]], <4 x i32> [[RHS:%.*]], <2 x i32> [[PARAM1:%.*]], <4 x i32> [[PARAM2:%.*]]) #[[ATTR2]] {3082; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 83083; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 83084; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83085; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 83086; CHECK-NEXT: call void @llvm.donothing()3087; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <2 x i32> [[TMP3]], i32 [[TMP1]], i32 03088; CHECK-NEXT: [[LHSVEC_TMP:%.*]] = insertelement <2 x i32> [[PARAM1]], i32 [[LHS]], i32 03089; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <2 x i32> [[_MSPROP]], i32 [[TMP1]], i32 13090; CHECK-NEXT: [[LHSVEC:%.*]] = insertelement <2 x i32> [[LHSVEC_TMP]], i32 [[LHS]], i32 13091; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <4 x i32> [[TMP2]], <4 x i32> [[TMP4]], <2 x i32> <i32 2, i32 3>3092; CHECK-NEXT: [[RHS_HIGH:%.*]] = shufflevector <4 x i32> [[RHS]], <4 x i32> [[PARAM2]], <2 x i32> <i32 2, i32 3>3093; CHECK-NEXT: [[_MSPROP3:%.*]] = sext <2 x i32> [[_MSPROP1]] to <2 x i64>3094; CHECK-NEXT: [[LHS_EXT:%.*]] = sext <2 x i32> [[LHSVEC]] to <2 x i64>3095; CHECK-NEXT: [[_MSPROP4:%.*]] = sext <2 x i32> [[_MSPROP2]] to <2 x i64>3096; CHECK-NEXT: [[RHS_EXT:%.*]] = sext <2 x i32> [[RHS_HIGH]] to <2 x i64>3097; CHECK-NEXT: [[_MSPROP5:%.*]] = or <2 x i64> [[_MSPROP3]], [[_MSPROP4]]3098; CHECK-NEXT: [[RES:%.*]] = sub <2 x i64> [[LHS_EXT]], [[RHS_EXT]]3099; CHECK-NEXT: store <2 x i64> [[_MSPROP5]], ptr @__msan_retval_tls, align 83100; CHECK-NEXT: ret <2 x i64> [[RES]]3101;3102 %lhsvec.tmp = insertelement <2 x i32> %param1, i32 %lhs, i32 03103 %lhsvec = insertelement <2 x i32> %lhsvec.tmp, i32 %lhs, i32 13104 3105 %rhs.high = shufflevector <4 x i32> %rhs, <4 x i32> %param2, <2 x i32> <i32 2, i32 3>3106 3107 %lhs.ext = sext <2 x i32> %lhsvec to <2 x i64>3108 %rhs.ext = sext <2 x i32> %rhs.high to <2 x i64>3109 3110 %res = sub <2 x i64> %lhs.ext, %rhs.ext3111 ret <2 x i64> %res3112}3113 3114define <8 x i8> @addhn8b_natural(ptr %A, ptr %B) nounwind #0 {3115; CHECK-LABEL: define <8 x i8> @addhn8b_natural(3116; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {3117; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83118; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83119; CHECK-NEXT: call void @llvm.donothing()3120; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03121; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]3122; CHECK: 3:3123; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]3124; CHECK-NEXT: unreachable3125; CHECK: 4:3126; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i16>, ptr [[A]], align 163127; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i643128; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885763129; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr3130; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 163131; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 03132; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]3133; CHECK: 8:3134; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]3135; CHECK-NEXT: unreachable3136; CHECK: 9:3137; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i16>, ptr [[B]], align 163138; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i643139; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885763140; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr3141; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 163142; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[_MSLD]], [[_MSLD1]]3143; CHECK-NEXT: [[SUM:%.*]] = add <8 x i16> [[TMPVAR1]], [[TMPVAR2]]3144; CHECK-NEXT: [[TMP13:%.*]] = lshr <8 x i16> [[_MSPROP]], splat (i16 8)3145; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i16> [[TMP13]], zeroinitializer3146; CHECK-NEXT: [[HIGH_BITS:%.*]] = lshr <8 x i16> [[SUM]], splat (i16 8)3147; CHECK-NEXT: [[_MSPROP2:%.*]] = trunc <8 x i16> [[TMP14]] to <8 x i8>3148; CHECK-NEXT: [[NARROWED:%.*]] = trunc <8 x i16> [[HIGH_BITS]] to <8 x i8>3149; CHECK-NEXT: store <8 x i8> [[_MSPROP2]], ptr @__msan_retval_tls, align 83150; CHECK-NEXT: ret <8 x i8> [[NARROWED]]3151;3152 %tmpvar1 = load <8 x i16>, ptr %A3153 %tmpvar2 = load <8 x i16>, ptr %B3154 %sum = add <8 x i16> %tmpvar1, %tmpvar23155 %high_bits = lshr <8 x i16> %sum, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>3156 %narrowed = trunc <8 x i16> %high_bits to <8 x i8>3157 ret <8 x i8> %narrowed3158}3159 3160define <4 x i16> @addhn4h_natural(ptr %A, ptr %B) nounwind #0 {3161; CHECK-LABEL: define <4 x i16> @addhn4h_natural(3162; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {3163; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83164; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83165; CHECK-NEXT: call void @llvm.donothing()3166; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03167; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]3168; CHECK: 3:3169; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]3170; CHECK-NEXT: unreachable3171; CHECK: 4:3172; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i32>, ptr [[A]], align 163173; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i643174; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885763175; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr3176; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 163177; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 03178; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]3179; CHECK: 8:3180; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]3181; CHECK-NEXT: unreachable3182; CHECK: 9:3183; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i32>, ptr [[B]], align 163184; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i643185; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885763186; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr3187; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 163188; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[_MSLD]], [[_MSLD1]]3189; CHECK-NEXT: [[SUM:%.*]] = add <4 x i32> [[TMPVAR1]], [[TMPVAR2]]3190; CHECK-NEXT: [[TMP13:%.*]] = lshr <4 x i32> [[_MSPROP]], splat (i32 16)3191; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i32> [[TMP13]], zeroinitializer3192; CHECK-NEXT: [[HIGH_BITS:%.*]] = lshr <4 x i32> [[SUM]], splat (i32 16)3193; CHECK-NEXT: [[_MSPROP2:%.*]] = trunc <4 x i32> [[TMP14]] to <4 x i16>3194; CHECK-NEXT: [[NARROWED:%.*]] = trunc <4 x i32> [[HIGH_BITS]] to <4 x i16>3195; CHECK-NEXT: store <4 x i16> [[_MSPROP2]], ptr @__msan_retval_tls, align 83196; CHECK-NEXT: ret <4 x i16> [[NARROWED]]3197;3198 %tmpvar1 = load <4 x i32>, ptr %A3199 %tmpvar2 = load <4 x i32>, ptr %B3200 %sum = add <4 x i32> %tmpvar1, %tmpvar23201 %high_bits = lshr <4 x i32> %sum, <i32 16, i32 16, i32 16, i32 16>3202 %narrowed = trunc <4 x i32> %high_bits to <4 x i16>3203 ret <4 x i16> %narrowed3204}3205 3206define <2 x i32> @addhn2s_natural(ptr %A, ptr %B) nounwind #0 {3207; CHECK-LABEL: define <2 x i32> @addhn2s_natural(3208; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {3209; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83210; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83211; CHECK-NEXT: call void @llvm.donothing()3212; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03213; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]3214; CHECK: 3:3215; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]3216; CHECK-NEXT: unreachable3217; CHECK: 4:3218; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i64>, ptr [[A]], align 163219; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i643220; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885763221; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr3222; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 163223; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 03224; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]3225; CHECK: 8:3226; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]3227; CHECK-NEXT: unreachable3228; CHECK: 9:3229; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x i64>, ptr [[B]], align 163230; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i643231; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885763232; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr3233; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 163234; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[_MSLD]], [[_MSLD1]]3235; CHECK-NEXT: [[SUM:%.*]] = add <2 x i64> [[TMPVAR1]], [[TMPVAR2]]3236; CHECK-NEXT: [[TMP13:%.*]] = lshr <2 x i64> [[_MSPROP]], splat (i64 32)3237; CHECK-NEXT: [[TMP14:%.*]] = or <2 x i64> [[TMP13]], zeroinitializer3238; CHECK-NEXT: [[HIGH_BITS:%.*]] = lshr <2 x i64> [[SUM]], splat (i64 32)3239; CHECK-NEXT: [[_MSPROP2:%.*]] = trunc <2 x i64> [[TMP14]] to <2 x i32>3240; CHECK-NEXT: [[NARROWED:%.*]] = trunc <2 x i64> [[HIGH_BITS]] to <2 x i32>3241; CHECK-NEXT: store <2 x i32> [[_MSPROP2]], ptr @__msan_retval_tls, align 83242; CHECK-NEXT: ret <2 x i32> [[NARROWED]]3243;3244 %tmpvar1 = load <2 x i64>, ptr %A3245 %tmpvar2 = load <2 x i64>, ptr %B3246 %sum = add <2 x i64> %tmpvar1, %tmpvar23247 %high_bits = lshr <2 x i64> %sum, <i64 32, i64 32>3248 %narrowed = trunc <2 x i64> %high_bits to <2 x i32>3249 ret <2 x i32> %narrowed3250}3251 3252define <16 x i8> @addhn2_16b_natural(<8 x i8> %low, ptr %A, ptr %B) nounwind #0 {3253; CHECK-LABEL: define <16 x i8> @addhn2_16b_natural(3254; CHECK-SAME: <8 x i8> [[LOW:%.*]], ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {3255; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83256; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83257; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i8>, ptr @__msan_param_tls, align 83258; CHECK-NEXT: call void @llvm.donothing()3259; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03260; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]3261; CHECK: 4:3262; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]3263; CHECK-NEXT: unreachable3264; CHECK: 5:3265; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i16>, ptr [[A]], align 163266; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i643267; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 1935140464885763268; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr3269; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP8]], align 163270; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP2]], 03271; CHECK-NEXT: br i1 [[_MSCMP4]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]3272; CHECK: 9:3273; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]3274; CHECK-NEXT: unreachable3275; CHECK: 10:3276; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i16>, ptr [[B]], align 163277; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i643278; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 1935140464885763279; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr3280; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP13]], align 163281; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[_MSLD]], [[_MSLD1]]3282; CHECK-NEXT: [[SUM:%.*]] = add <8 x i16> [[TMPVAR1]], [[TMPVAR2]]3283; CHECK-NEXT: [[TMP14:%.*]] = lshr <8 x i16> [[_MSPROP]], splat (i16 8)3284; CHECK-NEXT: [[TMP15:%.*]] = or <8 x i16> [[TMP14]], zeroinitializer3285; CHECK-NEXT: [[HIGH_BITS:%.*]] = lshr <8 x i16> [[SUM]], splat (i16 8)3286; CHECK-NEXT: [[_MSPROP2:%.*]] = trunc <8 x i16> [[TMP15]] to <8 x i8>3287; CHECK-NEXT: [[NARROWED:%.*]] = trunc <8 x i16> [[HIGH_BITS]] to <8 x i8>3288; CHECK-NEXT: [[_MSPROP3:%.*]] = shufflevector <8 x i8> [[TMP3]], <8 x i8> [[_MSPROP2]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>3289; CHECK-NEXT: [[RES:%.*]] = shufflevector <8 x i8> [[LOW]], <8 x i8> [[NARROWED]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>3290; CHECK-NEXT: store <16 x i8> [[_MSPROP3]], ptr @__msan_retval_tls, align 83291; CHECK-NEXT: ret <16 x i8> [[RES]]3292;3293 %tmpvar1 = load <8 x i16>, ptr %A3294 %tmpvar2 = load <8 x i16>, ptr %B3295 %sum = add <8 x i16> %tmpvar1, %tmpvar23296 %high_bits = lshr <8 x i16> %sum, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>3297 %narrowed = trunc <8 x i16> %high_bits to <8 x i8>3298 %res = shufflevector <8 x i8> %low, <8 x i8> %narrowed, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>3299 ret <16 x i8> %res3300}3301 3302define <8 x i16> @addhn2_8h_natural(<4 x i16> %low, ptr %A, ptr %B) nounwind #0 {3303; CHECK-LABEL: define <8 x i16> @addhn2_8h_natural(3304; CHECK-SAME: <4 x i16> [[LOW:%.*]], ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {3305; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83306; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83307; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i16>, ptr @__msan_param_tls, align 83308; CHECK-NEXT: call void @llvm.donothing()3309; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03310; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]3311; CHECK: 4:3312; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]3313; CHECK-NEXT: unreachable3314; CHECK: 5:3315; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i32>, ptr [[A]], align 163316; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i643317; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 1935140464885763318; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr3319; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP8]], align 163320; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP2]], 03321; CHECK-NEXT: br i1 [[_MSCMP4]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]3322; CHECK: 9:3323; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]3324; CHECK-NEXT: unreachable3325; CHECK: 10:3326; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i32>, ptr [[B]], align 163327; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i643328; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 1935140464885763329; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr3330; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP13]], align 163331; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[_MSLD]], [[_MSLD1]]3332; CHECK-NEXT: [[SUM:%.*]] = add <4 x i32> [[TMPVAR1]], [[TMPVAR2]]3333; CHECK-NEXT: [[TMP14:%.*]] = lshr <4 x i32> [[_MSPROP]], splat (i32 16)3334; CHECK-NEXT: [[TMP15:%.*]] = or <4 x i32> [[TMP14]], zeroinitializer3335; CHECK-NEXT: [[HIGH_BITS:%.*]] = lshr <4 x i32> [[SUM]], splat (i32 16)3336; CHECK-NEXT: [[_MSPROP2:%.*]] = trunc <4 x i32> [[TMP15]] to <4 x i16>3337; CHECK-NEXT: [[NARROWED:%.*]] = trunc <4 x i32> [[HIGH_BITS]] to <4 x i16>3338; CHECK-NEXT: [[_MSPROP3:%.*]] = shufflevector <4 x i16> [[TMP3]], <4 x i16> [[_MSPROP2]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>3339; CHECK-NEXT: [[RES:%.*]] = shufflevector <4 x i16> [[LOW]], <4 x i16> [[NARROWED]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>3340; CHECK-NEXT: store <8 x i16> [[_MSPROP3]], ptr @__msan_retval_tls, align 83341; CHECK-NEXT: ret <8 x i16> [[RES]]3342;3343 %tmpvar1 = load <4 x i32>, ptr %A3344 %tmpvar2 = load <4 x i32>, ptr %B3345 %sum = add <4 x i32> %tmpvar1, %tmpvar23346 %high_bits = lshr <4 x i32> %sum, <i32 16, i32 16, i32 16, i32 16>3347 %narrowed = trunc <4 x i32> %high_bits to <4 x i16>3348 %res = shufflevector <4 x i16> %low, <4 x i16> %narrowed, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>3349 ret <8 x i16> %res3350}3351 3352define <4 x i32> @addhn2_4s_natural(<2 x i32> %low, ptr %A, ptr %B) nounwind #0 {3353; CHECK-LABEL: define <4 x i32> @addhn2_4s_natural(3354; CHECK-SAME: <2 x i32> [[LOW:%.*]], ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {3355; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83356; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83357; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 83358; CHECK-NEXT: call void @llvm.donothing()3359; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03360; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]3361; CHECK: 4:3362; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]3363; CHECK-NEXT: unreachable3364; CHECK: 5:3365; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i64>, ptr [[A]], align 163366; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i643367; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 1935140464885763368; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr3369; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP8]], align 163370; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP2]], 03371; CHECK-NEXT: br i1 [[_MSCMP4]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]3372; CHECK: 9:3373; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]3374; CHECK-NEXT: unreachable3375; CHECK: 10:3376; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x i64>, ptr [[B]], align 163377; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i643378; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 1935140464885763379; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr3380; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP13]], align 163381; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[_MSLD]], [[_MSLD1]]3382; CHECK-NEXT: [[SUM:%.*]] = add <2 x i64> [[TMPVAR1]], [[TMPVAR2]]3383; CHECK-NEXT: [[TMP14:%.*]] = lshr <2 x i64> [[_MSPROP]], splat (i64 32)3384; CHECK-NEXT: [[TMP15:%.*]] = or <2 x i64> [[TMP14]], zeroinitializer3385; CHECK-NEXT: [[HIGH_BITS:%.*]] = lshr <2 x i64> [[SUM]], splat (i64 32)3386; CHECK-NEXT: [[_MSPROP2:%.*]] = trunc <2 x i64> [[TMP15]] to <2 x i32>3387; CHECK-NEXT: [[NARROWED:%.*]] = trunc <2 x i64> [[HIGH_BITS]] to <2 x i32>3388; CHECK-NEXT: [[_MSPROP3:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> [[_MSPROP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>3389; CHECK-NEXT: [[RES:%.*]] = shufflevector <2 x i32> [[LOW]], <2 x i32> [[NARROWED]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>3390; CHECK-NEXT: store <4 x i32> [[_MSPROP3]], ptr @__msan_retval_tls, align 83391; CHECK-NEXT: ret <4 x i32> [[RES]]3392;3393 %tmpvar1 = load <2 x i64>, ptr %A3394 %tmpvar2 = load <2 x i64>, ptr %B3395 %sum = add <2 x i64> %tmpvar1, %tmpvar23396 %high_bits = lshr <2 x i64> %sum, <i64 32, i64 32>3397 %narrowed = trunc <2 x i64> %high_bits to <2 x i32>3398 %res = shufflevector <2 x i32> %low, <2 x i32> %narrowed, <4 x i32> <i32 0, i32 1, i32 2, i32 3>3399 ret <4 x i32> %res3400}3401 3402define <4 x i32> @addhn_addhn2_4s(ptr %A, ptr %B, ptr %C, ptr %D) nounwind #0 {3403; CHECK-LABEL: define <4 x i32> @addhn_addhn2_4s(3404; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]], ptr [[D:%.*]]) #[[ATTR0]] {3405; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83406; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83407; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83408; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 24), align 83409; CHECK-NEXT: call void @llvm.donothing()3410; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03411; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP5:%.*]], label [[TMP6:%.*]], !prof [[PROF1]]3412; CHECK: 5:3413; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]3414; CHECK-NEXT: unreachable3415; CHECK: 6:3416; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i64>, ptr [[A]], align 163417; CHECK-NEXT: [[TMP7:%.*]] = ptrtoint ptr [[A]] to i643418; CHECK-NEXT: [[TMP8:%.*]] = xor i64 [[TMP7]], 1935140464885763419; CHECK-NEXT: [[TMP9:%.*]] = inttoptr i64 [[TMP8]] to ptr3420; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP9]], align 163421; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i64 [[TMP2]], 03422; CHECK-NEXT: br i1 [[_MSCMP8]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]3423; CHECK: 10:3424; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]3425; CHECK-NEXT: unreachable3426; CHECK: 11:3427; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x i64>, ptr [[B]], align 163428; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[B]] to i643429; CHECK-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], 1935140464885763430; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr3431; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP14]], align 163432; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[_MSLD]], [[_MSLD1]]3433; CHECK-NEXT: [[SUM1:%.*]] = add <2 x i64> [[TMPVAR1]], [[TMPVAR2]]3434; CHECK-NEXT: [[TMP15:%.*]] = lshr <2 x i64> [[_MSPROP]], splat (i64 32)3435; CHECK-NEXT: [[TMP16:%.*]] = or <2 x i64> [[TMP15]], zeroinitializer3436; CHECK-NEXT: [[LOW_BITS:%.*]] = lshr <2 x i64> [[SUM1]], splat (i64 32)3437; CHECK-NEXT: [[_MSPROP2:%.*]] = trunc <2 x i64> [[TMP16]] to <2 x i32>3438; CHECK-NEXT: [[NARROWED1:%.*]] = trunc <2 x i64> [[LOW_BITS]] to <2 x i32>3439; CHECK-NEXT: [[_MSCMP9:%.*]] = icmp ne i64 [[TMP3]], 03440; CHECK-NEXT: br i1 [[_MSCMP9]], label [[TMP17:%.*]], label [[TMP18:%.*]], !prof [[PROF1]]3441; CHECK: 17:3442; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]3443; CHECK-NEXT: unreachable3444; CHECK: 18:3445; CHECK-NEXT: [[TMPVAR3:%.*]] = load <2 x i64>, ptr [[C]], align 163446; CHECK-NEXT: [[TMP19:%.*]] = ptrtoint ptr [[C]] to i643447; CHECK-NEXT: [[TMP20:%.*]] = xor i64 [[TMP19]], 1935140464885763448; CHECK-NEXT: [[TMP21:%.*]] = inttoptr i64 [[TMP20]] to ptr3449; CHECK-NEXT: [[_MSLD3:%.*]] = load <2 x i64>, ptr [[TMP21]], align 163450; CHECK-NEXT: [[_MSCMP10:%.*]] = icmp ne i64 [[TMP4]], 03451; CHECK-NEXT: br i1 [[_MSCMP10]], label [[TMP22:%.*]], label [[TMP23:%.*]], !prof [[PROF1]]3452; CHECK: 22:3453; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]3454; CHECK-NEXT: unreachable3455; CHECK: 23:3456; CHECK-NEXT: [[TMPVAR4:%.*]] = load <2 x i64>, ptr [[D]], align 163457; CHECK-NEXT: [[TMP24:%.*]] = ptrtoint ptr [[D]] to i643458; CHECK-NEXT: [[TMP25:%.*]] = xor i64 [[TMP24]], 1935140464885763459; CHECK-NEXT: [[TMP26:%.*]] = inttoptr i64 [[TMP25]] to ptr3460; CHECK-NEXT: [[_MSLD4:%.*]] = load <2 x i64>, ptr [[TMP26]], align 163461; CHECK-NEXT: [[_MSPROP5:%.*]] = or <2 x i64> [[_MSLD3]], [[_MSLD4]]3462; CHECK-NEXT: [[SUM2:%.*]] = add <2 x i64> [[TMPVAR3]], [[TMPVAR4]]3463; CHECK-NEXT: [[TMP27:%.*]] = lshr <2 x i64> [[_MSPROP]], splat (i64 32)3464; CHECK-NEXT: [[TMP28:%.*]] = or <2 x i64> [[TMP27]], zeroinitializer3465; CHECK-NEXT: [[HIGH_BITS:%.*]] = lshr <2 x i64> [[SUM1]], splat (i64 32)3466; CHECK-NEXT: [[_MSPROP6:%.*]] = trunc <2 x i64> [[TMP28]] to <2 x i32>3467; CHECK-NEXT: [[NARROWED2:%.*]] = trunc <2 x i64> [[HIGH_BITS]] to <2 x i32>3468; CHECK-NEXT: [[_MSPROP7:%.*]] = shufflevector <2 x i32> [[_MSPROP2]], <2 x i32> [[_MSPROP6]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>3469; CHECK-NEXT: [[RES:%.*]] = shufflevector <2 x i32> [[NARROWED1]], <2 x i32> [[NARROWED2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>3470; CHECK-NEXT: store <4 x i32> [[_MSPROP7]], ptr @__msan_retval_tls, align 83471; CHECK-NEXT: ret <4 x i32> [[RES]]3472;3473 %tmpvar1 = load <2 x i64>, ptr %A3474 %tmpvar2 = load <2 x i64>, ptr %B3475 %sum1 = add <2 x i64> %tmpvar1, %tmpvar23476 %low_bits = lshr <2 x i64> %sum1, <i64 32, i64 32>3477 %narrowed1 = trunc <2 x i64> %low_bits to <2 x i32>3478 %tmpvar3 = load <2 x i64>, ptr %C3479 %tmpvar4 = load <2 x i64>, ptr %D3480 %sum2 = add <2 x i64> %tmpvar3, %tmpvar43481 %high_bits = lshr <2 x i64> %sum1, <i64 32, i64 32>3482 %narrowed2 = trunc <2 x i64> %high_bits to <2 x i32>3483 %res = shufflevector <2 x i32> %narrowed1, <2 x i32> %narrowed2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>3484 ret <4 x i32> %res3485}3486 3487define <8 x i8> @subhn8b_natural(ptr %A, ptr %B) nounwind #0 {3488; CHECK-LABEL: define <8 x i8> @subhn8b_natural(3489; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {3490; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83491; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83492; CHECK-NEXT: call void @llvm.donothing()3493; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03494; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]3495; CHECK: 3:3496; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]3497; CHECK-NEXT: unreachable3498; CHECK: 4:3499; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i16>, ptr [[A]], align 163500; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i643501; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885763502; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr3503; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 163504; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 03505; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]3506; CHECK: 8:3507; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]3508; CHECK-NEXT: unreachable3509; CHECK: 9:3510; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i16>, ptr [[B]], align 163511; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i643512; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885763513; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr3514; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 163515; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[_MSLD]], [[_MSLD1]]3516; CHECK-NEXT: [[DIFF:%.*]] = sub <8 x i16> [[TMPVAR1]], [[TMPVAR2]]3517; CHECK-NEXT: [[TMP13:%.*]] = lshr <8 x i16> [[_MSPROP]], splat (i16 8)3518; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i16> [[TMP13]], zeroinitializer3519; CHECK-NEXT: [[HIGH_BITS:%.*]] = lshr <8 x i16> [[DIFF]], splat (i16 8)3520; CHECK-NEXT: [[_MSPROP2:%.*]] = trunc <8 x i16> [[TMP14]] to <8 x i8>3521; CHECK-NEXT: [[NARROWED:%.*]] = trunc <8 x i16> [[HIGH_BITS]] to <8 x i8>3522; CHECK-NEXT: store <8 x i8> [[_MSPROP2]], ptr @__msan_retval_tls, align 83523; CHECK-NEXT: ret <8 x i8> [[NARROWED]]3524;3525 %tmpvar1 = load <8 x i16>, ptr %A3526 %tmpvar2 = load <8 x i16>, ptr %B3527 %diff = sub <8 x i16> %tmpvar1, %tmpvar23528 %high_bits = lshr <8 x i16> %diff, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>3529 %narrowed = trunc <8 x i16> %high_bits to <8 x i8>3530 ret <8 x i8> %narrowed3531}3532 3533define <4 x i16> @subhn4h_natural(ptr %A, ptr %B) nounwind #0 {3534; CHECK-LABEL: define <4 x i16> @subhn4h_natural(3535; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {3536; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83537; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83538; CHECK-NEXT: call void @llvm.donothing()3539; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03540; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]3541; CHECK: 3:3542; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]3543; CHECK-NEXT: unreachable3544; CHECK: 4:3545; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i32>, ptr [[A]], align 163546; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i643547; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885763548; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr3549; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 163550; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 03551; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]3552; CHECK: 8:3553; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]3554; CHECK-NEXT: unreachable3555; CHECK: 9:3556; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i32>, ptr [[B]], align 163557; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i643558; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885763559; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr3560; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 163561; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[_MSLD]], [[_MSLD1]]3562; CHECK-NEXT: [[DIFF:%.*]] = sub <4 x i32> [[TMPVAR1]], [[TMPVAR2]]3563; CHECK-NEXT: [[TMP13:%.*]] = lshr <4 x i32> [[_MSPROP]], splat (i32 16)3564; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i32> [[TMP13]], zeroinitializer3565; CHECK-NEXT: [[HIGH_BITS:%.*]] = lshr <4 x i32> [[DIFF]], splat (i32 16)3566; CHECK-NEXT: [[_MSPROP2:%.*]] = trunc <4 x i32> [[TMP14]] to <4 x i16>3567; CHECK-NEXT: [[NARROWED:%.*]] = trunc <4 x i32> [[HIGH_BITS]] to <4 x i16>3568; CHECK-NEXT: store <4 x i16> [[_MSPROP2]], ptr @__msan_retval_tls, align 83569; CHECK-NEXT: ret <4 x i16> [[NARROWED]]3570;3571 %tmpvar1 = load <4 x i32>, ptr %A3572 %tmpvar2 = load <4 x i32>, ptr %B3573 %diff = sub <4 x i32> %tmpvar1, %tmpvar23574 %high_bits = lshr <4 x i32> %diff, <i32 16, i32 16, i32 16, i32 16>3575 %narrowed = trunc <4 x i32> %high_bits to <4 x i16>3576 ret <4 x i16> %narrowed3577}3578 3579define <2 x i32> @subhn2s_natural(ptr %A, ptr %B) nounwind #0 {3580; CHECK-LABEL: define <2 x i32> @subhn2s_natural(3581; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {3582; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83583; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83584; CHECK-NEXT: call void @llvm.donothing()3585; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03586; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]3587; CHECK: 3:3588; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]3589; CHECK-NEXT: unreachable3590; CHECK: 4:3591; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i64>, ptr [[A]], align 163592; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i643593; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885763594; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr3595; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 163596; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 03597; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]3598; CHECK: 8:3599; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]3600; CHECK-NEXT: unreachable3601; CHECK: 9:3602; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x i64>, ptr [[B]], align 163603; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i643604; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885763605; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr3606; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 163607; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[_MSLD]], [[_MSLD1]]3608; CHECK-NEXT: [[DIFF:%.*]] = sub <2 x i64> [[TMPVAR1]], [[TMPVAR2]]3609; CHECK-NEXT: [[TMP13:%.*]] = lshr <2 x i64> [[_MSPROP]], splat (i64 32)3610; CHECK-NEXT: [[TMP14:%.*]] = or <2 x i64> [[TMP13]], zeroinitializer3611; CHECK-NEXT: [[HIGH_BITS:%.*]] = lshr <2 x i64> [[DIFF]], splat (i64 32)3612; CHECK-NEXT: [[_MSPROP2:%.*]] = trunc <2 x i64> [[TMP14]] to <2 x i32>3613; CHECK-NEXT: [[NARROWED:%.*]] = trunc <2 x i64> [[HIGH_BITS]] to <2 x i32>3614; CHECK-NEXT: store <2 x i32> [[_MSPROP2]], ptr @__msan_retval_tls, align 83615; CHECK-NEXT: ret <2 x i32> [[NARROWED]]3616;3617 %tmpvar1 = load <2 x i64>, ptr %A3618 %tmpvar2 = load <2 x i64>, ptr %B3619 %diff = sub <2 x i64> %tmpvar1, %tmpvar23620 %high_bits = lshr <2 x i64> %diff, <i64 32, i64 32>3621 %narrowed = trunc <2 x i64> %high_bits to <2 x i32>3622 ret <2 x i32> %narrowed3623}3624 3625define <16 x i8> @subhn2_16b_natural(<8 x i8> %low, ptr %A, ptr %B) nounwind #0 {3626; CHECK-LABEL: define <16 x i8> @subhn2_16b_natural(3627; CHECK-SAME: <8 x i8> [[LOW:%.*]], ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {3628; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83629; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83630; CHECK-NEXT: [[TMP3:%.*]] = load <8 x i8>, ptr @__msan_param_tls, align 83631; CHECK-NEXT: call void @llvm.donothing()3632; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03633; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]3634; CHECK: 4:3635; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]3636; CHECK-NEXT: unreachable3637; CHECK: 5:3638; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i16>, ptr [[A]], align 163639; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i643640; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 1935140464885763641; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr3642; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP8]], align 163643; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP2]], 03644; CHECK-NEXT: br i1 [[_MSCMP4]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]3645; CHECK: 9:3646; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]3647; CHECK-NEXT: unreachable3648; CHECK: 10:3649; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i16>, ptr [[B]], align 163650; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i643651; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 1935140464885763652; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr3653; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP13]], align 163654; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[_MSLD]], [[_MSLD1]]3655; CHECK-NEXT: [[DIFF:%.*]] = sub <8 x i16> [[TMPVAR1]], [[TMPVAR2]]3656; CHECK-NEXT: [[TMP14:%.*]] = lshr <8 x i16> [[_MSPROP]], splat (i16 8)3657; CHECK-NEXT: [[TMP15:%.*]] = or <8 x i16> [[TMP14]], zeroinitializer3658; CHECK-NEXT: [[HIGH_BITS:%.*]] = lshr <8 x i16> [[DIFF]], splat (i16 8)3659; CHECK-NEXT: [[_MSPROP2:%.*]] = trunc <8 x i16> [[TMP15]] to <8 x i8>3660; CHECK-NEXT: [[NARROWED:%.*]] = trunc <8 x i16> [[HIGH_BITS]] to <8 x i8>3661; CHECK-NEXT: [[_MSPROP3:%.*]] = shufflevector <8 x i8> [[TMP3]], <8 x i8> [[_MSPROP2]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>3662; CHECK-NEXT: [[RES:%.*]] = shufflevector <8 x i8> [[LOW]], <8 x i8> [[NARROWED]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>3663; CHECK-NEXT: store <16 x i8> [[_MSPROP3]], ptr @__msan_retval_tls, align 83664; CHECK-NEXT: ret <16 x i8> [[RES]]3665;3666 %tmpvar1 = load <8 x i16>, ptr %A3667 %tmpvar2 = load <8 x i16>, ptr %B3668 %diff = sub <8 x i16> %tmpvar1, %tmpvar23669 %high_bits = lshr <8 x i16> %diff, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>3670 %narrowed = trunc <8 x i16> %high_bits to <8 x i8>3671 %res = shufflevector <8 x i8> %low, <8 x i8> %narrowed, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>3672 ret <16 x i8> %res3673}3674 3675define <8 x i16> @subhn2_8h_natural(<4 x i16> %low, ptr %A, ptr %B) nounwind #0 {3676; CHECK-LABEL: define <8 x i16> @subhn2_8h_natural(3677; CHECK-SAME: <4 x i16> [[LOW:%.*]], ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {3678; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83679; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83680; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i16>, ptr @__msan_param_tls, align 83681; CHECK-NEXT: call void @llvm.donothing()3682; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03683; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]3684; CHECK: 4:3685; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]3686; CHECK-NEXT: unreachable3687; CHECK: 5:3688; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i32>, ptr [[A]], align 163689; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i643690; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 1935140464885763691; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr3692; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP8]], align 163693; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP2]], 03694; CHECK-NEXT: br i1 [[_MSCMP4]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]3695; CHECK: 9:3696; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]3697; CHECK-NEXT: unreachable3698; CHECK: 10:3699; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i32>, ptr [[B]], align 163700; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i643701; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 1935140464885763702; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr3703; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP13]], align 163704; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[_MSLD]], [[_MSLD1]]3705; CHECK-NEXT: [[DIFF:%.*]] = sub <4 x i32> [[TMPVAR1]], [[TMPVAR2]]3706; CHECK-NEXT: [[TMP14:%.*]] = lshr <4 x i32> [[_MSPROP]], splat (i32 16)3707; CHECK-NEXT: [[TMP15:%.*]] = or <4 x i32> [[TMP14]], zeroinitializer3708; CHECK-NEXT: [[HIGH_BITS:%.*]] = lshr <4 x i32> [[DIFF]], splat (i32 16)3709; CHECK-NEXT: [[_MSPROP2:%.*]] = trunc <4 x i32> [[TMP15]] to <4 x i16>3710; CHECK-NEXT: [[NARROWED:%.*]] = trunc <4 x i32> [[HIGH_BITS]] to <4 x i16>3711; CHECK-NEXT: [[_MSPROP3:%.*]] = shufflevector <4 x i16> [[TMP3]], <4 x i16> [[_MSPROP2]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>3712; CHECK-NEXT: [[RES:%.*]] = shufflevector <4 x i16> [[LOW]], <4 x i16> [[NARROWED]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>3713; CHECK-NEXT: store <8 x i16> [[_MSPROP3]], ptr @__msan_retval_tls, align 83714; CHECK-NEXT: ret <8 x i16> [[RES]]3715;3716 %tmpvar1 = load <4 x i32>, ptr %A3717 %tmpvar2 = load <4 x i32>, ptr %B3718 %diff = sub <4 x i32> %tmpvar1, %tmpvar23719 %high_bits = lshr <4 x i32> %diff, <i32 16, i32 16, i32 16, i32 16>3720 %narrowed = trunc <4 x i32> %high_bits to <4 x i16>3721 %res = shufflevector <4 x i16> %low, <4 x i16> %narrowed, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>3722 ret <8 x i16> %res3723}3724 3725define <4 x i32> @subhn2_4s_natural(<2 x i32> %low, ptr %A, ptr %B) nounwind #0 {3726; CHECK-LABEL: define <4 x i32> @subhn2_4s_natural(3727; CHECK-SAME: <2 x i32> [[LOW:%.*]], ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {3728; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83729; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83730; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 83731; CHECK-NEXT: call void @llvm.donothing()3732; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03733; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]3734; CHECK: 4:3735; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]3736; CHECK-NEXT: unreachable3737; CHECK: 5:3738; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i64>, ptr [[A]], align 163739; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i643740; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 1935140464885763741; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr3742; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP8]], align 163743; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP2]], 03744; CHECK-NEXT: br i1 [[_MSCMP4]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]3745; CHECK: 9:3746; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4]]3747; CHECK-NEXT: unreachable3748; CHECK: 10:3749; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x i64>, ptr [[B]], align 163750; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i643751; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 1935140464885763752; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr3753; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP13]], align 163754; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[_MSLD]], [[_MSLD1]]3755; CHECK-NEXT: [[DIFF:%.*]] = sub <2 x i64> [[TMPVAR1]], [[TMPVAR2]]3756; CHECK-NEXT: [[TMP14:%.*]] = lshr <2 x i64> [[_MSPROP]], splat (i64 32)3757; CHECK-NEXT: [[TMP15:%.*]] = or <2 x i64> [[TMP14]], zeroinitializer3758; CHECK-NEXT: [[HIGH_BITS:%.*]] = lshr <2 x i64> [[DIFF]], splat (i64 32)3759; CHECK-NEXT: [[_MSPROP2:%.*]] = trunc <2 x i64> [[TMP15]] to <2 x i32>3760; CHECK-NEXT: [[NARROWED:%.*]] = trunc <2 x i64> [[HIGH_BITS]] to <2 x i32>3761; CHECK-NEXT: [[_MSPROP3:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> [[_MSPROP2]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>3762; CHECK-NEXT: [[RES:%.*]] = shufflevector <2 x i32> [[LOW]], <2 x i32> [[NARROWED]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>3763; CHECK-NEXT: store <4 x i32> [[_MSPROP3]], ptr @__msan_retval_tls, align 83764; CHECK-NEXT: ret <4 x i32> [[RES]]3765;3766 %tmpvar1 = load <2 x i64>, ptr %A3767 %tmpvar2 = load <2 x i64>, ptr %B3768 %diff = sub <2 x i64> %tmpvar1, %tmpvar23769 %high_bits = lshr <2 x i64> %diff, <i64 32, i64 32>3770 %narrowed = trunc <2 x i64> %high_bits to <2 x i32>3771 %res = shufflevector <2 x i32> %low, <2 x i32> %narrowed, <4 x i32> <i32 0, i32 1, i32 2, i32 3>3772 ret <4 x i32> %res3773}3774 3775attributes #0 = { sanitize_memory }3776;.3777; CHECK: [[PROF1]] = !{!"branch_weights", i32 1, i32 1048575}3778;.3779