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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: opt < %s -passes=msan -S | FileCheck %s3;4; Forked from llvm/test/CodeGen/AArch64/arm64-vaddv.ll5 6target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"7target triple = "aarch64--linux-android9001"8 9define signext i8 @test_vaddv_s8(<8 x i8> %a1) #0 {10; CHECK-LABEL: define signext i8 @test_vaddv_s8(11; CHECK-SAME: <8 x i8> [[A1:%.*]]) #[[ATTR0:[0-9]+]] {12; CHECK-NEXT: entry:13; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i8>, ptr @__msan_param_tls, align 814; CHECK-NEXT: call void @llvm.donothing()15; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> [[TMP0]])16; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[TMP1]] to i3217; CHECK-NEXT: [[VADDV_I:%.*]] = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8> [[A1]])18; CHECK-NEXT: [[_MSPROP:%.*]] = trunc i32 [[TMP2]] to i819; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[VADDV_I]] to i820; CHECK-NEXT: store i8 [[_MSPROP]], ptr @__msan_retval_tls, align 821; CHECK-NEXT: ret i8 [[TMP4]]22;23entry:24 %vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8> %a1)25 %0 = trunc i32 %vaddv.i to i826 ret i8 %027}28 29define <8 x i8> @test_vaddv_s8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) #0 {30; CHECK-LABEL: define <8 x i8> @test_vaddv_s8_used_by_laneop(31; CHECK-SAME: <8 x i8> [[A1:%.*]], <8 x i8> [[A2:%.*]]) #[[ATTR0]] {32; CHECK-NEXT: entry:33; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 834; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr @__msan_param_tls, align 835; CHECK-NEXT: call void @llvm.donothing()36; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> [[TMP0]])37; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i3238; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8> [[A2]])39; CHECK-NEXT: [[_MSPROP1:%.*]] = trunc i32 [[TMP3]] to i840; CHECK-NEXT: [[TMP6:%.*]] = trunc i32 [[TMP5]] to i841; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <8 x i8> [[TMP1]], i8 [[_MSPROP1]], i32 342; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i8> [[A1]], i8 [[TMP6]], i32 343; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 844; CHECK-NEXT: ret <8 x i8> [[TMP7]]45;46entry:47 %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8> %a2)48 %1 = trunc i32 %0 to i849 %2 = insertelement <8 x i8> %a1, i8 %1, i32 350 ret <8 x i8> %251}52 53define signext i16 @test_vaddv_s16(<4 x i16> %a1) #0 {54; CHECK-LABEL: define signext i16 @test_vaddv_s16(55; CHECK-SAME: <4 x i16> [[A1:%.*]]) #[[ATTR0]] {56; CHECK-NEXT: entry:57; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr @__msan_param_tls, align 858; CHECK-NEXT: call void @llvm.donothing()59; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP0]])60; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[TMP1]] to i3261; CHECK-NEXT: [[VADDV_I:%.*]] = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16> [[A1]])62; CHECK-NEXT: [[_MSPROP:%.*]] = trunc i32 [[TMP2]] to i1663; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[VADDV_I]] to i1664; CHECK-NEXT: store i16 [[_MSPROP]], ptr @__msan_retval_tls, align 865; CHECK-NEXT: ret i16 [[TMP4]]66;67entry:68 %vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16> %a1)69 %0 = trunc i32 %vaddv.i to i1670 ret i16 %071}72 73define <4 x i16> @test_vaddv_s16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) #0 {74; CHECK-LABEL: define <4 x i16> @test_vaddv_s16_used_by_laneop(75; CHECK-SAME: <4 x i16> [[A1:%.*]], <4 x i16> [[A2:%.*]]) #[[ATTR0]] {76; CHECK-NEXT: entry:77; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 878; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @__msan_param_tls, align 879; CHECK-NEXT: call void @llvm.donothing()80; CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP0]])81; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[TMP2]] to i3282; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16> [[A2]])83; CHECK-NEXT: [[_MSPROP1:%.*]] = trunc i32 [[TMP3]] to i1684; CHECK-NEXT: [[TMP6:%.*]] = trunc i32 [[TMP5]] to i1685; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <4 x i16> [[TMP1]], i16 [[_MSPROP1]], i32 386; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i16> [[A1]], i16 [[TMP6]], i32 387; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 888; CHECK-NEXT: ret <4 x i16> [[TMP7]]89;90entry:91 %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16> %a2)92 %1 = trunc i32 %0 to i1693 %2 = insertelement <4 x i16> %a1, i16 %1, i32 394 ret <4 x i16> %295}96 97define i32 @test_vaddv_s32(<2 x i32> %a1) #0 {98; CHECK-LABEL: define i32 @test_vaddv_s32(99; CHECK-SAME: <2 x i32> [[A1:%.*]]) #[[ATTR0]] {100; CHECK-NEXT: entry:101; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8102; CHECK-NEXT: call void @llvm.donothing()103; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> [[TMP0]])104; CHECK-NEXT: [[VADDV_I:%.*]] = tail call i32 @llvm.aarch64.neon.saddv.i32.v2i32(<2 x i32> [[A1]])105; CHECK-NEXT: store i32 [[TMP1]], ptr @__msan_retval_tls, align 8106; CHECK-NEXT: ret i32 [[VADDV_I]]107;108; 2 x i32 is not supported by the ISA, thus, this is a special case109entry:110 %vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v2i32(<2 x i32> %a1)111 ret i32 %vaddv.i112}113 114define <2 x i32> @test_vaddv_s32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) #0 {115; CHECK-LABEL: define <2 x i32> @test_vaddv_s32_used_by_laneop(116; CHECK-SAME: <2 x i32> [[A1:%.*]], <2 x i32> [[A2:%.*]]) #[[ATTR0]] {117; CHECK-NEXT: entry:118; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8119; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8120; CHECK-NEXT: call void @llvm.donothing()121; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> [[TMP0]])122; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.saddv.i32.v2i32(<2 x i32> [[A2]])123; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[TMP2]], i32 1124; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> [[A1]], i32 [[TMP5]], i32 1125; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8126; CHECK-NEXT: ret <2 x i32> [[TMP6]]127;128entry:129 %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v2i32(<2 x i32> %a2)130 %1 = insertelement <2 x i32> %a1, i32 %0, i32 1131 ret <2 x i32> %1132}133 134define i64 @test_vaddv_s64(<2 x i64> %a1) #0 {135; CHECK-LABEL: define i64 @test_vaddv_s64(136; CHECK-SAME: <2 x i64> [[A1:%.*]]) #[[ATTR0]] {137; CHECK-NEXT: entry:138; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8139; CHECK-NEXT: call void @llvm.donothing()140; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> [[TMP0]])141; CHECK-NEXT: [[VADDV_I:%.*]] = tail call i64 @llvm.aarch64.neon.saddv.i64.v2i64(<2 x i64> [[A1]])142; CHECK-NEXT: store i64 [[TMP1]], ptr @__msan_retval_tls, align 8143; CHECK-NEXT: ret i64 [[VADDV_I]]144;145entry:146 %vaddv.i = tail call i64 @llvm.aarch64.neon.saddv.i64.v2i64(<2 x i64> %a1)147 ret i64 %vaddv.i148}149 150define <2 x i64> @test_vaddv_s64_used_by_laneop(<2 x i64> %a1, <2 x i64> %a2) #0 {151; CHECK-LABEL: define <2 x i64> @test_vaddv_s64_used_by_laneop(152; CHECK-SAME: <2 x i64> [[A1:%.*]], <2 x i64> [[A2:%.*]]) #[[ATTR0]] {153; CHECK-NEXT: entry:154; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8155; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8156; CHECK-NEXT: call void @llvm.donothing()157; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> [[TMP0]])158; CHECK-NEXT: [[TMP5:%.*]] = tail call i64 @llvm.aarch64.neon.saddv.i64.v2i64(<2 x i64> [[A2]])159; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <2 x i64> [[TMP1]], i64 [[TMP2]], i64 1160; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> [[A1]], i64 [[TMP5]], i64 1161; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 8162; CHECK-NEXT: ret <2 x i64> [[TMP6]]163;164entry:165 %0 = tail call i64 @llvm.aarch64.neon.saddv.i64.v2i64(<2 x i64> %a2)166 %1 = insertelement <2 x i64> %a1, i64 %0, i64 1167 ret <2 x i64> %1168}169 170define zeroext i8 @test_vaddv_u8(<8 x i8> %a1) #0 {171; CHECK-LABEL: define zeroext i8 @test_vaddv_u8(172; CHECK-SAME: <8 x i8> [[A1:%.*]]) #[[ATTR0]] {173; CHECK-NEXT: entry:174; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i8>, ptr @__msan_param_tls, align 8175; CHECK-NEXT: call void @llvm.donothing()176; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> [[TMP0]])177; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[TMP1]] to i32178; CHECK-NEXT: [[VADDV_I:%.*]] = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i8(<8 x i8> [[A1]])179; CHECK-NEXT: [[_MSPROP:%.*]] = trunc i32 [[TMP2]] to i8180; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[VADDV_I]] to i8181; CHECK-NEXT: store i8 [[_MSPROP]], ptr @__msan_retval_tls, align 8182; CHECK-NEXT: ret i8 [[TMP4]]183;184entry:185 %vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i8(<8 x i8> %a1)186 %0 = trunc i32 %vaddv.i to i8187 ret i8 %0188}189 190define <8 x i8> @test_vaddv_u8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) #0 {191; CHECK-LABEL: define <8 x i8> @test_vaddv_u8_used_by_laneop(192; CHECK-SAME: <8 x i8> [[A1:%.*]], <8 x i8> [[A2:%.*]]) #[[ATTR0]] {193; CHECK-NEXT: entry:194; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8195; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr @__msan_param_tls, align 8196; CHECK-NEXT: call void @llvm.donothing()197; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> [[TMP0]])198; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i32199; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i8(<8 x i8> [[A2]])200; CHECK-NEXT: [[_MSPROP1:%.*]] = trunc i32 [[TMP3]] to i8201; CHECK-NEXT: [[TMP6:%.*]] = trunc i32 [[TMP5]] to i8202; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <8 x i8> [[TMP1]], i8 [[_MSPROP1]], i32 3203; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i8> [[A1]], i8 [[TMP6]], i32 3204; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8205; CHECK-NEXT: ret <8 x i8> [[TMP7]]206;207entry:208 %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i8(<8 x i8> %a2)209 %1 = trunc i32 %0 to i8210 %2 = insertelement <8 x i8> %a1, i8 %1, i32 3211 ret <8 x i8> %2212}213 214define i32 @test_vaddv_u8_masked(<8 x i8> %a1) #0 {215; CHECK-LABEL: define i32 @test_vaddv_u8_masked(216; CHECK-SAME: <8 x i8> [[A1:%.*]]) #[[ATTR0]] {217; CHECK-NEXT: entry:218; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i8>, ptr @__msan_param_tls, align 8219; CHECK-NEXT: call void @llvm.donothing()220; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.vector.reduce.or.v8i8(<8 x i8> [[TMP0]])221; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[TMP1]] to i32222; CHECK-NEXT: [[VADDV_I:%.*]] = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i8(<8 x i8> [[A1]])223; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], 0224; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[VADDV_I]], 0225; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP2]], 511226; CHECK-NEXT: [[TMP8:%.*]] = or i32 [[TMP3]], [[TMP4]]227; CHECK-NEXT: [[TMP6:%.*]] = or i32 [[TMP8]], [[TMP5]]228; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[VADDV_I]], 511229; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8230; CHECK-NEXT: ret i32 [[TMP7]]231;232entry:233 %vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i8(<8 x i8> %a1)234 %0 = and i32 %vaddv.i, 511 ; 0x1ff235 ret i32 %0236}237 238define zeroext i16 @test_vaddv_u16(<4 x i16> %a1) #0 {239; CHECK-LABEL: define zeroext i16 @test_vaddv_u16(240; CHECK-SAME: <4 x i16> [[A1:%.*]]) #[[ATTR0]] {241; CHECK-NEXT: entry:242; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr @__msan_param_tls, align 8243; CHECK-NEXT: call void @llvm.donothing()244; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP0]])245; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[TMP1]] to i32246; CHECK-NEXT: [[VADDV_I:%.*]] = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i16(<4 x i16> [[A1]])247; CHECK-NEXT: [[_MSPROP:%.*]] = trunc i32 [[TMP2]] to i16248; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[VADDV_I]] to i16249; CHECK-NEXT: store i16 [[_MSPROP]], ptr @__msan_retval_tls, align 8250; CHECK-NEXT: ret i16 [[TMP4]]251;252entry:253 %vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i16(<4 x i16> %a1)254 %0 = trunc i32 %vaddv.i to i16255 ret i16 %0256}257 258define <4 x i16> @test_vaddv_u16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) #0 {259; CHECK-LABEL: define <4 x i16> @test_vaddv_u16_used_by_laneop(260; CHECK-SAME: <4 x i16> [[A1:%.*]], <4 x i16> [[A2:%.*]]) #[[ATTR0]] {261; CHECK-NEXT: entry:262; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8263; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @__msan_param_tls, align 8264; CHECK-NEXT: call void @llvm.donothing()265; CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP0]])266; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[TMP2]] to i32267; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i16(<4 x i16> [[A2]])268; CHECK-NEXT: [[_MSPROP1:%.*]] = trunc i32 [[TMP3]] to i16269; CHECK-NEXT: [[TMP6:%.*]] = trunc i32 [[TMP5]] to i16270; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <4 x i16> [[TMP1]], i16 [[_MSPROP1]], i32 3271; CHECK-NEXT: [[TMP7:%.*]] = insertelement <4 x i16> [[A1]], i16 [[TMP6]], i32 3272; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8273; CHECK-NEXT: ret <4 x i16> [[TMP7]]274;275entry:276 %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i16(<4 x i16> %a2)277 %1 = trunc i32 %0 to i16278 %2 = insertelement <4 x i16> %a1, i16 %1, i32 3279 ret <4 x i16> %2280}281 282define i32 @test_vaddv_u16_masked(<4 x i16> %a1) #0 {283; CHECK-LABEL: define i32 @test_vaddv_u16_masked(284; CHECK-SAME: <4 x i16> [[A1:%.*]]) #[[ATTR0]] {285; CHECK-NEXT: entry:286; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i16>, ptr @__msan_param_tls, align 8287; CHECK-NEXT: call void @llvm.donothing()288; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP0]])289; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[TMP1]] to i32290; CHECK-NEXT: [[VADDV_I:%.*]] = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i16(<4 x i16> [[A1]])291; CHECK-NEXT: [[TMP3:%.*]] = and i32 [[TMP2]], 0292; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[VADDV_I]], 0293; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP2]], 3276799294; CHECK-NEXT: [[TMP8:%.*]] = or i32 [[TMP3]], [[TMP4]]295; CHECK-NEXT: [[TMP6:%.*]] = or i32 [[TMP8]], [[TMP5]]296; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[VADDV_I]], 3276799297; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_tls, align 8298; CHECK-NEXT: ret i32 [[TMP7]]299;300entry:301 %vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i16(<4 x i16> %a1)302 %0 = and i32 %vaddv.i, 3276799 ; 0x31ffff303 ret i32 %0304}305 306define i32 @test_vaddv_u32(<2 x i32> %a1) #0 {307; CHECK-LABEL: define i32 @test_vaddv_u32(308; CHECK-SAME: <2 x i32> [[A1:%.*]]) #[[ATTR0]] {309; CHECK-NEXT: entry:310; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8311; CHECK-NEXT: call void @llvm.donothing()312; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> [[TMP0]])313; CHECK-NEXT: [[VADDV_I:%.*]] = tail call i32 @llvm.aarch64.neon.uaddv.i32.v2i32(<2 x i32> [[A1]])314; CHECK-NEXT: store i32 [[TMP1]], ptr @__msan_retval_tls, align 8315; CHECK-NEXT: ret i32 [[VADDV_I]]316;317; 2 x i32 is not supported by the ISA, thus, this is a special case318entry:319 %vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v2i32(<2 x i32> %a1)320 ret i32 %vaddv.i321}322 323define <2 x i32> @test_vaddv_u32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) #0 {324; CHECK-LABEL: define <2 x i32> @test_vaddv_u32_used_by_laneop(325; CHECK-SAME: <2 x i32> [[A1:%.*]], <2 x i32> [[A2:%.*]]) #[[ATTR0]] {326; CHECK-NEXT: entry:327; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8328; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8329; CHECK-NEXT: call void @llvm.donothing()330; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> [[TMP0]])331; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.uaddv.i32.v2i32(<2 x i32> [[A2]])332; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <2 x i32> [[TMP1]], i32 [[TMP2]], i32 1333; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> [[A1]], i32 [[TMP5]], i32 1334; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8335; CHECK-NEXT: ret <2 x i32> [[TMP6]]336;337entry:338 %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v2i32(<2 x i32> %a2)339 %1 = insertelement <2 x i32> %a1, i32 %0, i32 1340 ret <2 x i32> %1341}342 343define float @test_vaddv_f32(<2 x float> %a1) #0 {344; CHECK-LABEL: define float @test_vaddv_f32(345; CHECK-SAME: <2 x float> [[A1:%.*]]) #[[ATTR0]] {346; CHECK-NEXT: entry:347; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8348; CHECK-NEXT: call void @llvm.donothing()349; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.or.v2i32(<2 x i32> [[TMP0]])350; CHECK-NEXT: [[VADDV_I:%.*]] = tail call float @llvm.aarch64.neon.faddv.f32.v2f32(<2 x float> [[A1]])351; CHECK-NEXT: store i32 [[TMP1]], ptr @__msan_retval_tls, align 8352; CHECK-NEXT: ret float [[VADDV_I]]353;354entry:355 %vaddv.i = tail call float @llvm.aarch64.neon.faddv.f32.v2f32(<2 x float> %a1)356 ret float %vaddv.i357}358 359define float @test_vaddv_v4f32(<4 x float> %a1) #0 {360; CHECK-LABEL: define float @test_vaddv_v4f32(361; CHECK-SAME: <4 x float> [[A1:%.*]]) #[[ATTR0]] {362; CHECK-NEXT: entry:363; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8364; CHECK-NEXT: call void @llvm.donothing()365; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP0]])366; CHECK-NEXT: [[VADDV_I:%.*]] = tail call float @llvm.aarch64.neon.faddv.f32.v4f32(<4 x float> [[A1]])367; CHECK-NEXT: store i32 [[TMP1]], ptr @__msan_retval_tls, align 8368; CHECK-NEXT: ret float [[VADDV_I]]369;370entry:371 %vaddv.i = tail call float @llvm.aarch64.neon.faddv.f32.v4f32(<4 x float> %a1)372 ret float %vaddv.i373}374 375define double @test_vaddv_f64(<2 x double> %a1) #0 {376; CHECK-LABEL: define double @test_vaddv_f64(377; CHECK-SAME: <2 x double> [[A1:%.*]]) #[[ATTR0]] {378; CHECK-NEXT: entry:379; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8380; CHECK-NEXT: call void @llvm.donothing()381; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> [[TMP0]])382; CHECK-NEXT: [[VADDV_I:%.*]] = tail call double @llvm.aarch64.neon.faddv.f64.v2f64(<2 x double> [[A1]])383; CHECK-NEXT: store i64 [[TMP1]], ptr @__msan_retval_tls, align 8384; CHECK-NEXT: ret double [[VADDV_I]]385;386entry:387 %vaddv.i = tail call double @llvm.aarch64.neon.faddv.f64.v2f64(<2 x double> %a1)388 ret double %vaddv.i389}390 391define i64 @test_vaddv_u64(<2 x i64> %a1) #0 {392; CHECK-LABEL: define i64 @test_vaddv_u64(393; CHECK-SAME: <2 x i64> [[A1:%.*]]) #[[ATTR0]] {394; CHECK-NEXT: entry:395; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8396; CHECK-NEXT: call void @llvm.donothing()397; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> [[TMP0]])398; CHECK-NEXT: [[VADDV_I:%.*]] = tail call i64 @llvm.aarch64.neon.uaddv.i64.v2i64(<2 x i64> [[A1]])399; CHECK-NEXT: store i64 [[TMP1]], ptr @__msan_retval_tls, align 8400; CHECK-NEXT: ret i64 [[VADDV_I]]401;402entry:403 %vaddv.i = tail call i64 @llvm.aarch64.neon.uaddv.i64.v2i64(<2 x i64> %a1)404 ret i64 %vaddv.i405}406 407define <2 x i64> @test_vaddv_u64_used_by_laneop(<2 x i64> %a1, <2 x i64> %a2) #0 {408; CHECK-LABEL: define <2 x i64> @test_vaddv_u64_used_by_laneop(409; CHECK-SAME: <2 x i64> [[A1:%.*]], <2 x i64> [[A2:%.*]]) #[[ATTR0]] {410; CHECK-NEXT: entry:411; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8412; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8413; CHECK-NEXT: call void @llvm.donothing()414; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> [[TMP0]])415; CHECK-NEXT: [[TMP5:%.*]] = tail call i64 @llvm.aarch64.neon.uaddv.i64.v2i64(<2 x i64> [[A2]])416; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <2 x i64> [[TMP1]], i64 [[TMP2]], i64 1417; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i64> [[A1]], i64 [[TMP5]], i64 1418; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 8419; CHECK-NEXT: ret <2 x i64> [[TMP6]]420;421entry:422 %0 = tail call i64 @llvm.aarch64.neon.uaddv.i64.v2i64(<2 x i64> %a2)423 %1 = insertelement <2 x i64> %a1, i64 %0, i64 1424 ret <2 x i64> %1425}426 427define <1 x i64> @test_vaddv_u64_to_vec(<2 x i64> %a1, <1 x i64> %param1) #0 {428; CHECK-LABEL: define <1 x i64> @test_vaddv_u64_to_vec(429; CHECK-SAME: <2 x i64> [[A1:%.*]], <1 x i64> [[PARAM1:%.*]]) #[[ATTR0]] {430; CHECK-NEXT: entry:431; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8432; CHECK-NEXT: [[TMP2:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8433; CHECK-NEXT: call void @llvm.donothing()434; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.vector.reduce.or.v2i64(<2 x i64> [[TMP0]])435; CHECK-NEXT: [[VADDV_I:%.*]] = tail call i64 @llvm.aarch64.neon.uaddv.i64.v2i64(<2 x i64> [[A1]])436; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <1 x i64> [[TMP2]], i64 [[TMP3]], i32 0437; CHECK-NEXT: [[VEC:%.*]] = insertelement <1 x i64> [[PARAM1]], i64 [[VADDV_I]], i32 0438; CHECK-NEXT: store <1 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 8439; CHECK-NEXT: ret <1 x i64> [[VEC]]440;441entry:442 %vaddv.i = tail call i64 @llvm.aarch64.neon.uaddv.i64.v2i64(<2 x i64> %a1)443 %vec = insertelement <1 x i64> %param1, i64 %vaddv.i, i32 0444 ret <1 x i64> %vec445}446 447define signext i8 @test_vaddvq_s8(<16 x i8> %a1) #0 {448; CHECK-LABEL: define signext i8 @test_vaddvq_s8(449; CHECK-SAME: <16 x i8> [[A1:%.*]]) #[[ATTR0]] {450; CHECK-NEXT: entry:451; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @__msan_param_tls, align 8452; CHECK-NEXT: call void @llvm.donothing()453; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> [[TMP0]])454; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[TMP1]] to i32455; CHECK-NEXT: [[VADDV_I:%.*]] = tail call i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8> [[A1]])456; CHECK-NEXT: [[_MSPROP:%.*]] = trunc i32 [[TMP2]] to i8457; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[VADDV_I]] to i8458; CHECK-NEXT: store i8 [[_MSPROP]], ptr @__msan_retval_tls, align 8459; CHECK-NEXT: ret i8 [[TMP4]]460;461entry:462 %vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8> %a1)463 %0 = trunc i32 %vaddv.i to i8464 ret i8 %0465}466 467define <16 x i8> @test_vaddvq_s8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) #0 {468; CHECK-LABEL: define <16 x i8> @test_vaddvq_s8_used_by_laneop(469; CHECK-SAME: <16 x i8> [[A1:%.*]], <16 x i8> [[A2:%.*]]) #[[ATTR0]] {470; CHECK-NEXT: entry:471; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8472; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @__msan_param_tls, align 8473; CHECK-NEXT: call void @llvm.donothing()474; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> [[TMP0]])475; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i32476; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8> [[A2]])477; CHECK-NEXT: [[_MSPROP1:%.*]] = trunc i32 [[TMP3]] to i8478; CHECK-NEXT: [[TMP6:%.*]] = trunc i32 [[TMP5]] to i8479; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <16 x i8> [[TMP1]], i8 [[_MSPROP1]], i32 3480; CHECK-NEXT: [[TMP7:%.*]] = insertelement <16 x i8> [[A1]], i8 [[TMP6]], i32 3481; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8482; CHECK-NEXT: ret <16 x i8> [[TMP7]]483;484entry:485 %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8> %a2)486 %1 = trunc i32 %0 to i8487 %2 = insertelement <16 x i8> %a1, i8 %1, i32 3488 ret <16 x i8> %2489}490 491define signext i16 @test_vaddvq_s16(<8 x i16> %a1) #0 {492; CHECK-LABEL: define signext i16 @test_vaddvq_s16(493; CHECK-SAME: <8 x i16> [[A1:%.*]]) #[[ATTR0]] {494; CHECK-NEXT: entry:495; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8496; CHECK-NEXT: call void @llvm.donothing()497; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> [[TMP0]])498; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[TMP1]] to i32499; CHECK-NEXT: [[VADDV_I:%.*]] = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16> [[A1]])500; CHECK-NEXT: [[_MSPROP:%.*]] = trunc i32 [[TMP2]] to i16501; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[VADDV_I]] to i16502; CHECK-NEXT: store i16 [[_MSPROP]], ptr @__msan_retval_tls, align 8503; CHECK-NEXT: ret i16 [[TMP4]]504;505entry:506 %vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16> %a1)507 %0 = trunc i32 %vaddv.i to i16508 ret i16 %0509}510 511define <8 x i16> @test_vaddvq_s16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) #0 {512; CHECK-LABEL: define <8 x i16> @test_vaddvq_s16_used_by_laneop(513; CHECK-SAME: <8 x i16> [[A1:%.*]], <8 x i16> [[A2:%.*]]) #[[ATTR0]] {514; CHECK-NEXT: entry:515; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8516; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8517; CHECK-NEXT: call void @llvm.donothing()518; CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> [[TMP0]])519; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[TMP2]] to i32520; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16> [[A2]])521; CHECK-NEXT: [[_MSPROP1:%.*]] = trunc i32 [[TMP3]] to i16522; CHECK-NEXT: [[TMP6:%.*]] = trunc i32 [[TMP5]] to i16523; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <8 x i16> [[TMP1]], i16 [[_MSPROP1]], i32 3524; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i16> [[A1]], i16 [[TMP6]], i32 3525; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8526; CHECK-NEXT: ret <8 x i16> [[TMP7]]527;528entry:529 %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16> %a2)530 %1 = trunc i32 %0 to i16531 %2 = insertelement <8 x i16> %a1, i16 %1, i32 3532 ret <8 x i16> %2533}534 535define i32 @test_vaddvq_s32(<4 x i32> %a1) #0 {536; CHECK-LABEL: define i32 @test_vaddvq_s32(537; CHECK-SAME: <4 x i32> [[A1:%.*]]) #[[ATTR0]] {538; CHECK-NEXT: entry:539; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8540; CHECK-NEXT: call void @llvm.donothing()541; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP0]])542; CHECK-NEXT: [[VADDV_I:%.*]] = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32> [[A1]])543; CHECK-NEXT: store i32 [[TMP1]], ptr @__msan_retval_tls, align 8544; CHECK-NEXT: ret i32 [[VADDV_I]]545;546entry:547 %vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32> %a1)548 ret i32 %vaddv.i549}550 551define <4 x i32> @test_vaddvq_s32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) #0 {552; CHECK-LABEL: define <4 x i32> @test_vaddvq_s32_used_by_laneop(553; CHECK-SAME: <4 x i32> [[A1:%.*]], <4 x i32> [[A2:%.*]]) #[[ATTR0]] {554; CHECK-NEXT: entry:555; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8556; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8557; CHECK-NEXT: call void @llvm.donothing()558; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP0]])559; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32> [[A2]])560; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[TMP2]], i32 3561; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[A1]], i32 [[TMP5]], i32 3562; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8563; CHECK-NEXT: ret <4 x i32> [[TMP6]]564;565entry:566 %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32> %a2)567 %1 = insertelement <4 x i32> %a1, i32 %0, i32 3568 ret <4 x i32> %1569}570 571define zeroext i8 @test_vaddvq_u8(<16 x i8> %a1) #0 {572; CHECK-LABEL: define zeroext i8 @test_vaddvq_u8(573; CHECK-SAME: <16 x i8> [[A1:%.*]]) #[[ATTR0]] {574; CHECK-NEXT: entry:575; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr @__msan_param_tls, align 8576; CHECK-NEXT: call void @llvm.donothing()577; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> [[TMP0]])578; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[TMP1]] to i32579; CHECK-NEXT: [[VADDV_I:%.*]] = tail call i32 @llvm.aarch64.neon.uaddv.i32.v16i8(<16 x i8> [[A1]])580; CHECK-NEXT: [[_MSPROP:%.*]] = trunc i32 [[TMP2]] to i8581; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[VADDV_I]] to i8582; CHECK-NEXT: store i8 [[_MSPROP]], ptr @__msan_retval_tls, align 8583; CHECK-NEXT: ret i8 [[TMP4]]584;585entry:586 %vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v16i8(<16 x i8> %a1)587 %0 = trunc i32 %vaddv.i to i8588 ret i8 %0589}590 591define <16 x i8> @test_vaddvq_u8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) #0 {592; CHECK-LABEL: define <16 x i8> @test_vaddvq_u8_used_by_laneop(593; CHECK-SAME: <16 x i8> [[A1:%.*]], <16 x i8> [[A2:%.*]]) #[[ATTR0]] {594; CHECK-NEXT: entry:595; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8596; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @__msan_param_tls, align 8597; CHECK-NEXT: call void @llvm.donothing()598; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.vector.reduce.or.v16i8(<16 x i8> [[TMP0]])599; CHECK-NEXT: [[TMP3:%.*]] = zext i8 [[TMP2]] to i32600; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.uaddv.i32.v16i8(<16 x i8> [[A2]])601; CHECK-NEXT: [[_MSPROP1:%.*]] = trunc i32 [[TMP3]] to i8602; CHECK-NEXT: [[TMP6:%.*]] = trunc i32 [[TMP5]] to i8603; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <16 x i8> [[TMP1]], i8 [[_MSPROP1]], i32 3604; CHECK-NEXT: [[TMP7:%.*]] = insertelement <16 x i8> [[A1]], i8 [[TMP6]], i32 3605; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8606; CHECK-NEXT: ret <16 x i8> [[TMP7]]607;608entry:609 %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v16i8(<16 x i8> %a2)610 %1 = trunc i32 %0 to i8611 %2 = insertelement <16 x i8> %a1, i8 %1, i32 3612 ret <16 x i8> %2613}614 615define zeroext i16 @test_vaddvq_u16(<8 x i16> %a1) #0 {616; CHECK-LABEL: define zeroext i16 @test_vaddvq_u16(617; CHECK-SAME: <8 x i16> [[A1:%.*]]) #[[ATTR0]] {618; CHECK-NEXT: entry:619; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8620; CHECK-NEXT: call void @llvm.donothing()621; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> [[TMP0]])622; CHECK-NEXT: [[TMP2:%.*]] = zext i16 [[TMP1]] to i32623; CHECK-NEXT: [[VADDV_I:%.*]] = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i16(<8 x i16> [[A1]])624; CHECK-NEXT: [[_MSPROP:%.*]] = trunc i32 [[TMP2]] to i16625; CHECK-NEXT: [[TMP4:%.*]] = trunc i32 [[VADDV_I]] to i16626; CHECK-NEXT: store i16 [[_MSPROP]], ptr @__msan_retval_tls, align 8627; CHECK-NEXT: ret i16 [[TMP4]]628;629entry:630 %vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i16(<8 x i16> %a1)631 %0 = trunc i32 %vaddv.i to i16632 ret i16 %0633}634 635define <8 x i16> @test_vaddvq_u16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) #0 {636; CHECK-LABEL: define <8 x i16> @test_vaddvq_u16_used_by_laneop(637; CHECK-SAME: <8 x i16> [[A1:%.*]], <8 x i16> [[A2:%.*]]) #[[ATTR0]] {638; CHECK-NEXT: entry:639; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8640; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8641; CHECK-NEXT: call void @llvm.donothing()642; CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.vector.reduce.or.v8i16(<8 x i16> [[TMP0]])643; CHECK-NEXT: [[TMP3:%.*]] = zext i16 [[TMP2]] to i32644; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i16(<8 x i16> [[A2]])645; CHECK-NEXT: [[_MSPROP1:%.*]] = trunc i32 [[TMP3]] to i16646; CHECK-NEXT: [[TMP6:%.*]] = trunc i32 [[TMP5]] to i16647; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <8 x i16> [[TMP1]], i16 [[_MSPROP1]], i32 3648; CHECK-NEXT: [[TMP7:%.*]] = insertelement <8 x i16> [[A1]], i16 [[TMP6]], i32 3649; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8650; CHECK-NEXT: ret <8 x i16> [[TMP7]]651;652entry:653 %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i16(<8 x i16> %a2)654 %1 = trunc i32 %0 to i16655 %2 = insertelement <8 x i16> %a1, i16 %1, i32 3656 ret <8 x i16> %2657}658 659define i32 @test_vaddvq_u32(<4 x i32> %a1) #0 {660; CHECK-LABEL: define i32 @test_vaddvq_u32(661; CHECK-SAME: <4 x i32> [[A1:%.*]]) #[[ATTR0]] {662; CHECK-NEXT: entry:663; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8664; CHECK-NEXT: call void @llvm.donothing()665; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP0]])666; CHECK-NEXT: [[VADDV_I:%.*]] = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i32(<4 x i32> [[A1]])667; CHECK-NEXT: store i32 [[TMP1]], ptr @__msan_retval_tls, align 8668; CHECK-NEXT: ret i32 [[VADDV_I]]669;670entry:671 %vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i32(<4 x i32> %a1)672 ret i32 %vaddv.i673}674 675define <4 x i32> @test_vaddvq_u32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) #0 {676; CHECK-LABEL: define <4 x i32> @test_vaddvq_u32_used_by_laneop(677; CHECK-SAME: <4 x i32> [[A1:%.*]], <4 x i32> [[A2:%.*]]) #[[ATTR0]] {678; CHECK-NEXT: entry:679; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 8680; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8681; CHECK-NEXT: call void @llvm.donothing()682; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.vector.reduce.or.v4i32(<4 x i32> [[TMP0]])683; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i32(<4 x i32> [[A2]])684; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <4 x i32> [[TMP1]], i32 [[TMP2]], i32 3685; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i32> [[A1]], i32 [[TMP5]], i32 3686; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8687; CHECK-NEXT: ret <4 x i32> [[TMP6]]688;689entry:690 %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i32(<4 x i32> %a2)691 %1 = insertelement <4 x i32> %a1, i32 %0, i32 3692 ret <4 x i32> %1693}694 695declare i32 @llvm.aarch64.neon.uaddv.i32.v4i32(<4 x i32>)696 697declare i32 @llvm.aarch64.neon.uaddv.i32.v8i16(<8 x i16>)698 699declare i32 @llvm.aarch64.neon.uaddv.i32.v16i8(<16 x i8>)700 701declare i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32>)702 703declare i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16>)704 705declare i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8>)706 707declare i64 @llvm.aarch64.neon.uaddv.i64.v2i64(<2 x i64>)708 709declare i32 @llvm.aarch64.neon.uaddv.i32.v2i32(<2 x i32>)710 711declare i32 @llvm.aarch64.neon.uaddv.i32.v4i16(<4 x i16>)712 713declare i32 @llvm.aarch64.neon.uaddv.i32.v8i8(<8 x i8>)714 715declare i32 @llvm.aarch64.neon.saddv.i32.v2i32(<2 x i32>)716 717declare i64 @llvm.aarch64.neon.saddv.i64.v2i64(<2 x i64>)718 719declare i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16>)720 721declare i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8>)722 723declare float @llvm.aarch64.neon.faddv.f32.v2f32(<2 x float> %a1)724declare float @llvm.aarch64.neon.faddv.f32.v4f32(<4 x float> %a1)725declare double @llvm.aarch64.neon.faddv.f64.v2f64(<2 x double> %a1)726 727attributes #0 = { sanitize_memory }728