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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: opt < %s -passes=msan -S | FileCheck %s3;4; Suboptimally handled by visitInstruction: llvm.aarch64.neon.5; - vcvtfp2fxs, vcvtfp2fxu6; - vcvtfxs2fp, vcvtfxu2fp7;8; Forked from llvm/test/CodeGen/AArch64/arm64-vcvt.ll9 10target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"11target triple = "aarch64--linux-android9001"12 13define <2 x i32> @fcvtas_2s(<2 x float> %A) nounwind #0 {14; CHECK-LABEL: define <2 x i32> @fcvtas_2s(15; CHECK-SAME: <2 x float> [[A:%.*]]) #[[ATTR0:[0-9]+]] {16; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 817; CHECK-NEXT: call void @llvm.donothing()18; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer19; CHECK-NEXT: [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i32>20; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i32> @llvm.aarch64.neon.fcvtas.v2i32.v2f32(<2 x float> [[A]])21; CHECK-NEXT: store <2 x i32> [[TMP3]], ptr @__msan_retval_tls, align 822; CHECK-NEXT: ret <2 x i32> [[TMPVAR3]]23;24 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.fcvtas.v2i32.v2f32(<2 x float> %A)25 ret <2 x i32> %tmpvar326}27 28define <4 x i32> @fcvtas_4s(<4 x float> %A) nounwind #0 {29; CHECK-LABEL: define <4 x i32> @fcvtas_4s(30; CHECK-SAME: <4 x float> [[A:%.*]]) #[[ATTR0]] {31; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 832; CHECK-NEXT: call void @llvm.donothing()33; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <4 x i32> [[TMP1]], zeroinitializer34; CHECK-NEXT: [[TMP3:%.*]] = sext <4 x i1> [[TMP2]] to <4 x i32>35; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i32> @llvm.aarch64.neon.fcvtas.v4i32.v4f32(<4 x float> [[A]])36; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr @__msan_retval_tls, align 837; CHECK-NEXT: ret <4 x i32> [[TMPVAR3]]38;39 %tmpvar3 = call <4 x i32> @llvm.aarch64.neon.fcvtas.v4i32.v4f32(<4 x float> %A)40 ret <4 x i32> %tmpvar341}42 43define <2 x i64> @fcvtas_2d(<2 x double> %A) nounwind #0 {44; CHECK-LABEL: define <2 x i64> @fcvtas_2d(45; CHECK-SAME: <2 x double> [[A:%.*]]) #[[ATTR0]] {46; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 847; CHECK-NEXT: call void @llvm.donothing()48; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer49; CHECK-NEXT: [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i64>50; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i64> @llvm.aarch64.neon.fcvtas.v2i64.v2f64(<2 x double> [[A]])51; CHECK-NEXT: store <2 x i64> [[TMP3]], ptr @__msan_retval_tls, align 852; CHECK-NEXT: ret <2 x i64> [[TMPVAR3]]53;54 %tmpvar3 = call <2 x i64> @llvm.aarch64.neon.fcvtas.v2i64.v2f64(<2 x double> %A)55 ret <2 x i64> %tmpvar356}57 58define <1 x i64> @fcvtas_1d(<1 x double> %A) nounwind #0 {59; CHECK-LABEL: define <1 x i64> @fcvtas_1d(60; CHECK-SAME: <1 x double> [[A:%.*]]) #[[ATTR0]] {61; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 862; CHECK-NEXT: call void @llvm.donothing()63; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <1 x i64> [[TMP1]], zeroinitializer64; CHECK-NEXT: [[TMP3:%.*]] = sext <1 x i1> [[TMP2]] to <1 x i64>65; CHECK-NEXT: [[TMPVAR3:%.*]] = call <1 x i64> @llvm.aarch64.neon.fcvtas.v1i64.v1f64(<1 x double> [[A]])66; CHECK-NEXT: store <1 x i64> [[TMP3]], ptr @__msan_retval_tls, align 867; CHECK-NEXT: ret <1 x i64> [[TMPVAR3]]68;69 %tmpvar3 = call <1 x i64> @llvm.aarch64.neon.fcvtas.v1i64.v1f64(<1 x double> %A)70 ret <1 x i64> %tmpvar371}72 73declare <2 x i32> @llvm.aarch64.neon.fcvtas.v2i32.v2f32(<2 x float>) nounwind readnone74declare <4 x i32> @llvm.aarch64.neon.fcvtas.v4i32.v4f32(<4 x float>) nounwind readnone75declare <2 x i64> @llvm.aarch64.neon.fcvtas.v2i64.v2f64(<2 x double>) nounwind readnone76declare <1 x i64> @llvm.aarch64.neon.fcvtas.v1i64.v1f64(<1 x double>) nounwind readnone77 78define <2 x i32> @fcvtau_2s(<2 x float> %A) nounwind #0 {79; CHECK-LABEL: define <2 x i32> @fcvtau_2s(80; CHECK-SAME: <2 x float> [[A:%.*]]) #[[ATTR0]] {81; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 882; CHECK-NEXT: call void @llvm.donothing()83; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer84; CHECK-NEXT: [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i32>85; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i32> @llvm.aarch64.neon.fcvtau.v2i32.v2f32(<2 x float> [[A]])86; CHECK-NEXT: store <2 x i32> [[TMP3]], ptr @__msan_retval_tls, align 887; CHECK-NEXT: ret <2 x i32> [[TMPVAR3]]88;89 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.fcvtau.v2i32.v2f32(<2 x float> %A)90 ret <2 x i32> %tmpvar391}92 93define <4 x i32> @fcvtau_4s(<4 x float> %A) nounwind #0 {94; CHECK-LABEL: define <4 x i32> @fcvtau_4s(95; CHECK-SAME: <4 x float> [[A:%.*]]) #[[ATTR0]] {96; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 897; CHECK-NEXT: call void @llvm.donothing()98; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <4 x i32> [[TMP1]], zeroinitializer99; CHECK-NEXT: [[TMP3:%.*]] = sext <4 x i1> [[TMP2]] to <4 x i32>100; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i32> @llvm.aarch64.neon.fcvtau.v4i32.v4f32(<4 x float> [[A]])101; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr @__msan_retval_tls, align 8102; CHECK-NEXT: ret <4 x i32> [[TMPVAR3]]103;104 %tmpvar3 = call <4 x i32> @llvm.aarch64.neon.fcvtau.v4i32.v4f32(<4 x float> %A)105 ret <4 x i32> %tmpvar3106}107 108define <2 x i64> @fcvtau_2d(<2 x double> %A) nounwind #0 {109; CHECK-LABEL: define <2 x i64> @fcvtau_2d(110; CHECK-SAME: <2 x double> [[A:%.*]]) #[[ATTR0]] {111; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8112; CHECK-NEXT: call void @llvm.donothing()113; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer114; CHECK-NEXT: [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i64>115; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i64> @llvm.aarch64.neon.fcvtau.v2i64.v2f64(<2 x double> [[A]])116; CHECK-NEXT: store <2 x i64> [[TMP3]], ptr @__msan_retval_tls, align 8117; CHECK-NEXT: ret <2 x i64> [[TMPVAR3]]118;119 %tmpvar3 = call <2 x i64> @llvm.aarch64.neon.fcvtau.v2i64.v2f64(<2 x double> %A)120 ret <2 x i64> %tmpvar3121}122 123define <1 x i64> @fcvtau_1d(<1 x double> %A) nounwind #0 {124; CHECK-LABEL: define <1 x i64> @fcvtau_1d(125; CHECK-SAME: <1 x double> [[A:%.*]]) #[[ATTR0]] {126; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8127; CHECK-NEXT: call void @llvm.donothing()128; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <1 x i64> [[TMP1]], zeroinitializer129; CHECK-NEXT: [[TMP3:%.*]] = sext <1 x i1> [[TMP2]] to <1 x i64>130; CHECK-NEXT: [[TMPVAR3:%.*]] = call <1 x i64> @llvm.aarch64.neon.fcvtau.v1i64.v1f64(<1 x double> [[A]])131; CHECK-NEXT: store <1 x i64> [[TMP3]], ptr @__msan_retval_tls, align 8132; CHECK-NEXT: ret <1 x i64> [[TMPVAR3]]133;134 %tmpvar3 = call <1 x i64> @llvm.aarch64.neon.fcvtau.v1i64.v1f64(<1 x double> %A)135 ret <1 x i64> %tmpvar3136}137 138declare <2 x i32> @llvm.aarch64.neon.fcvtau.v2i32.v2f32(<2 x float>) nounwind readnone139declare <4 x i32> @llvm.aarch64.neon.fcvtau.v4i32.v4f32(<4 x float>) nounwind readnone140declare <2 x i64> @llvm.aarch64.neon.fcvtau.v2i64.v2f64(<2 x double>) nounwind readnone141declare <1 x i64> @llvm.aarch64.neon.fcvtau.v1i64.v1f64(<1 x double>) nounwind readnone142 143define <2 x i32> @fcvtms_2s(<2 x float> %A) nounwind #0 {144; CHECK-LABEL: define <2 x i32> @fcvtms_2s(145; CHECK-SAME: <2 x float> [[A:%.*]]) #[[ATTR0]] {146; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8147; CHECK-NEXT: call void @llvm.donothing()148; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer149; CHECK-NEXT: [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i32>150; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i32> @llvm.aarch64.neon.fcvtms.v2i32.v2f32(<2 x float> [[A]])151; CHECK-NEXT: store <2 x i32> [[TMP3]], ptr @__msan_retval_tls, align 8152; CHECK-NEXT: ret <2 x i32> [[TMPVAR3]]153;154 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.fcvtms.v2i32.v2f32(<2 x float> %A)155 ret <2 x i32> %tmpvar3156}157 158define <4 x i32> @fcvtms_4s(<4 x float> %A) nounwind #0 {159; CHECK-LABEL: define <4 x i32> @fcvtms_4s(160; CHECK-SAME: <4 x float> [[A:%.*]]) #[[ATTR0]] {161; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8162; CHECK-NEXT: call void @llvm.donothing()163; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <4 x i32> [[TMP1]], zeroinitializer164; CHECK-NEXT: [[TMP3:%.*]] = sext <4 x i1> [[TMP2]] to <4 x i32>165; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i32> @llvm.aarch64.neon.fcvtms.v4i32.v4f32(<4 x float> [[A]])166; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr @__msan_retval_tls, align 8167; CHECK-NEXT: ret <4 x i32> [[TMPVAR3]]168;169 %tmpvar3 = call <4 x i32> @llvm.aarch64.neon.fcvtms.v4i32.v4f32(<4 x float> %A)170 ret <4 x i32> %tmpvar3171}172 173define <2 x i64> @fcvtms_2d(<2 x double> %A) nounwind #0 {174; CHECK-LABEL: define <2 x i64> @fcvtms_2d(175; CHECK-SAME: <2 x double> [[A:%.*]]) #[[ATTR0]] {176; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8177; CHECK-NEXT: call void @llvm.donothing()178; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer179; CHECK-NEXT: [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i64>180; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i64> @llvm.aarch64.neon.fcvtms.v2i64.v2f64(<2 x double> [[A]])181; CHECK-NEXT: store <2 x i64> [[TMP3]], ptr @__msan_retval_tls, align 8182; CHECK-NEXT: ret <2 x i64> [[TMPVAR3]]183;184 %tmpvar3 = call <2 x i64> @llvm.aarch64.neon.fcvtms.v2i64.v2f64(<2 x double> %A)185 ret <2 x i64> %tmpvar3186}187 188define <1 x i64> @fcvtms_1d(<1 x double> %A) nounwind #0 {189; CHECK-LABEL: define <1 x i64> @fcvtms_1d(190; CHECK-SAME: <1 x double> [[A:%.*]]) #[[ATTR0]] {191; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8192; CHECK-NEXT: call void @llvm.donothing()193; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <1 x i64> [[TMP1]], zeroinitializer194; CHECK-NEXT: [[TMP3:%.*]] = sext <1 x i1> [[TMP2]] to <1 x i64>195; CHECK-NEXT: [[TMPVAR3:%.*]] = call <1 x i64> @llvm.aarch64.neon.fcvtms.v1i64.v1f64(<1 x double> [[A]])196; CHECK-NEXT: store <1 x i64> [[TMP3]], ptr @__msan_retval_tls, align 8197; CHECK-NEXT: ret <1 x i64> [[TMPVAR3]]198;199 %tmpvar3 = call <1 x i64> @llvm.aarch64.neon.fcvtms.v1i64.v1f64(<1 x double> %A)200 ret <1 x i64> %tmpvar3201}202 203declare <2 x i32> @llvm.aarch64.neon.fcvtms.v2i32.v2f32(<2 x float>) nounwind readnone204declare <4 x i32> @llvm.aarch64.neon.fcvtms.v4i32.v4f32(<4 x float>) nounwind readnone205declare <2 x i64> @llvm.aarch64.neon.fcvtms.v2i64.v2f64(<2 x double>) nounwind readnone206declare <1 x i64> @llvm.aarch64.neon.fcvtms.v1i64.v1f64(<1 x double>) nounwind readnone207 208define <2 x i32> @fcvtmu_2s(<2 x float> %A) nounwind #0 {209; CHECK-LABEL: define <2 x i32> @fcvtmu_2s(210; CHECK-SAME: <2 x float> [[A:%.*]]) #[[ATTR0]] {211; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8212; CHECK-NEXT: call void @llvm.donothing()213; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer214; CHECK-NEXT: [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i32>215; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i32> @llvm.aarch64.neon.fcvtmu.v2i32.v2f32(<2 x float> [[A]])216; CHECK-NEXT: store <2 x i32> [[TMP3]], ptr @__msan_retval_tls, align 8217; CHECK-NEXT: ret <2 x i32> [[TMPVAR3]]218;219 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.fcvtmu.v2i32.v2f32(<2 x float> %A)220 ret <2 x i32> %tmpvar3221}222 223define <4 x i32> @fcvtmu_4s(<4 x float> %A) nounwind #0 {224; CHECK-LABEL: define <4 x i32> @fcvtmu_4s(225; CHECK-SAME: <4 x float> [[A:%.*]]) #[[ATTR0]] {226; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8227; CHECK-NEXT: call void @llvm.donothing()228; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <4 x i32> [[TMP1]], zeroinitializer229; CHECK-NEXT: [[TMP3:%.*]] = sext <4 x i1> [[TMP2]] to <4 x i32>230; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i32> @llvm.aarch64.neon.fcvtmu.v4i32.v4f32(<4 x float> [[A]])231; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr @__msan_retval_tls, align 8232; CHECK-NEXT: ret <4 x i32> [[TMPVAR3]]233;234 %tmpvar3 = call <4 x i32> @llvm.aarch64.neon.fcvtmu.v4i32.v4f32(<4 x float> %A)235 ret <4 x i32> %tmpvar3236}237 238define <2 x i64> @fcvtmu_2d(<2 x double> %A) nounwind #0 {239; CHECK-LABEL: define <2 x i64> @fcvtmu_2d(240; CHECK-SAME: <2 x double> [[A:%.*]]) #[[ATTR0]] {241; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8242; CHECK-NEXT: call void @llvm.donothing()243; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer244; CHECK-NEXT: [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i64>245; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i64> @llvm.aarch64.neon.fcvtmu.v2i64.v2f64(<2 x double> [[A]])246; CHECK-NEXT: store <2 x i64> [[TMP3]], ptr @__msan_retval_tls, align 8247; CHECK-NEXT: ret <2 x i64> [[TMPVAR3]]248;249 %tmpvar3 = call <2 x i64> @llvm.aarch64.neon.fcvtmu.v2i64.v2f64(<2 x double> %A)250 ret <2 x i64> %tmpvar3251}252 253define <1 x i64> @fcvtmu_1d(<1 x double> %A) nounwind #0 {254; CHECK-LABEL: define <1 x i64> @fcvtmu_1d(255; CHECK-SAME: <1 x double> [[A:%.*]]) #[[ATTR0]] {256; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8257; CHECK-NEXT: call void @llvm.donothing()258; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <1 x i64> [[TMP1]], zeroinitializer259; CHECK-NEXT: [[TMP3:%.*]] = sext <1 x i1> [[TMP2]] to <1 x i64>260; CHECK-NEXT: [[TMPVAR3:%.*]] = call <1 x i64> @llvm.aarch64.neon.fcvtmu.v1i64.v1f64(<1 x double> [[A]])261; CHECK-NEXT: store <1 x i64> [[TMP3]], ptr @__msan_retval_tls, align 8262; CHECK-NEXT: ret <1 x i64> [[TMPVAR3]]263;264 %tmpvar3 = call <1 x i64> @llvm.aarch64.neon.fcvtmu.v1i64.v1f64(<1 x double> %A)265 ret <1 x i64> %tmpvar3266}267 268declare <2 x i32> @llvm.aarch64.neon.fcvtmu.v2i32.v2f32(<2 x float>) nounwind readnone269declare <4 x i32> @llvm.aarch64.neon.fcvtmu.v4i32.v4f32(<4 x float>) nounwind readnone270declare <2 x i64> @llvm.aarch64.neon.fcvtmu.v2i64.v2f64(<2 x double>) nounwind readnone271declare <1 x i64> @llvm.aarch64.neon.fcvtmu.v1i64.v1f64(<1 x double>) nounwind readnone272 273define <2 x i32> @fcvtps_2s(<2 x float> %A) nounwind #0 {274; CHECK-LABEL: define <2 x i32> @fcvtps_2s(275; CHECK-SAME: <2 x float> [[A:%.*]]) #[[ATTR0]] {276; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8277; CHECK-NEXT: call void @llvm.donothing()278; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer279; CHECK-NEXT: [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i32>280; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i32> @llvm.aarch64.neon.fcvtps.v2i32.v2f32(<2 x float> [[A]])281; CHECK-NEXT: store <2 x i32> [[TMP3]], ptr @__msan_retval_tls, align 8282; CHECK-NEXT: ret <2 x i32> [[TMPVAR3]]283;284 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.fcvtps.v2i32.v2f32(<2 x float> %A)285 ret <2 x i32> %tmpvar3286}287 288define <4 x i32> @fcvtps_4s(<4 x float> %A) nounwind #0 {289; CHECK-LABEL: define <4 x i32> @fcvtps_4s(290; CHECK-SAME: <4 x float> [[A:%.*]]) #[[ATTR0]] {291; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8292; CHECK-NEXT: call void @llvm.donothing()293; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <4 x i32> [[TMP1]], zeroinitializer294; CHECK-NEXT: [[TMP3:%.*]] = sext <4 x i1> [[TMP2]] to <4 x i32>295; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i32> @llvm.aarch64.neon.fcvtps.v4i32.v4f32(<4 x float> [[A]])296; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr @__msan_retval_tls, align 8297; CHECK-NEXT: ret <4 x i32> [[TMPVAR3]]298;299 %tmpvar3 = call <4 x i32> @llvm.aarch64.neon.fcvtps.v4i32.v4f32(<4 x float> %A)300 ret <4 x i32> %tmpvar3301}302 303define <2 x i64> @fcvtps_2d(<2 x double> %A) nounwind #0 {304; CHECK-LABEL: define <2 x i64> @fcvtps_2d(305; CHECK-SAME: <2 x double> [[A:%.*]]) #[[ATTR0]] {306; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8307; CHECK-NEXT: call void @llvm.donothing()308; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer309; CHECK-NEXT: [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i64>310; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i64> @llvm.aarch64.neon.fcvtps.v2i64.v2f64(<2 x double> [[A]])311; CHECK-NEXT: store <2 x i64> [[TMP3]], ptr @__msan_retval_tls, align 8312; CHECK-NEXT: ret <2 x i64> [[TMPVAR3]]313;314 %tmpvar3 = call <2 x i64> @llvm.aarch64.neon.fcvtps.v2i64.v2f64(<2 x double> %A)315 ret <2 x i64> %tmpvar3316}317 318define <1 x i64> @fcvtps_1d(<1 x double> %A) nounwind #0 {319; CHECK-LABEL: define <1 x i64> @fcvtps_1d(320; CHECK-SAME: <1 x double> [[A:%.*]]) #[[ATTR0]] {321; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8322; CHECK-NEXT: call void @llvm.donothing()323; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <1 x i64> [[TMP1]], zeroinitializer324; CHECK-NEXT: [[TMP3:%.*]] = sext <1 x i1> [[TMP2]] to <1 x i64>325; CHECK-NEXT: [[TMPVAR3:%.*]] = call <1 x i64> @llvm.aarch64.neon.fcvtps.v1i64.v1f64(<1 x double> [[A]])326; CHECK-NEXT: store <1 x i64> [[TMP3]], ptr @__msan_retval_tls, align 8327; CHECK-NEXT: ret <1 x i64> [[TMPVAR3]]328;329 %tmpvar3 = call <1 x i64> @llvm.aarch64.neon.fcvtps.v1i64.v1f64(<1 x double> %A)330 ret <1 x i64> %tmpvar3331}332 333declare <2 x i32> @llvm.aarch64.neon.fcvtps.v2i32.v2f32(<2 x float>) nounwind readnone334declare <4 x i32> @llvm.aarch64.neon.fcvtps.v4i32.v4f32(<4 x float>) nounwind readnone335declare <2 x i64> @llvm.aarch64.neon.fcvtps.v2i64.v2f64(<2 x double>) nounwind readnone336declare <1 x i64> @llvm.aarch64.neon.fcvtps.v1i64.v1f64(<1 x double>) nounwind readnone337 338define <2 x i32> @fcvtpu_2s(<2 x float> %A) nounwind #0 {339; CHECK-LABEL: define <2 x i32> @fcvtpu_2s(340; CHECK-SAME: <2 x float> [[A:%.*]]) #[[ATTR0]] {341; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8342; CHECK-NEXT: call void @llvm.donothing()343; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer344; CHECK-NEXT: [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i32>345; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i32> @llvm.aarch64.neon.fcvtpu.v2i32.v2f32(<2 x float> [[A]])346; CHECK-NEXT: store <2 x i32> [[TMP3]], ptr @__msan_retval_tls, align 8347; CHECK-NEXT: ret <2 x i32> [[TMPVAR3]]348;349 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.fcvtpu.v2i32.v2f32(<2 x float> %A)350 ret <2 x i32> %tmpvar3351}352 353define <4 x i32> @fcvtpu_4s(<4 x float> %A) nounwind #0 {354; CHECK-LABEL: define <4 x i32> @fcvtpu_4s(355; CHECK-SAME: <4 x float> [[A:%.*]]) #[[ATTR0]] {356; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8357; CHECK-NEXT: call void @llvm.donothing()358; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <4 x i32> [[TMP1]], zeroinitializer359; CHECK-NEXT: [[TMP3:%.*]] = sext <4 x i1> [[TMP2]] to <4 x i32>360; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i32> @llvm.aarch64.neon.fcvtpu.v4i32.v4f32(<4 x float> [[A]])361; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr @__msan_retval_tls, align 8362; CHECK-NEXT: ret <4 x i32> [[TMPVAR3]]363;364 %tmpvar3 = call <4 x i32> @llvm.aarch64.neon.fcvtpu.v4i32.v4f32(<4 x float> %A)365 ret <4 x i32> %tmpvar3366}367 368define <2 x i64> @fcvtpu_2d(<2 x double> %A) nounwind #0 {369; CHECK-LABEL: define <2 x i64> @fcvtpu_2d(370; CHECK-SAME: <2 x double> [[A:%.*]]) #[[ATTR0]] {371; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8372; CHECK-NEXT: call void @llvm.donothing()373; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer374; CHECK-NEXT: [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i64>375; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i64> @llvm.aarch64.neon.fcvtpu.v2i64.v2f64(<2 x double> [[A]])376; CHECK-NEXT: store <2 x i64> [[TMP3]], ptr @__msan_retval_tls, align 8377; CHECK-NEXT: ret <2 x i64> [[TMPVAR3]]378;379 %tmpvar3 = call <2 x i64> @llvm.aarch64.neon.fcvtpu.v2i64.v2f64(<2 x double> %A)380 ret <2 x i64> %tmpvar3381}382 383define <1 x i64> @fcvtpu_1d(<1 x double> %A) nounwind #0 {384; CHECK-LABEL: define <1 x i64> @fcvtpu_1d(385; CHECK-SAME: <1 x double> [[A:%.*]]) #[[ATTR0]] {386; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8387; CHECK-NEXT: call void @llvm.donothing()388; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <1 x i64> [[TMP1]], zeroinitializer389; CHECK-NEXT: [[TMP3:%.*]] = sext <1 x i1> [[TMP2]] to <1 x i64>390; CHECK-NEXT: [[TMPVAR3:%.*]] = call <1 x i64> @llvm.aarch64.neon.fcvtpu.v1i64.v1f64(<1 x double> [[A]])391; CHECK-NEXT: store <1 x i64> [[TMP3]], ptr @__msan_retval_tls, align 8392; CHECK-NEXT: ret <1 x i64> [[TMPVAR3]]393;394 %tmpvar3 = call <1 x i64> @llvm.aarch64.neon.fcvtpu.v1i64.v1f64(<1 x double> %A)395 ret <1 x i64> %tmpvar3396}397 398declare <2 x i32> @llvm.aarch64.neon.fcvtpu.v2i32.v2f32(<2 x float>) nounwind readnone399declare <4 x i32> @llvm.aarch64.neon.fcvtpu.v4i32.v4f32(<4 x float>) nounwind readnone400declare <2 x i64> @llvm.aarch64.neon.fcvtpu.v2i64.v2f64(<2 x double>) nounwind readnone401declare <1 x i64> @llvm.aarch64.neon.fcvtpu.v1i64.v1f64(<1 x double>) nounwind readnone402 403define <2 x i32> @fcvtns_2s(<2 x float> %A) nounwind #0 {404; CHECK-LABEL: define <2 x i32> @fcvtns_2s(405; CHECK-SAME: <2 x float> [[A:%.*]]) #[[ATTR0]] {406; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8407; CHECK-NEXT: call void @llvm.donothing()408; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer409; CHECK-NEXT: [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i32>410; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i32> @llvm.aarch64.neon.fcvtns.v2i32.v2f32(<2 x float> [[A]])411; CHECK-NEXT: store <2 x i32> [[TMP3]], ptr @__msan_retval_tls, align 8412; CHECK-NEXT: ret <2 x i32> [[TMPVAR3]]413;414 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.fcvtns.v2i32.v2f32(<2 x float> %A)415 ret <2 x i32> %tmpvar3416}417 418define <4 x i32> @fcvtns_4s(<4 x float> %A) nounwind #0 {419; CHECK-LABEL: define <4 x i32> @fcvtns_4s(420; CHECK-SAME: <4 x float> [[A:%.*]]) #[[ATTR0]] {421; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8422; CHECK-NEXT: call void @llvm.donothing()423; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <4 x i32> [[TMP1]], zeroinitializer424; CHECK-NEXT: [[TMP3:%.*]] = sext <4 x i1> [[TMP2]] to <4 x i32>425; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i32> @llvm.aarch64.neon.fcvtns.v4i32.v4f32(<4 x float> [[A]])426; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr @__msan_retval_tls, align 8427; CHECK-NEXT: ret <4 x i32> [[TMPVAR3]]428;429 %tmpvar3 = call <4 x i32> @llvm.aarch64.neon.fcvtns.v4i32.v4f32(<4 x float> %A)430 ret <4 x i32> %tmpvar3431}432 433define <2 x i64> @fcvtns_2d(<2 x double> %A) nounwind #0 {434; CHECK-LABEL: define <2 x i64> @fcvtns_2d(435; CHECK-SAME: <2 x double> [[A:%.*]]) #[[ATTR0]] {436; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8437; CHECK-NEXT: call void @llvm.donothing()438; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer439; CHECK-NEXT: [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i64>440; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i64> @llvm.aarch64.neon.fcvtns.v2i64.v2f64(<2 x double> [[A]])441; CHECK-NEXT: store <2 x i64> [[TMP3]], ptr @__msan_retval_tls, align 8442; CHECK-NEXT: ret <2 x i64> [[TMPVAR3]]443;444 %tmpvar3 = call <2 x i64> @llvm.aarch64.neon.fcvtns.v2i64.v2f64(<2 x double> %A)445 ret <2 x i64> %tmpvar3446}447 448define <1 x i64> @fcvtns_1d(<1 x double> %A) nounwind #0 {449; CHECK-LABEL: define <1 x i64> @fcvtns_1d(450; CHECK-SAME: <1 x double> [[A:%.*]]) #[[ATTR0]] {451; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8452; CHECK-NEXT: call void @llvm.donothing()453; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <1 x i64> [[TMP1]], zeroinitializer454; CHECK-NEXT: [[TMP3:%.*]] = sext <1 x i1> [[TMP2]] to <1 x i64>455; CHECK-NEXT: [[TMPVAR3:%.*]] = call <1 x i64> @llvm.aarch64.neon.fcvtns.v1i64.v1f64(<1 x double> [[A]])456; CHECK-NEXT: store <1 x i64> [[TMP3]], ptr @__msan_retval_tls, align 8457; CHECK-NEXT: ret <1 x i64> [[TMPVAR3]]458;459 %tmpvar3 = call <1 x i64> @llvm.aarch64.neon.fcvtns.v1i64.v1f64(<1 x double> %A)460 ret <1 x i64> %tmpvar3461}462 463declare <2 x i32> @llvm.aarch64.neon.fcvtns.v2i32.v2f32(<2 x float>) nounwind readnone464declare <4 x i32> @llvm.aarch64.neon.fcvtns.v4i32.v4f32(<4 x float>) nounwind readnone465declare <2 x i64> @llvm.aarch64.neon.fcvtns.v2i64.v2f64(<2 x double>) nounwind readnone466declare <1 x i64> @llvm.aarch64.neon.fcvtns.v1i64.v1f64(<1 x double>) nounwind readnone467 468define <2 x i32> @fcvtnu_2s(<2 x float> %A) nounwind #0 {469; CHECK-LABEL: define <2 x i32> @fcvtnu_2s(470; CHECK-SAME: <2 x float> [[A:%.*]]) #[[ATTR0]] {471; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8472; CHECK-NEXT: call void @llvm.donothing()473; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer474; CHECK-NEXT: [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i32>475; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i32> @llvm.aarch64.neon.fcvtnu.v2i32.v2f32(<2 x float> [[A]])476; CHECK-NEXT: store <2 x i32> [[TMP3]], ptr @__msan_retval_tls, align 8477; CHECK-NEXT: ret <2 x i32> [[TMPVAR3]]478;479 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.fcvtnu.v2i32.v2f32(<2 x float> %A)480 ret <2 x i32> %tmpvar3481}482 483define <4 x i32> @fcvtnu_4s(<4 x float> %A) nounwind #0 {484; CHECK-LABEL: define <4 x i32> @fcvtnu_4s(485; CHECK-SAME: <4 x float> [[A:%.*]]) #[[ATTR0]] {486; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8487; CHECK-NEXT: call void @llvm.donothing()488; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <4 x i32> [[TMP1]], zeroinitializer489; CHECK-NEXT: [[TMP3:%.*]] = sext <4 x i1> [[TMP2]] to <4 x i32>490; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i32> @llvm.aarch64.neon.fcvtnu.v4i32.v4f32(<4 x float> [[A]])491; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr @__msan_retval_tls, align 8492; CHECK-NEXT: ret <4 x i32> [[TMPVAR3]]493;494 %tmpvar3 = call <4 x i32> @llvm.aarch64.neon.fcvtnu.v4i32.v4f32(<4 x float> %A)495 ret <4 x i32> %tmpvar3496}497 498define <2 x i64> @fcvtnu_2d(<2 x double> %A) nounwind #0 {499; CHECK-LABEL: define <2 x i64> @fcvtnu_2d(500; CHECK-SAME: <2 x double> [[A:%.*]]) #[[ATTR0]] {501; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8502; CHECK-NEXT: call void @llvm.donothing()503; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer504; CHECK-NEXT: [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i64>505; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i64> @llvm.aarch64.neon.fcvtnu.v2i64.v2f64(<2 x double> [[A]])506; CHECK-NEXT: store <2 x i64> [[TMP3]], ptr @__msan_retval_tls, align 8507; CHECK-NEXT: ret <2 x i64> [[TMPVAR3]]508;509 %tmpvar3 = call <2 x i64> @llvm.aarch64.neon.fcvtnu.v2i64.v2f64(<2 x double> %A)510 ret <2 x i64> %tmpvar3511}512 513define <1 x i64> @fcvtnu_1d(<1 x double> %A) nounwind #0 {514; CHECK-LABEL: define <1 x i64> @fcvtnu_1d(515; CHECK-SAME: <1 x double> [[A:%.*]]) #[[ATTR0]] {516; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8517; CHECK-NEXT: call void @llvm.donothing()518; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <1 x i64> [[TMP1]], zeroinitializer519; CHECK-NEXT: [[TMP3:%.*]] = sext <1 x i1> [[TMP2]] to <1 x i64>520; CHECK-NEXT: [[TMPVAR3:%.*]] = call <1 x i64> @llvm.aarch64.neon.fcvtnu.v1i64.v1f64(<1 x double> [[A]])521; CHECK-NEXT: store <1 x i64> [[TMP3]], ptr @__msan_retval_tls, align 8522; CHECK-NEXT: ret <1 x i64> [[TMPVAR3]]523;524 %tmpvar3 = call <1 x i64> @llvm.aarch64.neon.fcvtnu.v1i64.v1f64(<1 x double> %A)525 ret <1 x i64> %tmpvar3526}527 528declare <2 x i32> @llvm.aarch64.neon.fcvtnu.v2i32.v2f32(<2 x float>) nounwind readnone529declare <4 x i32> @llvm.aarch64.neon.fcvtnu.v4i32.v4f32(<4 x float>) nounwind readnone530declare <2 x i64> @llvm.aarch64.neon.fcvtnu.v2i64.v2f64(<2 x double>) nounwind readnone531declare <1 x i64> @llvm.aarch64.neon.fcvtnu.v1i64.v1f64(<1 x double>) nounwind readnone532 533define <2 x i32> @fcvtzs_2s(<2 x float> %A) nounwind #0 {534; CHECK-LABEL: define <2 x i32> @fcvtzs_2s(535; CHECK-SAME: <2 x float> [[A:%.*]]) #[[ATTR0]] {536; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8537; CHECK-NEXT: call void @llvm.donothing()538; CHECK-NEXT: [[TMPVAR3:%.*]] = fptosi <2 x float> [[A]] to <2 x i32>539; CHECK-NEXT: store <2 x i32> [[TMP1]], ptr @__msan_retval_tls, align 8540; CHECK-NEXT: ret <2 x i32> [[TMPVAR3]]541;542 %tmpvar3 = fptosi <2 x float> %A to <2 x i32>543 ret <2 x i32> %tmpvar3544}545 546define <4 x i32> @fcvtzs_4s(<4 x float> %A) nounwind #0 {547; CHECK-LABEL: define <4 x i32> @fcvtzs_4s(548; CHECK-SAME: <4 x float> [[A:%.*]]) #[[ATTR0]] {549; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8550; CHECK-NEXT: call void @llvm.donothing()551; CHECK-NEXT: [[TMPVAR3:%.*]] = fptosi <4 x float> [[A]] to <4 x i32>552; CHECK-NEXT: store <4 x i32> [[TMP1]], ptr @__msan_retval_tls, align 8553; CHECK-NEXT: ret <4 x i32> [[TMPVAR3]]554;555 %tmpvar3 = fptosi <4 x float> %A to <4 x i32>556 ret <4 x i32> %tmpvar3557}558 559define <2 x i64> @fcvtzs_2d(<2 x double> %A) nounwind #0 {560; CHECK-LABEL: define <2 x i64> @fcvtzs_2d(561; CHECK-SAME: <2 x double> [[A:%.*]]) #[[ATTR0]] {562; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8563; CHECK-NEXT: call void @llvm.donothing()564; CHECK-NEXT: [[TMPVAR3:%.*]] = fptosi <2 x double> [[A]] to <2 x i64>565; CHECK-NEXT: store <2 x i64> [[TMP1]], ptr @__msan_retval_tls, align 8566; CHECK-NEXT: ret <2 x i64> [[TMPVAR3]]567;568 %tmpvar3 = fptosi <2 x double> %A to <2 x i64>569 ret <2 x i64> %tmpvar3570}571 572define <1 x i64> @fcvtzs_1d(<1 x double> %A) nounwind #0 {573; CHECK-LABEL: define <1 x i64> @fcvtzs_1d(574; CHECK-SAME: <1 x double> [[A:%.*]]) #[[ATTR0]] {575; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8576; CHECK-NEXT: call void @llvm.donothing()577; CHECK-NEXT: [[TMPVAR3:%.*]] = fptosi <1 x double> [[A]] to <1 x i64>578; CHECK-NEXT: store <1 x i64> [[TMP1]], ptr @__msan_retval_tls, align 8579; CHECK-NEXT: ret <1 x i64> [[TMPVAR3]]580;581 %tmpvar3 = fptosi <1 x double> %A to <1 x i64>582 ret <1 x i64> %tmpvar3583}584 585define <2 x i32> @fcvtzs_2s_intrinsic(<2 x float> %A) nounwind #0 {586; CHECK-LABEL: define <2 x i32> @fcvtzs_2s_intrinsic(587; CHECK-SAME: <2 x float> [[A:%.*]]) #[[ATTR0]] {588; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8589; CHECK-NEXT: call void @llvm.donothing()590; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer591; CHECK-NEXT: [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i32>592; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i32> @llvm.aarch64.neon.fcvtzs.v2i32.v2f32(<2 x float> [[A]])593; CHECK-NEXT: store <2 x i32> [[TMP3]], ptr @__msan_retval_tls, align 8594; CHECK-NEXT: ret <2 x i32> [[TMPVAR3]]595;596 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.fcvtzs.v2i32.v2f32(<2 x float> %A)597 ret <2 x i32> %tmpvar3598}599 600define <4 x i32> @fcvtzs_4s_intrinsic(<4 x float> %A) nounwind #0 {601; CHECK-LABEL: define <4 x i32> @fcvtzs_4s_intrinsic(602; CHECK-SAME: <4 x float> [[A:%.*]]) #[[ATTR0]] {603; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8604; CHECK-NEXT: call void @llvm.donothing()605; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <4 x i32> [[TMP1]], zeroinitializer606; CHECK-NEXT: [[TMP3:%.*]] = sext <4 x i1> [[TMP2]] to <4 x i32>607; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i32> @llvm.aarch64.neon.fcvtzs.v4i32.v4f32(<4 x float> [[A]])608; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr @__msan_retval_tls, align 8609; CHECK-NEXT: ret <4 x i32> [[TMPVAR3]]610;611 %tmpvar3 = call <4 x i32> @llvm.aarch64.neon.fcvtzs.v4i32.v4f32(<4 x float> %A)612 ret <4 x i32> %tmpvar3613}614 615define <2 x i64> @fcvtzs_2d_intrinsic(<2 x double> %A) nounwind #0 {616; CHECK-LABEL: define <2 x i64> @fcvtzs_2d_intrinsic(617; CHECK-SAME: <2 x double> [[A:%.*]]) #[[ATTR0]] {618; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8619; CHECK-NEXT: call void @llvm.donothing()620; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer621; CHECK-NEXT: [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i64>622; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i64> @llvm.aarch64.neon.fcvtzs.v2i64.v2f64(<2 x double> [[A]])623; CHECK-NEXT: store <2 x i64> [[TMP3]], ptr @__msan_retval_tls, align 8624; CHECK-NEXT: ret <2 x i64> [[TMPVAR3]]625;626 %tmpvar3 = call <2 x i64> @llvm.aarch64.neon.fcvtzs.v2i64.v2f64(<2 x double> %A)627 ret <2 x i64> %tmpvar3628}629 630define <1 x i64> @fcvtzs_1d_intrinsic(<1 x double> %A) nounwind #0 {631; CHECK-LABEL: define <1 x i64> @fcvtzs_1d_intrinsic(632; CHECK-SAME: <1 x double> [[A:%.*]]) #[[ATTR0]] {633; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8634; CHECK-NEXT: call void @llvm.donothing()635; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <1 x i64> [[TMP1]], zeroinitializer636; CHECK-NEXT: [[TMP3:%.*]] = sext <1 x i1> [[TMP2]] to <1 x i64>637; CHECK-NEXT: [[TMPVAR3:%.*]] = call <1 x i64> @llvm.aarch64.neon.fcvtzs.v1i64.v1f64(<1 x double> [[A]])638; CHECK-NEXT: store <1 x i64> [[TMP3]], ptr @__msan_retval_tls, align 8639; CHECK-NEXT: ret <1 x i64> [[TMPVAR3]]640;641 %tmpvar3 = call <1 x i64> @llvm.aarch64.neon.fcvtzs.v1i64.v1f64(<1 x double> %A)642 ret <1 x i64> %tmpvar3643}644 645declare <2 x i32> @llvm.aarch64.neon.fcvtzs.v2i32.v2f32(<2 x float>) nounwind readnone646declare <4 x i32> @llvm.aarch64.neon.fcvtzs.v4i32.v4f32(<4 x float>) nounwind readnone647declare <2 x i64> @llvm.aarch64.neon.fcvtzs.v2i64.v2f64(<2 x double>) nounwind readnone648declare <1 x i64> @llvm.aarch64.neon.fcvtzs.v1i64.v1f64(<1 x double>) nounwind readnone649 650define <2 x i32> @fcvtzu_2s(<2 x float> %A) nounwind #0 {651; CHECK-LABEL: define <2 x i32> @fcvtzu_2s(652; CHECK-SAME: <2 x float> [[A:%.*]]) #[[ATTR0]] {653; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8654; CHECK-NEXT: call void @llvm.donothing()655; CHECK-NEXT: [[TMPVAR3:%.*]] = fptoui <2 x float> [[A]] to <2 x i32>656; CHECK-NEXT: store <2 x i32> [[TMP1]], ptr @__msan_retval_tls, align 8657; CHECK-NEXT: ret <2 x i32> [[TMPVAR3]]658;659 %tmpvar3 = fptoui <2 x float> %A to <2 x i32>660 ret <2 x i32> %tmpvar3661}662 663define <4 x i32> @fcvtzu_4s(<4 x float> %A) nounwind #0 {664; CHECK-LABEL: define <4 x i32> @fcvtzu_4s(665; CHECK-SAME: <4 x float> [[A:%.*]]) #[[ATTR0]] {666; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8667; CHECK-NEXT: call void @llvm.donothing()668; CHECK-NEXT: [[TMPVAR3:%.*]] = fptoui <4 x float> [[A]] to <4 x i32>669; CHECK-NEXT: store <4 x i32> [[TMP1]], ptr @__msan_retval_tls, align 8670; CHECK-NEXT: ret <4 x i32> [[TMPVAR3]]671;672 %tmpvar3 = fptoui <4 x float> %A to <4 x i32>673 ret <4 x i32> %tmpvar3674}675 676define <2 x i64> @fcvtzu_2d(<2 x double> %A) nounwind #0 {677; CHECK-LABEL: define <2 x i64> @fcvtzu_2d(678; CHECK-SAME: <2 x double> [[A:%.*]]) #[[ATTR0]] {679; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8680; CHECK-NEXT: call void @llvm.donothing()681; CHECK-NEXT: [[TMPVAR3:%.*]] = fptoui <2 x double> [[A]] to <2 x i64>682; CHECK-NEXT: store <2 x i64> [[TMP1]], ptr @__msan_retval_tls, align 8683; CHECK-NEXT: ret <2 x i64> [[TMPVAR3]]684;685 %tmpvar3 = fptoui <2 x double> %A to <2 x i64>686 ret <2 x i64> %tmpvar3687}688 689define <1 x i64> @fcvtzu_1d(<1 x double> %A) nounwind #0 {690; CHECK-LABEL: define <1 x i64> @fcvtzu_1d(691; CHECK-SAME: <1 x double> [[A:%.*]]) #[[ATTR0]] {692; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8693; CHECK-NEXT: call void @llvm.donothing()694; CHECK-NEXT: [[TMPVAR3:%.*]] = fptoui <1 x double> [[A]] to <1 x i64>695; CHECK-NEXT: store <1 x i64> [[TMP1]], ptr @__msan_retval_tls, align 8696; CHECK-NEXT: ret <1 x i64> [[TMPVAR3]]697;698 %tmpvar3 = fptoui <1 x double> %A to <1 x i64>699 ret <1 x i64> %tmpvar3700}701 702define <2 x i32> @fcvtzu_2s_intrinsic(<2 x float> %A) nounwind #0 {703; CHECK-LABEL: define <2 x i32> @fcvtzu_2s_intrinsic(704; CHECK-SAME: <2 x float> [[A:%.*]]) #[[ATTR0]] {705; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8706; CHECK-NEXT: call void @llvm.donothing()707; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i32> [[TMP1]], zeroinitializer708; CHECK-NEXT: [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i32>709; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i32> @llvm.aarch64.neon.fcvtzu.v2i32.v2f32(<2 x float> [[A]])710; CHECK-NEXT: store <2 x i32> [[TMP3]], ptr @__msan_retval_tls, align 8711; CHECK-NEXT: ret <2 x i32> [[TMPVAR3]]712;713 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.fcvtzu.v2i32.v2f32(<2 x float> %A)714 ret <2 x i32> %tmpvar3715}716 717define <4 x i32> @fcvtzu_4s_intrinsic(<4 x float> %A) nounwind #0 {718; CHECK-LABEL: define <4 x i32> @fcvtzu_4s_intrinsic(719; CHECK-SAME: <4 x float> [[A:%.*]]) #[[ATTR0]] {720; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8721; CHECK-NEXT: call void @llvm.donothing()722; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <4 x i32> [[TMP1]], zeroinitializer723; CHECK-NEXT: [[TMP3:%.*]] = sext <4 x i1> [[TMP2]] to <4 x i32>724; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i32> @llvm.aarch64.neon.fcvtzu.v4i32.v4f32(<4 x float> [[A]])725; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr @__msan_retval_tls, align 8726; CHECK-NEXT: ret <4 x i32> [[TMPVAR3]]727;728 %tmpvar3 = call <4 x i32> @llvm.aarch64.neon.fcvtzu.v4i32.v4f32(<4 x float> %A)729 ret <4 x i32> %tmpvar3730}731 732define <2 x i64> @fcvtzu_2d_intrinsic(<2 x double> %A) nounwind #0 {733; CHECK-LABEL: define <2 x i64> @fcvtzu_2d_intrinsic(734; CHECK-SAME: <2 x double> [[A:%.*]]) #[[ATTR0]] {735; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8736; CHECK-NEXT: call void @llvm.donothing()737; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer738; CHECK-NEXT: [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i64>739; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i64> @llvm.aarch64.neon.fcvtzu.v2i64.v2f64(<2 x double> [[A]])740; CHECK-NEXT: store <2 x i64> [[TMP3]], ptr @__msan_retval_tls, align 8741; CHECK-NEXT: ret <2 x i64> [[TMPVAR3]]742;743 %tmpvar3 = call <2 x i64> @llvm.aarch64.neon.fcvtzu.v2i64.v2f64(<2 x double> %A)744 ret <2 x i64> %tmpvar3745}746 747define <1 x i64> @fcvtzu_1d_intrinsic(<1 x double> %A) nounwind #0 {748; CHECK-LABEL: define <1 x i64> @fcvtzu_1d_intrinsic(749; CHECK-SAME: <1 x double> [[A:%.*]]) #[[ATTR0]] {750; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 8751; CHECK-NEXT: call void @llvm.donothing()752; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <1 x i64> [[TMP1]], zeroinitializer753; CHECK-NEXT: [[TMP3:%.*]] = sext <1 x i1> [[TMP2]] to <1 x i64>754; CHECK-NEXT: [[TMPVAR3:%.*]] = call <1 x i64> @llvm.aarch64.neon.fcvtzu.v1i64.v1f64(<1 x double> [[A]])755; CHECK-NEXT: store <1 x i64> [[TMP3]], ptr @__msan_retval_tls, align 8756; CHECK-NEXT: ret <1 x i64> [[TMPVAR3]]757;758 %tmpvar3 = call <1 x i64> @llvm.aarch64.neon.fcvtzu.v1i64.v1f64(<1 x double> %A)759 ret <1 x i64> %tmpvar3760}761 762declare <2 x i32> @llvm.aarch64.neon.fcvtzu.v2i32.v2f32(<2 x float>) nounwind readnone763declare <4 x i32> @llvm.aarch64.neon.fcvtzu.v4i32.v4f32(<4 x float>) nounwind readnone764declare <2 x i64> @llvm.aarch64.neon.fcvtzu.v2i64.v2f64(<2 x double>) nounwind readnone765declare <1 x i64> @llvm.aarch64.neon.fcvtzu.v1i64.v1f64(<1 x double>) nounwind readnone766 767define <2 x float> @frinta_2s(<2 x float> %A) nounwind #0 {768; CHECK-LABEL: define <2 x float> @frinta_2s(769; CHECK-SAME: <2 x float> [[A:%.*]]) #[[ATTR0]] {770; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8771; CHECK-NEXT: call void @llvm.donothing()772; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x float> @llvm.round.v2f32(<2 x float> [[A]])773; CHECK-NEXT: store <2 x i32> [[TMP1]], ptr @__msan_retval_tls, align 8774; CHECK-NEXT: ret <2 x float> [[TMPVAR3]]775;776 %tmpvar3 = call <2 x float> @llvm.round.v2f32(<2 x float> %A)777 ret <2 x float> %tmpvar3778}779 780define <4 x float> @frinta_4s(<4 x float> %A) nounwind #0 {781; CHECK-LABEL: define <4 x float> @frinta_4s(782; CHECK-SAME: <4 x float> [[A:%.*]]) #[[ATTR0]] {783; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8784; CHECK-NEXT: call void @llvm.donothing()785; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x float> @llvm.round.v4f32(<4 x float> [[A]])786; CHECK-NEXT: store <4 x i32> [[TMP1]], ptr @__msan_retval_tls, align 8787; CHECK-NEXT: ret <4 x float> [[TMPVAR3]]788;789 %tmpvar3 = call <4 x float> @llvm.round.v4f32(<4 x float> %A)790 ret <4 x float> %tmpvar3791}792 793define <2 x double> @frinta_2d(<2 x double> %A) nounwind #0 {794; CHECK-LABEL: define <2 x double> @frinta_2d(795; CHECK-SAME: <2 x double> [[A:%.*]]) #[[ATTR0]] {796; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8797; CHECK-NEXT: call void @llvm.donothing()798; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x double> @llvm.round.v2f64(<2 x double> [[A]])799; CHECK-NEXT: store <2 x i64> [[TMP1]], ptr @__msan_retval_tls, align 8800; CHECK-NEXT: ret <2 x double> [[TMPVAR3]]801;802 %tmpvar3 = call <2 x double> @llvm.round.v2f64(<2 x double> %A)803 ret <2 x double> %tmpvar3804}805 806declare <2 x float> @llvm.round.v2f32(<2 x float>) nounwind readnone807declare <4 x float> @llvm.round.v4f32(<4 x float>) nounwind readnone808declare <2 x double> @llvm.round.v2f64(<2 x double>) nounwind readnone809 810define <2 x float> @frinti_2s(<2 x float> %A) nounwind #0 {811; CHECK-LABEL: define <2 x float> @frinti_2s(812; CHECK-SAME: <2 x float> [[A:%.*]]) #[[ATTR0]] {813; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8814; CHECK-NEXT: call void @llvm.donothing()815; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x float> @llvm.nearbyint.v2f32(<2 x float> [[A]])816; CHECK-NEXT: store <2 x i32> [[TMP1]], ptr @__msan_retval_tls, align 8817; CHECK-NEXT: ret <2 x float> [[TMPVAR3]]818;819 %tmpvar3 = call <2 x float> @llvm.nearbyint.v2f32(<2 x float> %A)820 ret <2 x float> %tmpvar3821}822 823define <4 x float> @frinti_4s(<4 x float> %A) nounwind #0 {824; CHECK-LABEL: define <4 x float> @frinti_4s(825; CHECK-SAME: <4 x float> [[A:%.*]]) #[[ATTR0]] {826; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8827; CHECK-NEXT: call void @llvm.donothing()828; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> [[A]])829; CHECK-NEXT: store <4 x i32> [[TMP1]], ptr @__msan_retval_tls, align 8830; CHECK-NEXT: ret <4 x float> [[TMPVAR3]]831;832 %tmpvar3 = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %A)833 ret <4 x float> %tmpvar3834}835 836define <2 x double> @frinti_2d(<2 x double> %A) nounwind #0 {837; CHECK-LABEL: define <2 x double> @frinti_2d(838; CHECK-SAME: <2 x double> [[A:%.*]]) #[[ATTR0]] {839; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8840; CHECK-NEXT: call void @llvm.donothing()841; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> [[A]])842; CHECK-NEXT: store <2 x i64> [[TMP1]], ptr @__msan_retval_tls, align 8843; CHECK-NEXT: ret <2 x double> [[TMPVAR3]]844;845 %tmpvar3 = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %A)846 ret <2 x double> %tmpvar3847}848 849declare <2 x float> @llvm.nearbyint.v2f32(<2 x float>) nounwind readnone850declare <4 x float> @llvm.nearbyint.v4f32(<4 x float>) nounwind readnone851declare <2 x double> @llvm.nearbyint.v2f64(<2 x double>) nounwind readnone852 853define <2 x float> @frintm_2s(<2 x float> %A) nounwind #0 {854; CHECK-LABEL: define <2 x float> @frintm_2s(855; CHECK-SAME: <2 x float> [[A:%.*]]) #[[ATTR0]] {856; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8857; CHECK-NEXT: call void @llvm.donothing()858; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x float> @llvm.floor.v2f32(<2 x float> [[A]])859; CHECK-NEXT: store <2 x i32> [[TMP1]], ptr @__msan_retval_tls, align 8860; CHECK-NEXT: ret <2 x float> [[TMPVAR3]]861;862 %tmpvar3 = call <2 x float> @llvm.floor.v2f32(<2 x float> %A)863 ret <2 x float> %tmpvar3864}865 866define <4 x float> @frintm_4s(<4 x float> %A) nounwind #0 {867; CHECK-LABEL: define <4 x float> @frintm_4s(868; CHECK-SAME: <4 x float> [[A:%.*]]) #[[ATTR0]] {869; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8870; CHECK-NEXT: call void @llvm.donothing()871; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x float> @llvm.floor.v4f32(<4 x float> [[A]])872; CHECK-NEXT: store <4 x i32> [[TMP1]], ptr @__msan_retval_tls, align 8873; CHECK-NEXT: ret <4 x float> [[TMPVAR3]]874;875 %tmpvar3 = call <4 x float> @llvm.floor.v4f32(<4 x float> %A)876 ret <4 x float> %tmpvar3877}878 879define <2 x double> @frintm_2d(<2 x double> %A) nounwind #0 {880; CHECK-LABEL: define <2 x double> @frintm_2d(881; CHECK-SAME: <2 x double> [[A:%.*]]) #[[ATTR0]] {882; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8883; CHECK-NEXT: call void @llvm.donothing()884; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x double> @llvm.floor.v2f64(<2 x double> [[A]])885; CHECK-NEXT: store <2 x i64> [[TMP1]], ptr @__msan_retval_tls, align 8886; CHECK-NEXT: ret <2 x double> [[TMPVAR3]]887;888 %tmpvar3 = call <2 x double> @llvm.floor.v2f64(<2 x double> %A)889 ret <2 x double> %tmpvar3890}891 892declare <2 x float> @llvm.floor.v2f32(<2 x float>) nounwind readnone893declare <4 x float> @llvm.floor.v4f32(<4 x float>) nounwind readnone894declare <2 x double> @llvm.floor.v2f64(<2 x double>) nounwind readnone895 896define <2 x float> @frintn_2s(<2 x float> %A) nounwind #0 {897; CHECK-LABEL: define <2 x float> @frintn_2s(898; CHECK-SAME: <2 x float> [[A:%.*]]) #[[ATTR0]] {899; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8900; CHECK-NEXT: call void @llvm.donothing()901; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x float> @llvm.roundeven.v2f32(<2 x float> [[A]])902; CHECK-NEXT: store <2 x i32> [[TMP1]], ptr @__msan_retval_tls, align 8903; CHECK-NEXT: ret <2 x float> [[TMPVAR3]]904;905 %tmpvar3 = call <2 x float> @llvm.roundeven.v2f32(<2 x float> %A)906 ret <2 x float> %tmpvar3907}908 909define <4 x float> @frintn_4s(<4 x float> %A) nounwind #0 {910; CHECK-LABEL: define <4 x float> @frintn_4s(911; CHECK-SAME: <4 x float> [[A:%.*]]) #[[ATTR0]] {912; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8913; CHECK-NEXT: call void @llvm.donothing()914; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x float> @llvm.roundeven.v4f32(<4 x float> [[A]])915; CHECK-NEXT: store <4 x i32> [[TMP1]], ptr @__msan_retval_tls, align 8916; CHECK-NEXT: ret <4 x float> [[TMPVAR3]]917;918 %tmpvar3 = call <4 x float> @llvm.roundeven.v4f32(<4 x float> %A)919 ret <4 x float> %tmpvar3920}921 922define <2 x double> @frintn_2d(<2 x double> %A) nounwind #0 {923; CHECK-LABEL: define <2 x double> @frintn_2d(924; CHECK-SAME: <2 x double> [[A:%.*]]) #[[ATTR0]] {925; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8926; CHECK-NEXT: call void @llvm.donothing()927; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x double> @llvm.roundeven.v2f64(<2 x double> [[A]])928; CHECK-NEXT: store <2 x i64> [[TMP1]], ptr @__msan_retval_tls, align 8929; CHECK-NEXT: ret <2 x double> [[TMPVAR3]]930;931 %tmpvar3 = call <2 x double> @llvm.roundeven.v2f64(<2 x double> %A)932 ret <2 x double> %tmpvar3933}934 935declare <2 x float> @llvm.roundeven.v2f32(<2 x float>) nounwind readnone936declare <4 x float> @llvm.roundeven.v4f32(<4 x float>) nounwind readnone937declare <2 x double> @llvm.roundeven.v2f64(<2 x double>) nounwind readnone938 939define <2 x float> @frintp_2s(<2 x float> %A) nounwind #0 {940; CHECK-LABEL: define <2 x float> @frintp_2s(941; CHECK-SAME: <2 x float> [[A:%.*]]) #[[ATTR0]] {942; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8943; CHECK-NEXT: call void @llvm.donothing()944; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x float> @llvm.ceil.v2f32(<2 x float> [[A]])945; CHECK-NEXT: store <2 x i32> [[TMP1]], ptr @__msan_retval_tls, align 8946; CHECK-NEXT: ret <2 x float> [[TMPVAR3]]947;948 %tmpvar3 = call <2 x float> @llvm.ceil.v2f32(<2 x float> %A)949 ret <2 x float> %tmpvar3950}951 952define <4 x float> @frintp_4s(<4 x float> %A) nounwind #0 {953; CHECK-LABEL: define <4 x float> @frintp_4s(954; CHECK-SAME: <4 x float> [[A:%.*]]) #[[ATTR0]] {955; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8956; CHECK-NEXT: call void @llvm.donothing()957; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x float> @llvm.ceil.v4f32(<4 x float> [[A]])958; CHECK-NEXT: store <4 x i32> [[TMP1]], ptr @__msan_retval_tls, align 8959; CHECK-NEXT: ret <4 x float> [[TMPVAR3]]960;961 %tmpvar3 = call <4 x float> @llvm.ceil.v4f32(<4 x float> %A)962 ret <4 x float> %tmpvar3963}964 965define <2 x double> @frintp_2d(<2 x double> %A) nounwind #0 {966; CHECK-LABEL: define <2 x double> @frintp_2d(967; CHECK-SAME: <2 x double> [[A:%.*]]) #[[ATTR0]] {968; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8969; CHECK-NEXT: call void @llvm.donothing()970; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x double> @llvm.ceil.v2f64(<2 x double> [[A]])971; CHECK-NEXT: store <2 x i64> [[TMP1]], ptr @__msan_retval_tls, align 8972; CHECK-NEXT: ret <2 x double> [[TMPVAR3]]973;974 %tmpvar3 = call <2 x double> @llvm.ceil.v2f64(<2 x double> %A)975 ret <2 x double> %tmpvar3976}977 978declare <2 x float> @llvm.ceil.v2f32(<2 x float>) nounwind readnone979declare <4 x float> @llvm.ceil.v4f32(<4 x float>) nounwind readnone980declare <2 x double> @llvm.ceil.v2f64(<2 x double>) nounwind readnone981 982define <2 x float> @frintx_2s(<2 x float> %A) nounwind #0 {983; CHECK-LABEL: define <2 x float> @frintx_2s(984; CHECK-SAME: <2 x float> [[A:%.*]]) #[[ATTR0]] {985; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8986; CHECK-NEXT: call void @llvm.donothing()987; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x float> @llvm.rint.v2f32(<2 x float> [[A]])988; CHECK-NEXT: store <2 x i32> [[TMP1]], ptr @__msan_retval_tls, align 8989; CHECK-NEXT: ret <2 x float> [[TMPVAR3]]990;991 %tmpvar3 = call <2 x float> @llvm.rint.v2f32(<2 x float> %A)992 ret <2 x float> %tmpvar3993}994 995define <4 x float> @frintx_4s(<4 x float> %A) nounwind #0 {996; CHECK-LABEL: define <4 x float> @frintx_4s(997; CHECK-SAME: <4 x float> [[A:%.*]]) #[[ATTR0]] {998; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8999; CHECK-NEXT: call void @llvm.donothing()1000; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x float> @llvm.rint.v4f32(<4 x float> [[A]])1001; CHECK-NEXT: store <4 x i32> [[TMP1]], ptr @__msan_retval_tls, align 81002; CHECK-NEXT: ret <4 x float> [[TMPVAR3]]1003;1004 %tmpvar3 = call <4 x float> @llvm.rint.v4f32(<4 x float> %A)1005 ret <4 x float> %tmpvar31006}1007 1008define <2 x double> @frintx_2d(<2 x double> %A) nounwind #0 {1009; CHECK-LABEL: define <2 x double> @frintx_2d(1010; CHECK-SAME: <2 x double> [[A:%.*]]) #[[ATTR0]] {1011; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81012; CHECK-NEXT: call void @llvm.donothing()1013; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x double> @llvm.rint.v2f64(<2 x double> [[A]])1014; CHECK-NEXT: store <2 x i64> [[TMP1]], ptr @__msan_retval_tls, align 81015; CHECK-NEXT: ret <2 x double> [[TMPVAR3]]1016;1017 %tmpvar3 = call <2 x double> @llvm.rint.v2f64(<2 x double> %A)1018 ret <2 x double> %tmpvar31019}1020 1021declare <2 x float> @llvm.rint.v2f32(<2 x float>) nounwind readnone1022declare <4 x float> @llvm.rint.v4f32(<4 x float>) nounwind readnone1023declare <2 x double> @llvm.rint.v2f64(<2 x double>) nounwind readnone1024 1025define <2 x float> @frintz_2s(<2 x float> %A) nounwind #0 {1026; CHECK-LABEL: define <2 x float> @frintz_2s(1027; CHECK-SAME: <2 x float> [[A:%.*]]) #[[ATTR0]] {1028; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 81029; CHECK-NEXT: call void @llvm.donothing()1030; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x float> @llvm.trunc.v2f32(<2 x float> [[A]])1031; CHECK-NEXT: store <2 x i32> [[TMP1]], ptr @__msan_retval_tls, align 81032; CHECK-NEXT: ret <2 x float> [[TMPVAR3]]1033;1034 %tmpvar3 = call <2 x float> @llvm.trunc.v2f32(<2 x float> %A)1035 ret <2 x float> %tmpvar31036}1037 1038define <4 x float> @frintz_4s(<4 x float> %A) nounwind #0 {1039; CHECK-LABEL: define <4 x float> @frintz_4s(1040; CHECK-SAME: <4 x float> [[A:%.*]]) #[[ATTR0]] {1041; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81042; CHECK-NEXT: call void @llvm.donothing()1043; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x float> @llvm.trunc.v4f32(<4 x float> [[A]])1044; CHECK-NEXT: store <4 x i32> [[TMP1]], ptr @__msan_retval_tls, align 81045; CHECK-NEXT: ret <4 x float> [[TMPVAR3]]1046;1047 %tmpvar3 = call <4 x float> @llvm.trunc.v4f32(<4 x float> %A)1048 ret <4 x float> %tmpvar31049}1050 1051define <2 x double> @frintz_2d(<2 x double> %A) nounwind #0 {1052; CHECK-LABEL: define <2 x double> @frintz_2d(1053; CHECK-SAME: <2 x double> [[A:%.*]]) #[[ATTR0]] {1054; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81055; CHECK-NEXT: call void @llvm.donothing()1056; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x double> @llvm.trunc.v2f64(<2 x double> [[A]])1057; CHECK-NEXT: store <2 x i64> [[TMP1]], ptr @__msan_retval_tls, align 81058; CHECK-NEXT: ret <2 x double> [[TMPVAR3]]1059;1060 %tmpvar3 = call <2 x double> @llvm.trunc.v2f64(<2 x double> %A)1061 ret <2 x double> %tmpvar31062}1063 1064declare <2 x float> @llvm.trunc.v2f32(<2 x float>) nounwind readnone1065declare <4 x float> @llvm.trunc.v4f32(<4 x float>) nounwind readnone1066declare <2 x double> @llvm.trunc.v2f64(<2 x double>) nounwind readnone1067 1068define <2 x float> @fcvtxn_2s(<2 x double> %A) nounwind #0 {1069; CHECK-LABEL: define <2 x float> @fcvtxn_2s(1070; CHECK-SAME: <2 x double> [[A:%.*]]) #[[ATTR0]] {1071; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81072; CHECK-NEXT: call void @llvm.donothing()1073; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer1074; CHECK-NEXT: [[TMP3:%.*]] = sext <2 x i1> [[TMP2]] to <2 x i32>1075; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> [[A]])1076; CHECK-NEXT: store <2 x i32> [[TMP3]], ptr @__msan_retval_tls, align 81077; CHECK-NEXT: ret <2 x float> [[TMPVAR3]]1078;1079 %tmpvar3 = call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %A)1080 ret <2 x float> %tmpvar31081}1082 1083define <4 x float> @fcvtxn_4s(<2 x float> %ret, <2 x double> %A) nounwind #0 {1084; CHECK-LABEL: define <4 x float> @fcvtxn_4s(1085; CHECK-SAME: <2 x float> [[RET:%.*]], <2 x double> [[A:%.*]]) #[[ATTR0]] {1086; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81087; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 81088; CHECK-NEXT: call void @llvm.donothing()1089; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer1090; CHECK-NEXT: [[TMP4:%.*]] = sext <2 x i1> [[TMP3]] to <2 x i32>1091; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> [[A]])1092; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>1093; CHECK-NEXT: [[RES:%.*]] = shufflevector <2 x float> [[RET]], <2 x float> [[TMPVAR3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>1094; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 81095; CHECK-NEXT: ret <4 x float> [[RES]]1096;1097 %tmpvar3 = call <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double> %A)1098 %res = shufflevector <2 x float> %ret, <2 x float> %tmpvar3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>1099 ret <4 x float> %res1100}1101 1102declare <2 x float> @llvm.aarch64.neon.fcvtxn.v2f32.v2f64(<2 x double>) nounwind readnone1103 1104define <2 x i32> @fcvtzsc_2s(<2 x float> %A) nounwind #0 {1105; CHECK-LABEL: define <2 x i32> @fcvtzsc_2s(1106; CHECK-SAME: <2 x float> [[A:%.*]]) #[[ATTR0]] {1107; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 81108; CHECK-NEXT: call void @llvm.donothing()1109; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to i641110; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 01111; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1:![0-9]+]]1112; CHECK: 3:1113; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5:[0-9]+]]1114; CHECK-NEXT: unreachable1115; CHECK: 4:1116; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i32> @llvm.aarch64.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float> [[A]], i32 1)1117; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81118; CHECK-NEXT: ret <2 x i32> [[TMPVAR3]]1119;1120 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float> %A, i32 1)1121 ret <2 x i32> %tmpvar31122}1123 1124define <4 x i32> @fcvtzsc_4s(<4 x float> %A) nounwind #0 {1125; CHECK-LABEL: define <4 x i32> @fcvtzsc_4s(1126; CHECK-SAME: <4 x float> [[A:%.*]]) #[[ATTR0]] {1127; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81128; CHECK-NEXT: call void @llvm.donothing()1129; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[TMP1]] to i1281130; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 01131; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1132; CHECK: 3:1133; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1134; CHECK-NEXT: unreachable1135; CHECK: 4:1136; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i32> @llvm.aarch64.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float> [[A]], i32 1)1137; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81138; CHECK-NEXT: ret <4 x i32> [[TMPVAR3]]1139;1140 %tmpvar3 = call <4 x i32> @llvm.aarch64.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float> %A, i32 1)1141 ret <4 x i32> %tmpvar31142}1143 1144define <2 x i64> @fcvtzsc_2d(<2 x double> %A) nounwind #0 {1145; CHECK-LABEL: define <2 x i64> @fcvtzsc_2d(1146; CHECK-SAME: <2 x double> [[A:%.*]]) #[[ATTR0]] {1147; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81148; CHECK-NEXT: call void @llvm.donothing()1149; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to i1281150; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 01151; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1152; CHECK: 3:1153; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1154; CHECK-NEXT: unreachable1155; CHECK: 4:1156; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i64> @llvm.aarch64.neon.vcvtfp2fxs.v2i64.v2f64(<2 x double> [[A]], i32 1)1157; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 81158; CHECK-NEXT: ret <2 x i64> [[TMPVAR3]]1159;1160 %tmpvar3 = call <2 x i64> @llvm.aarch64.neon.vcvtfp2fxs.v2i64.v2f64(<2 x double> %A, i32 1)1161 ret <2 x i64> %tmpvar31162}1163 1164declare <2 x i32> @llvm.aarch64.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float>, i32) nounwind readnone1165declare <4 x i32> @llvm.aarch64.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float>, i32) nounwind readnone1166declare <2 x i64> @llvm.aarch64.neon.vcvtfp2fxs.v2i64.v2f64(<2 x double>, i32) nounwind readnone1167 1168define <2 x i32> @fcvtzuc_2s(<2 x float> %A) nounwind #0 {1169; CHECK-LABEL: define <2 x i32> @fcvtzuc_2s(1170; CHECK-SAME: <2 x float> [[A:%.*]]) #[[ATTR0]] {1171; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 81172; CHECK-NEXT: call void @llvm.donothing()1173; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to i641174; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 01175; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1176; CHECK: 3:1177; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1178; CHECK-NEXT: unreachable1179; CHECK: 4:1180; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i32> @llvm.aarch64.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float> [[A]], i32 1)1181; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81182; CHECK-NEXT: ret <2 x i32> [[TMPVAR3]]1183;1184 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float> %A, i32 1)1185 ret <2 x i32> %tmpvar31186}1187 1188define <4 x i32> @fcvtzuc_4s(<4 x float> %A) nounwind #0 {1189; CHECK-LABEL: define <4 x i32> @fcvtzuc_4s(1190; CHECK-SAME: <4 x float> [[A:%.*]]) #[[ATTR0]] {1191; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81192; CHECK-NEXT: call void @llvm.donothing()1193; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[TMP1]] to i1281194; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 01195; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1196; CHECK: 3:1197; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1198; CHECK-NEXT: unreachable1199; CHECK: 4:1200; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i32> @llvm.aarch64.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float> [[A]], i32 1)1201; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81202; CHECK-NEXT: ret <4 x i32> [[TMPVAR3]]1203;1204 %tmpvar3 = call <4 x i32> @llvm.aarch64.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float> %A, i32 1)1205 ret <4 x i32> %tmpvar31206}1207 1208define <2 x i64> @fcvtzuc_2d(<2 x double> %A) nounwind #0 {1209; CHECK-LABEL: define <2 x i64> @fcvtzuc_2d(1210; CHECK-SAME: <2 x double> [[A:%.*]]) #[[ATTR0]] {1211; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81212; CHECK-NEXT: call void @llvm.donothing()1213; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to i1281214; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 01215; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1216; CHECK: 3:1217; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1218; CHECK-NEXT: unreachable1219; CHECK: 4:1220; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i64> @llvm.aarch64.neon.vcvtfp2fxu.v2i64.v2f64(<2 x double> [[A]], i32 1)1221; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 81222; CHECK-NEXT: ret <2 x i64> [[TMPVAR3]]1223;1224 %tmpvar3 = call <2 x i64> @llvm.aarch64.neon.vcvtfp2fxu.v2i64.v2f64(<2 x double> %A, i32 1)1225 ret <2 x i64> %tmpvar31226}1227 1228declare <2 x i32> @llvm.aarch64.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float>, i32) nounwind readnone1229declare <4 x i32> @llvm.aarch64.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float>, i32) nounwind readnone1230declare <2 x i64> @llvm.aarch64.neon.vcvtfp2fxu.v2i64.v2f64(<2 x double>, i32) nounwind readnone1231 1232define <2 x float> @scvtf_2sc(<2 x i32> %A) nounwind #0 {1233; CHECK-LABEL: define <2 x float> @scvtf_2sc(1234; CHECK-SAME: <2 x i32> [[A:%.*]]) #[[ATTR0]] {1235; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 81236; CHECK-NEXT: call void @llvm.donothing()1237; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to i641238; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 01239; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1240; CHECK: 3:1241; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1242; CHECK-NEXT: unreachable1243; CHECK: 4:1244; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x float> @llvm.aarch64.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32> [[A]], i32 1)1245; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81246; CHECK-NEXT: ret <2 x float> [[TMPVAR3]]1247;1248 %tmpvar3 = call <2 x float> @llvm.aarch64.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32> %A, i32 1)1249 ret <2 x float> %tmpvar31250}1251 1252define <4 x float> @scvtf_4sc(<4 x i32> %A) nounwind #0 {1253; CHECK-LABEL: define <4 x float> @scvtf_4sc(1254; CHECK-SAME: <4 x i32> [[A:%.*]]) #[[ATTR0]] {1255; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81256; CHECK-NEXT: call void @llvm.donothing()1257; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[TMP1]] to i1281258; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 01259; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1260; CHECK: 3:1261; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1262; CHECK-NEXT: unreachable1263; CHECK: 4:1264; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x float> @llvm.aarch64.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> [[A]], i32 1)1265; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81266; CHECK-NEXT: ret <4 x float> [[TMPVAR3]]1267;1268 %tmpvar3 = call <4 x float> @llvm.aarch64.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> %A, i32 1)1269 ret <4 x float> %tmpvar31270}1271 1272define <2 x double> @scvtf_2dc(<2 x i64> %A) nounwind #0 {1273; CHECK-LABEL: define <2 x double> @scvtf_2dc(1274; CHECK-SAME: <2 x i64> [[A:%.*]]) #[[ATTR0]] {1275; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81276; CHECK-NEXT: call void @llvm.donothing()1277; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to i1281278; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 01279; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1280; CHECK: 3:1281; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1282; CHECK-NEXT: unreachable1283; CHECK: 4:1284; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x double> @llvm.aarch64.neon.vcvtfxs2fp.v2f64.v2i64(<2 x i64> [[A]], i32 1)1285; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 81286; CHECK-NEXT: ret <2 x double> [[TMPVAR3]]1287;1288 %tmpvar3 = call <2 x double> @llvm.aarch64.neon.vcvtfxs2fp.v2f64.v2i64(<2 x i64> %A, i32 1)1289 ret <2 x double> %tmpvar31290}1291 1292declare <2 x float> @llvm.aarch64.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone1293declare <4 x float> @llvm.aarch64.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone1294declare <2 x double> @llvm.aarch64.neon.vcvtfxs2fp.v2f64.v2i64(<2 x i64>, i32) nounwind readnone1295 1296define <2 x float> @ucvtf_2sc(<2 x i32> %A) nounwind #0 {1297; CHECK-LABEL: define <2 x float> @ucvtf_2sc(1298; CHECK-SAME: <2 x i32> [[A:%.*]]) #[[ATTR0]] {1299; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 81300; CHECK-NEXT: call void @llvm.donothing()1301; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i32> [[TMP1]] to i641302; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 01303; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1304; CHECK: 3:1305; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1306; CHECK-NEXT: unreachable1307; CHECK: 4:1308; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x float> @llvm.aarch64.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> [[A]], i32 1)1309; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81310; CHECK-NEXT: ret <2 x float> [[TMPVAR3]]1311;1312 %tmpvar3 = call <2 x float> @llvm.aarch64.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> %A, i32 1)1313 ret <2 x float> %tmpvar31314}1315 1316define <4 x float> @ucvtf_4sc(<4 x i32> %A) nounwind #0 {1317; CHECK-LABEL: define <4 x float> @ucvtf_4sc(1318; CHECK-SAME: <4 x i32> [[A:%.*]]) #[[ATTR0]] {1319; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 81320; CHECK-NEXT: call void @llvm.donothing()1321; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[TMP1]] to i1281322; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 01323; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1324; CHECK: 3:1325; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1326; CHECK-NEXT: unreachable1327; CHECK: 4:1328; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x float> @llvm.aarch64.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> [[A]], i32 1)1329; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 81330; CHECK-NEXT: ret <4 x float> [[TMPVAR3]]1331;1332 %tmpvar3 = call <4 x float> @llvm.aarch64.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> %A, i32 1)1333 ret <4 x float> %tmpvar31334}1335 1336define <2 x double> @ucvtf_2dc(<2 x i64> %A) nounwind #0 {1337; CHECK-LABEL: define <2 x double> @ucvtf_2dc(1338; CHECK-SAME: <2 x i64> [[A:%.*]]) #[[ATTR0]] {1339; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 81340; CHECK-NEXT: call void @llvm.donothing()1341; CHECK-NEXT: [[TMP2:%.*]] = bitcast <2 x i64> [[TMP1]] to i1281342; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i128 [[TMP2]], 01343; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1344; CHECK: 3:1345; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1346; CHECK-NEXT: unreachable1347; CHECK: 4:1348; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x double> @llvm.aarch64.neon.vcvtfxu2fp.v2f64.v2i64(<2 x i64> [[A]], i32 1)1349; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 81350; CHECK-NEXT: ret <2 x double> [[TMPVAR3]]1351;1352 %tmpvar3 = call <2 x double> @llvm.aarch64.neon.vcvtfxu2fp.v2f64.v2i64(<2 x i64> %A, i32 1)1353 ret <2 x double> %tmpvar31354}1355 1356 1357define void @autogen_SD28458(<8 x double> %val.f64, ptr %addr.f32) #0 {1358; CHECK-LABEL: define void @autogen_SD28458(1359; CHECK-SAME: <8 x double> [[VAL_F64:%.*]], ptr [[ADDR_F32:%.*]]) #[[ATTR3:[0-9]+]] {1360; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @__msan_param_tls, align 81361; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 64), align 81362; CHECK-NEXT: call void @llvm.donothing()1363; CHECK-NEXT: [[TMP3:%.*]] = trunc <8 x i64> [[TMP1]] to <8 x i32>1364; CHECK-NEXT: [[TR53:%.*]] = fptrunc <8 x double> [[VAL_F64]] to <8 x float>1365; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 01366; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP4:%.*]], label [[TMP5:%.*]], !prof [[PROF1]]1367; CHECK: 4:1368; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1369; CHECK-NEXT: unreachable1370; CHECK: 5:1371; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[ADDR_F32]] to i641372; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 1935140464885761373; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr1374; CHECK-NEXT: store <8 x i32> [[TMP3]], ptr [[TMP8]], align 321375; CHECK-NEXT: store <8 x float> [[TR53]], ptr [[ADDR_F32]], align 321376; CHECK-NEXT: ret void1377;1378 %Tr53 = fptrunc <8 x double> %val.f64 to <8 x float>1379 store <8 x float> %Tr53, ptr %addr.f321380 ret void1381}1382 1383define void @autogen_SD19225(ptr %addr.f64, ptr %addr.f32) #0 {1384; CHECK-LABEL: define void @autogen_SD19225(1385; CHECK-SAME: ptr [[ADDR_F64:%.*]], ptr [[ADDR_F32:%.*]]) #[[ATTR3]] {1386; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81387; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_param_tls, align 81388; CHECK-NEXT: call void @llvm.donothing()1389; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01390; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1391; CHECK: 3:1392; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1393; CHECK-NEXT: unreachable1394; CHECK: 4:1395; CHECK-NEXT: [[A:%.*]] = load <8 x float>, ptr [[ADDR_F32]], align 321396; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[ADDR_F32]] to i641397; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761398; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1399; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i32>, ptr [[TMP7]], align 321400; CHECK-NEXT: [[TMP8:%.*]] = zext <8 x i32> [[_MSLD]] to <8 x i64>1401; CHECK-NEXT: [[TR53:%.*]] = fpext <8 x float> [[A]] to <8 x double>1402; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP2]], 01403; CHECK-NEXT: br i1 [[_MSCMP1]], label [[TMP9:%.*]], label [[TMP10:%.*]], !prof [[PROF1]]1404; CHECK: 9:1405; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1406; CHECK-NEXT: unreachable1407; CHECK: 10:1408; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[ADDR_F64]] to i641409; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 1935140464885761410; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr1411; CHECK-NEXT: store <8 x i64> [[TMP8]], ptr [[TMP13]], align 641412; CHECK-NEXT: store <8 x double> [[TR53]], ptr [[ADDR_F64]], align 641413; CHECK-NEXT: ret void1414;1415 %A = load <8 x float>, ptr %addr.f321416 %Tr53 = fpext <8 x float> %A to <8 x double>1417 store <8 x double> %Tr53, ptr %addr.f641418 ret void1419}1420 1421declare <2 x float> @llvm.aarch64.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone1422declare <4 x float> @llvm.aarch64.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone1423declare <2 x double> @llvm.aarch64.neon.vcvtfxu2fp.v2f64.v2i64(<2 x i64>, i32) nounwind readnone1424 1425attributes #0 = { sanitize_memory }1426;.1427; CHECK: [[PROF1]] = !{!"branch_weights", i32 1, i32 1048575}1428;.1429