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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt < %s -passes=msan -S | FileCheck %s3;4; Forked from llvm/test/CodeGen/AArch64/arm64-vmax.ll5;6; Pairwise instructions which are explicitly handled by7; handlePairwiseShadowOrIntrinsic:8; - llvm.aarch64.neon.fmaxp (floating-point maximum pairwise)9; - llvm.aarch64.neon.fminp10; - llvm.aarch64.neon.fmaxnmp (floating-point maximum number pairwise)11; - llvm.aarch64.neon.fminnmp12; - llvm.aarch64.neon.smaxp13; - llvm.aarch64.neon.sminp14; - llvm.aarch64.neon.umaxp15; - llvm.aarch64.neon.uminp16;17; Other instructions which are handled correctly by heuristics:18; - llvm.aarch64.neon.fmax19; - llvm.aarch64.neon.fmin20; - llvm.aarch64.neon.smax21; - llvm.aarch64.neon.smin22; - llvm.aarch64.neon.umax23; - llvm.aarch64.neon.umin24 25target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"26target triple = "aarch64--linux-android9001"27 28define <8 x i8> @smax_8b(ptr %A, ptr %B) nounwind #0 {29; CHECK-LABEL: define <8 x i8> @smax_8b(30; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {31; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 832; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 833; CHECK-NEXT: call void @llvm.donothing()34; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 035; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1:![0-9]+]]36; CHECK: [[BB3]]:37; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3:[0-9]+]]38; CHECK-NEXT: unreachable39; CHECK: [[BB4]]:40; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i8>, ptr [[A]], align 841; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i6442; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 19351404648857643; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr44; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 845; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 046; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]47; CHECK: [[BB8]]:48; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]49; CHECK-NEXT: unreachable50; CHECK: [[BB9]]:51; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i8>, ptr [[B]], align 852; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i6453; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 19351404648857654; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr55; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP12]], align 856; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i8> [[_MSLD]], [[_MSLD1]]57; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i8> @llvm.aarch64.neon.smax.v8i8(<8 x i8> [[TMPVAR1]], <8 x i8> [[TMPVAR2]])58; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 859; CHECK-NEXT: ret <8 x i8> [[TMPVAR3]]60;61 %tmpvar1 = load <8 x i8>, ptr %A62 %tmpvar2 = load <8 x i8>, ptr %B63 %tmpvar3 = call <8 x i8> @llvm.aarch64.neon.smax.v8i8(<8 x i8> %tmpvar1, <8 x i8> %tmpvar2)64 ret <8 x i8> %tmpvar365}66 67define <16 x i8> @smax_16b(ptr %A, ptr %B) nounwind #0 {68; CHECK-LABEL: define <16 x i8> @smax_16b(69; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {70; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 871; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 872; CHECK-NEXT: call void @llvm.donothing()73; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 074; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]75; CHECK: [[BB3]]:76; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]77; CHECK-NEXT: unreachable78; CHECK: [[BB4]]:79; CHECK-NEXT: [[TMPVAR1:%.*]] = load <16 x i8>, ptr [[A]], align 1680; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i6481; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 19351404648857682; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr83; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP7]], align 1684; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 085; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]86; CHECK: [[BB8]]:87; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]88; CHECK-NEXT: unreachable89; CHECK: [[BB9]]:90; CHECK-NEXT: [[TMPVAR2:%.*]] = load <16 x i8>, ptr [[B]], align 1691; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i6492; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 19351404648857693; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr94; CHECK-NEXT: [[_MSLD1:%.*]] = load <16 x i8>, ptr [[TMP12]], align 1695; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[_MSLD]], [[_MSLD1]]96; CHECK-NEXT: [[TMPVAR3:%.*]] = call <16 x i8> @llvm.aarch64.neon.smax.v16i8(<16 x i8> [[TMPVAR1]], <16 x i8> [[TMPVAR2]])97; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 898; CHECK-NEXT: ret <16 x i8> [[TMPVAR3]]99;100 %tmpvar1 = load <16 x i8>, ptr %A101 %tmpvar2 = load <16 x i8>, ptr %B102 %tmpvar3 = call <16 x i8> @llvm.aarch64.neon.smax.v16i8(<16 x i8> %tmpvar1, <16 x i8> %tmpvar2)103 ret <16 x i8> %tmpvar3104}105 106define <4 x i16> @smax_4h(ptr %A, ptr %B) nounwind #0 {107; CHECK-LABEL: define <4 x i16> @smax_4h(108; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {109; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8110; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8111; CHECK-NEXT: call void @llvm.donothing()112; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0113; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]114; CHECK: [[BB3]]:115; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]116; CHECK-NEXT: unreachable117; CHECK: [[BB4]]:118; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i16>, ptr [[A]], align 8119; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64120; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576121; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr122; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 8123; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0124; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]125; CHECK: [[BB8]]:126; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]127; CHECK-NEXT: unreachable128; CHECK: [[BB9]]:129; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i16>, ptr [[B]], align 8130; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64131; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576132; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr133; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 8134; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[_MSLD]], [[_MSLD1]]135; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i16> @llvm.aarch64.neon.smax.v4i16(<4 x i16> [[TMPVAR1]], <4 x i16> [[TMPVAR2]])136; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8137; CHECK-NEXT: ret <4 x i16> [[TMPVAR3]]138;139 %tmpvar1 = load <4 x i16>, ptr %A140 %tmpvar2 = load <4 x i16>, ptr %B141 %tmpvar3 = call <4 x i16> @llvm.aarch64.neon.smax.v4i16(<4 x i16> %tmpvar1, <4 x i16> %tmpvar2)142 ret <4 x i16> %tmpvar3143}144 145define <8 x i16> @smax_8h(ptr %A, ptr %B) nounwind #0 {146; CHECK-LABEL: define <8 x i16> @smax_8h(147; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {148; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8149; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8150; CHECK-NEXT: call void @llvm.donothing()151; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0152; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]153; CHECK: [[BB3]]:154; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]155; CHECK-NEXT: unreachable156; CHECK: [[BB4]]:157; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i16>, ptr [[A]], align 16158; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64159; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576160; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr161; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 16162; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0163; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]164; CHECK: [[BB8]]:165; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]166; CHECK-NEXT: unreachable167; CHECK: [[BB9]]:168; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i16>, ptr [[B]], align 16169; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64170; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576171; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr172; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 16173; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[_MSLD]], [[_MSLD1]]174; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i16> @llvm.aarch64.neon.smax.v8i16(<8 x i16> [[TMPVAR1]], <8 x i16> [[TMPVAR2]])175; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8176; CHECK-NEXT: ret <8 x i16> [[TMPVAR3]]177;178 %tmpvar1 = load <8 x i16>, ptr %A179 %tmpvar2 = load <8 x i16>, ptr %B180 %tmpvar3 = call <8 x i16> @llvm.aarch64.neon.smax.v8i16(<8 x i16> %tmpvar1, <8 x i16> %tmpvar2)181 ret <8 x i16> %tmpvar3182}183 184define <2 x i32> @smax_2s(ptr %A, ptr %B) nounwind #0 {185; CHECK-LABEL: define <2 x i32> @smax_2s(186; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {187; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8188; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8189; CHECK-NEXT: call void @llvm.donothing()190; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0191; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]192; CHECK: [[BB3]]:193; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]194; CHECK-NEXT: unreachable195; CHECK: [[BB4]]:196; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i32>, ptr [[A]], align 8197; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64198; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576199; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr200; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 8201; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0202; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]203; CHECK: [[BB8]]:204; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]205; CHECK-NEXT: unreachable206; CHECK: [[BB9]]:207; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x i32>, ptr [[B]], align 8208; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64209; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576210; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr211; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 8212; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[_MSLD]], [[_MSLD1]]213; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i32> @llvm.aarch64.neon.smax.v2i32(<2 x i32> [[TMPVAR1]], <2 x i32> [[TMPVAR2]])214; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8215; CHECK-NEXT: ret <2 x i32> [[TMPVAR3]]216;217 %tmpvar1 = load <2 x i32>, ptr %A218 %tmpvar2 = load <2 x i32>, ptr %B219 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.smax.v2i32(<2 x i32> %tmpvar1, <2 x i32> %tmpvar2)220 ret <2 x i32> %tmpvar3221}222 223define <4 x i32> @smax_4s(ptr %A, ptr %B) nounwind #0 {224; CHECK-LABEL: define <4 x i32> @smax_4s(225; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {226; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8227; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8228; CHECK-NEXT: call void @llvm.donothing()229; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0230; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]231; CHECK: [[BB3]]:232; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]233; CHECK-NEXT: unreachable234; CHECK: [[BB4]]:235; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i32>, ptr [[A]], align 16236; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64237; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576238; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr239; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 16240; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0241; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]242; CHECK: [[BB8]]:243; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]244; CHECK-NEXT: unreachable245; CHECK: [[BB9]]:246; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i32>, ptr [[B]], align 16247; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64248; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576249; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr250; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 16251; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[_MSLD]], [[_MSLD1]]252; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i32> @llvm.aarch64.neon.smax.v4i32(<4 x i32> [[TMPVAR1]], <4 x i32> [[TMPVAR2]])253; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8254; CHECK-NEXT: ret <4 x i32> [[TMPVAR3]]255;256 %tmpvar1 = load <4 x i32>, ptr %A257 %tmpvar2 = load <4 x i32>, ptr %B258 %tmpvar3 = call <4 x i32> @llvm.aarch64.neon.smax.v4i32(<4 x i32> %tmpvar1, <4 x i32> %tmpvar2)259 ret <4 x i32> %tmpvar3260}261 262declare <8 x i8> @llvm.aarch64.neon.smax.v8i8(<8 x i8>, <8 x i8>) nounwind readnone263declare <16 x i8> @llvm.aarch64.neon.smax.v16i8(<16 x i8>, <16 x i8>) nounwind readnone264declare <4 x i16> @llvm.aarch64.neon.smax.v4i16(<4 x i16>, <4 x i16>) nounwind readnone265declare <8 x i16> @llvm.aarch64.neon.smax.v8i16(<8 x i16>, <8 x i16>) nounwind readnone266declare <2 x i32> @llvm.aarch64.neon.smax.v2i32(<2 x i32>, <2 x i32>) nounwind readnone267declare <4 x i32> @llvm.aarch64.neon.smax.v4i32(<4 x i32>, <4 x i32>) nounwind readnone268 269define <8 x i8> @umax_8b(ptr %A, ptr %B) nounwind #0 {270; CHECK-LABEL: define <8 x i8> @umax_8b(271; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {272; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8273; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8274; CHECK-NEXT: call void @llvm.donothing()275; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0276; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]277; CHECK: [[BB3]]:278; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]279; CHECK-NEXT: unreachable280; CHECK: [[BB4]]:281; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i8>, ptr [[A]], align 8282; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64283; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576284; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr285; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 8286; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0287; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]288; CHECK: [[BB8]]:289; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]290; CHECK-NEXT: unreachable291; CHECK: [[BB9]]:292; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i8>, ptr [[B]], align 8293; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64294; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576295; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr296; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP12]], align 8297; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i8> [[_MSLD]], [[_MSLD1]]298; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i8> @llvm.aarch64.neon.umax.v8i8(<8 x i8> [[TMPVAR1]], <8 x i8> [[TMPVAR2]])299; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8300; CHECK-NEXT: ret <8 x i8> [[TMPVAR3]]301;302 %tmpvar1 = load <8 x i8>, ptr %A303 %tmpvar2 = load <8 x i8>, ptr %B304 %tmpvar3 = call <8 x i8> @llvm.aarch64.neon.umax.v8i8(<8 x i8> %tmpvar1, <8 x i8> %tmpvar2)305 ret <8 x i8> %tmpvar3306}307 308define <16 x i8> @umax_16b(ptr %A, ptr %B) nounwind #0 {309; CHECK-LABEL: define <16 x i8> @umax_16b(310; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {311; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8312; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8313; CHECK-NEXT: call void @llvm.donothing()314; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0315; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]316; CHECK: [[BB3]]:317; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]318; CHECK-NEXT: unreachable319; CHECK: [[BB4]]:320; CHECK-NEXT: [[TMPVAR1:%.*]] = load <16 x i8>, ptr [[A]], align 16321; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64322; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576323; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr324; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP7]], align 16325; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0326; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]327; CHECK: [[BB8]]:328; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]329; CHECK-NEXT: unreachable330; CHECK: [[BB9]]:331; CHECK-NEXT: [[TMPVAR2:%.*]] = load <16 x i8>, ptr [[B]], align 16332; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64333; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576334; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr335; CHECK-NEXT: [[_MSLD1:%.*]] = load <16 x i8>, ptr [[TMP12]], align 16336; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[_MSLD]], [[_MSLD1]]337; CHECK-NEXT: [[TMPVAR3:%.*]] = call <16 x i8> @llvm.aarch64.neon.umax.v16i8(<16 x i8> [[TMPVAR1]], <16 x i8> [[TMPVAR2]])338; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8339; CHECK-NEXT: ret <16 x i8> [[TMPVAR3]]340;341 %tmpvar1 = load <16 x i8>, ptr %A342 %tmpvar2 = load <16 x i8>, ptr %B343 %tmpvar3 = call <16 x i8> @llvm.aarch64.neon.umax.v16i8(<16 x i8> %tmpvar1, <16 x i8> %tmpvar2)344 ret <16 x i8> %tmpvar3345}346 347define <4 x i16> @umax_4h(ptr %A, ptr %B) nounwind #0 {348; CHECK-LABEL: define <4 x i16> @umax_4h(349; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {350; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8351; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8352; CHECK-NEXT: call void @llvm.donothing()353; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0354; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]355; CHECK: [[BB3]]:356; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]357; CHECK-NEXT: unreachable358; CHECK: [[BB4]]:359; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i16>, ptr [[A]], align 8360; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64361; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576362; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr363; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 8364; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0365; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]366; CHECK: [[BB8]]:367; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]368; CHECK-NEXT: unreachable369; CHECK: [[BB9]]:370; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i16>, ptr [[B]], align 8371; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64372; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576373; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr374; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 8375; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[_MSLD]], [[_MSLD1]]376; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i16> @llvm.aarch64.neon.umax.v4i16(<4 x i16> [[TMPVAR1]], <4 x i16> [[TMPVAR2]])377; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8378; CHECK-NEXT: ret <4 x i16> [[TMPVAR3]]379;380 %tmpvar1 = load <4 x i16>, ptr %A381 %tmpvar2 = load <4 x i16>, ptr %B382 %tmpvar3 = call <4 x i16> @llvm.aarch64.neon.umax.v4i16(<4 x i16> %tmpvar1, <4 x i16> %tmpvar2)383 ret <4 x i16> %tmpvar3384}385 386define <8 x i16> @umax_8h(ptr %A, ptr %B) nounwind #0 {387; CHECK-LABEL: define <8 x i16> @umax_8h(388; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {389; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8390; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8391; CHECK-NEXT: call void @llvm.donothing()392; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0393; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]394; CHECK: [[BB3]]:395; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]396; CHECK-NEXT: unreachable397; CHECK: [[BB4]]:398; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i16>, ptr [[A]], align 16399; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64400; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576401; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr402; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 16403; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0404; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]405; CHECK: [[BB8]]:406; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]407; CHECK-NEXT: unreachable408; CHECK: [[BB9]]:409; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i16>, ptr [[B]], align 16410; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64411; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576412; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr413; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 16414; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[_MSLD]], [[_MSLD1]]415; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i16> @llvm.aarch64.neon.umax.v8i16(<8 x i16> [[TMPVAR1]], <8 x i16> [[TMPVAR2]])416; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8417; CHECK-NEXT: ret <8 x i16> [[TMPVAR3]]418;419 %tmpvar1 = load <8 x i16>, ptr %A420 %tmpvar2 = load <8 x i16>, ptr %B421 %tmpvar3 = call <8 x i16> @llvm.aarch64.neon.umax.v8i16(<8 x i16> %tmpvar1, <8 x i16> %tmpvar2)422 ret <8 x i16> %tmpvar3423}424 425define <2 x i32> @umax_2s(ptr %A, ptr %B) nounwind #0 {426; CHECK-LABEL: define <2 x i32> @umax_2s(427; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {428; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8429; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8430; CHECK-NEXT: call void @llvm.donothing()431; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0432; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]433; CHECK: [[BB3]]:434; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]435; CHECK-NEXT: unreachable436; CHECK: [[BB4]]:437; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i32>, ptr [[A]], align 8438; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64439; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576440; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr441; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 8442; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0443; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]444; CHECK: [[BB8]]:445; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]446; CHECK-NEXT: unreachable447; CHECK: [[BB9]]:448; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x i32>, ptr [[B]], align 8449; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64450; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576451; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr452; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 8453; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[_MSLD]], [[_MSLD1]]454; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i32> @llvm.aarch64.neon.umax.v2i32(<2 x i32> [[TMPVAR1]], <2 x i32> [[TMPVAR2]])455; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8456; CHECK-NEXT: ret <2 x i32> [[TMPVAR3]]457;458 %tmpvar1 = load <2 x i32>, ptr %A459 %tmpvar2 = load <2 x i32>, ptr %B460 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.umax.v2i32(<2 x i32> %tmpvar1, <2 x i32> %tmpvar2)461 ret <2 x i32> %tmpvar3462}463 464define <4 x i32> @umax_4s(ptr %A, ptr %B) nounwind #0 {465; CHECK-LABEL: define <4 x i32> @umax_4s(466; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {467; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8468; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8469; CHECK-NEXT: call void @llvm.donothing()470; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0471; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]472; CHECK: [[BB3]]:473; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]474; CHECK-NEXT: unreachable475; CHECK: [[BB4]]:476; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i32>, ptr [[A]], align 16477; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64478; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576479; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr480; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 16481; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0482; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]483; CHECK: [[BB8]]:484; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]485; CHECK-NEXT: unreachable486; CHECK: [[BB9]]:487; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i32>, ptr [[B]], align 16488; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64489; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576490; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr491; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 16492; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[_MSLD]], [[_MSLD1]]493; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i32> @llvm.aarch64.neon.umax.v4i32(<4 x i32> [[TMPVAR1]], <4 x i32> [[TMPVAR2]])494; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8495; CHECK-NEXT: ret <4 x i32> [[TMPVAR3]]496;497 %tmpvar1 = load <4 x i32>, ptr %A498 %tmpvar2 = load <4 x i32>, ptr %B499 %tmpvar3 = call <4 x i32> @llvm.aarch64.neon.umax.v4i32(<4 x i32> %tmpvar1, <4 x i32> %tmpvar2)500 ret <4 x i32> %tmpvar3501}502 503declare <8 x i8> @llvm.aarch64.neon.umax.v8i8(<8 x i8>, <8 x i8>) nounwind readnone504declare <16 x i8> @llvm.aarch64.neon.umax.v16i8(<16 x i8>, <16 x i8>) nounwind readnone505declare <4 x i16> @llvm.aarch64.neon.umax.v4i16(<4 x i16>, <4 x i16>) nounwind readnone506declare <8 x i16> @llvm.aarch64.neon.umax.v8i16(<8 x i16>, <8 x i16>) nounwind readnone507declare <2 x i32> @llvm.aarch64.neon.umax.v2i32(<2 x i32>, <2 x i32>) nounwind readnone508declare <4 x i32> @llvm.aarch64.neon.umax.v4i32(<4 x i32>, <4 x i32>) nounwind readnone509 510define <8 x i8> @smin_8b(ptr %A, ptr %B) nounwind #0 {511; CHECK-LABEL: define <8 x i8> @smin_8b(512; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {513; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8514; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8515; CHECK-NEXT: call void @llvm.donothing()516; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0517; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]518; CHECK: [[BB3]]:519; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]520; CHECK-NEXT: unreachable521; CHECK: [[BB4]]:522; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i8>, ptr [[A]], align 8523; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64524; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576525; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr526; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 8527; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0528; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]529; CHECK: [[BB8]]:530; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]531; CHECK-NEXT: unreachable532; CHECK: [[BB9]]:533; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i8>, ptr [[B]], align 8534; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64535; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576536; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr537; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP12]], align 8538; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i8> [[_MSLD]], [[_MSLD1]]539; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i8> @llvm.aarch64.neon.smin.v8i8(<8 x i8> [[TMPVAR1]], <8 x i8> [[TMPVAR2]])540; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8541; CHECK-NEXT: ret <8 x i8> [[TMPVAR3]]542;543 %tmpvar1 = load <8 x i8>, ptr %A544 %tmpvar2 = load <8 x i8>, ptr %B545 %tmpvar3 = call <8 x i8> @llvm.aarch64.neon.smin.v8i8(<8 x i8> %tmpvar1, <8 x i8> %tmpvar2)546 ret <8 x i8> %tmpvar3547}548 549define <16 x i8> @smin_16b(ptr %A, ptr %B) nounwind #0 {550; CHECK-LABEL: define <16 x i8> @smin_16b(551; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {552; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8553; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8554; CHECK-NEXT: call void @llvm.donothing()555; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0556; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]557; CHECK: [[BB3]]:558; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]559; CHECK-NEXT: unreachable560; CHECK: [[BB4]]:561; CHECK-NEXT: [[TMPVAR1:%.*]] = load <16 x i8>, ptr [[A]], align 16562; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64563; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576564; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr565; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP7]], align 16566; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0567; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]568; CHECK: [[BB8]]:569; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]570; CHECK-NEXT: unreachable571; CHECK: [[BB9]]:572; CHECK-NEXT: [[TMPVAR2:%.*]] = load <16 x i8>, ptr [[B]], align 16573; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64574; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576575; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr576; CHECK-NEXT: [[_MSLD1:%.*]] = load <16 x i8>, ptr [[TMP12]], align 16577; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[_MSLD]], [[_MSLD1]]578; CHECK-NEXT: [[TMPVAR3:%.*]] = call <16 x i8> @llvm.aarch64.neon.smin.v16i8(<16 x i8> [[TMPVAR1]], <16 x i8> [[TMPVAR2]])579; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8580; CHECK-NEXT: ret <16 x i8> [[TMPVAR3]]581;582 %tmpvar1 = load <16 x i8>, ptr %A583 %tmpvar2 = load <16 x i8>, ptr %B584 %tmpvar3 = call <16 x i8> @llvm.aarch64.neon.smin.v16i8(<16 x i8> %tmpvar1, <16 x i8> %tmpvar2)585 ret <16 x i8> %tmpvar3586}587 588define <4 x i16> @smin_4h(ptr %A, ptr %B) nounwind #0 {589; CHECK-LABEL: define <4 x i16> @smin_4h(590; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {591; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8592; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8593; CHECK-NEXT: call void @llvm.donothing()594; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0595; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]596; CHECK: [[BB3]]:597; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]598; CHECK-NEXT: unreachable599; CHECK: [[BB4]]:600; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i16>, ptr [[A]], align 8601; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64602; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576603; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr604; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 8605; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0606; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]607; CHECK: [[BB8]]:608; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]609; CHECK-NEXT: unreachable610; CHECK: [[BB9]]:611; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i16>, ptr [[B]], align 8612; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64613; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576614; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr615; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 8616; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[_MSLD]], [[_MSLD1]]617; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i16> @llvm.aarch64.neon.smin.v4i16(<4 x i16> [[TMPVAR1]], <4 x i16> [[TMPVAR2]])618; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8619; CHECK-NEXT: ret <4 x i16> [[TMPVAR3]]620;621 %tmpvar1 = load <4 x i16>, ptr %A622 %tmpvar2 = load <4 x i16>, ptr %B623 %tmpvar3 = call <4 x i16> @llvm.aarch64.neon.smin.v4i16(<4 x i16> %tmpvar1, <4 x i16> %tmpvar2)624 ret <4 x i16> %tmpvar3625}626 627define <8 x i16> @smin_8h(ptr %A, ptr %B) nounwind #0 {628; CHECK-LABEL: define <8 x i16> @smin_8h(629; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {630; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8631; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8632; CHECK-NEXT: call void @llvm.donothing()633; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0634; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]635; CHECK: [[BB3]]:636; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]637; CHECK-NEXT: unreachable638; CHECK: [[BB4]]:639; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i16>, ptr [[A]], align 16640; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64641; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576642; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr643; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 16644; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0645; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]646; CHECK: [[BB8]]:647; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]648; CHECK-NEXT: unreachable649; CHECK: [[BB9]]:650; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i16>, ptr [[B]], align 16651; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64652; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576653; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr654; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 16655; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[_MSLD]], [[_MSLD1]]656; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i16> @llvm.aarch64.neon.smin.v8i16(<8 x i16> [[TMPVAR1]], <8 x i16> [[TMPVAR2]])657; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8658; CHECK-NEXT: ret <8 x i16> [[TMPVAR3]]659;660 %tmpvar1 = load <8 x i16>, ptr %A661 %tmpvar2 = load <8 x i16>, ptr %B662 %tmpvar3 = call <8 x i16> @llvm.aarch64.neon.smin.v8i16(<8 x i16> %tmpvar1, <8 x i16> %tmpvar2)663 ret <8 x i16> %tmpvar3664}665 666define <2 x i32> @smin_2s(ptr %A, ptr %B) nounwind #0 {667; CHECK-LABEL: define <2 x i32> @smin_2s(668; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {669; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8670; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8671; CHECK-NEXT: call void @llvm.donothing()672; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0673; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]674; CHECK: [[BB3]]:675; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]676; CHECK-NEXT: unreachable677; CHECK: [[BB4]]:678; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i32>, ptr [[A]], align 8679; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64680; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576681; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr682; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 8683; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0684; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]685; CHECK: [[BB8]]:686; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]687; CHECK-NEXT: unreachable688; CHECK: [[BB9]]:689; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x i32>, ptr [[B]], align 8690; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64691; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576692; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr693; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 8694; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[_MSLD]], [[_MSLD1]]695; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i32> @llvm.aarch64.neon.smin.v2i32(<2 x i32> [[TMPVAR1]], <2 x i32> [[TMPVAR2]])696; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8697; CHECK-NEXT: ret <2 x i32> [[TMPVAR3]]698;699 %tmpvar1 = load <2 x i32>, ptr %A700 %tmpvar2 = load <2 x i32>, ptr %B701 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.smin.v2i32(<2 x i32> %tmpvar1, <2 x i32> %tmpvar2)702 ret <2 x i32> %tmpvar3703}704 705define <4 x i32> @smin_4s(ptr %A, ptr %B) nounwind #0 {706; CHECK-LABEL: define <4 x i32> @smin_4s(707; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {708; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8709; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8710; CHECK-NEXT: call void @llvm.donothing()711; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0712; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]713; CHECK: [[BB3]]:714; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]715; CHECK-NEXT: unreachable716; CHECK: [[BB4]]:717; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i32>, ptr [[A]], align 16718; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64719; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576720; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr721; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 16722; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0723; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]724; CHECK: [[BB8]]:725; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]726; CHECK-NEXT: unreachable727; CHECK: [[BB9]]:728; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i32>, ptr [[B]], align 16729; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64730; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576731; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr732; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 16733; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[_MSLD]], [[_MSLD1]]734; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i32> @llvm.aarch64.neon.smin.v4i32(<4 x i32> [[TMPVAR1]], <4 x i32> [[TMPVAR2]])735; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8736; CHECK-NEXT: ret <4 x i32> [[TMPVAR3]]737;738 %tmpvar1 = load <4 x i32>, ptr %A739 %tmpvar2 = load <4 x i32>, ptr %B740 %tmpvar3 = call <4 x i32> @llvm.aarch64.neon.smin.v4i32(<4 x i32> %tmpvar1, <4 x i32> %tmpvar2)741 ret <4 x i32> %tmpvar3742}743 744declare <8 x i8> @llvm.aarch64.neon.smin.v8i8(<8 x i8>, <8 x i8>) nounwind readnone745declare <16 x i8> @llvm.aarch64.neon.smin.v16i8(<16 x i8>, <16 x i8>) nounwind readnone746declare <4 x i16> @llvm.aarch64.neon.smin.v4i16(<4 x i16>, <4 x i16>) nounwind readnone747declare <8 x i16> @llvm.aarch64.neon.smin.v8i16(<8 x i16>, <8 x i16>) nounwind readnone748declare <2 x i32> @llvm.aarch64.neon.smin.v2i32(<2 x i32>, <2 x i32>) nounwind readnone749declare <4 x i32> @llvm.aarch64.neon.smin.v4i32(<4 x i32>, <4 x i32>) nounwind readnone750 751define <8 x i8> @umin_8b(ptr %A, ptr %B) nounwind #0 {752; CHECK-LABEL: define <8 x i8> @umin_8b(753; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {754; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8755; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8756; CHECK-NEXT: call void @llvm.donothing()757; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0758; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]759; CHECK: [[BB3]]:760; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]761; CHECK-NEXT: unreachable762; CHECK: [[BB4]]:763; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i8>, ptr [[A]], align 8764; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64765; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576766; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr767; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 8768; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0769; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]770; CHECK: [[BB8]]:771; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]772; CHECK-NEXT: unreachable773; CHECK: [[BB9]]:774; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i8>, ptr [[B]], align 8775; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64776; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576777; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr778; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP12]], align 8779; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i8> [[_MSLD]], [[_MSLD1]]780; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i8> @llvm.aarch64.neon.umin.v8i8(<8 x i8> [[TMPVAR1]], <8 x i8> [[TMPVAR2]])781; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8782; CHECK-NEXT: ret <8 x i8> [[TMPVAR3]]783;784 %tmpvar1 = load <8 x i8>, ptr %A785 %tmpvar2 = load <8 x i8>, ptr %B786 %tmpvar3 = call <8 x i8> @llvm.aarch64.neon.umin.v8i8(<8 x i8> %tmpvar1, <8 x i8> %tmpvar2)787 ret <8 x i8> %tmpvar3788}789 790define <16 x i8> @umin_16b(ptr %A, ptr %B) nounwind #0 {791; CHECK-LABEL: define <16 x i8> @umin_16b(792; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {793; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8794; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8795; CHECK-NEXT: call void @llvm.donothing()796; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0797; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]798; CHECK: [[BB3]]:799; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]800; CHECK-NEXT: unreachable801; CHECK: [[BB4]]:802; CHECK-NEXT: [[TMPVAR1:%.*]] = load <16 x i8>, ptr [[A]], align 16803; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64804; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576805; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr806; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP7]], align 16807; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0808; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]809; CHECK: [[BB8]]:810; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]811; CHECK-NEXT: unreachable812; CHECK: [[BB9]]:813; CHECK-NEXT: [[TMPVAR2:%.*]] = load <16 x i8>, ptr [[B]], align 16814; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64815; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576816; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr817; CHECK-NEXT: [[_MSLD1:%.*]] = load <16 x i8>, ptr [[TMP12]], align 16818; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[_MSLD]], [[_MSLD1]]819; CHECK-NEXT: [[TMPVAR3:%.*]] = call <16 x i8> @llvm.aarch64.neon.umin.v16i8(<16 x i8> [[TMPVAR1]], <16 x i8> [[TMPVAR2]])820; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8821; CHECK-NEXT: ret <16 x i8> [[TMPVAR3]]822;823 %tmpvar1 = load <16 x i8>, ptr %A824 %tmpvar2 = load <16 x i8>, ptr %B825 %tmpvar3 = call <16 x i8> @llvm.aarch64.neon.umin.v16i8(<16 x i8> %tmpvar1, <16 x i8> %tmpvar2)826 ret <16 x i8> %tmpvar3827}828 829define <4 x i16> @umin_4h(ptr %A, ptr %B) nounwind #0 {830; CHECK-LABEL: define <4 x i16> @umin_4h(831; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {832; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8833; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8834; CHECK-NEXT: call void @llvm.donothing()835; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0836; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]837; CHECK: [[BB3]]:838; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]839; CHECK-NEXT: unreachable840; CHECK: [[BB4]]:841; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i16>, ptr [[A]], align 8842; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64843; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576844; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr845; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 8846; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0847; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]848; CHECK: [[BB8]]:849; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]850; CHECK-NEXT: unreachable851; CHECK: [[BB9]]:852; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i16>, ptr [[B]], align 8853; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64854; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576855; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr856; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 8857; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[_MSLD]], [[_MSLD1]]858; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i16> @llvm.aarch64.neon.umin.v4i16(<4 x i16> [[TMPVAR1]], <4 x i16> [[TMPVAR2]])859; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8860; CHECK-NEXT: ret <4 x i16> [[TMPVAR3]]861;862 %tmpvar1 = load <4 x i16>, ptr %A863 %tmpvar2 = load <4 x i16>, ptr %B864 %tmpvar3 = call <4 x i16> @llvm.aarch64.neon.umin.v4i16(<4 x i16> %tmpvar1, <4 x i16> %tmpvar2)865 ret <4 x i16> %tmpvar3866}867 868define <8 x i16> @umin_8h(ptr %A, ptr %B) nounwind #0 {869; CHECK-LABEL: define <8 x i16> @umin_8h(870; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {871; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8872; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8873; CHECK-NEXT: call void @llvm.donothing()874; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0875; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]876; CHECK: [[BB3]]:877; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]878; CHECK-NEXT: unreachable879; CHECK: [[BB4]]:880; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i16>, ptr [[A]], align 16881; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64882; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576883; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr884; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 16885; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0886; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]887; CHECK: [[BB8]]:888; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]889; CHECK-NEXT: unreachable890; CHECK: [[BB9]]:891; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i16>, ptr [[B]], align 16892; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64893; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576894; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr895; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 16896; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[_MSLD]], [[_MSLD1]]897; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i16> @llvm.aarch64.neon.umin.v8i16(<8 x i16> [[TMPVAR1]], <8 x i16> [[TMPVAR2]])898; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8899; CHECK-NEXT: ret <8 x i16> [[TMPVAR3]]900;901 %tmpvar1 = load <8 x i16>, ptr %A902 %tmpvar2 = load <8 x i16>, ptr %B903 %tmpvar3 = call <8 x i16> @llvm.aarch64.neon.umin.v8i16(<8 x i16> %tmpvar1, <8 x i16> %tmpvar2)904 ret <8 x i16> %tmpvar3905}906 907define <2 x i32> @umin_2s(ptr %A, ptr %B) nounwind #0 {908; CHECK-LABEL: define <2 x i32> @umin_2s(909; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {910; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8911; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8912; CHECK-NEXT: call void @llvm.donothing()913; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0914; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]915; CHECK: [[BB3]]:916; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]917; CHECK-NEXT: unreachable918; CHECK: [[BB4]]:919; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i32>, ptr [[A]], align 8920; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64921; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576922; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr923; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 8924; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0925; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]926; CHECK: [[BB8]]:927; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]928; CHECK-NEXT: unreachable929; CHECK: [[BB9]]:930; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x i32>, ptr [[B]], align 8931; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64932; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576933; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr934; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 8935; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[_MSLD]], [[_MSLD1]]936; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i32> @llvm.aarch64.neon.umin.v2i32(<2 x i32> [[TMPVAR1]], <2 x i32> [[TMPVAR2]])937; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8938; CHECK-NEXT: ret <2 x i32> [[TMPVAR3]]939;940 %tmpvar1 = load <2 x i32>, ptr %A941 %tmpvar2 = load <2 x i32>, ptr %B942 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.umin.v2i32(<2 x i32> %tmpvar1, <2 x i32> %tmpvar2)943 ret <2 x i32> %tmpvar3944}945 946define <4 x i32> @umin_4s(ptr %A, ptr %B) nounwind #0 {947; CHECK-LABEL: define <4 x i32> @umin_4s(948; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {949; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8950; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8951; CHECK-NEXT: call void @llvm.donothing()952; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0953; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]954; CHECK: [[BB3]]:955; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]956; CHECK-NEXT: unreachable957; CHECK: [[BB4]]:958; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i32>, ptr [[A]], align 16959; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64960; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576961; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr962; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 16963; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0964; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]965; CHECK: [[BB8]]:966; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]967; CHECK-NEXT: unreachable968; CHECK: [[BB9]]:969; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i32>, ptr [[B]], align 16970; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64971; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576972; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr973; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 16974; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[_MSLD]], [[_MSLD1]]975; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i32> @llvm.aarch64.neon.umin.v4i32(<4 x i32> [[TMPVAR1]], <4 x i32> [[TMPVAR2]])976; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8977; CHECK-NEXT: ret <4 x i32> [[TMPVAR3]]978;979 %tmpvar1 = load <4 x i32>, ptr %A980 %tmpvar2 = load <4 x i32>, ptr %B981 %tmpvar3 = call <4 x i32> @llvm.aarch64.neon.umin.v4i32(<4 x i32> %tmpvar1, <4 x i32> %tmpvar2)982 ret <4 x i32> %tmpvar3983}984 985declare <8 x i8> @llvm.aarch64.neon.umin.v8i8(<8 x i8>, <8 x i8>) nounwind readnone986declare <16 x i8> @llvm.aarch64.neon.umin.v16i8(<16 x i8>, <16 x i8>) nounwind readnone987declare <4 x i16> @llvm.aarch64.neon.umin.v4i16(<4 x i16>, <4 x i16>) nounwind readnone988declare <8 x i16> @llvm.aarch64.neon.umin.v8i16(<8 x i16>, <8 x i16>) nounwind readnone989declare <2 x i32> @llvm.aarch64.neon.umin.v2i32(<2 x i32>, <2 x i32>) nounwind readnone990declare <4 x i32> @llvm.aarch64.neon.umin.v4i32(<4 x i32>, <4 x i32>) nounwind readnone991 992 993define <8 x i8> @smaxp_8b(ptr %A, ptr %B) nounwind #0 {994; CHECK-LABEL: define <8 x i8> @smaxp_8b(995; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {996; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8997; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8998; CHECK-NEXT: call void @llvm.donothing()999; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01000; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]1001; CHECK: [[BB3]]:1002; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1003; CHECK-NEXT: unreachable1004; CHECK: [[BB4]]:1005; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i8>, ptr [[A]], align 81006; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641007; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761008; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1009; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 81010; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01011; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]1012; CHECK: [[BB8]]:1013; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1014; CHECK-NEXT: unreachable1015; CHECK: [[BB9]]:1016; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i8>, ptr [[B]], align 81017; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641018; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761019; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1020; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP12]], align 81021; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <8 x i8> [[_MSLD]], <8 x i8> [[_MSLD1]], <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>1022; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <8 x i8> [[_MSLD]], <8 x i8> [[_MSLD1]], <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>1023; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i8> [[TMP13]], [[TMP14]]1024; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i8> @llvm.aarch64.neon.smaxp.v8i8(<8 x i8> [[TMPVAR1]], <8 x i8> [[TMPVAR2]])1025; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 81026; CHECK-NEXT: ret <8 x i8> [[TMPVAR3]]1027;1028 %tmpvar1 = load <8 x i8>, ptr %A1029 %tmpvar2 = load <8 x i8>, ptr %B1030 %tmpvar3 = call <8 x i8> @llvm.aarch64.neon.smaxp.v8i8(<8 x i8> %tmpvar1, <8 x i8> %tmpvar2)1031 ret <8 x i8> %tmpvar31032}1033 1034define <16 x i8> @smaxp_16b(ptr %A, ptr %B) nounwind #0 {1035; CHECK-LABEL: define <16 x i8> @smaxp_16b(1036; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1037; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81038; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81039; CHECK-NEXT: call void @llvm.donothing()1040; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01041; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]1042; CHECK: [[BB3]]:1043; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1044; CHECK-NEXT: unreachable1045; CHECK: [[BB4]]:1046; CHECK-NEXT: [[TMPVAR1:%.*]] = load <16 x i8>, ptr [[A]], align 161047; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641048; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761049; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1050; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP7]], align 161051; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01052; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]1053; CHECK: [[BB8]]:1054; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1055; CHECK-NEXT: unreachable1056; CHECK: [[BB9]]:1057; CHECK-NEXT: [[TMPVAR2:%.*]] = load <16 x i8>, ptr [[B]], align 161058; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641059; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761060; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1061; CHECK-NEXT: [[_MSLD1:%.*]] = load <16 x i8>, ptr [[TMP12]], align 161062; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <16 x i8> [[_MSLD]], <16 x i8> [[_MSLD1]], <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>1063; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <16 x i8> [[_MSLD]], <16 x i8> [[_MSLD1]], <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>1064; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP13]], [[TMP14]]1065; CHECK-NEXT: [[TMPVAR3:%.*]] = call <16 x i8> @llvm.aarch64.neon.smaxp.v16i8(<16 x i8> [[TMPVAR1]], <16 x i8> [[TMPVAR2]])1066; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 81067; CHECK-NEXT: ret <16 x i8> [[TMPVAR3]]1068;1069 %tmpvar1 = load <16 x i8>, ptr %A1070 %tmpvar2 = load <16 x i8>, ptr %B1071 %tmpvar3 = call <16 x i8> @llvm.aarch64.neon.smaxp.v16i8(<16 x i8> %tmpvar1, <16 x i8> %tmpvar2)1072 ret <16 x i8> %tmpvar31073}1074 1075define <4 x i16> @smaxp_4h(ptr %A, ptr %B) nounwind #0 {1076; CHECK-LABEL: define <4 x i16> @smaxp_4h(1077; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1078; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81079; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81080; CHECK-NEXT: call void @llvm.donothing()1081; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01082; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]1083; CHECK: [[BB3]]:1084; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1085; CHECK-NEXT: unreachable1086; CHECK: [[BB4]]:1087; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i16>, ptr [[A]], align 81088; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641089; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761090; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1091; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 81092; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01093; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]1094; CHECK: [[BB8]]:1095; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1096; CHECK-NEXT: unreachable1097; CHECK: [[BB9]]:1098; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i16>, ptr [[B]], align 81099; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641100; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761101; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1102; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 81103; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <4 x i16> [[_MSLD]], <4 x i16> [[_MSLD1]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>1104; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x i16> [[_MSLD]], <4 x i16> [[_MSLD1]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>1105; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[TMP13]], [[TMP14]]1106; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i16> @llvm.aarch64.neon.smaxp.v4i16(<4 x i16> [[TMPVAR1]], <4 x i16> [[TMPVAR2]])1107; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 81108; CHECK-NEXT: ret <4 x i16> [[TMPVAR3]]1109;1110 %tmpvar1 = load <4 x i16>, ptr %A1111 %tmpvar2 = load <4 x i16>, ptr %B1112 %tmpvar3 = call <4 x i16> @llvm.aarch64.neon.smaxp.v4i16(<4 x i16> %tmpvar1, <4 x i16> %tmpvar2)1113 ret <4 x i16> %tmpvar31114}1115 1116define <8 x i16> @smaxp_8h(ptr %A, ptr %B) nounwind #0 {1117; CHECK-LABEL: define <8 x i16> @smaxp_8h(1118; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1119; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81120; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81121; CHECK-NEXT: call void @llvm.donothing()1122; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01123; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]1124; CHECK: [[BB3]]:1125; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1126; CHECK-NEXT: unreachable1127; CHECK: [[BB4]]:1128; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i16>, ptr [[A]], align 161129; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641130; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761131; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1132; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 161133; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01134; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]1135; CHECK: [[BB8]]:1136; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1137; CHECK-NEXT: unreachable1138; CHECK: [[BB9]]:1139; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i16>, ptr [[B]], align 161140; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641141; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761142; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1143; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 161144; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <8 x i16> [[_MSLD]], <8 x i16> [[_MSLD1]], <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>1145; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <8 x i16> [[_MSLD]], <8 x i16> [[_MSLD1]], <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>1146; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP13]], [[TMP14]]1147; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i16> @llvm.aarch64.neon.smaxp.v8i16(<8 x i16> [[TMPVAR1]], <8 x i16> [[TMPVAR2]])1148; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 81149; CHECK-NEXT: ret <8 x i16> [[TMPVAR3]]1150;1151 %tmpvar1 = load <8 x i16>, ptr %A1152 %tmpvar2 = load <8 x i16>, ptr %B1153 %tmpvar3 = call <8 x i16> @llvm.aarch64.neon.smaxp.v8i16(<8 x i16> %tmpvar1, <8 x i16> %tmpvar2)1154 ret <8 x i16> %tmpvar31155}1156 1157define <2 x i32> @smaxp_2s(ptr %A, ptr %B) nounwind #0 {1158; CHECK-LABEL: define <2 x i32> @smaxp_2s(1159; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1160; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81161; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81162; CHECK-NEXT: call void @llvm.donothing()1163; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01164; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]1165; CHECK: [[BB3]]:1166; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1167; CHECK-NEXT: unreachable1168; CHECK: [[BB4]]:1169; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i32>, ptr [[A]], align 81170; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641171; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761172; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1173; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 81174; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01175; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]1176; CHECK: [[BB8]]:1177; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1178; CHECK-NEXT: unreachable1179; CHECK: [[BB9]]:1180; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x i32>, ptr [[B]], align 81181; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641182; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761183; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1184; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 81185; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <2 x i32> [[_MSLD]], <2 x i32> [[_MSLD1]], <2 x i32> <i32 0, i32 2>1186; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <2 x i32> [[_MSLD]], <2 x i32> [[_MSLD1]], <2 x i32> <i32 1, i32 3>1187; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[TMP13]], [[TMP14]]1188; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i32> @llvm.aarch64.neon.smaxp.v2i32(<2 x i32> [[TMPVAR1]], <2 x i32> [[TMPVAR2]])1189; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 81190; CHECK-NEXT: ret <2 x i32> [[TMPVAR3]]1191;1192 %tmpvar1 = load <2 x i32>, ptr %A1193 %tmpvar2 = load <2 x i32>, ptr %B1194 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.smaxp.v2i32(<2 x i32> %tmpvar1, <2 x i32> %tmpvar2)1195 ret <2 x i32> %tmpvar31196}1197 1198define <4 x i32> @smaxp_4s(ptr %A, ptr %B) nounwind #0 {1199; CHECK-LABEL: define <4 x i32> @smaxp_4s(1200; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1201; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81202; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81203; CHECK-NEXT: call void @llvm.donothing()1204; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01205; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]1206; CHECK: [[BB3]]:1207; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1208; CHECK-NEXT: unreachable1209; CHECK: [[BB4]]:1210; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i32>, ptr [[A]], align 161211; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641212; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761213; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1214; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 161215; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01216; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]1217; CHECK: [[BB8]]:1218; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1219; CHECK-NEXT: unreachable1220; CHECK: [[BB9]]:1221; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i32>, ptr [[B]], align 161222; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641223; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761224; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1225; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 161226; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> [[_MSLD1]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>1227; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> [[_MSLD1]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>1228; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP13]], [[TMP14]]1229; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i32> @llvm.aarch64.neon.smaxp.v4i32(<4 x i32> [[TMPVAR1]], <4 x i32> [[TMPVAR2]])1230; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 81231; CHECK-NEXT: ret <4 x i32> [[TMPVAR3]]1232;1233 %tmpvar1 = load <4 x i32>, ptr %A1234 %tmpvar2 = load <4 x i32>, ptr %B1235 %tmpvar3 = call <4 x i32> @llvm.aarch64.neon.smaxp.v4i32(<4 x i32> %tmpvar1, <4 x i32> %tmpvar2)1236 ret <4 x i32> %tmpvar31237}1238 1239declare <8 x i8> @llvm.aarch64.neon.smaxp.v8i8(<8 x i8>, <8 x i8>) nounwind readnone1240declare <16 x i8> @llvm.aarch64.neon.smaxp.v16i8(<16 x i8>, <16 x i8>) nounwind readnone1241declare <4 x i16> @llvm.aarch64.neon.smaxp.v4i16(<4 x i16>, <4 x i16>) nounwind readnone1242declare <8 x i16> @llvm.aarch64.neon.smaxp.v8i16(<8 x i16>, <8 x i16>) nounwind readnone1243declare <2 x i32> @llvm.aarch64.neon.smaxp.v2i32(<2 x i32>, <2 x i32>) nounwind readnone1244declare <4 x i32> @llvm.aarch64.neon.smaxp.v4i32(<4 x i32>, <4 x i32>) nounwind readnone1245 1246define <8 x i8> @umaxp_8b(ptr %A, ptr %B) nounwind #0 {1247; CHECK-LABEL: define <8 x i8> @umaxp_8b(1248; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1249; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81250; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81251; CHECK-NEXT: call void @llvm.donothing()1252; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01253; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]1254; CHECK: [[BB3]]:1255; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1256; CHECK-NEXT: unreachable1257; CHECK: [[BB4]]:1258; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i8>, ptr [[A]], align 81259; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641260; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761261; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1262; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 81263; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01264; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]1265; CHECK: [[BB8]]:1266; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1267; CHECK-NEXT: unreachable1268; CHECK: [[BB9]]:1269; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i8>, ptr [[B]], align 81270; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641271; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761272; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1273; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP12]], align 81274; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <8 x i8> [[_MSLD]], <8 x i8> [[_MSLD1]], <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>1275; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <8 x i8> [[_MSLD]], <8 x i8> [[_MSLD1]], <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>1276; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i8> [[TMP13]], [[TMP14]]1277; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i8> @llvm.aarch64.neon.umaxp.v8i8(<8 x i8> [[TMPVAR1]], <8 x i8> [[TMPVAR2]])1278; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 81279; CHECK-NEXT: ret <8 x i8> [[TMPVAR3]]1280;1281 %tmpvar1 = load <8 x i8>, ptr %A1282 %tmpvar2 = load <8 x i8>, ptr %B1283 %tmpvar3 = call <8 x i8> @llvm.aarch64.neon.umaxp.v8i8(<8 x i8> %tmpvar1, <8 x i8> %tmpvar2)1284 ret <8 x i8> %tmpvar31285}1286 1287define <16 x i8> @umaxp_16b(ptr %A, ptr %B) nounwind #0 {1288; CHECK-LABEL: define <16 x i8> @umaxp_16b(1289; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1290; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81291; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81292; CHECK-NEXT: call void @llvm.donothing()1293; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01294; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]1295; CHECK: [[BB3]]:1296; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1297; CHECK-NEXT: unreachable1298; CHECK: [[BB4]]:1299; CHECK-NEXT: [[TMPVAR1:%.*]] = load <16 x i8>, ptr [[A]], align 161300; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641301; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761302; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1303; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP7]], align 161304; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01305; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]1306; CHECK: [[BB8]]:1307; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1308; CHECK-NEXT: unreachable1309; CHECK: [[BB9]]:1310; CHECK-NEXT: [[TMPVAR2:%.*]] = load <16 x i8>, ptr [[B]], align 161311; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641312; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761313; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1314; CHECK-NEXT: [[_MSLD1:%.*]] = load <16 x i8>, ptr [[TMP12]], align 161315; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <16 x i8> [[_MSLD]], <16 x i8> [[_MSLD1]], <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>1316; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <16 x i8> [[_MSLD]], <16 x i8> [[_MSLD1]], <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>1317; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP13]], [[TMP14]]1318; CHECK-NEXT: [[TMPVAR3:%.*]] = call <16 x i8> @llvm.aarch64.neon.umaxp.v16i8(<16 x i8> [[TMPVAR1]], <16 x i8> [[TMPVAR2]])1319; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 81320; CHECK-NEXT: ret <16 x i8> [[TMPVAR3]]1321;1322 %tmpvar1 = load <16 x i8>, ptr %A1323 %tmpvar2 = load <16 x i8>, ptr %B1324 %tmpvar3 = call <16 x i8> @llvm.aarch64.neon.umaxp.v16i8(<16 x i8> %tmpvar1, <16 x i8> %tmpvar2)1325 ret <16 x i8> %tmpvar31326}1327 1328define <4 x i16> @umaxp_4h(ptr %A, ptr %B) nounwind #0 {1329; CHECK-LABEL: define <4 x i16> @umaxp_4h(1330; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1331; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81332; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81333; CHECK-NEXT: call void @llvm.donothing()1334; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01335; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]1336; CHECK: [[BB3]]:1337; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1338; CHECK-NEXT: unreachable1339; CHECK: [[BB4]]:1340; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i16>, ptr [[A]], align 81341; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641342; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761343; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1344; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 81345; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01346; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]1347; CHECK: [[BB8]]:1348; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1349; CHECK-NEXT: unreachable1350; CHECK: [[BB9]]:1351; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i16>, ptr [[B]], align 81352; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641353; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761354; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1355; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 81356; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <4 x i16> [[_MSLD]], <4 x i16> [[_MSLD1]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>1357; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x i16> [[_MSLD]], <4 x i16> [[_MSLD1]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>1358; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[TMP13]], [[TMP14]]1359; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i16> @llvm.aarch64.neon.umaxp.v4i16(<4 x i16> [[TMPVAR1]], <4 x i16> [[TMPVAR2]])1360; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 81361; CHECK-NEXT: ret <4 x i16> [[TMPVAR3]]1362;1363 %tmpvar1 = load <4 x i16>, ptr %A1364 %tmpvar2 = load <4 x i16>, ptr %B1365 %tmpvar3 = call <4 x i16> @llvm.aarch64.neon.umaxp.v4i16(<4 x i16> %tmpvar1, <4 x i16> %tmpvar2)1366 ret <4 x i16> %tmpvar31367}1368 1369define <8 x i16> @umaxp_8h(ptr %A, ptr %B) nounwind #0 {1370; CHECK-LABEL: define <8 x i16> @umaxp_8h(1371; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1372; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81373; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81374; CHECK-NEXT: call void @llvm.donothing()1375; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01376; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]1377; CHECK: [[BB3]]:1378; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1379; CHECK-NEXT: unreachable1380; CHECK: [[BB4]]:1381; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i16>, ptr [[A]], align 161382; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641383; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761384; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1385; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 161386; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01387; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]1388; CHECK: [[BB8]]:1389; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1390; CHECK-NEXT: unreachable1391; CHECK: [[BB9]]:1392; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i16>, ptr [[B]], align 161393; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641394; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761395; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1396; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 161397; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <8 x i16> [[_MSLD]], <8 x i16> [[_MSLD1]], <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>1398; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <8 x i16> [[_MSLD]], <8 x i16> [[_MSLD1]], <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>1399; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP13]], [[TMP14]]1400; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i16> @llvm.aarch64.neon.umaxp.v8i16(<8 x i16> [[TMPVAR1]], <8 x i16> [[TMPVAR2]])1401; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 81402; CHECK-NEXT: ret <8 x i16> [[TMPVAR3]]1403;1404 %tmpvar1 = load <8 x i16>, ptr %A1405 %tmpvar2 = load <8 x i16>, ptr %B1406 %tmpvar3 = call <8 x i16> @llvm.aarch64.neon.umaxp.v8i16(<8 x i16> %tmpvar1, <8 x i16> %tmpvar2)1407 ret <8 x i16> %tmpvar31408}1409 1410define <2 x i32> @umaxp_2s(ptr %A, ptr %B) nounwind #0 {1411; CHECK-LABEL: define <2 x i32> @umaxp_2s(1412; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1413; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81414; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81415; CHECK-NEXT: call void @llvm.donothing()1416; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01417; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]1418; CHECK: [[BB3]]:1419; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1420; CHECK-NEXT: unreachable1421; CHECK: [[BB4]]:1422; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i32>, ptr [[A]], align 81423; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641424; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761425; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1426; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 81427; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01428; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]1429; CHECK: [[BB8]]:1430; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1431; CHECK-NEXT: unreachable1432; CHECK: [[BB9]]:1433; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x i32>, ptr [[B]], align 81434; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641435; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761436; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1437; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 81438; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <2 x i32> [[_MSLD]], <2 x i32> [[_MSLD1]], <2 x i32> <i32 0, i32 2>1439; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <2 x i32> [[_MSLD]], <2 x i32> [[_MSLD1]], <2 x i32> <i32 1, i32 3>1440; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[TMP13]], [[TMP14]]1441; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i32> @llvm.aarch64.neon.umaxp.v2i32(<2 x i32> [[TMPVAR1]], <2 x i32> [[TMPVAR2]])1442; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 81443; CHECK-NEXT: ret <2 x i32> [[TMPVAR3]]1444;1445 %tmpvar1 = load <2 x i32>, ptr %A1446 %tmpvar2 = load <2 x i32>, ptr %B1447 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.umaxp.v2i32(<2 x i32> %tmpvar1, <2 x i32> %tmpvar2)1448 ret <2 x i32> %tmpvar31449}1450 1451define <4 x i32> @umaxp_4s(ptr %A, ptr %B) nounwind #0 {1452; CHECK-LABEL: define <4 x i32> @umaxp_4s(1453; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1454; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81455; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81456; CHECK-NEXT: call void @llvm.donothing()1457; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01458; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]1459; CHECK: [[BB3]]:1460; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1461; CHECK-NEXT: unreachable1462; CHECK: [[BB4]]:1463; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i32>, ptr [[A]], align 161464; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641465; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761466; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1467; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 161468; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01469; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]1470; CHECK: [[BB8]]:1471; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1472; CHECK-NEXT: unreachable1473; CHECK: [[BB9]]:1474; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i32>, ptr [[B]], align 161475; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641476; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761477; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1478; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 161479; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> [[_MSLD1]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>1480; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> [[_MSLD1]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>1481; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP13]], [[TMP14]]1482; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i32> @llvm.aarch64.neon.umaxp.v4i32(<4 x i32> [[TMPVAR1]], <4 x i32> [[TMPVAR2]])1483; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 81484; CHECK-NEXT: ret <4 x i32> [[TMPVAR3]]1485;1486 %tmpvar1 = load <4 x i32>, ptr %A1487 %tmpvar2 = load <4 x i32>, ptr %B1488 %tmpvar3 = call <4 x i32> @llvm.aarch64.neon.umaxp.v4i32(<4 x i32> %tmpvar1, <4 x i32> %tmpvar2)1489 ret <4 x i32> %tmpvar31490}1491 1492declare <8 x i8> @llvm.aarch64.neon.umaxp.v8i8(<8 x i8>, <8 x i8>) nounwind readnone1493declare <16 x i8> @llvm.aarch64.neon.umaxp.v16i8(<16 x i8>, <16 x i8>) nounwind readnone1494declare <4 x i16> @llvm.aarch64.neon.umaxp.v4i16(<4 x i16>, <4 x i16>) nounwind readnone1495declare <8 x i16> @llvm.aarch64.neon.umaxp.v8i16(<8 x i16>, <8 x i16>) nounwind readnone1496declare <2 x i32> @llvm.aarch64.neon.umaxp.v2i32(<2 x i32>, <2 x i32>) nounwind readnone1497declare <4 x i32> @llvm.aarch64.neon.umaxp.v4i32(<4 x i32>, <4 x i32>) nounwind readnone1498 1499 1500define <8 x i8> @sminp_8b(ptr %A, ptr %B) nounwind #0 {1501; CHECK-LABEL: define <8 x i8> @sminp_8b(1502; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1503; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81504; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81505; CHECK-NEXT: call void @llvm.donothing()1506; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01507; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]1508; CHECK: [[BB3]]:1509; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1510; CHECK-NEXT: unreachable1511; CHECK: [[BB4]]:1512; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i8>, ptr [[A]], align 81513; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641514; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761515; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1516; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 81517; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01518; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]1519; CHECK: [[BB8]]:1520; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1521; CHECK-NEXT: unreachable1522; CHECK: [[BB9]]:1523; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i8>, ptr [[B]], align 81524; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641525; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761526; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1527; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP12]], align 81528; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <8 x i8> [[_MSLD]], <8 x i8> [[_MSLD1]], <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>1529; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <8 x i8> [[_MSLD]], <8 x i8> [[_MSLD1]], <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>1530; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i8> [[TMP13]], [[TMP14]]1531; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i8> @llvm.aarch64.neon.sminp.v8i8(<8 x i8> [[TMPVAR1]], <8 x i8> [[TMPVAR2]])1532; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 81533; CHECK-NEXT: ret <8 x i8> [[TMPVAR3]]1534;1535 %tmpvar1 = load <8 x i8>, ptr %A1536 %tmpvar2 = load <8 x i8>, ptr %B1537 %tmpvar3 = call <8 x i8> @llvm.aarch64.neon.sminp.v8i8(<8 x i8> %tmpvar1, <8 x i8> %tmpvar2)1538 ret <8 x i8> %tmpvar31539}1540 1541define <16 x i8> @sminp_16b(ptr %A, ptr %B) nounwind #0 {1542; CHECK-LABEL: define <16 x i8> @sminp_16b(1543; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1544; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81545; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81546; CHECK-NEXT: call void @llvm.donothing()1547; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01548; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]1549; CHECK: [[BB3]]:1550; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1551; CHECK-NEXT: unreachable1552; CHECK: [[BB4]]:1553; CHECK-NEXT: [[TMPVAR1:%.*]] = load <16 x i8>, ptr [[A]], align 161554; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641555; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761556; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1557; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP7]], align 161558; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01559; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]1560; CHECK: [[BB8]]:1561; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1562; CHECK-NEXT: unreachable1563; CHECK: [[BB9]]:1564; CHECK-NEXT: [[TMPVAR2:%.*]] = load <16 x i8>, ptr [[B]], align 161565; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641566; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761567; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1568; CHECK-NEXT: [[_MSLD1:%.*]] = load <16 x i8>, ptr [[TMP12]], align 161569; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <16 x i8> [[_MSLD]], <16 x i8> [[_MSLD1]], <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>1570; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <16 x i8> [[_MSLD]], <16 x i8> [[_MSLD1]], <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>1571; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP13]], [[TMP14]]1572; CHECK-NEXT: [[TMPVAR3:%.*]] = call <16 x i8> @llvm.aarch64.neon.sminp.v16i8(<16 x i8> [[TMPVAR1]], <16 x i8> [[TMPVAR2]])1573; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 81574; CHECK-NEXT: ret <16 x i8> [[TMPVAR3]]1575;1576 %tmpvar1 = load <16 x i8>, ptr %A1577 %tmpvar2 = load <16 x i8>, ptr %B1578 %tmpvar3 = call <16 x i8> @llvm.aarch64.neon.sminp.v16i8(<16 x i8> %tmpvar1, <16 x i8> %tmpvar2)1579 ret <16 x i8> %tmpvar31580}1581 1582define <4 x i16> @sminp_4h(ptr %A, ptr %B) nounwind #0 {1583; CHECK-LABEL: define <4 x i16> @sminp_4h(1584; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1585; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81586; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81587; CHECK-NEXT: call void @llvm.donothing()1588; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01589; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]1590; CHECK: [[BB3]]:1591; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1592; CHECK-NEXT: unreachable1593; CHECK: [[BB4]]:1594; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i16>, ptr [[A]], align 81595; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641596; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761597; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1598; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 81599; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01600; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]1601; CHECK: [[BB8]]:1602; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1603; CHECK-NEXT: unreachable1604; CHECK: [[BB9]]:1605; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i16>, ptr [[B]], align 81606; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641607; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761608; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1609; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 81610; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <4 x i16> [[_MSLD]], <4 x i16> [[_MSLD1]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>1611; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x i16> [[_MSLD]], <4 x i16> [[_MSLD1]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>1612; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[TMP13]], [[TMP14]]1613; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i16> @llvm.aarch64.neon.sminp.v4i16(<4 x i16> [[TMPVAR1]], <4 x i16> [[TMPVAR2]])1614; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 81615; CHECK-NEXT: ret <4 x i16> [[TMPVAR3]]1616;1617 %tmpvar1 = load <4 x i16>, ptr %A1618 %tmpvar2 = load <4 x i16>, ptr %B1619 %tmpvar3 = call <4 x i16> @llvm.aarch64.neon.sminp.v4i16(<4 x i16> %tmpvar1, <4 x i16> %tmpvar2)1620 ret <4 x i16> %tmpvar31621}1622 1623define <8 x i16> @sminp_8h(ptr %A, ptr %B) nounwind #0 {1624; CHECK-LABEL: define <8 x i16> @sminp_8h(1625; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1626; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81627; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81628; CHECK-NEXT: call void @llvm.donothing()1629; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01630; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]1631; CHECK: [[BB3]]:1632; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1633; CHECK-NEXT: unreachable1634; CHECK: [[BB4]]:1635; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i16>, ptr [[A]], align 161636; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641637; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761638; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1639; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 161640; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01641; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]1642; CHECK: [[BB8]]:1643; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1644; CHECK-NEXT: unreachable1645; CHECK: [[BB9]]:1646; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i16>, ptr [[B]], align 161647; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641648; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761649; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1650; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 161651; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <8 x i16> [[_MSLD]], <8 x i16> [[_MSLD1]], <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>1652; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <8 x i16> [[_MSLD]], <8 x i16> [[_MSLD1]], <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>1653; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP13]], [[TMP14]]1654; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i16> @llvm.aarch64.neon.sminp.v8i16(<8 x i16> [[TMPVAR1]], <8 x i16> [[TMPVAR2]])1655; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 81656; CHECK-NEXT: ret <8 x i16> [[TMPVAR3]]1657;1658 %tmpvar1 = load <8 x i16>, ptr %A1659 %tmpvar2 = load <8 x i16>, ptr %B1660 %tmpvar3 = call <8 x i16> @llvm.aarch64.neon.sminp.v8i16(<8 x i16> %tmpvar1, <8 x i16> %tmpvar2)1661 ret <8 x i16> %tmpvar31662}1663 1664define <2 x i32> @sminp_2s(ptr %A, ptr %B) nounwind #0 {1665; CHECK-LABEL: define <2 x i32> @sminp_2s(1666; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1667; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81668; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81669; CHECK-NEXT: call void @llvm.donothing()1670; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01671; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]1672; CHECK: [[BB3]]:1673; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1674; CHECK-NEXT: unreachable1675; CHECK: [[BB4]]:1676; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i32>, ptr [[A]], align 81677; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641678; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761679; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1680; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 81681; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01682; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]1683; CHECK: [[BB8]]:1684; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1685; CHECK-NEXT: unreachable1686; CHECK: [[BB9]]:1687; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x i32>, ptr [[B]], align 81688; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641689; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761690; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1691; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 81692; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <2 x i32> [[_MSLD]], <2 x i32> [[_MSLD1]], <2 x i32> <i32 0, i32 2>1693; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <2 x i32> [[_MSLD]], <2 x i32> [[_MSLD1]], <2 x i32> <i32 1, i32 3>1694; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[TMP13]], [[TMP14]]1695; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i32> @llvm.aarch64.neon.sminp.v2i32(<2 x i32> [[TMPVAR1]], <2 x i32> [[TMPVAR2]])1696; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 81697; CHECK-NEXT: ret <2 x i32> [[TMPVAR3]]1698;1699 %tmpvar1 = load <2 x i32>, ptr %A1700 %tmpvar2 = load <2 x i32>, ptr %B1701 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.sminp.v2i32(<2 x i32> %tmpvar1, <2 x i32> %tmpvar2)1702 ret <2 x i32> %tmpvar31703}1704 1705define <4 x i32> @sminp_4s(ptr %A, ptr %B) nounwind #0 {1706; CHECK-LABEL: define <4 x i32> @sminp_4s(1707; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1708; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81709; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81710; CHECK-NEXT: call void @llvm.donothing()1711; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01712; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]1713; CHECK: [[BB3]]:1714; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1715; CHECK-NEXT: unreachable1716; CHECK: [[BB4]]:1717; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i32>, ptr [[A]], align 161718; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641719; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761720; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1721; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 161722; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01723; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]1724; CHECK: [[BB8]]:1725; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1726; CHECK-NEXT: unreachable1727; CHECK: [[BB9]]:1728; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i32>, ptr [[B]], align 161729; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641730; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761731; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1732; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 161733; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> [[_MSLD1]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>1734; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> [[_MSLD1]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>1735; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP13]], [[TMP14]]1736; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i32> @llvm.aarch64.neon.sminp.v4i32(<4 x i32> [[TMPVAR1]], <4 x i32> [[TMPVAR2]])1737; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 81738; CHECK-NEXT: ret <4 x i32> [[TMPVAR3]]1739;1740 %tmpvar1 = load <4 x i32>, ptr %A1741 %tmpvar2 = load <4 x i32>, ptr %B1742 %tmpvar3 = call <4 x i32> @llvm.aarch64.neon.sminp.v4i32(<4 x i32> %tmpvar1, <4 x i32> %tmpvar2)1743 ret <4 x i32> %tmpvar31744}1745 1746declare <8 x i8> @llvm.aarch64.neon.sminp.v8i8(<8 x i8>, <8 x i8>) nounwind readnone1747declare <16 x i8> @llvm.aarch64.neon.sminp.v16i8(<16 x i8>, <16 x i8>) nounwind readnone1748declare <4 x i16> @llvm.aarch64.neon.sminp.v4i16(<4 x i16>, <4 x i16>) nounwind readnone1749declare <8 x i16> @llvm.aarch64.neon.sminp.v8i16(<8 x i16>, <8 x i16>) nounwind readnone1750declare <2 x i32> @llvm.aarch64.neon.sminp.v2i32(<2 x i32>, <2 x i32>) nounwind readnone1751declare <4 x i32> @llvm.aarch64.neon.sminp.v4i32(<4 x i32>, <4 x i32>) nounwind readnone1752 1753define <8 x i8> @uminp_8b(ptr %A, ptr %B) nounwind #0 {1754; CHECK-LABEL: define <8 x i8> @uminp_8b(1755; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1756; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81757; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81758; CHECK-NEXT: call void @llvm.donothing()1759; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01760; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]1761; CHECK: [[BB3]]:1762; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1763; CHECK-NEXT: unreachable1764; CHECK: [[BB4]]:1765; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i8>, ptr [[A]], align 81766; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641767; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761768; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1769; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 81770; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01771; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]1772; CHECK: [[BB8]]:1773; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1774; CHECK-NEXT: unreachable1775; CHECK: [[BB9]]:1776; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i8>, ptr [[B]], align 81777; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641778; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761779; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1780; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP12]], align 81781; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <8 x i8> [[_MSLD]], <8 x i8> [[_MSLD1]], <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>1782; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <8 x i8> [[_MSLD]], <8 x i8> [[_MSLD1]], <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>1783; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i8> [[TMP13]], [[TMP14]]1784; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i8> @llvm.aarch64.neon.uminp.v8i8(<8 x i8> [[TMPVAR1]], <8 x i8> [[TMPVAR2]])1785; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 81786; CHECK-NEXT: ret <8 x i8> [[TMPVAR3]]1787;1788 %tmpvar1 = load <8 x i8>, ptr %A1789 %tmpvar2 = load <8 x i8>, ptr %B1790 %tmpvar3 = call <8 x i8> @llvm.aarch64.neon.uminp.v8i8(<8 x i8> %tmpvar1, <8 x i8> %tmpvar2)1791 ret <8 x i8> %tmpvar31792}1793 1794define <16 x i8> @uminp_16b(ptr %A, ptr %B) nounwind #0 {1795; CHECK-LABEL: define <16 x i8> @uminp_16b(1796; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1797; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81798; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81799; CHECK-NEXT: call void @llvm.donothing()1800; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01801; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]1802; CHECK: [[BB3]]:1803; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1804; CHECK-NEXT: unreachable1805; CHECK: [[BB4]]:1806; CHECK-NEXT: [[TMPVAR1:%.*]] = load <16 x i8>, ptr [[A]], align 161807; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641808; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761809; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1810; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP7]], align 161811; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01812; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]1813; CHECK: [[BB8]]:1814; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1815; CHECK-NEXT: unreachable1816; CHECK: [[BB9]]:1817; CHECK-NEXT: [[TMPVAR2:%.*]] = load <16 x i8>, ptr [[B]], align 161818; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641819; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761820; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1821; CHECK-NEXT: [[_MSLD1:%.*]] = load <16 x i8>, ptr [[TMP12]], align 161822; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <16 x i8> [[_MSLD]], <16 x i8> [[_MSLD1]], <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>1823; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <16 x i8> [[_MSLD]], <16 x i8> [[_MSLD1]], <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>1824; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP13]], [[TMP14]]1825; CHECK-NEXT: [[TMPVAR3:%.*]] = call <16 x i8> @llvm.aarch64.neon.uminp.v16i8(<16 x i8> [[TMPVAR1]], <16 x i8> [[TMPVAR2]])1826; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 81827; CHECK-NEXT: ret <16 x i8> [[TMPVAR3]]1828;1829 %tmpvar1 = load <16 x i8>, ptr %A1830 %tmpvar2 = load <16 x i8>, ptr %B1831 %tmpvar3 = call <16 x i8> @llvm.aarch64.neon.uminp.v16i8(<16 x i8> %tmpvar1, <16 x i8> %tmpvar2)1832 ret <16 x i8> %tmpvar31833}1834 1835define <4 x i16> @uminp_4h(ptr %A, ptr %B) nounwind #0 {1836; CHECK-LABEL: define <4 x i16> @uminp_4h(1837; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1838; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81839; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81840; CHECK-NEXT: call void @llvm.donothing()1841; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01842; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]1843; CHECK: [[BB3]]:1844; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1845; CHECK-NEXT: unreachable1846; CHECK: [[BB4]]:1847; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i16>, ptr [[A]], align 81848; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641849; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761850; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1851; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 81852; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01853; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]1854; CHECK: [[BB8]]:1855; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1856; CHECK-NEXT: unreachable1857; CHECK: [[BB9]]:1858; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i16>, ptr [[B]], align 81859; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641860; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761861; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1862; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 81863; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <4 x i16> [[_MSLD]], <4 x i16> [[_MSLD1]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>1864; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x i16> [[_MSLD]], <4 x i16> [[_MSLD1]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>1865; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[TMP13]], [[TMP14]]1866; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i16> @llvm.aarch64.neon.uminp.v4i16(<4 x i16> [[TMPVAR1]], <4 x i16> [[TMPVAR2]])1867; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 81868; CHECK-NEXT: ret <4 x i16> [[TMPVAR3]]1869;1870 %tmpvar1 = load <4 x i16>, ptr %A1871 %tmpvar2 = load <4 x i16>, ptr %B1872 %tmpvar3 = call <4 x i16> @llvm.aarch64.neon.uminp.v4i16(<4 x i16> %tmpvar1, <4 x i16> %tmpvar2)1873 ret <4 x i16> %tmpvar31874}1875 1876define <8 x i16> @uminp_8h(ptr %A, ptr %B) nounwind #0 {1877; CHECK-LABEL: define <8 x i16> @uminp_8h(1878; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1879; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81880; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81881; CHECK-NEXT: call void @llvm.donothing()1882; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01883; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]1884; CHECK: [[BB3]]:1885; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1886; CHECK-NEXT: unreachable1887; CHECK: [[BB4]]:1888; CHECK-NEXT: [[TMPVAR1:%.*]] = load <8 x i16>, ptr [[A]], align 161889; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641890; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761891; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1892; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 161893; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01894; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]1895; CHECK: [[BB8]]:1896; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1897; CHECK-NEXT: unreachable1898; CHECK: [[BB9]]:1899; CHECK-NEXT: [[TMPVAR2:%.*]] = load <8 x i16>, ptr [[B]], align 161900; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641901; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761902; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1903; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 161904; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <8 x i16> [[_MSLD]], <8 x i16> [[_MSLD1]], <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>1905; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <8 x i16> [[_MSLD]], <8 x i16> [[_MSLD1]], <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>1906; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP13]], [[TMP14]]1907; CHECK-NEXT: [[TMPVAR3:%.*]] = call <8 x i16> @llvm.aarch64.neon.uminp.v8i16(<8 x i16> [[TMPVAR1]], <8 x i16> [[TMPVAR2]])1908; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 81909; CHECK-NEXT: ret <8 x i16> [[TMPVAR3]]1910;1911 %tmpvar1 = load <8 x i16>, ptr %A1912 %tmpvar2 = load <8 x i16>, ptr %B1913 %tmpvar3 = call <8 x i16> @llvm.aarch64.neon.uminp.v8i16(<8 x i16> %tmpvar1, <8 x i16> %tmpvar2)1914 ret <8 x i16> %tmpvar31915}1916 1917define <2 x i32> @uminp_2s(ptr %A, ptr %B) nounwind #0 {1918; CHECK-LABEL: define <2 x i32> @uminp_2s(1919; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1920; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81921; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81922; CHECK-NEXT: call void @llvm.donothing()1923; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01924; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]1925; CHECK: [[BB3]]:1926; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1927; CHECK-NEXT: unreachable1928; CHECK: [[BB4]]:1929; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x i32>, ptr [[A]], align 81930; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641931; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761932; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1933; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 81934; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01935; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]1936; CHECK: [[BB8]]:1937; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1938; CHECK-NEXT: unreachable1939; CHECK: [[BB9]]:1940; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x i32>, ptr [[B]], align 81941; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641942; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761943; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1944; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 81945; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <2 x i32> [[_MSLD]], <2 x i32> [[_MSLD1]], <2 x i32> <i32 0, i32 2>1946; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <2 x i32> [[_MSLD]], <2 x i32> [[_MSLD1]], <2 x i32> <i32 1, i32 3>1947; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[TMP13]], [[TMP14]]1948; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x i32> @llvm.aarch64.neon.uminp.v2i32(<2 x i32> [[TMPVAR1]], <2 x i32> [[TMPVAR2]])1949; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 81950; CHECK-NEXT: ret <2 x i32> [[TMPVAR3]]1951;1952 %tmpvar1 = load <2 x i32>, ptr %A1953 %tmpvar2 = load <2 x i32>, ptr %B1954 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.uminp.v2i32(<2 x i32> %tmpvar1, <2 x i32> %tmpvar2)1955 ret <2 x i32> %tmpvar31956}1957 1958define <4 x i32> @uminp_4s(ptr %A, ptr %B) nounwind #0 {1959; CHECK-LABEL: define <4 x i32> @uminp_4s(1960; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1961; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81962; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81963; CHECK-NEXT: call void @llvm.donothing()1964; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01965; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]1966; CHECK: [[BB3]]:1967; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1968; CHECK-NEXT: unreachable1969; CHECK: [[BB4]]:1970; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x i32>, ptr [[A]], align 161971; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641972; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761973; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1974; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 161975; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01976; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]1977; CHECK: [[BB8]]:1978; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]1979; CHECK-NEXT: unreachable1980; CHECK: [[BB9]]:1981; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x i32>, ptr [[B]], align 161982; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641983; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761984; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1985; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 161986; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> [[_MSLD1]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>1987; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> [[_MSLD1]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>1988; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP13]], [[TMP14]]1989; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x i32> @llvm.aarch64.neon.uminp.v4i32(<4 x i32> [[TMPVAR1]], <4 x i32> [[TMPVAR2]])1990; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 81991; CHECK-NEXT: ret <4 x i32> [[TMPVAR3]]1992;1993 %tmpvar1 = load <4 x i32>, ptr %A1994 %tmpvar2 = load <4 x i32>, ptr %B1995 %tmpvar3 = call <4 x i32> @llvm.aarch64.neon.uminp.v4i32(<4 x i32> %tmpvar1, <4 x i32> %tmpvar2)1996 ret <4 x i32> %tmpvar31997}1998 1999declare <8 x i8> @llvm.aarch64.neon.uminp.v8i8(<8 x i8>, <8 x i8>) nounwind readnone2000declare <16 x i8> @llvm.aarch64.neon.uminp.v16i8(<16 x i8>, <16 x i8>) nounwind readnone2001declare <4 x i16> @llvm.aarch64.neon.uminp.v4i16(<4 x i16>, <4 x i16>) nounwind readnone2002declare <8 x i16> @llvm.aarch64.neon.uminp.v8i16(<8 x i16>, <8 x i16>) nounwind readnone2003declare <2 x i32> @llvm.aarch64.neon.uminp.v2i32(<2 x i32>, <2 x i32>) nounwind readnone2004declare <4 x i32> @llvm.aarch64.neon.uminp.v4i32(<4 x i32>, <4 x i32>) nounwind readnone2005 2006define <2 x float> @fmax_2s(ptr %A, ptr %B) nounwind #0 {2007; CHECK-LABEL: define <2 x float> @fmax_2s(2008; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2009; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82010; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82011; CHECK-NEXT: call void @llvm.donothing()2012; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02013; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]2014; CHECK: [[BB3]]:2015; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2016; CHECK-NEXT: unreachable2017; CHECK: [[BB4]]:2018; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x float>, ptr [[A]], align 82019; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642020; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762021; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2022; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 82023; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02024; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]2025; CHECK: [[BB8]]:2026; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2027; CHECK-NEXT: unreachable2028; CHECK: [[BB9]]:2029; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x float>, ptr [[B]], align 82030; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642031; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762032; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2033; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 82034; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[_MSLD]], [[_MSLD1]]2035; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x float> @llvm.aarch64.neon.fmax.v2f32(<2 x float> [[TMPVAR1]], <2 x float> [[TMPVAR2]])2036; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 82037; CHECK-NEXT: ret <2 x float> [[TMPVAR3]]2038;2039 %tmpvar1 = load <2 x float>, ptr %A2040 %tmpvar2 = load <2 x float>, ptr %B2041 %tmpvar3 = call <2 x float> @llvm.aarch64.neon.fmax.v2f32(<2 x float> %tmpvar1, <2 x float> %tmpvar2)2042 ret <2 x float> %tmpvar32043}2044 2045define <4 x float> @fmax_4s(ptr %A, ptr %B) nounwind #0 {2046; CHECK-LABEL: define <4 x float> @fmax_4s(2047; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2048; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82049; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82050; CHECK-NEXT: call void @llvm.donothing()2051; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02052; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]2053; CHECK: [[BB3]]:2054; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2055; CHECK-NEXT: unreachable2056; CHECK: [[BB4]]:2057; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x float>, ptr [[A]], align 162058; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642059; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762060; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2061; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 162062; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02063; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]2064; CHECK: [[BB8]]:2065; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2066; CHECK-NEXT: unreachable2067; CHECK: [[BB9]]:2068; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x float>, ptr [[B]], align 162069; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642070; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762071; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2072; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 162073; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[_MSLD]], [[_MSLD1]]2074; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x float> @llvm.aarch64.neon.fmax.v4f32(<4 x float> [[TMPVAR1]], <4 x float> [[TMPVAR2]])2075; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 82076; CHECK-NEXT: ret <4 x float> [[TMPVAR3]]2077;2078 %tmpvar1 = load <4 x float>, ptr %A2079 %tmpvar2 = load <4 x float>, ptr %B2080 %tmpvar3 = call <4 x float> @llvm.aarch64.neon.fmax.v4f32(<4 x float> %tmpvar1, <4 x float> %tmpvar2)2081 ret <4 x float> %tmpvar32082}2083 2084define <2 x double> @fmax_2d(ptr %A, ptr %B) nounwind #0 {2085; CHECK-LABEL: define <2 x double> @fmax_2d(2086; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2087; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82088; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82089; CHECK-NEXT: call void @llvm.donothing()2090; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02091; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]2092; CHECK: [[BB3]]:2093; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2094; CHECK-NEXT: unreachable2095; CHECK: [[BB4]]:2096; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x double>, ptr [[A]], align 162097; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642098; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762099; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2100; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 162101; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02102; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]2103; CHECK: [[BB8]]:2104; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2105; CHECK-NEXT: unreachable2106; CHECK: [[BB9]]:2107; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x double>, ptr [[B]], align 162108; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642109; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762110; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2111; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 162112; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[_MSLD]], [[_MSLD1]]2113; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x double> @llvm.aarch64.neon.fmax.v2f64(<2 x double> [[TMPVAR1]], <2 x double> [[TMPVAR2]])2114; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 82115; CHECK-NEXT: ret <2 x double> [[TMPVAR3]]2116;2117 %tmpvar1 = load <2 x double>, ptr %A2118 %tmpvar2 = load <2 x double>, ptr %B2119 %tmpvar3 = call <2 x double> @llvm.aarch64.neon.fmax.v2f64(<2 x double> %tmpvar1, <2 x double> %tmpvar2)2120 ret <2 x double> %tmpvar32121}2122 2123declare <2 x float> @llvm.aarch64.neon.fmax.v2f32(<2 x float>, <2 x float>) nounwind readnone2124declare <4 x float> @llvm.aarch64.neon.fmax.v4f32(<4 x float>, <4 x float>) nounwind readnone2125declare <2 x double> @llvm.aarch64.neon.fmax.v2f64(<2 x double>, <2 x double>) nounwind readnone2126 2127define <2 x float> @fmaxp_2s(ptr %A, ptr %B) nounwind #0 {2128; CHECK-LABEL: define <2 x float> @fmaxp_2s(2129; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2130; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82131; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82132; CHECK-NEXT: call void @llvm.donothing()2133; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02134; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]2135; CHECK: [[BB3]]:2136; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2137; CHECK-NEXT: unreachable2138; CHECK: [[BB4]]:2139; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x float>, ptr [[A]], align 82140; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642141; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762142; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2143; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 82144; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02145; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]2146; CHECK: [[BB8]]:2147; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2148; CHECK-NEXT: unreachable2149; CHECK: [[BB9]]:2150; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x float>, ptr [[B]], align 82151; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642152; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762153; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2154; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 82155; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <2 x i32> [[_MSLD]], <2 x i32> [[_MSLD1]], <2 x i32> <i32 0, i32 2>2156; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <2 x i32> [[_MSLD]], <2 x i32> [[_MSLD1]], <2 x i32> <i32 1, i32 3>2157; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[TMP13]], [[TMP14]]2158; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x float> @llvm.aarch64.neon.fmaxp.v2f32(<2 x float> [[TMPVAR1]], <2 x float> [[TMPVAR2]])2159; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 82160; CHECK-NEXT: ret <2 x float> [[TMPVAR3]]2161;2162 %tmpvar1 = load <2 x float>, ptr %A2163 %tmpvar2 = load <2 x float>, ptr %B2164 %tmpvar3 = call <2 x float> @llvm.aarch64.neon.fmaxp.v2f32(<2 x float> %tmpvar1, <2 x float> %tmpvar2)2165 ret <2 x float> %tmpvar32166}2167 2168define <4 x float> @fmaxp_4s(ptr %A, ptr %B) nounwind #0 {2169; CHECK-LABEL: define <4 x float> @fmaxp_4s(2170; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2171; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82172; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82173; CHECK-NEXT: call void @llvm.donothing()2174; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02175; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]2176; CHECK: [[BB3]]:2177; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2178; CHECK-NEXT: unreachable2179; CHECK: [[BB4]]:2180; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x float>, ptr [[A]], align 162181; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642182; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762183; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2184; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 162185; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02186; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]2187; CHECK: [[BB8]]:2188; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2189; CHECK-NEXT: unreachable2190; CHECK: [[BB9]]:2191; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x float>, ptr [[B]], align 162192; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642193; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762194; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2195; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 162196; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> [[_MSLD1]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>2197; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> [[_MSLD1]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>2198; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP13]], [[TMP14]]2199; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x float> @llvm.aarch64.neon.fmaxp.v4f32(<4 x float> [[TMPVAR1]], <4 x float> [[TMPVAR2]])2200; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 82201; CHECK-NEXT: ret <4 x float> [[TMPVAR3]]2202;2203 %tmpvar1 = load <4 x float>, ptr %A2204 %tmpvar2 = load <4 x float>, ptr %B2205 %tmpvar3 = call <4 x float> @llvm.aarch64.neon.fmaxp.v4f32(<4 x float> %tmpvar1, <4 x float> %tmpvar2)2206 ret <4 x float> %tmpvar32207}2208 2209define <2 x double> @fmaxp_2d(ptr %A, ptr %B) nounwind #0 {2210; CHECK-LABEL: define <2 x double> @fmaxp_2d(2211; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2212; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82213; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82214; CHECK-NEXT: call void @llvm.donothing()2215; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02216; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]2217; CHECK: [[BB3]]:2218; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2219; CHECK-NEXT: unreachable2220; CHECK: [[BB4]]:2221; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x double>, ptr [[A]], align 162222; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642223; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762224; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2225; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 162226; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02227; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]2228; CHECK: [[BB8]]:2229; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2230; CHECK-NEXT: unreachable2231; CHECK: [[BB9]]:2232; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x double>, ptr [[B]], align 162233; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642234; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762235; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2236; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 162237; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <2 x i64> [[_MSLD]], <2 x i64> [[_MSLD1]], <2 x i32> <i32 0, i32 2>2238; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <2 x i64> [[_MSLD]], <2 x i64> [[_MSLD1]], <2 x i32> <i32 1, i32 3>2239; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP13]], [[TMP14]]2240; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x double> @llvm.aarch64.neon.fmaxp.v2f64(<2 x double> [[TMPVAR1]], <2 x double> [[TMPVAR2]])2241; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 82242; CHECK-NEXT: ret <2 x double> [[TMPVAR3]]2243;2244 %tmpvar1 = load <2 x double>, ptr %A2245 %tmpvar2 = load <2 x double>, ptr %B2246 %tmpvar3 = call <2 x double> @llvm.aarch64.neon.fmaxp.v2f64(<2 x double> %tmpvar1, <2 x double> %tmpvar2)2247 ret <2 x double> %tmpvar32248}2249 2250declare <2 x float> @llvm.aarch64.neon.fmaxp.v2f32(<2 x float>, <2 x float>) nounwind readnone2251declare <4 x float> @llvm.aarch64.neon.fmaxp.v4f32(<4 x float>, <4 x float>) nounwind readnone2252declare <2 x double> @llvm.aarch64.neon.fmaxp.v2f64(<2 x double>, <2 x double>) nounwind readnone2253 2254define <2 x float> @fmin_2s(ptr %A, ptr %B) nounwind #0 {2255; CHECK-LABEL: define <2 x float> @fmin_2s(2256; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2257; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82258; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82259; CHECK-NEXT: call void @llvm.donothing()2260; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02261; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]2262; CHECK: [[BB3]]:2263; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2264; CHECK-NEXT: unreachable2265; CHECK: [[BB4]]:2266; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x float>, ptr [[A]], align 82267; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642268; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762269; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2270; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 82271; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02272; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]2273; CHECK: [[BB8]]:2274; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2275; CHECK-NEXT: unreachable2276; CHECK: [[BB9]]:2277; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x float>, ptr [[B]], align 82278; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642279; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762280; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2281; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 82282; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[_MSLD]], [[_MSLD1]]2283; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x float> @llvm.aarch64.neon.fmin.v2f32(<2 x float> [[TMPVAR1]], <2 x float> [[TMPVAR2]])2284; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 82285; CHECK-NEXT: ret <2 x float> [[TMPVAR3]]2286;2287 %tmpvar1 = load <2 x float>, ptr %A2288 %tmpvar2 = load <2 x float>, ptr %B2289 %tmpvar3 = call <2 x float> @llvm.aarch64.neon.fmin.v2f32(<2 x float> %tmpvar1, <2 x float> %tmpvar2)2290 ret <2 x float> %tmpvar32291}2292 2293define <4 x float> @fmin_4s(ptr %A, ptr %B) nounwind #0 {2294; CHECK-LABEL: define <4 x float> @fmin_4s(2295; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2296; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82297; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82298; CHECK-NEXT: call void @llvm.donothing()2299; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02300; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]2301; CHECK: [[BB3]]:2302; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2303; CHECK-NEXT: unreachable2304; CHECK: [[BB4]]:2305; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x float>, ptr [[A]], align 162306; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642307; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762308; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2309; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 162310; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02311; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]2312; CHECK: [[BB8]]:2313; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2314; CHECK-NEXT: unreachable2315; CHECK: [[BB9]]:2316; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x float>, ptr [[B]], align 162317; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642318; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762319; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2320; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 162321; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[_MSLD]], [[_MSLD1]]2322; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x float> @llvm.aarch64.neon.fmin.v4f32(<4 x float> [[TMPVAR1]], <4 x float> [[TMPVAR2]])2323; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 82324; CHECK-NEXT: ret <4 x float> [[TMPVAR3]]2325;2326 %tmpvar1 = load <4 x float>, ptr %A2327 %tmpvar2 = load <4 x float>, ptr %B2328 %tmpvar3 = call <4 x float> @llvm.aarch64.neon.fmin.v4f32(<4 x float> %tmpvar1, <4 x float> %tmpvar2)2329 ret <4 x float> %tmpvar32330}2331 2332define <2 x double> @fmin_2d(ptr %A, ptr %B) nounwind #0 {2333; CHECK-LABEL: define <2 x double> @fmin_2d(2334; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2335; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82336; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82337; CHECK-NEXT: call void @llvm.donothing()2338; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02339; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]2340; CHECK: [[BB3]]:2341; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2342; CHECK-NEXT: unreachable2343; CHECK: [[BB4]]:2344; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x double>, ptr [[A]], align 162345; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642346; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762347; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2348; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 162349; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02350; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]2351; CHECK: [[BB8]]:2352; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2353; CHECK-NEXT: unreachable2354; CHECK: [[BB9]]:2355; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x double>, ptr [[B]], align 162356; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642357; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762358; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2359; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 162360; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[_MSLD]], [[_MSLD1]]2361; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x double> @llvm.aarch64.neon.fmin.v2f64(<2 x double> [[TMPVAR1]], <2 x double> [[TMPVAR2]])2362; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 82363; CHECK-NEXT: ret <2 x double> [[TMPVAR3]]2364;2365 %tmpvar1 = load <2 x double>, ptr %A2366 %tmpvar2 = load <2 x double>, ptr %B2367 %tmpvar3 = call <2 x double> @llvm.aarch64.neon.fmin.v2f64(<2 x double> %tmpvar1, <2 x double> %tmpvar2)2368 ret <2 x double> %tmpvar32369}2370 2371declare <2 x float> @llvm.aarch64.neon.fmin.v2f32(<2 x float>, <2 x float>) nounwind readnone2372declare <4 x float> @llvm.aarch64.neon.fmin.v4f32(<4 x float>, <4 x float>) nounwind readnone2373declare <2 x double> @llvm.aarch64.neon.fmin.v2f64(<2 x double>, <2 x double>) nounwind readnone2374 2375define <2 x float> @fminp_2s(ptr %A, ptr %B) nounwind #0 {2376; CHECK-LABEL: define <2 x float> @fminp_2s(2377; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2378; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82379; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82380; CHECK-NEXT: call void @llvm.donothing()2381; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02382; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]2383; CHECK: [[BB3]]:2384; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2385; CHECK-NEXT: unreachable2386; CHECK: [[BB4]]:2387; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x float>, ptr [[A]], align 82388; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642389; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762390; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2391; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 82392; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02393; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]2394; CHECK: [[BB8]]:2395; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2396; CHECK-NEXT: unreachable2397; CHECK: [[BB9]]:2398; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x float>, ptr [[B]], align 82399; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642400; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762401; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2402; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 82403; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <2 x i32> [[_MSLD]], <2 x i32> [[_MSLD1]], <2 x i32> <i32 0, i32 2>2404; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <2 x i32> [[_MSLD]], <2 x i32> [[_MSLD1]], <2 x i32> <i32 1, i32 3>2405; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[TMP13]], [[TMP14]]2406; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x float> @llvm.aarch64.neon.fminp.v2f32(<2 x float> [[TMPVAR1]], <2 x float> [[TMPVAR2]])2407; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 82408; CHECK-NEXT: ret <2 x float> [[TMPVAR3]]2409;2410 %tmpvar1 = load <2 x float>, ptr %A2411 %tmpvar2 = load <2 x float>, ptr %B2412 %tmpvar3 = call <2 x float> @llvm.aarch64.neon.fminp.v2f32(<2 x float> %tmpvar1, <2 x float> %tmpvar2)2413 ret <2 x float> %tmpvar32414}2415 2416define <4 x float> @fminp_4s(ptr %A, ptr %B) nounwind #0 {2417; CHECK-LABEL: define <4 x float> @fminp_4s(2418; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2419; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82420; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82421; CHECK-NEXT: call void @llvm.donothing()2422; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02423; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]2424; CHECK: [[BB3]]:2425; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2426; CHECK-NEXT: unreachable2427; CHECK: [[BB4]]:2428; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x float>, ptr [[A]], align 162429; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642430; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762431; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2432; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 162433; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02434; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]2435; CHECK: [[BB8]]:2436; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2437; CHECK-NEXT: unreachable2438; CHECK: [[BB9]]:2439; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x float>, ptr [[B]], align 162440; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642441; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762442; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2443; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 162444; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> [[_MSLD1]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>2445; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> [[_MSLD1]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>2446; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP13]], [[TMP14]]2447; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x float> @llvm.aarch64.neon.fminp.v4f32(<4 x float> [[TMPVAR1]], <4 x float> [[TMPVAR2]])2448; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 82449; CHECK-NEXT: ret <4 x float> [[TMPVAR3]]2450;2451 %tmpvar1 = load <4 x float>, ptr %A2452 %tmpvar2 = load <4 x float>, ptr %B2453 %tmpvar3 = call <4 x float> @llvm.aarch64.neon.fminp.v4f32(<4 x float> %tmpvar1, <4 x float> %tmpvar2)2454 ret <4 x float> %tmpvar32455}2456 2457define <2 x double> @fminp_2d(ptr %A, ptr %B) nounwind #0 {2458; CHECK-LABEL: define <2 x double> @fminp_2d(2459; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2460; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82461; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82462; CHECK-NEXT: call void @llvm.donothing()2463; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02464; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]2465; CHECK: [[BB3]]:2466; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2467; CHECK-NEXT: unreachable2468; CHECK: [[BB4]]:2469; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x double>, ptr [[A]], align 162470; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642471; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762472; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2473; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 162474; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02475; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]2476; CHECK: [[BB8]]:2477; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2478; CHECK-NEXT: unreachable2479; CHECK: [[BB9]]:2480; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x double>, ptr [[B]], align 162481; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642482; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762483; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2484; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 162485; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <2 x i64> [[_MSLD]], <2 x i64> [[_MSLD1]], <2 x i32> <i32 0, i32 2>2486; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <2 x i64> [[_MSLD]], <2 x i64> [[_MSLD1]], <2 x i32> <i32 1, i32 3>2487; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP13]], [[TMP14]]2488; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x double> @llvm.aarch64.neon.fminp.v2f64(<2 x double> [[TMPVAR1]], <2 x double> [[TMPVAR2]])2489; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 82490; CHECK-NEXT: ret <2 x double> [[TMPVAR3]]2491;2492 %tmpvar1 = load <2 x double>, ptr %A2493 %tmpvar2 = load <2 x double>, ptr %B2494 %tmpvar3 = call <2 x double> @llvm.aarch64.neon.fminp.v2f64(<2 x double> %tmpvar1, <2 x double> %tmpvar2)2495 ret <2 x double> %tmpvar32496}2497 2498declare <2 x float> @llvm.aarch64.neon.fminp.v2f32(<2 x float>, <2 x float>) nounwind readnone2499declare <4 x float> @llvm.aarch64.neon.fminp.v4f32(<4 x float>, <4 x float>) nounwind readnone2500declare <2 x double> @llvm.aarch64.neon.fminp.v2f64(<2 x double>, <2 x double>) nounwind readnone2501 2502define <2 x float> @fminnmp_2s(ptr %A, ptr %B) nounwind #0 {2503; CHECK-LABEL: define <2 x float> @fminnmp_2s(2504; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2505; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82506; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82507; CHECK-NEXT: call void @llvm.donothing()2508; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02509; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]2510; CHECK: [[BB3]]:2511; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2512; CHECK-NEXT: unreachable2513; CHECK: [[BB4]]:2514; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x float>, ptr [[A]], align 82515; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642516; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762517; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2518; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 82519; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02520; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]2521; CHECK: [[BB8]]:2522; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2523; CHECK-NEXT: unreachable2524; CHECK: [[BB9]]:2525; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x float>, ptr [[B]], align 82526; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642527; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762528; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2529; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 82530; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <2 x i32> [[_MSLD]], <2 x i32> [[_MSLD1]], <2 x i32> <i32 0, i32 2>2531; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <2 x i32> [[_MSLD]], <2 x i32> [[_MSLD1]], <2 x i32> <i32 1, i32 3>2532; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[TMP13]], [[TMP14]]2533; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x float> @llvm.aarch64.neon.fminnmp.v2f32(<2 x float> [[TMPVAR1]], <2 x float> [[TMPVAR2]])2534; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 82535; CHECK-NEXT: ret <2 x float> [[TMPVAR3]]2536;2537 %tmpvar1 = load <2 x float>, ptr %A2538 %tmpvar2 = load <2 x float>, ptr %B2539 %tmpvar3 = call <2 x float> @llvm.aarch64.neon.fminnmp.v2f32(<2 x float> %tmpvar1, <2 x float> %tmpvar2)2540 ret <2 x float> %tmpvar32541}2542 2543define <4 x float> @fminnmp_4s(ptr %A, ptr %B) nounwind #0 {2544; CHECK-LABEL: define <4 x float> @fminnmp_4s(2545; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2546; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82547; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82548; CHECK-NEXT: call void @llvm.donothing()2549; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02550; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]2551; CHECK: [[BB3]]:2552; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2553; CHECK-NEXT: unreachable2554; CHECK: [[BB4]]:2555; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x float>, ptr [[A]], align 162556; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642557; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762558; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2559; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 162560; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02561; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]2562; CHECK: [[BB8]]:2563; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2564; CHECK-NEXT: unreachable2565; CHECK: [[BB9]]:2566; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x float>, ptr [[B]], align 162567; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642568; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762569; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2570; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 162571; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> [[_MSLD1]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>2572; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> [[_MSLD1]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>2573; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP13]], [[TMP14]]2574; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x float> @llvm.aarch64.neon.fminnmp.v4f32(<4 x float> [[TMPVAR1]], <4 x float> [[TMPVAR2]])2575; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 82576; CHECK-NEXT: ret <4 x float> [[TMPVAR3]]2577;2578 %tmpvar1 = load <4 x float>, ptr %A2579 %tmpvar2 = load <4 x float>, ptr %B2580 %tmpvar3 = call <4 x float> @llvm.aarch64.neon.fminnmp.v4f32(<4 x float> %tmpvar1, <4 x float> %tmpvar2)2581 ret <4 x float> %tmpvar32582}2583 2584define <2 x double> @fminnmp_2d(ptr %A, ptr %B) nounwind #0 {2585; CHECK-LABEL: define <2 x double> @fminnmp_2d(2586; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2587; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82588; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82589; CHECK-NEXT: call void @llvm.donothing()2590; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02591; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]2592; CHECK: [[BB3]]:2593; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2594; CHECK-NEXT: unreachable2595; CHECK: [[BB4]]:2596; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x double>, ptr [[A]], align 162597; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642598; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762599; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2600; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 162601; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02602; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]2603; CHECK: [[BB8]]:2604; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2605; CHECK-NEXT: unreachable2606; CHECK: [[BB9]]:2607; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x double>, ptr [[B]], align 162608; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642609; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762610; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2611; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 162612; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <2 x i64> [[_MSLD]], <2 x i64> [[_MSLD1]], <2 x i32> <i32 0, i32 2>2613; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <2 x i64> [[_MSLD]], <2 x i64> [[_MSLD1]], <2 x i32> <i32 1, i32 3>2614; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP13]], [[TMP14]]2615; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x double> @llvm.aarch64.neon.fminnmp.v2f64(<2 x double> [[TMPVAR1]], <2 x double> [[TMPVAR2]])2616; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 82617; CHECK-NEXT: ret <2 x double> [[TMPVAR3]]2618;2619 %tmpvar1 = load <2 x double>, ptr %A2620 %tmpvar2 = load <2 x double>, ptr %B2621 %tmpvar3 = call <2 x double> @llvm.aarch64.neon.fminnmp.v2f64(<2 x double> %tmpvar1, <2 x double> %tmpvar2)2622 ret <2 x double> %tmpvar32623}2624 2625declare <2 x float> @llvm.aarch64.neon.fminnmp.v2f32(<2 x float>, <2 x float>) nounwind readnone2626declare <4 x float> @llvm.aarch64.neon.fminnmp.v4f32(<4 x float>, <4 x float>) nounwind readnone2627declare <2 x double> @llvm.aarch64.neon.fminnmp.v2f64(<2 x double>, <2 x double>) nounwind readnone2628 2629define <2 x float> @fmaxnmp_2s(ptr %A, ptr %B) nounwind #0 {2630; CHECK-LABEL: define <2 x float> @fmaxnmp_2s(2631; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2632; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82633; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82634; CHECK-NEXT: call void @llvm.donothing()2635; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02636; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]2637; CHECK: [[BB3]]:2638; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2639; CHECK-NEXT: unreachable2640; CHECK: [[BB4]]:2641; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x float>, ptr [[A]], align 82642; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642643; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762644; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2645; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 82646; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02647; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]2648; CHECK: [[BB8]]:2649; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2650; CHECK-NEXT: unreachable2651; CHECK: [[BB9]]:2652; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x float>, ptr [[B]], align 82653; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642654; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762655; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2656; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 82657; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <2 x i32> [[_MSLD]], <2 x i32> [[_MSLD1]], <2 x i32> <i32 0, i32 2>2658; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <2 x i32> [[_MSLD]], <2 x i32> [[_MSLD1]], <2 x i32> <i32 1, i32 3>2659; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[TMP13]], [[TMP14]]2660; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x float> @llvm.aarch64.neon.fmaxnmp.v2f32(<2 x float> [[TMPVAR1]], <2 x float> [[TMPVAR2]])2661; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 82662; CHECK-NEXT: ret <2 x float> [[TMPVAR3]]2663;2664 %tmpvar1 = load <2 x float>, ptr %A2665 %tmpvar2 = load <2 x float>, ptr %B2666 %tmpvar3 = call <2 x float> @llvm.aarch64.neon.fmaxnmp.v2f32(<2 x float> %tmpvar1, <2 x float> %tmpvar2)2667 ret <2 x float> %tmpvar32668}2669 2670define <4 x float> @fmaxnmp_4s(ptr %A, ptr %B) nounwind #0 {2671; CHECK-LABEL: define <4 x float> @fmaxnmp_4s(2672; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2673; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82674; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82675; CHECK-NEXT: call void @llvm.donothing()2676; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02677; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]2678; CHECK: [[BB3]]:2679; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2680; CHECK-NEXT: unreachable2681; CHECK: [[BB4]]:2682; CHECK-NEXT: [[TMPVAR1:%.*]] = load <4 x float>, ptr [[A]], align 162683; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642684; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762685; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2686; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 162687; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02688; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]2689; CHECK: [[BB8]]:2690; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2691; CHECK-NEXT: unreachable2692; CHECK: [[BB9]]:2693; CHECK-NEXT: [[TMPVAR2:%.*]] = load <4 x float>, ptr [[B]], align 162694; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642695; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762696; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2697; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 162698; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> [[_MSLD1]], <4 x i32> <i32 0, i32 2, i32 4, i32 6>2699; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> [[_MSLD1]], <4 x i32> <i32 1, i32 3, i32 5, i32 7>2700; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP13]], [[TMP14]]2701; CHECK-NEXT: [[TMPVAR3:%.*]] = call <4 x float> @llvm.aarch64.neon.fmaxnmp.v4f32(<4 x float> [[TMPVAR1]], <4 x float> [[TMPVAR2]])2702; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 82703; CHECK-NEXT: ret <4 x float> [[TMPVAR3]]2704;2705 %tmpvar1 = load <4 x float>, ptr %A2706 %tmpvar2 = load <4 x float>, ptr %B2707 %tmpvar3 = call <4 x float> @llvm.aarch64.neon.fmaxnmp.v4f32(<4 x float> %tmpvar1, <4 x float> %tmpvar2)2708 ret <4 x float> %tmpvar32709}2710 2711define <2 x double> @fmaxnmp_2d(ptr %A, ptr %B) nounwind #0 {2712; CHECK-LABEL: define <2 x double> @fmaxnmp_2d(2713; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2714; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82715; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82716; CHECK-NEXT: call void @llvm.donothing()2717; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02718; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]2719; CHECK: [[BB3]]:2720; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2721; CHECK-NEXT: unreachable2722; CHECK: [[BB4]]:2723; CHECK-NEXT: [[TMPVAR1:%.*]] = load <2 x double>, ptr [[A]], align 162724; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642725; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762726; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2727; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 162728; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02729; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]2730; CHECK: [[BB8]]:2731; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR3]]2732; CHECK-NEXT: unreachable2733; CHECK: [[BB9]]:2734; CHECK-NEXT: [[TMPVAR2:%.*]] = load <2 x double>, ptr [[B]], align 162735; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642736; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762737; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2738; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 162739; CHECK-NEXT: [[TMP13:%.*]] = shufflevector <2 x i64> [[_MSLD]], <2 x i64> [[_MSLD1]], <2 x i32> <i32 0, i32 2>2740; CHECK-NEXT: [[TMP14:%.*]] = shufflevector <2 x i64> [[_MSLD]], <2 x i64> [[_MSLD1]], <2 x i32> <i32 1, i32 3>2741; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP13]], [[TMP14]]2742; CHECK-NEXT: [[TMPVAR3:%.*]] = call <2 x double> @llvm.aarch64.neon.fmaxnmp.v2f64(<2 x double> [[TMPVAR1]], <2 x double> [[TMPVAR2]])2743; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 82744; CHECK-NEXT: ret <2 x double> [[TMPVAR3]]2745;2746 %tmpvar1 = load <2 x double>, ptr %A2747 %tmpvar2 = load <2 x double>, ptr %B2748 %tmpvar3 = call <2 x double> @llvm.aarch64.neon.fmaxnmp.v2f64(<2 x double> %tmpvar1, <2 x double> %tmpvar2)2749 ret <2 x double> %tmpvar32750}2751 2752declare <2 x float> @llvm.aarch64.neon.fmaxnmp.v2f32(<2 x float>, <2 x float>) nounwind readnone2753declare <4 x float> @llvm.aarch64.neon.fmaxnmp.v4f32(<4 x float>, <4 x float>) nounwind readnone2754declare <2 x double> @llvm.aarch64.neon.fmaxnmp.v2f64(<2 x double>, <2 x double>) nounwind readnone2755 2756attributes #0 = { sanitize_memory }2757;.2758; CHECK: [[PROF1]] = !{!"branch_weights", i32 1, i32 1048575}2759;.2760