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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt < %s -passes=msan -S | FileCheck %s3;4; Forked from llvm/test/CodeGen/AArch64/arm64-vmovn.ll5 6target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"7target triple = "aarch64--linux-android9001"8 9define <8 x i8> @xtn8b(<8 x i16> %A) nounwind #0 {10; CHECK-LABEL: define <8 x i8> @xtn8b(11; CHECK-SAME: <8 x i16> [[A:%.*]]) #[[ATTR0:[0-9]+]] {12; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 813; CHECK-NEXT: call void @llvm.donothing()14; CHECK-NEXT: [[_MSPROP:%.*]] = trunc <8 x i16> [[TMP1]] to <8 x i8>15; CHECK-NEXT: [[TMP3:%.*]] = trunc <8 x i16> [[A]] to <8 x i8>16; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 817; CHECK-NEXT: ret <8 x i8> [[TMP3]]18;19 %tmpvar3 = trunc <8 x i16> %A to <8 x i8>20 ret <8 x i8> %tmpvar321}22 23define <4 x i16> @xtn4h(<4 x i32> %A) nounwind #0 {24; CHECK-LABEL: define <4 x i16> @xtn4h(25; CHECK-SAME: <4 x i32> [[A:%.*]]) #[[ATTR0]] {26; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 827; CHECK-NEXT: call void @llvm.donothing()28; CHECK-NEXT: [[_MSPROP:%.*]] = trunc <4 x i32> [[TMP1]] to <4 x i16>29; CHECK-NEXT: [[TMP3:%.*]] = trunc <4 x i32> [[A]] to <4 x i16>30; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 831; CHECK-NEXT: ret <4 x i16> [[TMP3]]32;33 %tmpvar3 = trunc <4 x i32> %A to <4 x i16>34 ret <4 x i16> %tmpvar335}36 37define <2 x i32> @xtn2s(<2 x i64> %A) nounwind #0 {38; CHECK-LABEL: define <2 x i32> @xtn2s(39; CHECK-SAME: <2 x i64> [[A:%.*]]) #[[ATTR0]] {40; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 841; CHECK-NEXT: call void @llvm.donothing()42; CHECK-NEXT: [[_MSPROP:%.*]] = trunc <2 x i64> [[TMP1]] to <2 x i32>43; CHECK-NEXT: [[TMP3:%.*]] = trunc <2 x i64> [[A]] to <2 x i32>44; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 845; CHECK-NEXT: ret <2 x i32> [[TMP3]]46;47 %tmpvar3 = trunc <2 x i64> %A to <2 x i32>48 ret <2 x i32> %tmpvar349}50 51define <16 x i8> @xtn2_16b(<8 x i8> %ret, <8 x i16> %A) nounwind #0 {52; CHECK-LABEL: define <16 x i8> @xtn2_16b(53; CHECK-SAME: <8 x i8> [[RET:%.*]], <8 x i16> [[A:%.*]]) #[[ATTR0]] {54; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 855; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i8>, ptr @__msan_param_tls, align 856; CHECK-NEXT: call void @llvm.donothing()57; CHECK-NEXT: [[_MSPROP:%.*]] = trunc <8 x i16> [[TMP1]] to <8 x i8>58; CHECK-NEXT: [[TMP3:%.*]] = trunc <8 x i16> [[A]] to <8 x i8>59; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <8 x i8> [[TMP2]], <8 x i8> [[_MSPROP]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>60; CHECK-NEXT: [[RES:%.*]] = shufflevector <8 x i8> [[RET]], <8 x i8> [[TMP3]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>61; CHECK-NEXT: store <16 x i8> [[_MSPROP1]], ptr @__msan_retval_tls, align 862; CHECK-NEXT: ret <16 x i8> [[RES]]63;64 %tmpvar3 = trunc <8 x i16> %A to <8 x i8>65 %res = shufflevector <8 x i8> %ret, <8 x i8> %tmpvar3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>66 ret <16 x i8> %res67}68 69define <8 x i16> @xtn2_8h(<4 x i16> %ret, <4 x i32> %A) nounwind #0 {70; CHECK-LABEL: define <8 x i16> @xtn2_8h(71; CHECK-SAME: <4 x i16> [[RET:%.*]], <4 x i32> [[A:%.*]]) #[[ATTR0]] {72; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 873; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr @__msan_param_tls, align 874; CHECK-NEXT: call void @llvm.donothing()75; CHECK-NEXT: [[_MSPROP:%.*]] = trunc <4 x i32> [[TMP1]] to <4 x i16>76; CHECK-NEXT: [[TMP3:%.*]] = trunc <4 x i32> [[A]] to <4 x i16>77; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <4 x i16> [[TMP2]], <4 x i16> [[_MSPROP]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>78; CHECK-NEXT: [[RES:%.*]] = shufflevector <4 x i16> [[RET]], <4 x i16> [[TMP3]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>79; CHECK-NEXT: store <8 x i16> [[_MSPROP1]], ptr @__msan_retval_tls, align 880; CHECK-NEXT: ret <8 x i16> [[RES]]81;82 %tmpvar3 = trunc <4 x i32> %A to <4 x i16>83 %res = shufflevector <4 x i16> %ret, <4 x i16> %tmpvar3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>84 ret <8 x i16> %res85}86 87define <4 x i32> @xtn2_4s(<2 x i32> %ret, <2 x i64> %A) nounwind #0 {88; CHECK-LABEL: define <4 x i32> @xtn2_4s(89; CHECK-SAME: <2 x i32> [[RET:%.*]], <2 x i64> [[A:%.*]]) #[[ATTR0]] {90; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 891; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 892; CHECK-NEXT: call void @llvm.donothing()93; CHECK-NEXT: [[_MSPROP:%.*]] = trunc <2 x i64> [[TMP1]] to <2 x i32>94; CHECK-NEXT: [[TMP3:%.*]] = trunc <2 x i64> [[A]] to <2 x i32>95; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> [[_MSPROP]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>96; CHECK-NEXT: [[RES:%.*]] = shufflevector <2 x i32> [[RET]], <2 x i32> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>97; CHECK-NEXT: store <4 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 898; CHECK-NEXT: ret <4 x i32> [[RES]]99;100 %tmpvar3 = trunc <2 x i64> %A to <2 x i32>101 %res = shufflevector <2 x i32> %ret, <2 x i32> %tmpvar3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>102 ret <4 x i32> %res103}104 105define <8 x i8> @sqxtn8b(<8 x i16> %A) nounwind #0 {106; CHECK-LABEL: define <8 x i8> @sqxtn8b(107; CHECK-SAME: <8 x i16> [[A:%.*]]) #[[ATTR0]] {108; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8109; CHECK-NEXT: call void @llvm.donothing()110; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP1]], zeroinitializer111; CHECK-NEXT: [[TMP4:%.*]] = trunc <8 x i16> [[_MSPROP]] to <8 x i8>112; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqxtn.v8i8(<8 x i16> [[A]])113; CHECK-NEXT: store <8 x i8> [[TMP4]], ptr @__msan_retval_tls, align 8114; CHECK-NEXT: ret <8 x i8> [[TMP3]]115;116 %tmpvar3 = call <8 x i8> @llvm.aarch64.neon.sqxtn.v8i8(<8 x i16> %A)117 ret <8 x i8> %tmpvar3118}119 120define <4 x i16> @sqxtn4h(<4 x i32> %A) nounwind #0 {121; CHECK-LABEL: define <4 x i16> @sqxtn4h(122; CHECK-SAME: <4 x i32> [[A:%.*]]) #[[ATTR0]] {123; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8124; CHECK-NEXT: call void @llvm.donothing()125; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP1]], zeroinitializer126; CHECK-NEXT: [[TMP4:%.*]] = trunc <4 x i32> [[_MSPROP]] to <4 x i16>127; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32> [[A]])128; CHECK-NEXT: store <4 x i16> [[TMP4]], ptr @__msan_retval_tls, align 8129; CHECK-NEXT: ret <4 x i16> [[TMP3]]130;131 %tmpvar3 = call <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32> %A)132 ret <4 x i16> %tmpvar3133}134 135define <2 x i32> @sqxtn2s(<2 x i64> %A) nounwind #0 {136; CHECK-LABEL: define <2 x i32> @sqxtn2s(137; CHECK-SAME: <2 x i64> [[A:%.*]]) #[[ATTR0]] {138; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8139; CHECK-NEXT: call void @llvm.donothing()140; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP1]], zeroinitializer141; CHECK-NEXT: [[TMP4:%.*]] = trunc <2 x i64> [[_MSPROP]] to <2 x i32>142; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqxtn.v2i32(<2 x i64> [[A]])143; CHECK-NEXT: store <2 x i32> [[TMP4]], ptr @__msan_retval_tls, align 8144; CHECK-NEXT: ret <2 x i32> [[TMP3]]145;146 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.sqxtn.v2i32(<2 x i64> %A)147 ret <2 x i32> %tmpvar3148}149 150define <16 x i8> @sqxtn2_16b(<8 x i8> %ret, <8 x i16> %A) nounwind #0 {151; CHECK-LABEL: define <16 x i8> @sqxtn2_16b(152; CHECK-SAME: <8 x i8> [[RET:%.*]], <8 x i16> [[A:%.*]]) #[[ATTR0]] {153; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8154; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i8>, ptr @__msan_param_tls, align 8155; CHECK-NEXT: call void @llvm.donothing()156; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i16> [[TMP1]], zeroinitializer157; CHECK-NEXT: [[TMP5:%.*]] = trunc <8 x i16> [[_MSPROP1]] to <8 x i8>158; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqxtn.v8i8(<8 x i16> [[A]])159; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i8> [[TMP2]], <8 x i8> [[TMP5]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>160; CHECK-NEXT: [[RES:%.*]] = shufflevector <8 x i8> [[RET]], <8 x i8> [[TMP3]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>161; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8162; CHECK-NEXT: ret <16 x i8> [[RES]]163;164 %tmpvar3 = call <8 x i8> @llvm.aarch64.neon.sqxtn.v8i8(<8 x i16> %A)165 %res = shufflevector <8 x i8> %ret, <8 x i8> %tmpvar3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>166 ret <16 x i8> %res167}168 169define <8 x i16> @sqxtn2_8h(<4 x i16> %ret, <4 x i32> %A) nounwind #0 {170; CHECK-LABEL: define <8 x i16> @sqxtn2_8h(171; CHECK-SAME: <4 x i16> [[RET:%.*]], <4 x i32> [[A:%.*]]) #[[ATTR0]] {172; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8173; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr @__msan_param_tls, align 8174; CHECK-NEXT: call void @llvm.donothing()175; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[TMP1]], zeroinitializer176; CHECK-NEXT: [[TMP5:%.*]] = trunc <4 x i32> [[_MSPROP1]] to <4 x i16>177; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32> [[A]])178; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i16> [[TMP2]], <4 x i16> [[TMP5]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>179; CHECK-NEXT: [[RES:%.*]] = shufflevector <4 x i16> [[RET]], <4 x i16> [[TMP3]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>180; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8181; CHECK-NEXT: ret <8 x i16> [[RES]]182;183 %tmpvar3 = call <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32> %A)184 %res = shufflevector <4 x i16> %ret, <4 x i16> %tmpvar3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>185 ret <8 x i16> %res186}187 188define <4 x i32> @sqxtn2_4s(<2 x i32> %ret, <2 x i64> %A) nounwind #0 {189; CHECK-LABEL: define <4 x i32> @sqxtn2_4s(190; CHECK-SAME: <2 x i32> [[RET:%.*]], <2 x i64> [[A:%.*]]) #[[ATTR0]] {191; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8192; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8193; CHECK-NEXT: call void @llvm.donothing()194; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> [[TMP1]], zeroinitializer195; CHECK-NEXT: [[TMP4:%.*]] = trunc <2 x i64> [[_MSPROP1]] to <2 x i32>196; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqxtn.v2i32(<2 x i64> [[A]])197; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>198; CHECK-NEXT: [[RES:%.*]] = shufflevector <2 x i32> [[RET]], <2 x i32> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>199; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8200; CHECK-NEXT: ret <4 x i32> [[RES]]201;202 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.sqxtn.v2i32(<2 x i64> %A)203 %res = shufflevector <2 x i32> %ret, <2 x i32> %tmpvar3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>204 ret <4 x i32> %res205}206 207declare <8 x i8> @llvm.aarch64.neon.sqxtn.v8i8(<8 x i16>) nounwind readnone208declare <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32>) nounwind readnone209declare <2 x i32> @llvm.aarch64.neon.sqxtn.v2i32(<2 x i64>) nounwind readnone210 211define <8 x i8> @uqxtn8b(<8 x i16> %A) nounwind #0 {212; CHECK-LABEL: define <8 x i8> @uqxtn8b(213; CHECK-SAME: <8 x i16> [[A:%.*]]) #[[ATTR0]] {214; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8215; CHECK-NEXT: call void @llvm.donothing()216; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP1]], zeroinitializer217; CHECK-NEXT: [[TMP4:%.*]] = trunc <8 x i16> [[_MSPROP]] to <8 x i8>218; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqxtn.v8i8(<8 x i16> [[A]])219; CHECK-NEXT: store <8 x i8> [[TMP4]], ptr @__msan_retval_tls, align 8220; CHECK-NEXT: ret <8 x i8> [[TMP3]]221;222 %tmpvar3 = call <8 x i8> @llvm.aarch64.neon.uqxtn.v8i8(<8 x i16> %A)223 ret <8 x i8> %tmpvar3224}225 226define <4 x i16> @uqxtn4h(<4 x i32> %A) nounwind #0 {227; CHECK-LABEL: define <4 x i16> @uqxtn4h(228; CHECK-SAME: <4 x i32> [[A:%.*]]) #[[ATTR0]] {229; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8230; CHECK-NEXT: call void @llvm.donothing()231; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP1]], zeroinitializer232; CHECK-NEXT: [[TMP4:%.*]] = trunc <4 x i32> [[_MSPROP]] to <4 x i16>233; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32> [[A]])234; CHECK-NEXT: store <4 x i16> [[TMP4]], ptr @__msan_retval_tls, align 8235; CHECK-NEXT: ret <4 x i16> [[TMP3]]236;237 %tmpvar3 = call <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32> %A)238 ret <4 x i16> %tmpvar3239}240 241define <2 x i32> @uqxtn2s(<2 x i64> %A) nounwind #0 {242; CHECK-LABEL: define <2 x i32> @uqxtn2s(243; CHECK-SAME: <2 x i64> [[A:%.*]]) #[[ATTR0]] {244; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8245; CHECK-NEXT: call void @llvm.donothing()246; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP1]], zeroinitializer247; CHECK-NEXT: [[TMP4:%.*]] = trunc <2 x i64> [[_MSPROP]] to <2 x i32>248; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqxtn.v2i32(<2 x i64> [[A]])249; CHECK-NEXT: store <2 x i32> [[TMP4]], ptr @__msan_retval_tls, align 8250; CHECK-NEXT: ret <2 x i32> [[TMP3]]251;252 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.uqxtn.v2i32(<2 x i64> %A)253 ret <2 x i32> %tmpvar3254}255 256define <16 x i8> @uqxtn2_16b(<8 x i8> %ret, <8 x i16> %A) nounwind #0 {257; CHECK-LABEL: define <16 x i8> @uqxtn2_16b(258; CHECK-SAME: <8 x i8> [[RET:%.*]], <8 x i16> [[A:%.*]]) #[[ATTR0]] {259; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8260; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i8>, ptr @__msan_param_tls, align 8261; CHECK-NEXT: call void @llvm.donothing()262; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i16> [[TMP1]], zeroinitializer263; CHECK-NEXT: [[TMP5:%.*]] = trunc <8 x i16> [[_MSPROP1]] to <8 x i8>264; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqxtn.v8i8(<8 x i16> [[A]])265; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i8> [[TMP2]], <8 x i8> [[TMP5]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>266; CHECK-NEXT: [[RES:%.*]] = shufflevector <8 x i8> [[RET]], <8 x i8> [[TMP3]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>267; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8268; CHECK-NEXT: ret <16 x i8> [[RES]]269;270 %tmpvar3 = call <8 x i8> @llvm.aarch64.neon.uqxtn.v8i8(<8 x i16> %A)271 %res = shufflevector <8 x i8> %ret, <8 x i8> %tmpvar3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>272 ret <16 x i8> %res273}274 275define <8 x i16> @uqxtn2_8h(<4 x i16> %ret, <4 x i32> %A) nounwind #0 {276; CHECK-LABEL: define <8 x i16> @uqxtn2_8h(277; CHECK-SAME: <4 x i16> [[RET:%.*]], <4 x i32> [[A:%.*]]) #[[ATTR0]] {278; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8279; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr @__msan_param_tls, align 8280; CHECK-NEXT: call void @llvm.donothing()281; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[TMP1]], zeroinitializer282; CHECK-NEXT: [[TMP5:%.*]] = trunc <4 x i32> [[_MSPROP1]] to <4 x i16>283; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32> [[A]])284; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i16> [[TMP2]], <4 x i16> [[TMP5]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>285; CHECK-NEXT: [[RES:%.*]] = shufflevector <4 x i16> [[RET]], <4 x i16> [[TMP3]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>286; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8287; CHECK-NEXT: ret <8 x i16> [[RES]]288;289 %tmpvar3 = call <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32> %A)290 %res = shufflevector <4 x i16> %ret, <4 x i16> %tmpvar3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>291 ret <8 x i16> %res292}293 294define <4 x i32> @uqxtn2_4s(<2 x i32> %ret, <2 x i64> %A) nounwind #0 {295; CHECK-LABEL: define <4 x i32> @uqxtn2_4s(296; CHECK-SAME: <2 x i32> [[RET:%.*]], <2 x i64> [[A:%.*]]) #[[ATTR0]] {297; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8298; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8299; CHECK-NEXT: call void @llvm.donothing()300; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> [[TMP1]], zeroinitializer301; CHECK-NEXT: [[TMP4:%.*]] = trunc <2 x i64> [[_MSPROP1]] to <2 x i32>302; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqxtn.v2i32(<2 x i64> [[A]])303; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>304; CHECK-NEXT: [[RES:%.*]] = shufflevector <2 x i32> [[RET]], <2 x i32> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>305; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8306; CHECK-NEXT: ret <4 x i32> [[RES]]307;308 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.uqxtn.v2i32(<2 x i64> %A)309 %res = shufflevector <2 x i32> %ret, <2 x i32> %tmpvar3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>310 ret <4 x i32> %res311}312 313declare <8 x i8> @llvm.aarch64.neon.uqxtn.v8i8(<8 x i16>) nounwind readnone314declare <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32>) nounwind readnone315declare <2 x i32> @llvm.aarch64.neon.uqxtn.v2i32(<2 x i64>) nounwind readnone316 317define <8 x i8> @sqxtun8b(<8 x i16> %A) nounwind #0 {318; CHECK-LABEL: define <8 x i8> @sqxtun8b(319; CHECK-SAME: <8 x i16> [[A:%.*]]) #[[ATTR0]] {320; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8321; CHECK-NEXT: call void @llvm.donothing()322; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP1]], zeroinitializer323; CHECK-NEXT: [[TMP4:%.*]] = trunc <8 x i16> [[_MSPROP]] to <8 x i8>324; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqxtun.v8i8(<8 x i16> [[A]])325; CHECK-NEXT: store <8 x i8> [[TMP4]], ptr @__msan_retval_tls, align 8326; CHECK-NEXT: ret <8 x i8> [[TMP3]]327;328 %tmpvar3 = call <8 x i8> @llvm.aarch64.neon.sqxtun.v8i8(<8 x i16> %A)329 ret <8 x i8> %tmpvar3330}331 332define <4 x i16> @sqxtun4h(<4 x i32> %A) nounwind #0 {333; CHECK-LABEL: define <4 x i16> @sqxtun4h(334; CHECK-SAME: <4 x i32> [[A:%.*]]) #[[ATTR0]] {335; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8336; CHECK-NEXT: call void @llvm.donothing()337; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP1]], zeroinitializer338; CHECK-NEXT: [[TMP4:%.*]] = trunc <4 x i32> [[_MSPROP]] to <4 x i16>339; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32> [[A]])340; CHECK-NEXT: store <4 x i16> [[TMP4]], ptr @__msan_retval_tls, align 8341; CHECK-NEXT: ret <4 x i16> [[TMP3]]342;343 %tmpvar3 = call <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32> %A)344 ret <4 x i16> %tmpvar3345}346 347define <2 x i32> @sqxtun2s(<2 x i64> %A) nounwind #0 {348; CHECK-LABEL: define <2 x i32> @sqxtun2s(349; CHECK-SAME: <2 x i64> [[A:%.*]]) #[[ATTR0]] {350; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8351; CHECK-NEXT: call void @llvm.donothing()352; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP1]], zeroinitializer353; CHECK-NEXT: [[TMP4:%.*]] = trunc <2 x i64> [[_MSPROP]] to <2 x i32>354; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqxtun.v2i32(<2 x i64> [[A]])355; CHECK-NEXT: store <2 x i32> [[TMP4]], ptr @__msan_retval_tls, align 8356; CHECK-NEXT: ret <2 x i32> [[TMP3]]357;358 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.sqxtun.v2i32(<2 x i64> %A)359 ret <2 x i32> %tmpvar3360}361 362define <16 x i8> @sqxtun2_16b(<8 x i8> %ret, <8 x i16> %A) nounwind #0 {363; CHECK-LABEL: define <16 x i8> @sqxtun2_16b(364; CHECK-SAME: <8 x i8> [[RET:%.*]], <8 x i16> [[A:%.*]]) #[[ATTR0]] {365; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8366; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i8>, ptr @__msan_param_tls, align 8367; CHECK-NEXT: call void @llvm.donothing()368; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i16> [[TMP1]], zeroinitializer369; CHECK-NEXT: [[TMP5:%.*]] = trunc <8 x i16> [[_MSPROP1]] to <8 x i8>370; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqxtun.v8i8(<8 x i16> [[A]])371; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i8> [[TMP2]], <8 x i8> [[TMP5]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>372; CHECK-NEXT: [[RES:%.*]] = shufflevector <8 x i8> [[RET]], <8 x i8> [[TMP3]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>373; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8374; CHECK-NEXT: ret <16 x i8> [[RES]]375;376 %tmpvar3 = call <8 x i8> @llvm.aarch64.neon.sqxtun.v8i8(<8 x i16> %A)377 %res = shufflevector <8 x i8> %ret, <8 x i8> %tmpvar3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>378 ret <16 x i8> %res379}380 381define <8 x i16> @sqxtun2_8h(<4 x i16> %ret, <4 x i32> %A) nounwind #0 {382; CHECK-LABEL: define <8 x i16> @sqxtun2_8h(383; CHECK-SAME: <4 x i16> [[RET:%.*]], <4 x i32> [[A:%.*]]) #[[ATTR0]] {384; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8385; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr @__msan_param_tls, align 8386; CHECK-NEXT: call void @llvm.donothing()387; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[TMP1]], zeroinitializer388; CHECK-NEXT: [[TMP5:%.*]] = trunc <4 x i32> [[_MSPROP1]] to <4 x i16>389; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32> [[A]])390; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i16> [[TMP2]], <4 x i16> [[TMP5]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>391; CHECK-NEXT: [[RES:%.*]] = shufflevector <4 x i16> [[RET]], <4 x i16> [[TMP3]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>392; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8393; CHECK-NEXT: ret <8 x i16> [[RES]]394;395 %tmpvar3 = call <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32> %A)396 %res = shufflevector <4 x i16> %ret, <4 x i16> %tmpvar3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>397 ret <8 x i16> %res398}399 400define <4 x i32> @sqxtun2_4s(<2 x i32> %ret, <2 x i64> %A) nounwind #0 {401; CHECK-LABEL: define <4 x i32> @sqxtun2_4s(402; CHECK-SAME: <2 x i32> [[RET:%.*]], <2 x i64> [[A:%.*]]) #[[ATTR0]] {403; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8404; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 8405; CHECK-NEXT: call void @llvm.donothing()406; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> [[TMP1]], zeroinitializer407; CHECK-NEXT: [[TMP4:%.*]] = trunc <2 x i64> [[_MSPROP1]] to <2 x i32>408; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqxtun.v2i32(<2 x i64> [[A]])409; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> [[TMP4]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>410; CHECK-NEXT: [[RES:%.*]] = shufflevector <2 x i32> [[RET]], <2 x i32> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>411; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8412; CHECK-NEXT: ret <4 x i32> [[RES]]413;414 %tmpvar3 = call <2 x i32> @llvm.aarch64.neon.sqxtun.v2i32(<2 x i64> %A)415 %res = shufflevector <2 x i32> %ret, <2 x i32> %tmpvar3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>416 ret <4 x i32> %res417}418 419declare <8 x i8> @llvm.aarch64.neon.sqxtun.v8i8(<8 x i16>) nounwind readnone420declare <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32>) nounwind readnone421declare <2 x i32> @llvm.aarch64.neon.sqxtun.v2i32(<2 x i64>) nounwind readnone422 423attributes #0 = { sanitize_memory }424