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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt < %s -passes=msan -S | FileCheck %s3;4; Test memory sanitizer instrumentation for Arm vector multiplication5; instructions.6;7; Forked from llvm/test/CodeGen/AArch64/arm64-vmul.ll8 9target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"10target triple = "aarch64--linux-android9001"11 12define <8 x i16> @smull8h(ptr %A, ptr %B) nounwind sanitize_memory {13; CHECK-LABEL: define <8 x i16> @smull8h(14; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {15; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_param_tls, align 816; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 817; CHECK-NEXT: call void @llvm.donothing()18; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 019; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1:![0-9]+]]20; CHECK: [[BB3]]:21; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8:[0-9]+]]22; CHECK-NEXT: unreachable23; CHECK: [[BB4]]:24; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[A]], align 825; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i6426; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 19351404648857627; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr28; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 829; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP8]], 030; CHECK-NEXT: br i1 [[_MSCMP3]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]31; CHECK: [[BB8]]:32; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]33; CHECK-NEXT: unreachable34; CHECK: [[BB9]]:35; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i8>, ptr [[B]], align 836; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i6437; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 19351404648857638; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr39; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP12]], align 840; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i8> [[_MSLD]], [[_MSLD1]]41; CHECK-NEXT: [[_MSPROP2:%.*]] = or <8 x i8> [[_MSPROP]], zeroinitializer42; CHECK-NEXT: [[TMP13:%.*]] = zext <8 x i8> [[_MSPROP2]] to <8 x i16>43; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> [[TMP1]], <8 x i8> [[TMP2]])44; CHECK-NEXT: store <8 x i16> [[TMP13]], ptr @__msan_retval_tls, align 845; CHECK-NEXT: ret <8 x i16> [[TMP3]]46;47 %temp1 = load <8 x i8>, ptr %A48 %temp2 = load <8 x i8>, ptr %B49 %temp3 = call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> %temp1, <8 x i8> %temp2)50 ret <8 x i16> %temp351}52 53define <4 x i32> @smull4s(ptr %A, ptr %B) nounwind sanitize_memory {54; CHECK-LABEL: define <4 x i32> @smull4s(55; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {56; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_param_tls, align 857; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 858; CHECK-NEXT: call void @llvm.donothing()59; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 060; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]61; CHECK: [[BB3]]:62; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]63; CHECK-NEXT: unreachable64; CHECK: [[BB4]]:65; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 866; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i6467; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 19351404648857668; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr69; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 870; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP8]], 071; CHECK-NEXT: br i1 [[_MSCMP3]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]72; CHECK: [[BB8]]:73; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]74; CHECK-NEXT: unreachable75; CHECK: [[BB9]]:76; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr [[B]], align 877; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i6478; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 19351404648857679; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr80; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 881; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[_MSLD]], [[_MSLD1]]82; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i16> [[_MSPROP]], zeroinitializer83; CHECK-NEXT: [[TMP13:%.*]] = zext <4 x i16> [[_MSPROP2]] to <4 x i32>84; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[TMP1]], <4 x i16> [[TMP2]])85; CHECK-NEXT: store <4 x i32> [[TMP13]], ptr @__msan_retval_tls, align 886; CHECK-NEXT: ret <4 x i32> [[TMP3]]87;88 %temp1 = load <4 x i16>, ptr %A89 %temp2 = load <4 x i16>, ptr %B90 %temp3 = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %temp1, <4 x i16> %temp2)91 ret <4 x i32> %temp392}93 94define <2 x i64> @smull2d(ptr %A, ptr %B) nounwind sanitize_memory {95; CHECK-LABEL: define <2 x i64> @smull2d(96; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {97; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_param_tls, align 898; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 899; CHECK-NEXT: call void @llvm.donothing()100; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 0101; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]102; CHECK: [[BB3]]:103; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]104; CHECK-NEXT: unreachable105; CHECK: [[BB4]]:106; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 8107; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64108; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576109; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr110; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 8111; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP8]], 0112; CHECK-NEXT: br i1 [[_MSCMP3]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]113; CHECK: [[BB8]]:114; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]115; CHECK-NEXT: unreachable116; CHECK: [[BB9]]:117; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr [[B]], align 8118; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64119; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576120; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr121; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 8122; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[_MSLD]], [[_MSLD1]]123; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i32> [[_MSPROP]], zeroinitializer124; CHECK-NEXT: [[TMP13:%.*]] = zext <2 x i32> [[_MSPROP2]] to <2 x i64>125; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]])126; CHECK-NEXT: store <2 x i64> [[TMP13]], ptr @__msan_retval_tls, align 8127; CHECK-NEXT: ret <2 x i64> [[TMP3]]128;129 %temp1 = load <2 x i32>, ptr %A130 %temp2 = load <2 x i32>, ptr %B131 %temp3 = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %temp1, <2 x i32> %temp2)132 ret <2 x i64> %temp3133}134 135declare <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8>, <8 x i8>) nounwind readnone136declare <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone137declare <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32>, <2 x i32>) nounwind readnone138 139define <8 x i16> @umull8h(ptr %A, ptr %B) nounwind sanitize_memory {140; CHECK-LABEL: define <8 x i16> @umull8h(141; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {142; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_param_tls, align 8143; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8144; CHECK-NEXT: call void @llvm.donothing()145; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 0146; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]147; CHECK: [[BB3]]:148; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]149; CHECK-NEXT: unreachable150; CHECK: [[BB4]]:151; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[A]], align 8152; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64153; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576154; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr155; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 8156; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP8]], 0157; CHECK-NEXT: br i1 [[_MSCMP3]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]158; CHECK: [[BB8]]:159; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]160; CHECK-NEXT: unreachable161; CHECK: [[BB9]]:162; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i8>, ptr [[B]], align 8163; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64164; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576165; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr166; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP12]], align 8167; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i8> [[_MSLD]], [[_MSLD1]]168; CHECK-NEXT: [[_MSPROP2:%.*]] = or <8 x i8> [[_MSPROP]], zeroinitializer169; CHECK-NEXT: [[TMP13:%.*]] = zext <8 x i8> [[_MSPROP2]] to <8 x i16>170; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> [[TMP1]], <8 x i8> [[TMP2]])171; CHECK-NEXT: store <8 x i16> [[TMP13]], ptr @__msan_retval_tls, align 8172; CHECK-NEXT: ret <8 x i16> [[TMP3]]173;174 %temp1 = load <8 x i8>, ptr %A175 %temp2 = load <8 x i8>, ptr %B176 %temp3 = call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> %temp1, <8 x i8> %temp2)177 ret <8 x i16> %temp3178}179 180define <4 x i32> @umull4s(ptr %A, ptr %B) nounwind sanitize_memory {181; CHECK-LABEL: define <4 x i32> @umull4s(182; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {183; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_param_tls, align 8184; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8185; CHECK-NEXT: call void @llvm.donothing()186; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 0187; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]188; CHECK: [[BB3]]:189; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]190; CHECK-NEXT: unreachable191; CHECK: [[BB4]]:192; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 8193; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64194; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576195; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr196; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 8197; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP8]], 0198; CHECK-NEXT: br i1 [[_MSCMP3]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]199; CHECK: [[BB8]]:200; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]201; CHECK-NEXT: unreachable202; CHECK: [[BB9]]:203; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr [[B]], align 8204; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64205; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576206; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr207; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 8208; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[_MSLD]], [[_MSLD1]]209; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i16> [[_MSPROP]], zeroinitializer210; CHECK-NEXT: [[TMP13:%.*]] = zext <4 x i16> [[_MSPROP2]] to <4 x i32>211; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[TMP1]], <4 x i16> [[TMP2]])212; CHECK-NEXT: store <4 x i32> [[TMP13]], ptr @__msan_retval_tls, align 8213; CHECK-NEXT: ret <4 x i32> [[TMP3]]214;215 %temp1 = load <4 x i16>, ptr %A216 %temp2 = load <4 x i16>, ptr %B217 %temp3 = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %temp1, <4 x i16> %temp2)218 ret <4 x i32> %temp3219}220 221define <2 x i64> @umull2d(ptr %A, ptr %B) nounwind sanitize_memory {222; CHECK-LABEL: define <2 x i64> @umull2d(223; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {224; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_param_tls, align 8225; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8226; CHECK-NEXT: call void @llvm.donothing()227; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 0228; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]229; CHECK: [[BB3]]:230; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]231; CHECK-NEXT: unreachable232; CHECK: [[BB4]]:233; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 8234; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64235; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576236; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr237; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 8238; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP8]], 0239; CHECK-NEXT: br i1 [[_MSCMP3]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]240; CHECK: [[BB8]]:241; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]242; CHECK-NEXT: unreachable243; CHECK: [[BB9]]:244; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr [[B]], align 8245; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64246; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576247; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr248; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 8249; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[_MSLD]], [[_MSLD1]]250; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i32> [[_MSPROP]], zeroinitializer251; CHECK-NEXT: [[TMP13:%.*]] = zext <2 x i32> [[_MSPROP2]] to <2 x i64>252; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]])253; CHECK-NEXT: store <2 x i64> [[TMP13]], ptr @__msan_retval_tls, align 8254; CHECK-NEXT: ret <2 x i64> [[TMP3]]255;256 %temp1 = load <2 x i32>, ptr %A257 %temp2 = load <2 x i32>, ptr %B258 %temp3 = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %temp1, <2 x i32> %temp2)259 ret <2 x i64> %temp3260}261 262declare <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8>, <8 x i8>) nounwind readnone263declare <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone264declare <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32>, <2 x i32>) nounwind readnone265 266define <4 x i32> @sqdmull4s(ptr %A, ptr %B) nounwind sanitize_memory {267; CHECK-LABEL: define <4 x i32> @sqdmull4s(268; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {269; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_param_tls, align 8270; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8271; CHECK-NEXT: call void @llvm.donothing()272; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 0273; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]274; CHECK: [[BB3]]:275; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]276; CHECK-NEXT: unreachable277; CHECK: [[BB4]]:278; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 8279; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64280; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576281; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr282; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 8283; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP8]], 0284; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]285; CHECK: [[BB8]]:286; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]287; CHECK-NEXT: unreachable288; CHECK: [[BB9]]:289; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr [[B]], align 8290; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64291; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576292; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr293; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 8294; CHECK-NEXT: [[TMP13:%.*]] = bitcast <4 x i16> [[_MSLD]] to i64295; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP13]], 0296; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i16> [[_MSLD1]] to i64297; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP14]], 0298; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP3]], [[_MSCMP4]]299; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB15:.*]], label %[[BB16:.*]], !prof [[PROF1]]300; CHECK: [[BB15]]:301; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]302; CHECK-NEXT: unreachable303; CHECK: [[BB16]]:304; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[TMP1]], <4 x i16> [[TMP2]])305; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8306; CHECK-NEXT: ret <4 x i32> [[TMP3]]307;308 %temp1 = load <4 x i16>, ptr %A309 %temp2 = load <4 x i16>, ptr %B310 %temp3 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %temp1, <4 x i16> %temp2)311 ret <4 x i32> %temp3312}313 314define <2 x i64> @sqdmull2d(ptr %A, ptr %B) nounwind sanitize_memory {315; CHECK-LABEL: define <2 x i64> @sqdmull2d(316; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {317; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_param_tls, align 8318; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8319; CHECK-NEXT: call void @llvm.donothing()320; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 0321; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]322; CHECK: [[BB3]]:323; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]324; CHECK-NEXT: unreachable325; CHECK: [[BB4]]:326; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 8327; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64328; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576329; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr330; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 8331; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP8]], 0332; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]333; CHECK: [[BB8]]:334; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]335; CHECK-NEXT: unreachable336; CHECK: [[BB9]]:337; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr [[B]], align 8338; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64339; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576340; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr341; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 8342; CHECK-NEXT: [[TMP13:%.*]] = bitcast <2 x i32> [[_MSLD]] to i64343; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP13]], 0344; CHECK-NEXT: [[TMP14:%.*]] = bitcast <2 x i32> [[_MSLD1]] to i64345; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP14]], 0346; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP3]], [[_MSCMP4]]347; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB15:.*]], label %[[BB16:.*]], !prof [[PROF1]]348; CHECK: [[BB15]]:349; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]350; CHECK-NEXT: unreachable351; CHECK: [[BB16]]:352; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]])353; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8354; CHECK-NEXT: ret <2 x i64> [[TMP3]]355;356 %temp1 = load <2 x i32>, ptr %A357 %temp2 = load <2 x i32>, ptr %B358 %temp3 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %temp1, <2 x i32> %temp2)359 ret <2 x i64> %temp3360}361 362define <4 x i32> @sqdmull2_4s(ptr %A, ptr %B) nounwind sanitize_memory {363; CHECK-LABEL: define <4 x i32> @sqdmull2_4s(364; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {365; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_param_tls, align 8366; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8367; CHECK-NEXT: call void @llvm.donothing()368; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 0369; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]370; CHECK: [[BB3]]:371; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]372; CHECK-NEXT: unreachable373; CHECK: [[BB4]]:374; CHECK-NEXT: [[LOAD1:%.*]] = load <8 x i16>, ptr [[A]], align 16375; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64376; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576377; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr378; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 16379; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP8]], 0380; CHECK-NEXT: br i1 [[_MSCMP3]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]381; CHECK: [[BB8]]:382; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]383; CHECK-NEXT: unreachable384; CHECK: [[BB9]]:385; CHECK-NEXT: [[LOAD2:%.*]] = load <8 x i16>, ptr [[B]], align 16386; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64387; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576388; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr389; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 16390; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i16> [[_MSLD]], <8 x i16> splat (i16 -1), <4 x i32> <i32 4, i32 5, i32 6, i32 7>391; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i16> [[LOAD1]], <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>392; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <8 x i16> [[_MSLD1]], <8 x i16> splat (i16 -1), <4 x i32> <i32 4, i32 5, i32 6, i32 7>393; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i16> [[LOAD2]], <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>394; CHECK-NEXT: [[TMP13:%.*]] = bitcast <4 x i16> [[_MSPROP]] to i64395; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP13]], 0396; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i16> [[_MSPROP2]] to i64397; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i64 [[TMP14]], 0398; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP4]], [[_MSCMP5]]399; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB15:.*]], label %[[BB16:.*]], !prof [[PROF1]]400; CHECK: [[BB15]]:401; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]402; CHECK-NEXT: unreachable403; CHECK: [[BB16]]:404; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[TMP1]], <4 x i16> [[TMP2]])405; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 8406; CHECK-NEXT: ret <4 x i32> [[TMP3]]407;408 %load1 = load <8 x i16>, ptr %A409 %load2 = load <8 x i16>, ptr %B410 %temp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>411 %temp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>412 %temp3 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %temp1, <4 x i16> %temp2)413 ret <4 x i32> %temp3414}415 416define <2 x i64> @sqdmull2_2d(ptr %A, ptr %B) nounwind sanitize_memory {417; CHECK-LABEL: define <2 x i64> @sqdmull2_2d(418; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {419; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_param_tls, align 8420; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8421; CHECK-NEXT: call void @llvm.donothing()422; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 0423; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]424; CHECK: [[BB3]]:425; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]426; CHECK-NEXT: unreachable427; CHECK: [[BB4]]:428; CHECK-NEXT: [[LOAD1:%.*]] = load <4 x i32>, ptr [[A]], align 16429; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64430; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576431; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr432; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 16433; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP8]], 0434; CHECK-NEXT: br i1 [[_MSCMP3]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]435; CHECK: [[BB8]]:436; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]437; CHECK-NEXT: unreachable438; CHECK: [[BB9]]:439; CHECK-NEXT: [[LOAD2:%.*]] = load <4 x i32>, ptr [[B]], align 16440; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64441; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576442; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr443; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 16444; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> splat (i32 -1), <2 x i32> <i32 2, i32 3>445; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[LOAD1]], <4 x i32> undef, <2 x i32> <i32 2, i32 3>446; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <4 x i32> [[_MSLD1]], <4 x i32> splat (i32 -1), <2 x i32> <i32 2, i32 3>447; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[LOAD2]], <4 x i32> undef, <2 x i32> <i32 2, i32 3>448; CHECK-NEXT: [[TMP13:%.*]] = bitcast <2 x i32> [[_MSPROP]] to i64449; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP13]], 0450; CHECK-NEXT: [[TMP14:%.*]] = bitcast <2 x i32> [[_MSPROP2]] to i64451; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i64 [[TMP14]], 0452; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP4]], [[_MSCMP5]]453; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB15:.*]], label %[[BB16:.*]], !prof [[PROF1]]454; CHECK: [[BB15]]:455; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]456; CHECK-NEXT: unreachable457; CHECK: [[BB16]]:458; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]])459; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 8460; CHECK-NEXT: ret <2 x i64> [[TMP3]]461;462 %load1 = load <4 x i32>, ptr %A463 %load2 = load <4 x i32>, ptr %B464 %temp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>465 %temp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>466 %temp3 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %temp1, <2 x i32> %temp2)467 ret <2 x i64> %temp3468}469 470 471declare <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16>, <4 x i16>) nounwind readnone472declare <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32>, <2 x i32>) nounwind readnone473 474define <8 x i16> @pmull8h(ptr %A, ptr %B) nounwind sanitize_memory {475; CHECK-LABEL: define <8 x i16> @pmull8h(476; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {477; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_param_tls, align 8478; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8479; CHECK-NEXT: call void @llvm.donothing()480; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 0481; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]482; CHECK: [[BB3]]:483; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]484; CHECK-NEXT: unreachable485; CHECK: [[BB4]]:486; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[A]], align 8487; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64488; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576489; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr490; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 8491; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP8]], 0492; CHECK-NEXT: br i1 [[_MSCMP3]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]493; CHECK: [[BB8]]:494; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]495; CHECK-NEXT: unreachable496; CHECK: [[BB9]]:497; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i8>, ptr [[B]], align 8498; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64499; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576500; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr501; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP12]], align 8502; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i8> [[_MSLD]], [[_MSLD1]]503; CHECK-NEXT: [[_MSPROP2:%.*]] = or <8 x i8> [[_MSPROP]], zeroinitializer504; CHECK-NEXT: [[TMP13:%.*]] = zext <8 x i8> [[_MSPROP2]] to <8 x i16>505; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> [[TMP1]], <8 x i8> [[TMP2]])506; CHECK-NEXT: store <8 x i16> [[TMP13]], ptr @__msan_retval_tls, align 8507; CHECK-NEXT: ret <8 x i16> [[TMP3]]508;509 %temp1 = load <8 x i8>, ptr %A510 %temp2 = load <8 x i8>, ptr %B511 %temp3 = call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> %temp1, <8 x i8> %temp2)512 ret <8 x i16> %temp3513}514 515declare <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8>, <8 x i8>) nounwind readnone516 517define <4 x i16> @sqdmulh_4h(ptr %A, ptr %B) nounwind sanitize_memory {518; CHECK-LABEL: define <4 x i16> @sqdmulh_4h(519; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {520; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_param_tls, align 8521; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8522; CHECK-NEXT: call void @llvm.donothing()523; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 0524; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]525; CHECK: [[BB3]]:526; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]527; CHECK-NEXT: unreachable528; CHECK: [[BB4]]:529; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 8530; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64531; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576532; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr533; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 8534; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP8]], 0535; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]536; CHECK: [[BB8]]:537; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]538; CHECK-NEXT: unreachable539; CHECK: [[BB9]]:540; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr [[B]], align 8541; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64542; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576543; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr544; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 8545; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[_MSLD]], [[_MSLD1]]546; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqdmulh.v4i16(<4 x i16> [[TMP1]], <4 x i16> [[TMP2]])547; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8548; CHECK-NEXT: ret <4 x i16> [[TMP3]]549;550 %temp1 = load <4 x i16>, ptr %A551 %temp2 = load <4 x i16>, ptr %B552 %temp3 = call <4 x i16> @llvm.aarch64.neon.sqdmulh.v4i16(<4 x i16> %temp1, <4 x i16> %temp2)553 ret <4 x i16> %temp3554}555 556define <8 x i16> @sqdmulh_8h(ptr %A, ptr %B) nounwind sanitize_memory {557; CHECK-LABEL: define <8 x i16> @sqdmulh_8h(558; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {559; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_param_tls, align 8560; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8561; CHECK-NEXT: call void @llvm.donothing()562; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 0563; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]564; CHECK: [[BB3]]:565; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]566; CHECK-NEXT: unreachable567; CHECK: [[BB4]]:568; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 16569; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64570; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576571; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr572; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 16573; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP8]], 0574; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]575; CHECK: [[BB8]]:576; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]577; CHECK-NEXT: unreachable578; CHECK: [[BB9]]:579; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr [[B]], align 16580; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64581; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576582; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr583; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 16584; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[_MSLD]], [[_MSLD1]]585; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqdmulh.v8i16(<8 x i16> [[TMP1]], <8 x i16> [[TMP2]])586; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8587; CHECK-NEXT: ret <8 x i16> [[TMP3]]588;589 %temp1 = load <8 x i16>, ptr %A590 %temp2 = load <8 x i16>, ptr %B591 %temp3 = call <8 x i16> @llvm.aarch64.neon.sqdmulh.v8i16(<8 x i16> %temp1, <8 x i16> %temp2)592 ret <8 x i16> %temp3593}594 595define <2 x i32> @sqdmulh_2s(ptr %A, ptr %B) nounwind sanitize_memory {596; CHECK-LABEL: define <2 x i32> @sqdmulh_2s(597; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {598; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_param_tls, align 8599; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8600; CHECK-NEXT: call void @llvm.donothing()601; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 0602; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]603; CHECK: [[BB3]]:604; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]605; CHECK-NEXT: unreachable606; CHECK: [[BB4]]:607; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 8608; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64609; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576610; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr611; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 8612; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP8]], 0613; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]614; CHECK: [[BB8]]:615; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]616; CHECK-NEXT: unreachable617; CHECK: [[BB9]]:618; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr [[B]], align 8619; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64620; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576621; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr622; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 8623; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[_MSLD]], [[_MSLD1]]624; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]])625; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8626; CHECK-NEXT: ret <2 x i32> [[TMP3]]627;628 %temp1 = load <2 x i32>, ptr %A629 %temp2 = load <2 x i32>, ptr %B630 %temp3 = call <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32> %temp1, <2 x i32> %temp2)631 ret <2 x i32> %temp3632}633 634define <4 x i32> @sqdmulh_4s(ptr %A, ptr %B) nounwind sanitize_memory {635; CHECK-LABEL: define <4 x i32> @sqdmulh_4s(636; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {637; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_param_tls, align 8638; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8639; CHECK-NEXT: call void @llvm.donothing()640; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 0641; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]642; CHECK: [[BB3]]:643; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]644; CHECK-NEXT: unreachable645; CHECK: [[BB4]]:646; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 16647; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64648; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576649; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr650; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 16651; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP8]], 0652; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]653; CHECK: [[BB8]]:654; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]655; CHECK-NEXT: unreachable656; CHECK: [[BB9]]:657; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr [[B]], align 16658; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64659; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576660; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr661; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 16662; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[_MSLD]], [[_MSLD1]]663; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmulh.v4i32(<4 x i32> [[TMP1]], <4 x i32> [[TMP2]])664; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8665; CHECK-NEXT: ret <4 x i32> [[TMP3]]666;667 %temp1 = load <4 x i32>, ptr %A668 %temp2 = load <4 x i32>, ptr %B669 %temp3 = call <4 x i32> @llvm.aarch64.neon.sqdmulh.v4i32(<4 x i32> %temp1, <4 x i32> %temp2)670 ret <4 x i32> %temp3671}672 673define i32 @sqdmulh_1s(ptr %A, ptr %B) nounwind sanitize_memory {674; CHECK-LABEL: define i32 @sqdmulh_1s(675; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {676; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_param_tls, align 8677; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8678; CHECK-NEXT: call void @llvm.donothing()679; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 0680; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]681; CHECK: [[BB3]]:682; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]683; CHECK-NEXT: unreachable684; CHECK: [[BB4]]:685; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4686; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64687; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576688; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr689; CHECK-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP7]], align 4690; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP8]], 0691; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]692; CHECK: [[BB8]]:693; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]694; CHECK-NEXT: unreachable695; CHECK: [[BB9]]:696; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[B]], align 4697; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64698; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576699; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr700; CHECK-NEXT: [[_MSLD1:%.*]] = load i32, ptr [[TMP12]], align 4701; CHECK-NEXT: [[_MSPROP:%.*]] = or i32 [[_MSLD]], [[_MSLD1]]702; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.aarch64.neon.sqdmulh.i32(i32 [[TMP1]], i32 [[TMP2]])703; CHECK-NEXT: store i32 [[_MSPROP]], ptr @__msan_retval_tls, align 8704; CHECK-NEXT: ret i32 [[TMP3]]705;706 %temp1 = load i32, ptr %A707 %temp2 = load i32, ptr %B708 %temp3 = call i32 @llvm.aarch64.neon.sqdmulh.i32(i32 %temp1, i32 %temp2)709 ret i32 %temp3710}711 712declare <4 x i16> @llvm.aarch64.neon.sqdmulh.v4i16(<4 x i16>, <4 x i16>) nounwind readnone713declare <8 x i16> @llvm.aarch64.neon.sqdmulh.v8i16(<8 x i16>, <8 x i16>) nounwind readnone714declare <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32>, <2 x i32>) nounwind readnone715declare <4 x i32> @llvm.aarch64.neon.sqdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind readnone716declare i32 @llvm.aarch64.neon.sqdmulh.i32(i32, i32) nounwind readnone717 718define <4 x i16> @sqrdmulh_4h(ptr %A, ptr %B) nounwind sanitize_memory {719; CHECK-LABEL: define <4 x i16> @sqrdmulh_4h(720; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {721; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_param_tls, align 8722; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8723; CHECK-NEXT: call void @llvm.donothing()724; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 0725; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]726; CHECK: [[BB3]]:727; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]728; CHECK-NEXT: unreachable729; CHECK: [[BB4]]:730; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 8731; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64732; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576733; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr734; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 8735; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP8]], 0736; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]737; CHECK: [[BB8]]:738; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]739; CHECK-NEXT: unreachable740; CHECK: [[BB9]]:741; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr [[B]], align 8742; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64743; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576744; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr745; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 8746; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[_MSLD]], [[_MSLD1]]747; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> [[TMP1]], <4 x i16> [[TMP2]])748; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8749; CHECK-NEXT: ret <4 x i16> [[TMP3]]750;751 %temp1 = load <4 x i16>, ptr %A752 %temp2 = load <4 x i16>, ptr %B753 %temp3 = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %temp1, <4 x i16> %temp2)754 ret <4 x i16> %temp3755}756 757define <8 x i16> @sqrdmulh_8h(ptr %A, ptr %B) nounwind sanitize_memory {758; CHECK-LABEL: define <8 x i16> @sqrdmulh_8h(759; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {760; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_param_tls, align 8761; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8762; CHECK-NEXT: call void @llvm.donothing()763; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 0764; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]765; CHECK: [[BB3]]:766; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]767; CHECK-NEXT: unreachable768; CHECK: [[BB4]]:769; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 16770; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64771; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576772; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr773; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 16774; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP8]], 0775; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]776; CHECK: [[BB8]]:777; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]778; CHECK-NEXT: unreachable779; CHECK: [[BB9]]:780; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr [[B]], align 16781; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64782; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576783; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr784; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 16785; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[_MSLD]], [[_MSLD1]]786; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> [[TMP1]], <8 x i16> [[TMP2]])787; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8788; CHECK-NEXT: ret <8 x i16> [[TMP3]]789;790 %temp1 = load <8 x i16>, ptr %A791 %temp2 = load <8 x i16>, ptr %B792 %temp3 = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %temp1, <8 x i16> %temp2)793 ret <8 x i16> %temp3794}795 796define <2 x i32> @sqrdmulh_2s(ptr %A, ptr %B) nounwind sanitize_memory {797; CHECK-LABEL: define <2 x i32> @sqrdmulh_2s(798; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {799; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_param_tls, align 8800; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8801; CHECK-NEXT: call void @llvm.donothing()802; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 0803; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]804; CHECK: [[BB3]]:805; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]806; CHECK-NEXT: unreachable807; CHECK: [[BB4]]:808; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 8809; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64810; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576811; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr812; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 8813; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP8]], 0814; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]815; CHECK: [[BB8]]:816; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]817; CHECK-NEXT: unreachable818; CHECK: [[BB9]]:819; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr [[B]], align 8820; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64821; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576822; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr823; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 8824; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[_MSLD]], [[_MSLD1]]825; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]])826; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8827; CHECK-NEXT: ret <2 x i32> [[TMP3]]828;829 %temp1 = load <2 x i32>, ptr %A830 %temp2 = load <2 x i32>, ptr %B831 %temp3 = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> %temp1, <2 x i32> %temp2)832 ret <2 x i32> %temp3833}834 835define <4 x i32> @sqrdmulh_4s(ptr %A, ptr %B) nounwind sanitize_memory {836; CHECK-LABEL: define <4 x i32> @sqrdmulh_4s(837; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {838; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_param_tls, align 8839; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8840; CHECK-NEXT: call void @llvm.donothing()841; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 0842; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]843; CHECK: [[BB3]]:844; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]845; CHECK-NEXT: unreachable846; CHECK: [[BB4]]:847; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 16848; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64849; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576850; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr851; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 16852; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP8]], 0853; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]854; CHECK: [[BB8]]:855; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]856; CHECK-NEXT: unreachable857; CHECK: [[BB9]]:858; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr [[B]], align 16859; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64860; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576861; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr862; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 16863; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[_MSLD]], [[_MSLD1]]864; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> [[TMP1]], <4 x i32> [[TMP2]])865; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8866; CHECK-NEXT: ret <4 x i32> [[TMP3]]867;868 %temp1 = load <4 x i32>, ptr %A869 %temp2 = load <4 x i32>, ptr %B870 %temp3 = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %temp1, <4 x i32> %temp2)871 ret <4 x i32> %temp3872}873 874define i32 @sqrdmulh_1s(ptr %A, ptr %B) nounwind sanitize_memory {875; CHECK-LABEL: define i32 @sqrdmulh_1s(876; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {877; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_param_tls, align 8878; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8879; CHECK-NEXT: call void @llvm.donothing()880; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 0881; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]882; CHECK: [[BB3]]:883; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]884; CHECK-NEXT: unreachable885; CHECK: [[BB4]]:886; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 4887; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64888; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576889; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr890; CHECK-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP7]], align 4891; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP8]], 0892; CHECK-NEXT: br i1 [[_MSCMP2]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]893; CHECK: [[BB8]]:894; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]895; CHECK-NEXT: unreachable896; CHECK: [[BB9]]:897; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[B]], align 4898; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64899; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576900; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr901; CHECK-NEXT: [[_MSLD1:%.*]] = load i32, ptr [[TMP12]], align 4902; CHECK-NEXT: [[_MSPROP:%.*]] = or i32 [[_MSLD]], [[_MSLD1]]903; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.aarch64.neon.sqrdmulh.i32(i32 [[TMP1]], i32 [[TMP2]])904; CHECK-NEXT: store i32 [[_MSPROP]], ptr @__msan_retval_tls, align 8905; CHECK-NEXT: ret i32 [[TMP3]]906;907 %temp1 = load i32, ptr %A908 %temp2 = load i32, ptr %B909 %temp3 = call i32 @llvm.aarch64.neon.sqrdmulh.i32(i32 %temp1, i32 %temp2)910 ret i32 %temp3911}912 913declare <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16>, <4 x i16>) nounwind readnone914declare <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16>, <8 x i16>) nounwind readnone915declare <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32>, <2 x i32>) nounwind readnone916declare <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind readnone917declare i32 @llvm.aarch64.neon.sqrdmulh.i32(i32, i32) nounwind readnone918 919define <2 x float> @fmulx_2s(ptr %A, ptr %B) nounwind sanitize_memory {920; CHECK-LABEL: define <2 x float> @fmulx_2s(921; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {922; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_param_tls, align 8923; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8924; CHECK-NEXT: call void @llvm.donothing()925; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 0926; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]927; CHECK: [[BB3]]:928; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]929; CHECK-NEXT: unreachable930; CHECK: [[BB4]]:931; CHECK-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr [[A]], align 8932; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64933; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576934; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr935; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 8936; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP8]], 0937; CHECK-NEXT: br i1 [[_MSCMP3]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]938; CHECK: [[BB8]]:939; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]940; CHECK-NEXT: unreachable941; CHECK: [[BB9]]:942; CHECK-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr [[B]], align 8943; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64944; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576945; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr946; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 8947; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[_MSLD]], [[_MSLD1]]948; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i32> [[_MSPROP]], zeroinitializer949; CHECK-NEXT: [[TMP3:%.*]] = call <2 x float> @llvm.aarch64.neon.fmulx.v2f32(<2 x float> [[TMP1]], <2 x float> [[TMP2]])950; CHECK-NEXT: store <2 x i32> [[_MSPROP2]], ptr @__msan_retval_tls, align 8951; CHECK-NEXT: ret <2 x float> [[TMP3]]952;953 %temp1 = load <2 x float>, ptr %A954 %temp2 = load <2 x float>, ptr %B955 %temp3 = call <2 x float> @llvm.aarch64.neon.fmulx.v2f32(<2 x float> %temp1, <2 x float> %temp2)956 ret <2 x float> %temp3957}958 959define <4 x float> @fmulx_4s(ptr %A, ptr %B) nounwind sanitize_memory {960; CHECK-LABEL: define <4 x float> @fmulx_4s(961; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {962; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_param_tls, align 8963; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8964; CHECK-NEXT: call void @llvm.donothing()965; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 0966; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]967; CHECK: [[BB3]]:968; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]969; CHECK-NEXT: unreachable970; CHECK: [[BB4]]:971; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[A]], align 16972; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64973; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576974; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr975; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 16976; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP8]], 0977; CHECK-NEXT: br i1 [[_MSCMP3]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]978; CHECK: [[BB8]]:979; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]980; CHECK-NEXT: unreachable981; CHECK: [[BB9]]:982; CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr [[B]], align 16983; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64984; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576985; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr986; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 16987; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[_MSLD]], [[_MSLD1]]988; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i32> [[_MSPROP]], zeroinitializer989; CHECK-NEXT: [[TMP3:%.*]] = call <4 x float> @llvm.aarch64.neon.fmulx.v4f32(<4 x float> [[TMP1]], <4 x float> [[TMP2]])990; CHECK-NEXT: store <4 x i32> [[_MSPROP2]], ptr @__msan_retval_tls, align 8991; CHECK-NEXT: ret <4 x float> [[TMP3]]992;993 %temp1 = load <4 x float>, ptr %A994 %temp2 = load <4 x float>, ptr %B995 %temp3 = call <4 x float> @llvm.aarch64.neon.fmulx.v4f32(<4 x float> %temp1, <4 x float> %temp2)996 ret <4 x float> %temp3997}998 999define <2 x double> @fmulx_2d(ptr %A, ptr %B) nounwind sanitize_memory {1000; CHECK-LABEL: define <2 x double> @fmulx_2d(1001; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1002; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__msan_param_tls, align 81003; CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81004; CHECK-NEXT: call void @llvm.donothing()1005; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 01006; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB3:.*]], label %[[BB4:.*]], !prof [[PROF1]]1007; CHECK: [[BB3]]:1008; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1009; CHECK-NEXT: unreachable1010; CHECK: [[BB4]]:1011; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[A]], align 161012; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641013; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761014; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1015; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 161016; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP8]], 01017; CHECK-NEXT: br i1 [[_MSCMP3]], label %[[BB8:.*]], label %[[BB9:.*]], !prof [[PROF1]]1018; CHECK: [[BB8]]:1019; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1020; CHECK-NEXT: unreachable1021; CHECK: [[BB9]]:1022; CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr [[B]], align 161023; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641024; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761025; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1026; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 161027; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[_MSLD]], [[_MSLD1]]1028; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i64> [[_MSPROP]], zeroinitializer1029; CHECK-NEXT: [[TMP3:%.*]] = call <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double> [[TMP1]], <2 x double> [[TMP2]])1030; CHECK-NEXT: store <2 x i64> [[_MSPROP2]], ptr @__msan_retval_tls, align 81031; CHECK-NEXT: ret <2 x double> [[TMP3]]1032;1033 %temp1 = load <2 x double>, ptr %A1034 %temp2 = load <2 x double>, ptr %B1035 %temp3 = call <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double> %temp1, <2 x double> %temp2)1036 ret <2 x double> %temp31037}1038 1039declare <2 x float> @llvm.aarch64.neon.fmulx.v2f32(<2 x float>, <2 x float>) nounwind readnone1040declare <4 x float> @llvm.aarch64.neon.fmulx.v4f32(<4 x float>, <4 x float>) nounwind readnone1041declare <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double>, <2 x double>) nounwind readnone1042 1043define <4 x i32> @smlal4s(ptr %A, ptr %B, ptr %C) nounwind sanitize_memory {1044; CHECK-LABEL: define <4 x i32> @smlal4s(1045; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]]) #[[ATTR0]] {1046; CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr @__msan_param_tls, align 81047; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81048; CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81049; CHECK-NEXT: call void @llvm.donothing()1050; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP9]], 01051; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]1052; CHECK: [[BB4]]:1053; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1054; CHECK-NEXT: unreachable1055; CHECK: [[BB5]]:1056; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 81057; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i641058; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 1935140464885761059; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr1060; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP8]], align 81061; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i64 [[TMP10]], 01062; CHECK-NEXT: br i1 [[_MSCMP5]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]1063; CHECK: [[BB9]]:1064; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1065; CHECK-NEXT: unreachable1066; CHECK: [[BB10]]:1067; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr [[B]], align 81068; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i641069; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 1935140464885761070; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr1071; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP13]], align 81072; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i64 [[TMP14]], 01073; CHECK-NEXT: br i1 [[_MSCMP6]], label %[[BB14:.*]], label %[[BB15:.*]], !prof [[PROF1]]1074; CHECK: [[BB14]]:1075; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1076; CHECK-NEXT: unreachable1077; CHECK: [[BB15]]:1078; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr [[C]], align 161079; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[C]] to i641080; CHECK-NEXT: [[TMP17:%.*]] = xor i64 [[TMP16]], 1935140464885761081; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr1082; CHECK-NEXT: [[_MSLD2:%.*]] = load <4 x i32>, ptr [[TMP18]], align 161083; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[_MSLD]], [[_MSLD1]]1084; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i16> [[_MSPROP]], zeroinitializer1085; CHECK-NEXT: [[TMP19:%.*]] = zext <4 x i16> [[_MSPROP3]] to <4 x i32>1086; CHECK-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[TMP1]], <4 x i16> [[TMP2]])1087; CHECK-NEXT: [[_MSPROP4:%.*]] = or <4 x i32> [[_MSLD2]], [[TMP19]]1088; CHECK-NEXT: [[TMP5:%.*]] = add <4 x i32> [[TMP3]], [[TMP4]]1089; CHECK-NEXT: store <4 x i32> [[_MSPROP4]], ptr @__msan_retval_tls, align 81090; CHECK-NEXT: ret <4 x i32> [[TMP5]]1091;1092 %temp1 = load <4 x i16>, ptr %A1093 %temp2 = load <4 x i16>, ptr %B1094 %temp3 = load <4 x i32>, ptr %C1095 %temp4 = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %temp1, <4 x i16> %temp2)1096 %temp5 = add <4 x i32> %temp3, %temp41097 ret <4 x i32> %temp51098}1099 1100define <2 x i64> @smlal2d(ptr %A, ptr %B, ptr %C) nounwind sanitize_memory {1101; CHECK-LABEL: define <2 x i64> @smlal2d(1102; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]]) #[[ATTR0]] {1103; CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr @__msan_param_tls, align 81104; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81105; CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81106; CHECK-NEXT: call void @llvm.donothing()1107; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP9]], 01108; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]1109; CHECK: [[BB4]]:1110; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1111; CHECK-NEXT: unreachable1112; CHECK: [[BB5]]:1113; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 81114; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i641115; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 1935140464885761116; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr1117; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP8]], align 81118; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i64 [[TMP10]], 01119; CHECK-NEXT: br i1 [[_MSCMP5]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]1120; CHECK: [[BB9]]:1121; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1122; CHECK-NEXT: unreachable1123; CHECK: [[BB10]]:1124; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr [[B]], align 81125; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i641126; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 1935140464885761127; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr1128; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP13]], align 81129; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i64 [[TMP14]], 01130; CHECK-NEXT: br i1 [[_MSCMP6]], label %[[BB14:.*]], label %[[BB15:.*]], !prof [[PROF1]]1131; CHECK: [[BB14]]:1132; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1133; CHECK-NEXT: unreachable1134; CHECK: [[BB15]]:1135; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr [[C]], align 161136; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[C]] to i641137; CHECK-NEXT: [[TMP17:%.*]] = xor i64 [[TMP16]], 1935140464885761138; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr1139; CHECK-NEXT: [[_MSLD2:%.*]] = load <2 x i64>, ptr [[TMP18]], align 161140; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[_MSLD]], [[_MSLD1]]1141; CHECK-NEXT: [[_MSPROP3:%.*]] = or <2 x i32> [[_MSPROP]], zeroinitializer1142; CHECK-NEXT: [[TMP19:%.*]] = zext <2 x i32> [[_MSPROP3]] to <2 x i64>1143; CHECK-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]])1144; CHECK-NEXT: [[_MSPROP4:%.*]] = or <2 x i64> [[_MSLD2]], [[TMP19]]1145; CHECK-NEXT: [[TMP5:%.*]] = add <2 x i64> [[TMP3]], [[TMP4]]1146; CHECK-NEXT: store <2 x i64> [[_MSPROP4]], ptr @__msan_retval_tls, align 81147; CHECK-NEXT: ret <2 x i64> [[TMP5]]1148;1149 %temp1 = load <2 x i32>, ptr %A1150 %temp2 = load <2 x i32>, ptr %B1151 %temp3 = load <2 x i64>, ptr %C1152 %temp4 = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %temp1, <2 x i32> %temp2)1153 %temp5 = add <2 x i64> %temp3, %temp41154 ret <2 x i64> %temp51155}1156 1157define void @smlal8h_chain_with_constant(ptr %dst, <8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3) {1158; CHECK-LABEL: define void @smlal8h_chain_with_constant(1159; CHECK-SAME: ptr [[DST:%.*]], <8 x i8> [[V1:%.*]], <8 x i8> [[V2:%.*]], <8 x i8> [[V3:%.*]]) {1160; CHECK-NEXT: call void @llvm.donothing()1161; CHECK-NEXT: [[XOR:%.*]] = xor <8 x i8> [[V3]], splat (i8 -1)1162; CHECK-NEXT: [[SMULL_1:%.*]] = tail call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> [[V1]], <8 x i8> [[V3]])1163; CHECK-NEXT: [[ADD_1:%.*]] = add <8 x i16> [[SMULL_1]], splat (i16 257)1164; CHECK-NEXT: [[SMULL_2:%.*]] = tail call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> [[V2]], <8 x i8> [[XOR]])1165; CHECK-NEXT: [[ADD_2:%.*]] = add <8 x i16> [[ADD_1]], [[SMULL_2]]1166; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[DST]] to i641167; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 1935140464885761168; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr1169; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr [[TMP3]], align 161170; CHECK-NEXT: store <8 x i16> [[ADD_2]], ptr [[DST]], align 161171; CHECK-NEXT: ret void1172;1173 %xor = xor <8 x i8> %v3, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>1174 %smull.1 = tail call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> %v1, <8 x i8> %v3)1175 %add.1 = add <8 x i16> %smull.1, <i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257>1176 %smull.2 = tail call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> %v2, <8 x i8> %xor)1177 %add.2 = add <8 x i16> %add.1, %smull.21178 store <8 x i16> %add.2, ptr %dst1179 ret void1180}1181 1182define void @smlal2d_chain_with_constant(ptr %dst, <2 x i32> %v1, <2 x i32> %v2, <2 x i32> %v3) {1183; CHECK-LABEL: define void @smlal2d_chain_with_constant(1184; CHECK-SAME: ptr [[DST:%.*]], <2 x i32> [[V1:%.*]], <2 x i32> [[V2:%.*]], <2 x i32> [[V3:%.*]]) {1185; CHECK-NEXT: call void @llvm.donothing()1186; CHECK-NEXT: [[XOR:%.*]] = xor <2 x i32> [[V3]], splat (i32 -1)1187; CHECK-NEXT: [[SMULL_1:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[V1]], <2 x i32> [[V3]])1188; CHECK-NEXT: [[ADD_1:%.*]] = add <2 x i64> [[SMULL_1]], splat (i64 257)1189; CHECK-NEXT: [[SMULL_2:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[V2]], <2 x i32> [[XOR]])1190; CHECK-NEXT: [[ADD_2:%.*]] = add <2 x i64> [[ADD_1]], [[SMULL_2]]1191; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[DST]] to i641192; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 1935140464885761193; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr1194; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr [[TMP3]], align 161195; CHECK-NEXT: store <2 x i64> [[ADD_2]], ptr [[DST]], align 161196; CHECK-NEXT: ret void1197;1198 %xor = xor <2 x i32> %v3, <i32 -1, i32 -1>1199 %smull.1 = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %v1, <2 x i32> %v3)1200 %add.1 = add <2 x i64> %smull.1, <i64 257, i64 257>1201 %smull.2 = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %v2, <2 x i32> %xor)1202 %add.2 = add <2 x i64> %add.1, %smull.21203 store <2 x i64> %add.2, ptr %dst1204 ret void1205}1206 1207define <4 x i32> @smlsl4s(ptr %A, ptr %B, ptr %C) nounwind sanitize_memory {1208; CHECK-LABEL: define <4 x i32> @smlsl4s(1209; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]]) #[[ATTR0]] {1210; CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr @__msan_param_tls, align 81211; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81212; CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81213; CHECK-NEXT: call void @llvm.donothing()1214; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP9]], 01215; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]1216; CHECK: [[BB4]]:1217; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1218; CHECK-NEXT: unreachable1219; CHECK: [[BB5]]:1220; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 81221; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i641222; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 1935140464885761223; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr1224; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP8]], align 81225; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i64 [[TMP10]], 01226; CHECK-NEXT: br i1 [[_MSCMP5]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]1227; CHECK: [[BB9]]:1228; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1229; CHECK-NEXT: unreachable1230; CHECK: [[BB10]]:1231; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr [[B]], align 81232; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i641233; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 1935140464885761234; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr1235; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP13]], align 81236; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i64 [[TMP14]], 01237; CHECK-NEXT: br i1 [[_MSCMP6]], label %[[BB14:.*]], label %[[BB15:.*]], !prof [[PROF1]]1238; CHECK: [[BB14]]:1239; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1240; CHECK-NEXT: unreachable1241; CHECK: [[BB15]]:1242; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr [[C]], align 161243; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[C]] to i641244; CHECK-NEXT: [[TMP17:%.*]] = xor i64 [[TMP16]], 1935140464885761245; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr1246; CHECK-NEXT: [[_MSLD2:%.*]] = load <4 x i32>, ptr [[TMP18]], align 161247; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[_MSLD]], [[_MSLD1]]1248; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i16> [[_MSPROP]], zeroinitializer1249; CHECK-NEXT: [[TMP19:%.*]] = zext <4 x i16> [[_MSPROP3]] to <4 x i32>1250; CHECK-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[TMP1]], <4 x i16> [[TMP2]])1251; CHECK-NEXT: [[_MSPROP4:%.*]] = or <4 x i32> [[_MSLD2]], [[TMP19]]1252; CHECK-NEXT: [[TMP5:%.*]] = sub <4 x i32> [[TMP3]], [[TMP4]]1253; CHECK-NEXT: store <4 x i32> [[_MSPROP4]], ptr @__msan_retval_tls, align 81254; CHECK-NEXT: ret <4 x i32> [[TMP5]]1255;1256 %temp1 = load <4 x i16>, ptr %A1257 %temp2 = load <4 x i16>, ptr %B1258 %temp3 = load <4 x i32>, ptr %C1259 %temp4 = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %temp1, <4 x i16> %temp2)1260 %temp5 = sub <4 x i32> %temp3, %temp41261 ret <4 x i32> %temp51262}1263 1264define <2 x i64> @smlsl2d(ptr %A, ptr %B, ptr %C) nounwind sanitize_memory {1265; CHECK-LABEL: define <2 x i64> @smlsl2d(1266; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]]) #[[ATTR0]] {1267; CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr @__msan_param_tls, align 81268; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81269; CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81270; CHECK-NEXT: call void @llvm.donothing()1271; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP9]], 01272; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]1273; CHECK: [[BB4]]:1274; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1275; CHECK-NEXT: unreachable1276; CHECK: [[BB5]]:1277; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 81278; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i641279; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 1935140464885761280; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr1281; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP8]], align 81282; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i64 [[TMP10]], 01283; CHECK-NEXT: br i1 [[_MSCMP5]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]1284; CHECK: [[BB9]]:1285; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1286; CHECK-NEXT: unreachable1287; CHECK: [[BB10]]:1288; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr [[B]], align 81289; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i641290; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 1935140464885761291; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr1292; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP13]], align 81293; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i64 [[TMP14]], 01294; CHECK-NEXT: br i1 [[_MSCMP6]], label %[[BB14:.*]], label %[[BB15:.*]], !prof [[PROF1]]1295; CHECK: [[BB14]]:1296; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1297; CHECK-NEXT: unreachable1298; CHECK: [[BB15]]:1299; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr [[C]], align 161300; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[C]] to i641301; CHECK-NEXT: [[TMP17:%.*]] = xor i64 [[TMP16]], 1935140464885761302; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr1303; CHECK-NEXT: [[_MSLD2:%.*]] = load <2 x i64>, ptr [[TMP18]], align 161304; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[_MSLD]], [[_MSLD1]]1305; CHECK-NEXT: [[_MSPROP3:%.*]] = or <2 x i32> [[_MSPROP]], zeroinitializer1306; CHECK-NEXT: [[TMP19:%.*]] = zext <2 x i32> [[_MSPROP3]] to <2 x i64>1307; CHECK-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]])1308; CHECK-NEXT: [[_MSPROP4:%.*]] = or <2 x i64> [[_MSLD2]], [[TMP19]]1309; CHECK-NEXT: [[TMP5:%.*]] = sub <2 x i64> [[TMP3]], [[TMP4]]1310; CHECK-NEXT: store <2 x i64> [[_MSPROP4]], ptr @__msan_retval_tls, align 81311; CHECK-NEXT: ret <2 x i64> [[TMP5]]1312;1313 %temp1 = load <2 x i32>, ptr %A1314 %temp2 = load <2 x i32>, ptr %B1315 %temp3 = load <2 x i64>, ptr %C1316 %temp4 = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %temp1, <2 x i32> %temp2)1317 %temp5 = sub <2 x i64> %temp3, %temp41318 ret <2 x i64> %temp51319}1320 1321define void @smlsl8h_chain_with_constant(ptr %dst, <8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3) {1322; CHECK-LABEL: define void @smlsl8h_chain_with_constant(1323; CHECK-SAME: ptr [[DST:%.*]], <8 x i8> [[V1:%.*]], <8 x i8> [[V2:%.*]], <8 x i8> [[V3:%.*]]) {1324; CHECK-NEXT: call void @llvm.donothing()1325; CHECK-NEXT: [[XOR:%.*]] = xor <8 x i8> [[V3]], splat (i8 -1)1326; CHECK-NEXT: [[SMULL_1:%.*]] = tail call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> [[V1]], <8 x i8> [[V3]])1327; CHECK-NEXT: [[SUB_1:%.*]] = sub <8 x i16> splat (i16 257), [[SMULL_1]]1328; CHECK-NEXT: [[SMULL_2:%.*]] = tail call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> [[V2]], <8 x i8> [[XOR]])1329; CHECK-NEXT: [[SUB_2:%.*]] = sub <8 x i16> [[SUB_1]], [[SMULL_2]]1330; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[DST]] to i641331; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 1935140464885761332; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr1333; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr [[TMP3]], align 161334; CHECK-NEXT: store <8 x i16> [[SUB_2]], ptr [[DST]], align 161335; CHECK-NEXT: ret void1336;1337 %xor = xor <8 x i8> %v3, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>1338 %smull.1 = tail call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> %v1, <8 x i8> %v3)1339 %sub.1 = sub <8 x i16> <i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257>, %smull.11340 %smull.2 = tail call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> %v2, <8 x i8> %xor)1341 %sub.2 = sub <8 x i16> %sub.1, %smull.21342 store <8 x i16> %sub.2, ptr %dst1343 ret void1344}1345 1346define void @smlsl2d_chain_with_constant(ptr %dst, <2 x i32> %v1, <2 x i32> %v2, <2 x i32> %v3) {1347; CHECK-LABEL: define void @smlsl2d_chain_with_constant(1348; CHECK-SAME: ptr [[DST:%.*]], <2 x i32> [[V1:%.*]], <2 x i32> [[V2:%.*]], <2 x i32> [[V3:%.*]]) {1349; CHECK-NEXT: call void @llvm.donothing()1350; CHECK-NEXT: [[XOR:%.*]] = xor <2 x i32> [[V3]], splat (i32 -1)1351; CHECK-NEXT: [[SMULL_1:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[V1]], <2 x i32> [[V3]])1352; CHECK-NEXT: [[SUB_1:%.*]] = sub <2 x i64> splat (i64 257), [[SMULL_1]]1353; CHECK-NEXT: [[SMULL_2:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[V2]], <2 x i32> [[XOR]])1354; CHECK-NEXT: [[SUB_2:%.*]] = sub <2 x i64> [[SUB_1]], [[SMULL_2]]1355; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[DST]] to i641356; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 1935140464885761357; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr1358; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr [[TMP3]], align 161359; CHECK-NEXT: store <2 x i64> [[SUB_2]], ptr [[DST]], align 161360; CHECK-NEXT: ret void1361;1362 %xor = xor <2 x i32> %v3, <i32 -1, i32 -1>1363 %smull.1 = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %v1, <2 x i32> %v3)1364 %sub.1 = sub <2 x i64> <i64 257, i64 257>, %smull.11365 %smull.2 = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %v2, <2 x i32> %xor)1366 %sub.2 = sub <2 x i64> %sub.1, %smull.21367 store <2 x i64> %sub.2, ptr %dst1368 ret void1369}1370 1371declare <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32>, <4 x i32>)1372declare <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64>, <2 x i64>)1373declare <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32>, <4 x i32>)1374declare <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64>, <2 x i64>)1375 1376define <4 x i32> @sqdmlal4s(ptr %A, ptr %B, ptr %C) nounwind sanitize_memory {1377; CHECK-LABEL: define <4 x i32> @sqdmlal4s(1378; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]]) #[[ATTR0]] {1379; CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr @__msan_param_tls, align 81380; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81381; CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81382; CHECK-NEXT: call void @llvm.donothing()1383; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP9]], 01384; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]1385; CHECK: [[BB4]]:1386; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1387; CHECK-NEXT: unreachable1388; CHECK: [[BB5]]:1389; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 81390; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i641391; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 1935140464885761392; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr1393; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP8]], align 81394; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP10]], 01395; CHECK-NEXT: br i1 [[_MSCMP3]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]1396; CHECK: [[BB9]]:1397; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1398; CHECK-NEXT: unreachable1399; CHECK: [[BB10]]:1400; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr [[B]], align 81401; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i641402; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 1935140464885761403; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr1404; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP13]], align 81405; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP14]], 01406; CHECK-NEXT: br i1 [[_MSCMP4]], label %[[BB14:.*]], label %[[BB15:.*]], !prof [[PROF1]]1407; CHECK: [[BB14]]:1408; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1409; CHECK-NEXT: unreachable1410; CHECK: [[BB15]]:1411; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr [[C]], align 161412; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[C]] to i641413; CHECK-NEXT: [[TMP17:%.*]] = xor i64 [[TMP16]], 1935140464885761414; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr1415; CHECK-NEXT: [[_MSLD2:%.*]] = load <4 x i32>, ptr [[TMP18]], align 161416; CHECK-NEXT: [[TMP19:%.*]] = bitcast <4 x i16> [[_MSLD]] to i641417; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i64 [[TMP19]], 01418; CHECK-NEXT: [[TMP20:%.*]] = bitcast <4 x i16> [[_MSLD1]] to i641419; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i64 [[TMP20]], 01420; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP5]], [[_MSCMP6]]1421; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB21:.*]], label %[[BB22:.*]], !prof [[PROF1]]1422; CHECK: [[BB21]]:1423; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1424; CHECK-NEXT: unreachable1425; CHECK: [[BB22]]:1426; CHECK-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[TMP1]], <4 x i16> [[TMP2]])1427; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[_MSLD2]], zeroinitializer1428; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> [[TMP3]], <4 x i32> [[TMP4]])1429; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 81430; CHECK-NEXT: ret <4 x i32> [[TMP5]]1431;1432 %temp1 = load <4 x i16>, ptr %A1433 %temp2 = load <4 x i16>, ptr %B1434 %temp3 = load <4 x i32>, ptr %C1435 %temp4 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %temp1, <4 x i16> %temp2)1436 %temp5 = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %temp3, <4 x i32> %temp4)1437 ret <4 x i32> %temp51438}1439 1440define <2 x i64> @sqdmlal2d(ptr %A, ptr %B, ptr %C) nounwind sanitize_memory {1441; CHECK-LABEL: define <2 x i64> @sqdmlal2d(1442; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]]) #[[ATTR0]] {1443; CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr @__msan_param_tls, align 81444; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81445; CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81446; CHECK-NEXT: call void @llvm.donothing()1447; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP9]], 01448; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]1449; CHECK: [[BB4]]:1450; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1451; CHECK-NEXT: unreachable1452; CHECK: [[BB5]]:1453; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 81454; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i641455; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 1935140464885761456; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr1457; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP8]], align 81458; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP10]], 01459; CHECK-NEXT: br i1 [[_MSCMP3]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]1460; CHECK: [[BB9]]:1461; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1462; CHECK-NEXT: unreachable1463; CHECK: [[BB10]]:1464; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr [[B]], align 81465; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i641466; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 1935140464885761467; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr1468; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP13]], align 81469; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP14]], 01470; CHECK-NEXT: br i1 [[_MSCMP4]], label %[[BB14:.*]], label %[[BB15:.*]], !prof [[PROF1]]1471; CHECK: [[BB14]]:1472; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1473; CHECK-NEXT: unreachable1474; CHECK: [[BB15]]:1475; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr [[C]], align 161476; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[C]] to i641477; CHECK-NEXT: [[TMP17:%.*]] = xor i64 [[TMP16]], 1935140464885761478; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr1479; CHECK-NEXT: [[_MSLD2:%.*]] = load <2 x i64>, ptr [[TMP18]], align 161480; CHECK-NEXT: [[TMP19:%.*]] = bitcast <2 x i32> [[_MSLD]] to i641481; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i64 [[TMP19]], 01482; CHECK-NEXT: [[TMP20:%.*]] = bitcast <2 x i32> [[_MSLD1]] to i641483; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i64 [[TMP20]], 01484; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP5]], [[_MSCMP6]]1485; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB21:.*]], label %[[BB22:.*]], !prof [[PROF1]]1486; CHECK: [[BB21]]:1487; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1488; CHECK-NEXT: unreachable1489; CHECK: [[BB22]]:1490; CHECK-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]])1491; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[_MSLD2]], zeroinitializer1492; CHECK-NEXT: [[TMP5:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> [[TMP3]], <2 x i64> [[TMP4]])1493; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 81494; CHECK-NEXT: ret <2 x i64> [[TMP5]]1495;1496 %temp1 = load <2 x i32>, ptr %A1497 %temp2 = load <2 x i32>, ptr %B1498 %temp3 = load <2 x i64>, ptr %C1499 %temp4 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %temp1, <2 x i32> %temp2)1500 %temp5 = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %temp3, <2 x i64> %temp4)1501 ret <2 x i64> %temp51502}1503 1504define <4 x i32> @sqdmlal2_4s(ptr %A, ptr %B, ptr %C) nounwind sanitize_memory {1505; CHECK-LABEL: define <4 x i32> @sqdmlal2_4s(1506; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]]) #[[ATTR0]] {1507; CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr @__msan_param_tls, align 81508; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81509; CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81510; CHECK-NEXT: call void @llvm.donothing()1511; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP9]], 01512; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]1513; CHECK: [[BB4]]:1514; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1515; CHECK-NEXT: unreachable1516; CHECK: [[BB5]]:1517; CHECK-NEXT: [[LOAD1:%.*]] = load <8 x i16>, ptr [[A]], align 161518; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i641519; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 1935140464885761520; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr1521; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP8]], align 161522; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i64 [[TMP10]], 01523; CHECK-NEXT: br i1 [[_MSCMP5]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]1524; CHECK: [[BB9]]:1525; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1526; CHECK-NEXT: unreachable1527; CHECK: [[BB10]]:1528; CHECK-NEXT: [[LOAD2:%.*]] = load <8 x i16>, ptr [[B]], align 161529; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i641530; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 1935140464885761531; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr1532; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP13]], align 161533; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i64 [[TMP14]], 01534; CHECK-NEXT: br i1 [[_MSCMP6]], label %[[BB14:.*]], label %[[BB15:.*]], !prof [[PROF1]]1535; CHECK: [[BB14]]:1536; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1537; CHECK-NEXT: unreachable1538; CHECK: [[BB15]]:1539; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr [[C]], align 161540; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[C]] to i641541; CHECK-NEXT: [[TMP17:%.*]] = xor i64 [[TMP16]], 1935140464885761542; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr1543; CHECK-NEXT: [[_MSLD2:%.*]] = load <4 x i32>, ptr [[TMP18]], align 161544; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i16> [[_MSLD]], <8 x i16> splat (i16 -1), <4 x i32> <i32 4, i32 5, i32 6, i32 7>1545; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i16> [[LOAD1]], <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>1546; CHECK-NEXT: [[_MSPROP3:%.*]] = shufflevector <8 x i16> [[_MSLD1]], <8 x i16> splat (i16 -1), <4 x i32> <i32 4, i32 5, i32 6, i32 7>1547; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i16> [[LOAD2]], <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>1548; CHECK-NEXT: [[TMP19:%.*]] = bitcast <4 x i16> [[_MSPROP]] to i641549; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i64 [[TMP19]], 01550; CHECK-NEXT: [[TMP20:%.*]] = bitcast <4 x i16> [[_MSPROP3]] to i641551; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i64 [[TMP20]], 01552; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP7]], [[_MSCMP8]]1553; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB21:.*]], label %[[BB22:.*]], !prof [[PROF1]]1554; CHECK: [[BB21]]:1555; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1556; CHECK-NEXT: unreachable1557; CHECK: [[BB22]]:1558; CHECK-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[TMP1]], <4 x i16> [[TMP2]])1559; CHECK-NEXT: [[_MSPROP4:%.*]] = or <4 x i32> [[_MSLD2]], zeroinitializer1560; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> [[TMP3]], <4 x i32> [[TMP4]])1561; CHECK-NEXT: store <4 x i32> [[_MSPROP4]], ptr @__msan_retval_tls, align 81562; CHECK-NEXT: ret <4 x i32> [[TMP5]]1563;1564 %load1 = load <8 x i16>, ptr %A1565 %load2 = load <8 x i16>, ptr %B1566 %temp3 = load <4 x i32>, ptr %C1567 %temp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>1568 %temp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>1569 %temp4 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %temp1, <4 x i16> %temp2)1570 %temp5 = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %temp3, <4 x i32> %temp4)1571 ret <4 x i32> %temp51572}1573 1574define <2 x i64> @sqdmlal2_2d(ptr %A, ptr %B, ptr %C) nounwind sanitize_memory {1575; CHECK-LABEL: define <2 x i64> @sqdmlal2_2d(1576; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]]) #[[ATTR0]] {1577; CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr @__msan_param_tls, align 81578; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81579; CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81580; CHECK-NEXT: call void @llvm.donothing()1581; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP9]], 01582; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]1583; CHECK: [[BB4]]:1584; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1585; CHECK-NEXT: unreachable1586; CHECK: [[BB5]]:1587; CHECK-NEXT: [[LOAD1:%.*]] = load <4 x i32>, ptr [[A]], align 161588; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i641589; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 1935140464885761590; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr1591; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP8]], align 161592; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i64 [[TMP10]], 01593; CHECK-NEXT: br i1 [[_MSCMP5]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]1594; CHECK: [[BB9]]:1595; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1596; CHECK-NEXT: unreachable1597; CHECK: [[BB10]]:1598; CHECK-NEXT: [[LOAD2:%.*]] = load <4 x i32>, ptr [[B]], align 161599; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i641600; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 1935140464885761601; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr1602; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP13]], align 161603; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i64 [[TMP14]], 01604; CHECK-NEXT: br i1 [[_MSCMP6]], label %[[BB14:.*]], label %[[BB15:.*]], !prof [[PROF1]]1605; CHECK: [[BB14]]:1606; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1607; CHECK-NEXT: unreachable1608; CHECK: [[BB15]]:1609; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr [[C]], align 161610; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[C]] to i641611; CHECK-NEXT: [[TMP17:%.*]] = xor i64 [[TMP16]], 1935140464885761612; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr1613; CHECK-NEXT: [[_MSLD2:%.*]] = load <2 x i64>, ptr [[TMP18]], align 161614; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> splat (i32 -1), <2 x i32> <i32 2, i32 3>1615; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[LOAD1]], <4 x i32> undef, <2 x i32> <i32 2, i32 3>1616; CHECK-NEXT: [[_MSPROP3:%.*]] = shufflevector <4 x i32> [[_MSLD1]], <4 x i32> splat (i32 -1), <2 x i32> <i32 2, i32 3>1617; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[LOAD2]], <4 x i32> undef, <2 x i32> <i32 2, i32 3>1618; CHECK-NEXT: [[TMP19:%.*]] = bitcast <2 x i32> [[_MSPROP]] to i641619; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i64 [[TMP19]], 01620; CHECK-NEXT: [[TMP20:%.*]] = bitcast <2 x i32> [[_MSPROP3]] to i641621; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i64 [[TMP20]], 01622; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP7]], [[_MSCMP8]]1623; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB21:.*]], label %[[BB22:.*]], !prof [[PROF1]]1624; CHECK: [[BB21]]:1625; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1626; CHECK-NEXT: unreachable1627; CHECK: [[BB22]]:1628; CHECK-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]])1629; CHECK-NEXT: [[_MSPROP4:%.*]] = or <2 x i64> [[_MSLD2]], zeroinitializer1630; CHECK-NEXT: [[TMP5:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> [[TMP3]], <2 x i64> [[TMP4]])1631; CHECK-NEXT: store <2 x i64> [[_MSPROP4]], ptr @__msan_retval_tls, align 81632; CHECK-NEXT: ret <2 x i64> [[TMP5]]1633;1634 %load1 = load <4 x i32>, ptr %A1635 %load2 = load <4 x i32>, ptr %B1636 %temp3 = load <2 x i64>, ptr %C1637 %temp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>1638 %temp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>1639 %temp4 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %temp1, <2 x i32> %temp2)1640 %temp5 = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %temp3, <2 x i64> %temp4)1641 ret <2 x i64> %temp51642}1643 1644define <4 x i32> @sqdmlsl4s(ptr %A, ptr %B, ptr %C) nounwind sanitize_memory {1645; CHECK-LABEL: define <4 x i32> @sqdmlsl4s(1646; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]]) #[[ATTR0]] {1647; CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr @__msan_param_tls, align 81648; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81649; CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81650; CHECK-NEXT: call void @llvm.donothing()1651; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP9]], 01652; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]1653; CHECK: [[BB4]]:1654; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1655; CHECK-NEXT: unreachable1656; CHECK: [[BB5]]:1657; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 81658; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i641659; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 1935140464885761660; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr1661; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP8]], align 81662; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP10]], 01663; CHECK-NEXT: br i1 [[_MSCMP3]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]1664; CHECK: [[BB9]]:1665; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1666; CHECK-NEXT: unreachable1667; CHECK: [[BB10]]:1668; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr [[B]], align 81669; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i641670; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 1935140464885761671; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr1672; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP13]], align 81673; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP14]], 01674; CHECK-NEXT: br i1 [[_MSCMP4]], label %[[BB14:.*]], label %[[BB15:.*]], !prof [[PROF1]]1675; CHECK: [[BB14]]:1676; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1677; CHECK-NEXT: unreachable1678; CHECK: [[BB15]]:1679; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr [[C]], align 161680; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[C]] to i641681; CHECK-NEXT: [[TMP17:%.*]] = xor i64 [[TMP16]], 1935140464885761682; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr1683; CHECK-NEXT: [[_MSLD2:%.*]] = load <4 x i32>, ptr [[TMP18]], align 161684; CHECK-NEXT: [[TMP19:%.*]] = bitcast <4 x i16> [[_MSLD]] to i641685; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i64 [[TMP19]], 01686; CHECK-NEXT: [[TMP20:%.*]] = bitcast <4 x i16> [[_MSLD1]] to i641687; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i64 [[TMP20]], 01688; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP5]], [[_MSCMP6]]1689; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB21:.*]], label %[[BB22:.*]], !prof [[PROF1]]1690; CHECK: [[BB21]]:1691; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1692; CHECK-NEXT: unreachable1693; CHECK: [[BB22]]:1694; CHECK-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[TMP1]], <4 x i16> [[TMP2]])1695; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[_MSLD2]], zeroinitializer1696; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> [[TMP3]], <4 x i32> [[TMP4]])1697; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 81698; CHECK-NEXT: ret <4 x i32> [[TMP5]]1699;1700 %temp1 = load <4 x i16>, ptr %A1701 %temp2 = load <4 x i16>, ptr %B1702 %temp3 = load <4 x i32>, ptr %C1703 %temp4 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %temp1, <4 x i16> %temp2)1704 %temp5 = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %temp3, <4 x i32> %temp4)1705 ret <4 x i32> %temp51706}1707 1708define <2 x i64> @sqdmlsl2d(ptr %A, ptr %B, ptr %C) nounwind sanitize_memory {1709; CHECK-LABEL: define <2 x i64> @sqdmlsl2d(1710; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]]) #[[ATTR0]] {1711; CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr @__msan_param_tls, align 81712; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81713; CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81714; CHECK-NEXT: call void @llvm.donothing()1715; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP9]], 01716; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]1717; CHECK: [[BB4]]:1718; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1719; CHECK-NEXT: unreachable1720; CHECK: [[BB5]]:1721; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 81722; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i641723; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 1935140464885761724; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr1725; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP8]], align 81726; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP10]], 01727; CHECK-NEXT: br i1 [[_MSCMP3]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]1728; CHECK: [[BB9]]:1729; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1730; CHECK-NEXT: unreachable1731; CHECK: [[BB10]]:1732; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr [[B]], align 81733; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i641734; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 1935140464885761735; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr1736; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP13]], align 81737; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP14]], 01738; CHECK-NEXT: br i1 [[_MSCMP4]], label %[[BB14:.*]], label %[[BB15:.*]], !prof [[PROF1]]1739; CHECK: [[BB14]]:1740; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1741; CHECK-NEXT: unreachable1742; CHECK: [[BB15]]:1743; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr [[C]], align 161744; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[C]] to i641745; CHECK-NEXT: [[TMP17:%.*]] = xor i64 [[TMP16]], 1935140464885761746; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr1747; CHECK-NEXT: [[_MSLD2:%.*]] = load <2 x i64>, ptr [[TMP18]], align 161748; CHECK-NEXT: [[TMP19:%.*]] = bitcast <2 x i32> [[_MSLD]] to i641749; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i64 [[TMP19]], 01750; CHECK-NEXT: [[TMP20:%.*]] = bitcast <2 x i32> [[_MSLD1]] to i641751; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i64 [[TMP20]], 01752; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP5]], [[_MSCMP6]]1753; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB21:.*]], label %[[BB22:.*]], !prof [[PROF1]]1754; CHECK: [[BB21]]:1755; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1756; CHECK-NEXT: unreachable1757; CHECK: [[BB22]]:1758; CHECK-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]])1759; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[_MSLD2]], zeroinitializer1760; CHECK-NEXT: [[TMP5:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> [[TMP3]], <2 x i64> [[TMP4]])1761; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 81762; CHECK-NEXT: ret <2 x i64> [[TMP5]]1763;1764 %temp1 = load <2 x i32>, ptr %A1765 %temp2 = load <2 x i32>, ptr %B1766 %temp3 = load <2 x i64>, ptr %C1767 %temp4 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %temp1, <2 x i32> %temp2)1768 %temp5 = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %temp3, <2 x i64> %temp4)1769 ret <2 x i64> %temp51770}1771 1772define <4 x i32> @sqdmlsl2_4s(ptr %A, ptr %B, ptr %C) nounwind sanitize_memory {1773; CHECK-LABEL: define <4 x i32> @sqdmlsl2_4s(1774; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]]) #[[ATTR0]] {1775; CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr @__msan_param_tls, align 81776; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81777; CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81778; CHECK-NEXT: call void @llvm.donothing()1779; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP9]], 01780; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]1781; CHECK: [[BB4]]:1782; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1783; CHECK-NEXT: unreachable1784; CHECK: [[BB5]]:1785; CHECK-NEXT: [[LOAD1:%.*]] = load <8 x i16>, ptr [[A]], align 161786; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i641787; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 1935140464885761788; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr1789; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP8]], align 161790; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i64 [[TMP10]], 01791; CHECK-NEXT: br i1 [[_MSCMP5]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]1792; CHECK: [[BB9]]:1793; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1794; CHECK-NEXT: unreachable1795; CHECK: [[BB10]]:1796; CHECK-NEXT: [[LOAD2:%.*]] = load <8 x i16>, ptr [[B]], align 161797; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i641798; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 1935140464885761799; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr1800; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP13]], align 161801; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i64 [[TMP14]], 01802; CHECK-NEXT: br i1 [[_MSCMP6]], label %[[BB14:.*]], label %[[BB15:.*]], !prof [[PROF1]]1803; CHECK: [[BB14]]:1804; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1805; CHECK-NEXT: unreachable1806; CHECK: [[BB15]]:1807; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr [[C]], align 161808; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[C]] to i641809; CHECK-NEXT: [[TMP17:%.*]] = xor i64 [[TMP16]], 1935140464885761810; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr1811; CHECK-NEXT: [[_MSLD2:%.*]] = load <4 x i32>, ptr [[TMP18]], align 161812; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i16> [[_MSLD]], <8 x i16> splat (i16 -1), <4 x i32> <i32 4, i32 5, i32 6, i32 7>1813; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i16> [[LOAD1]], <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>1814; CHECK-NEXT: [[_MSPROP3:%.*]] = shufflevector <8 x i16> [[_MSLD1]], <8 x i16> splat (i16 -1), <4 x i32> <i32 4, i32 5, i32 6, i32 7>1815; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i16> [[LOAD2]], <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>1816; CHECK-NEXT: [[TMP19:%.*]] = bitcast <4 x i16> [[_MSPROP]] to i641817; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i64 [[TMP19]], 01818; CHECK-NEXT: [[TMP20:%.*]] = bitcast <4 x i16> [[_MSPROP3]] to i641819; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i64 [[TMP20]], 01820; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP7]], [[_MSCMP8]]1821; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB21:.*]], label %[[BB22:.*]], !prof [[PROF1]]1822; CHECK: [[BB21]]:1823; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1824; CHECK-NEXT: unreachable1825; CHECK: [[BB22]]:1826; CHECK-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[TMP1]], <4 x i16> [[TMP2]])1827; CHECK-NEXT: [[_MSPROP4:%.*]] = or <4 x i32> [[_MSLD2]], zeroinitializer1828; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> [[TMP3]], <4 x i32> [[TMP4]])1829; CHECK-NEXT: store <4 x i32> [[_MSPROP4]], ptr @__msan_retval_tls, align 81830; CHECK-NEXT: ret <4 x i32> [[TMP5]]1831;1832 %load1 = load <8 x i16>, ptr %A1833 %load2 = load <8 x i16>, ptr %B1834 %temp3 = load <4 x i32>, ptr %C1835 %temp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>1836 %temp2 = shufflevector <8 x i16> %load2, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>1837 %temp4 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %temp1, <4 x i16> %temp2)1838 %temp5 = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %temp3, <4 x i32> %temp4)1839 ret <4 x i32> %temp51840}1841 1842define <2 x i64> @sqdmlsl2_2d(ptr %A, ptr %B, ptr %C) nounwind sanitize_memory {1843; CHECK-LABEL: define <2 x i64> @sqdmlsl2_2d(1844; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]]) #[[ATTR0]] {1845; CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr @__msan_param_tls, align 81846; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81847; CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81848; CHECK-NEXT: call void @llvm.donothing()1849; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP9]], 01850; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]1851; CHECK: [[BB4]]:1852; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1853; CHECK-NEXT: unreachable1854; CHECK: [[BB5]]:1855; CHECK-NEXT: [[LOAD1:%.*]] = load <4 x i32>, ptr [[A]], align 161856; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i641857; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 1935140464885761858; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr1859; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP8]], align 161860; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i64 [[TMP10]], 01861; CHECK-NEXT: br i1 [[_MSCMP5]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]1862; CHECK: [[BB9]]:1863; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1864; CHECK-NEXT: unreachable1865; CHECK: [[BB10]]:1866; CHECK-NEXT: [[LOAD2:%.*]] = load <4 x i32>, ptr [[B]], align 161867; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i641868; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 1935140464885761869; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr1870; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP13]], align 161871; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i64 [[TMP14]], 01872; CHECK-NEXT: br i1 [[_MSCMP6]], label %[[BB14:.*]], label %[[BB15:.*]], !prof [[PROF1]]1873; CHECK: [[BB14]]:1874; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1875; CHECK-NEXT: unreachable1876; CHECK: [[BB15]]:1877; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr [[C]], align 161878; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[C]] to i641879; CHECK-NEXT: [[TMP17:%.*]] = xor i64 [[TMP16]], 1935140464885761880; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr1881; CHECK-NEXT: [[_MSLD2:%.*]] = load <2 x i64>, ptr [[TMP18]], align 161882; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> splat (i32 -1), <2 x i32> <i32 2, i32 3>1883; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[LOAD1]], <4 x i32> undef, <2 x i32> <i32 2, i32 3>1884; CHECK-NEXT: [[_MSPROP3:%.*]] = shufflevector <4 x i32> [[_MSLD1]], <4 x i32> splat (i32 -1), <2 x i32> <i32 2, i32 3>1885; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[LOAD2]], <4 x i32> undef, <2 x i32> <i32 2, i32 3>1886; CHECK-NEXT: [[TMP19:%.*]] = bitcast <2 x i32> [[_MSPROP]] to i641887; CHECK-NEXT: [[_MSCMP7:%.*]] = icmp ne i64 [[TMP19]], 01888; CHECK-NEXT: [[TMP20:%.*]] = bitcast <2 x i32> [[_MSPROP3]] to i641889; CHECK-NEXT: [[_MSCMP8:%.*]] = icmp ne i64 [[TMP20]], 01890; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP7]], [[_MSCMP8]]1891; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB21:.*]], label %[[BB22:.*]], !prof [[PROF1]]1892; CHECK: [[BB21]]:1893; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1894; CHECK-NEXT: unreachable1895; CHECK: [[BB22]]:1896; CHECK-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]])1897; CHECK-NEXT: [[_MSPROP4:%.*]] = or <2 x i64> [[_MSLD2]], zeroinitializer1898; CHECK-NEXT: [[TMP5:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> [[TMP3]], <2 x i64> [[TMP4]])1899; CHECK-NEXT: store <2 x i64> [[_MSPROP4]], ptr @__msan_retval_tls, align 81900; CHECK-NEXT: ret <2 x i64> [[TMP5]]1901;1902 %load1 = load <4 x i32>, ptr %A1903 %load2 = load <4 x i32>, ptr %B1904 %temp3 = load <2 x i64>, ptr %C1905 %temp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>1906 %temp2 = shufflevector <4 x i32> %load2, <4 x i32> undef, <2 x i32> <i32 2, i32 3>1907 %temp4 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %temp1, <2 x i32> %temp2)1908 %temp5 = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %temp3, <2 x i64> %temp4)1909 ret <2 x i64> %temp51910}1911 1912define <4 x i32> @umlal4s(ptr %A, ptr %B, ptr %C) nounwind sanitize_memory {1913; CHECK-LABEL: define <4 x i32> @umlal4s(1914; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]]) #[[ATTR0]] {1915; CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr @__msan_param_tls, align 81916; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81917; CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81918; CHECK-NEXT: call void @llvm.donothing()1919; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP9]], 01920; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]1921; CHECK: [[BB4]]:1922; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1923; CHECK-NEXT: unreachable1924; CHECK: [[BB5]]:1925; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 81926; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i641927; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 1935140464885761928; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr1929; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP8]], align 81930; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i64 [[TMP10]], 01931; CHECK-NEXT: br i1 [[_MSCMP5]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]1932; CHECK: [[BB9]]:1933; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1934; CHECK-NEXT: unreachable1935; CHECK: [[BB10]]:1936; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr [[B]], align 81937; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i641938; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 1935140464885761939; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr1940; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP13]], align 81941; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i64 [[TMP14]], 01942; CHECK-NEXT: br i1 [[_MSCMP6]], label %[[BB14:.*]], label %[[BB15:.*]], !prof [[PROF1]]1943; CHECK: [[BB14]]:1944; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1945; CHECK-NEXT: unreachable1946; CHECK: [[BB15]]:1947; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr [[C]], align 161948; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[C]] to i641949; CHECK-NEXT: [[TMP17:%.*]] = xor i64 [[TMP16]], 1935140464885761950; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr1951; CHECK-NEXT: [[_MSLD2:%.*]] = load <4 x i32>, ptr [[TMP18]], align 161952; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[_MSLD]], [[_MSLD1]]1953; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i16> [[_MSPROP]], zeroinitializer1954; CHECK-NEXT: [[TMP19:%.*]] = zext <4 x i16> [[_MSPROP3]] to <4 x i32>1955; CHECK-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[TMP1]], <4 x i16> [[TMP2]])1956; CHECK-NEXT: [[_MSPROP4:%.*]] = or <4 x i32> [[_MSLD2]], [[TMP19]]1957; CHECK-NEXT: [[TMP5:%.*]] = add <4 x i32> [[TMP3]], [[TMP4]]1958; CHECK-NEXT: store <4 x i32> [[_MSPROP4]], ptr @__msan_retval_tls, align 81959; CHECK-NEXT: ret <4 x i32> [[TMP5]]1960;1961 %temp1 = load <4 x i16>, ptr %A1962 %temp2 = load <4 x i16>, ptr %B1963 %temp3 = load <4 x i32>, ptr %C1964 %temp4 = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %temp1, <4 x i16> %temp2)1965 %temp5 = add <4 x i32> %temp3, %temp41966 ret <4 x i32> %temp51967}1968 1969define <2 x i64> @umlal2d(ptr %A, ptr %B, ptr %C) nounwind sanitize_memory {1970; CHECK-LABEL: define <2 x i64> @umlal2d(1971; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]]) #[[ATTR0]] {1972; CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr @__msan_param_tls, align 81973; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81974; CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 81975; CHECK-NEXT: call void @llvm.donothing()1976; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP9]], 01977; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]1978; CHECK: [[BB4]]:1979; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1980; CHECK-NEXT: unreachable1981; CHECK: [[BB5]]:1982; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 81983; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i641984; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 1935140464885761985; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr1986; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP8]], align 81987; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i64 [[TMP10]], 01988; CHECK-NEXT: br i1 [[_MSCMP5]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]1989; CHECK: [[BB9]]:1990; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]1991; CHECK-NEXT: unreachable1992; CHECK: [[BB10]]:1993; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr [[B]], align 81994; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i641995; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 1935140464885761996; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr1997; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP13]], align 81998; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i64 [[TMP14]], 01999; CHECK-NEXT: br i1 [[_MSCMP6]], label %[[BB14:.*]], label %[[BB15:.*]], !prof [[PROF1]]2000; CHECK: [[BB14]]:2001; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2002; CHECK-NEXT: unreachable2003; CHECK: [[BB15]]:2004; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr [[C]], align 162005; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[C]] to i642006; CHECK-NEXT: [[TMP17:%.*]] = xor i64 [[TMP16]], 1935140464885762007; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr2008; CHECK-NEXT: [[_MSLD2:%.*]] = load <2 x i64>, ptr [[TMP18]], align 162009; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[_MSLD]], [[_MSLD1]]2010; CHECK-NEXT: [[_MSPROP3:%.*]] = or <2 x i32> [[_MSPROP]], zeroinitializer2011; CHECK-NEXT: [[TMP19:%.*]] = zext <2 x i32> [[_MSPROP3]] to <2 x i64>2012; CHECK-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]])2013; CHECK-NEXT: [[_MSPROP4:%.*]] = or <2 x i64> [[_MSLD2]], [[TMP19]]2014; CHECK-NEXT: [[TMP5:%.*]] = add <2 x i64> [[TMP3]], [[TMP4]]2015; CHECK-NEXT: store <2 x i64> [[_MSPROP4]], ptr @__msan_retval_tls, align 82016; CHECK-NEXT: ret <2 x i64> [[TMP5]]2017;2018 %temp1 = load <2 x i32>, ptr %A2019 %temp2 = load <2 x i32>, ptr %B2020 %temp3 = load <2 x i64>, ptr %C2021 %temp4 = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %temp1, <2 x i32> %temp2)2022 %temp5 = add <2 x i64> %temp3, %temp42023 ret <2 x i64> %temp52024}2025 2026define void @umlal8h_chain_with_constant(ptr %dst, <8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3) {2027; CHECK-LABEL: define void @umlal8h_chain_with_constant(2028; CHECK-SAME: ptr [[DST:%.*]], <8 x i8> [[V1:%.*]], <8 x i8> [[V2:%.*]], <8 x i8> [[V3:%.*]]) {2029; CHECK-NEXT: call void @llvm.donothing()2030; CHECK-NEXT: [[XOR:%.*]] = xor <8 x i8> [[V3]], splat (i8 -1)2031; CHECK-NEXT: [[UMULL_1:%.*]] = tail call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> [[V1]], <8 x i8> [[V3]])2032; CHECK-NEXT: [[ADD_1:%.*]] = add <8 x i16> [[UMULL_1]], splat (i16 257)2033; CHECK-NEXT: [[UMULL_2:%.*]] = tail call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> [[V2]], <8 x i8> [[XOR]])2034; CHECK-NEXT: [[ADD_2:%.*]] = add <8 x i16> [[ADD_1]], [[UMULL_2]]2035; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[DST]] to i642036; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 1935140464885762037; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr2038; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr [[TMP3]], align 162039; CHECK-NEXT: store <8 x i16> [[ADD_2]], ptr [[DST]], align 162040; CHECK-NEXT: ret void2041;2042 %xor = xor <8 x i8> %v3, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>2043 %umull.1 = tail call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> %v1, <8 x i8> %v3)2044 %add.1 = add <8 x i16> %umull.1, <i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257>2045 %umull.2 = tail call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> %v2, <8 x i8> %xor)2046 %add.2 = add <8 x i16> %add.1, %umull.22047 store <8 x i16> %add.2, ptr %dst2048 ret void2049}2050 2051define void @umlal2d_chain_with_constant(ptr %dst, <2 x i32> %v1, <2 x i32> %v2, <2 x i32> %v3) {2052; CHECK-LABEL: define void @umlal2d_chain_with_constant(2053; CHECK-SAME: ptr [[DST:%.*]], <2 x i32> [[V1:%.*]], <2 x i32> [[V2:%.*]], <2 x i32> [[V3:%.*]]) {2054; CHECK-NEXT: call void @llvm.donothing()2055; CHECK-NEXT: [[XOR:%.*]] = xor <2 x i32> [[V3]], splat (i32 -1)2056; CHECK-NEXT: [[UMULL_1:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[V1]], <2 x i32> [[V3]])2057; CHECK-NEXT: [[ADD_1:%.*]] = add <2 x i64> [[UMULL_1]], splat (i64 257)2058; CHECK-NEXT: [[UMULL_2:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[V2]], <2 x i32> [[XOR]])2059; CHECK-NEXT: [[ADD_2:%.*]] = add <2 x i64> [[ADD_1]], [[UMULL_2]]2060; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[DST]] to i642061; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 1935140464885762062; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr2063; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr [[TMP3]], align 162064; CHECK-NEXT: store <2 x i64> [[ADD_2]], ptr [[DST]], align 162065; CHECK-NEXT: ret void2066;2067 %xor = xor <2 x i32> %v3, <i32 -1, i32 -1>2068 %umull.1 = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %v1, <2 x i32> %v3)2069 %add.1 = add <2 x i64> %umull.1, <i64 257, i64 257>2070 %umull.2 = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %v2, <2 x i32> %xor)2071 %add.2 = add <2 x i64> %add.1, %umull.22072 store <2 x i64> %add.2, ptr %dst2073 ret void2074}2075 2076define <4 x i32> @umlsl4s(ptr %A, ptr %B, ptr %C) nounwind sanitize_memory {2077; CHECK-LABEL: define <4 x i32> @umlsl4s(2078; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]]) #[[ATTR0]] {2079; CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr @__msan_param_tls, align 82080; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82081; CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82082; CHECK-NEXT: call void @llvm.donothing()2083; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP9]], 02084; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]2085; CHECK: [[BB4]]:2086; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2087; CHECK-NEXT: unreachable2088; CHECK: [[BB5]]:2089; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 82090; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i642091; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 1935140464885762092; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr2093; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP8]], align 82094; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i64 [[TMP10]], 02095; CHECK-NEXT: br i1 [[_MSCMP5]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]2096; CHECK: [[BB9]]:2097; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2098; CHECK-NEXT: unreachable2099; CHECK: [[BB10]]:2100; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr [[B]], align 82101; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i642102; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 1935140464885762103; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr2104; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP13]], align 82105; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i64 [[TMP14]], 02106; CHECK-NEXT: br i1 [[_MSCMP6]], label %[[BB14:.*]], label %[[BB15:.*]], !prof [[PROF1]]2107; CHECK: [[BB14]]:2108; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2109; CHECK-NEXT: unreachable2110; CHECK: [[BB15]]:2111; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr [[C]], align 162112; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[C]] to i642113; CHECK-NEXT: [[TMP17:%.*]] = xor i64 [[TMP16]], 1935140464885762114; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr2115; CHECK-NEXT: [[_MSLD2:%.*]] = load <4 x i32>, ptr [[TMP18]], align 162116; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[_MSLD]], [[_MSLD1]]2117; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i16> [[_MSPROP]], zeroinitializer2118; CHECK-NEXT: [[TMP19:%.*]] = zext <4 x i16> [[_MSPROP3]] to <4 x i32>2119; CHECK-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[TMP1]], <4 x i16> [[TMP2]])2120; CHECK-NEXT: [[_MSPROP4:%.*]] = or <4 x i32> [[_MSLD2]], [[TMP19]]2121; CHECK-NEXT: [[TMP5:%.*]] = sub <4 x i32> [[TMP3]], [[TMP4]]2122; CHECK-NEXT: store <4 x i32> [[_MSPROP4]], ptr @__msan_retval_tls, align 82123; CHECK-NEXT: ret <4 x i32> [[TMP5]]2124;2125 %temp1 = load <4 x i16>, ptr %A2126 %temp2 = load <4 x i16>, ptr %B2127 %temp3 = load <4 x i32>, ptr %C2128 %temp4 = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %temp1, <4 x i16> %temp2)2129 %temp5 = sub <4 x i32> %temp3, %temp42130 ret <4 x i32> %temp52131}2132 2133define <2 x i64> @umlsl2d(ptr %A, ptr %B, ptr %C) nounwind sanitize_memory {2134; CHECK-LABEL: define <2 x i64> @umlsl2d(2135; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]]) #[[ATTR0]] {2136; CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr @__msan_param_tls, align 82137; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82138; CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82139; CHECK-NEXT: call void @llvm.donothing()2140; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP9]], 02141; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]2142; CHECK: [[BB4]]:2143; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2144; CHECK-NEXT: unreachable2145; CHECK: [[BB5]]:2146; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 82147; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i642148; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 1935140464885762149; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr2150; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP8]], align 82151; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i64 [[TMP10]], 02152; CHECK-NEXT: br i1 [[_MSCMP5]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]2153; CHECK: [[BB9]]:2154; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2155; CHECK-NEXT: unreachable2156; CHECK: [[BB10]]:2157; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr [[B]], align 82158; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i642159; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 1935140464885762160; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr2161; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP13]], align 82162; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i64 [[TMP14]], 02163; CHECK-NEXT: br i1 [[_MSCMP6]], label %[[BB14:.*]], label %[[BB15:.*]], !prof [[PROF1]]2164; CHECK: [[BB14]]:2165; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2166; CHECK-NEXT: unreachable2167; CHECK: [[BB15]]:2168; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr [[C]], align 162169; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[C]] to i642170; CHECK-NEXT: [[TMP17:%.*]] = xor i64 [[TMP16]], 1935140464885762171; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr2172; CHECK-NEXT: [[_MSLD2:%.*]] = load <2 x i64>, ptr [[TMP18]], align 162173; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[_MSLD]], [[_MSLD1]]2174; CHECK-NEXT: [[_MSPROP3:%.*]] = or <2 x i32> [[_MSPROP]], zeroinitializer2175; CHECK-NEXT: [[TMP19:%.*]] = zext <2 x i32> [[_MSPROP3]] to <2 x i64>2176; CHECK-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]])2177; CHECK-NEXT: [[_MSPROP4:%.*]] = or <2 x i64> [[_MSLD2]], [[TMP19]]2178; CHECK-NEXT: [[TMP5:%.*]] = sub <2 x i64> [[TMP3]], [[TMP4]]2179; CHECK-NEXT: store <2 x i64> [[_MSPROP4]], ptr @__msan_retval_tls, align 82180; CHECK-NEXT: ret <2 x i64> [[TMP5]]2181;2182 %temp1 = load <2 x i32>, ptr %A2183 %temp2 = load <2 x i32>, ptr %B2184 %temp3 = load <2 x i64>, ptr %C2185 %temp4 = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %temp1, <2 x i32> %temp2)2186 %temp5 = sub <2 x i64> %temp3, %temp42187 ret <2 x i64> %temp52188}2189 2190define void @umlsl8h_chain_with_constant(ptr %dst, <8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3) {2191; CHECK-LABEL: define void @umlsl8h_chain_with_constant(2192; CHECK-SAME: ptr [[DST:%.*]], <8 x i8> [[V1:%.*]], <8 x i8> [[V2:%.*]], <8 x i8> [[V3:%.*]]) {2193; CHECK-NEXT: call void @llvm.donothing()2194; CHECK-NEXT: [[XOR:%.*]] = xor <8 x i8> [[V3]], splat (i8 -1)2195; CHECK-NEXT: [[UMULL_1:%.*]] = tail call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> [[V1]], <8 x i8> [[V3]])2196; CHECK-NEXT: [[ADD_1:%.*]] = sub <8 x i16> splat (i16 257), [[UMULL_1]]2197; CHECK-NEXT: [[UMULL_2:%.*]] = tail call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> [[V2]], <8 x i8> [[XOR]])2198; CHECK-NEXT: [[ADD_2:%.*]] = sub <8 x i16> [[ADD_1]], [[UMULL_2]]2199; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[DST]] to i642200; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 1935140464885762201; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr2202; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr [[TMP3]], align 162203; CHECK-NEXT: store <8 x i16> [[ADD_2]], ptr [[DST]], align 162204; CHECK-NEXT: ret void2205;2206 %xor = xor <8 x i8> %v3, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>2207 %umull.1 = tail call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> %v1, <8 x i8> %v3)2208 %add.1 = sub <8 x i16> <i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257>, %umull.12209 %umull.2 = tail call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> %v2, <8 x i8> %xor)2210 %add.2 = sub <8 x i16> %add.1, %umull.22211 store <8 x i16> %add.2, ptr %dst2212 ret void2213}2214 2215define void @umlsl2d_chain_with_constant(ptr %dst, <2 x i32> %v1, <2 x i32> %v2, <2 x i32> %v3) {2216; CHECK-LABEL: define void @umlsl2d_chain_with_constant(2217; CHECK-SAME: ptr [[DST:%.*]], <2 x i32> [[V1:%.*]], <2 x i32> [[V2:%.*]], <2 x i32> [[V3:%.*]]) {2218; CHECK-NEXT: call void @llvm.donothing()2219; CHECK-NEXT: [[XOR:%.*]] = xor <2 x i32> [[V3]], splat (i32 -1)2220; CHECK-NEXT: [[UMULL_1:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[V1]], <2 x i32> [[V3]])2221; CHECK-NEXT: [[ADD_1:%.*]] = sub <2 x i64> splat (i64 257), [[UMULL_1]]2222; CHECK-NEXT: [[UMULL_2:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[V2]], <2 x i32> [[XOR]])2223; CHECK-NEXT: [[ADD_2:%.*]] = sub <2 x i64> [[ADD_1]], [[UMULL_2]]2224; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[DST]] to i642225; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 1935140464885762226; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr2227; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr [[TMP3]], align 162228; CHECK-NEXT: store <2 x i64> [[ADD_2]], ptr [[DST]], align 162229; CHECK-NEXT: ret void2230;2231 %xor = xor <2 x i32> %v3, <i32 -1, i32 -1>2232 %umull.1 = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %v1, <2 x i32> %v3)2233 %add.1 = sub <2 x i64> <i64 257, i64 257>, %umull.12234 %umull.2 = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %v2, <2 x i32> %xor)2235 %add.2 = sub <2 x i64> %add.1, %umull.22236 store <2 x i64> %add.2, ptr %dst2237 ret void2238}2239 2240define <2 x float> @fmla_2s(ptr %A, ptr %B, ptr %C) nounwind sanitize_memory {2241; CHECK-LABEL: define <2 x float> @fmla_2s(2242; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]]) #[[ATTR0]] {2243; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr @__msan_param_tls, align 82244; CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82245; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82246; CHECK-NEXT: call void @llvm.donothing()2247; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP5]], 02248; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]2249; CHECK: [[BB4]]:2250; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2251; CHECK-NEXT: unreachable2252; CHECK: [[BB5]]:2253; CHECK-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr [[A]], align 82254; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i642255; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 1935140464885762256; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr2257; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP8]], align 82258; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP9]], 02259; CHECK-NEXT: br i1 [[_MSCMP4]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]2260; CHECK: [[BB9]]:2261; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2262; CHECK-NEXT: unreachable2263; CHECK: [[BB10]]:2264; CHECK-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr [[B]], align 82265; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i642266; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 1935140464885762267; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr2268; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP13]], align 82269; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i64 [[TMP10]], 02270; CHECK-NEXT: br i1 [[_MSCMP5]], label %[[BB14:.*]], label %[[BB15:.*]], !prof [[PROF1]]2271; CHECK: [[BB14]]:2272; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2273; CHECK-NEXT: unreachable2274; CHECK: [[BB15]]:2275; CHECK-NEXT: [[TMP3:%.*]] = load <2 x float>, ptr [[C]], align 82276; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[C]] to i642277; CHECK-NEXT: [[TMP17:%.*]] = xor i64 [[TMP16]], 1935140464885762278; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr2279; CHECK-NEXT: [[_MSLD2:%.*]] = load <2 x i32>, ptr [[TMP18]], align 82280; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[_MSLD]], [[_MSLD1]]2281; CHECK-NEXT: [[_MSPROP3:%.*]] = or <2 x i32> [[_MSPROP]], [[_MSLD2]]2282; CHECK-NEXT: [[TMP4:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float> [[TMP1]], <2 x float> [[TMP2]], <2 x float> [[TMP3]])2283; CHECK-NEXT: store <2 x i32> [[_MSPROP3]], ptr @__msan_retval_tls, align 82284; CHECK-NEXT: ret <2 x float> [[TMP4]]2285;2286 %temp1 = load <2 x float>, ptr %A2287 %temp2 = load <2 x float>, ptr %B2288 %temp3 = load <2 x float>, ptr %C2289 %temp4 = call <2 x float> @llvm.fma.v2f32(<2 x float> %temp1, <2 x float> %temp2, <2 x float> %temp3)2290 ret <2 x float> %temp42291}2292 2293define <4 x float> @fmla_4s(ptr %A, ptr %B, ptr %C) nounwind sanitize_memory {2294; CHECK-LABEL: define <4 x float> @fmla_4s(2295; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]]) #[[ATTR0]] {2296; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr @__msan_param_tls, align 82297; CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82298; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82299; CHECK-NEXT: call void @llvm.donothing()2300; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP5]], 02301; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]2302; CHECK: [[BB4]]:2303; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2304; CHECK-NEXT: unreachable2305; CHECK: [[BB5]]:2306; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[A]], align 162307; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i642308; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 1935140464885762309; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr2310; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP8]], align 162311; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP9]], 02312; CHECK-NEXT: br i1 [[_MSCMP4]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]2313; CHECK: [[BB9]]:2314; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2315; CHECK-NEXT: unreachable2316; CHECK: [[BB10]]:2317; CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr [[B]], align 162318; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i642319; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 1935140464885762320; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr2321; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP13]], align 162322; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i64 [[TMP10]], 02323; CHECK-NEXT: br i1 [[_MSCMP5]], label %[[BB14:.*]], label %[[BB15:.*]], !prof [[PROF1]]2324; CHECK: [[BB14]]:2325; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2326; CHECK-NEXT: unreachable2327; CHECK: [[BB15]]:2328; CHECK-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr [[C]], align 162329; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[C]] to i642330; CHECK-NEXT: [[TMP17:%.*]] = xor i64 [[TMP16]], 1935140464885762331; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr2332; CHECK-NEXT: [[_MSLD2:%.*]] = load <4 x i32>, ptr [[TMP18]], align 162333; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[_MSLD]], [[_MSLD1]]2334; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i32> [[_MSPROP]], [[_MSLD2]]2335; CHECK-NEXT: [[TMP4:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[TMP1]], <4 x float> [[TMP2]], <4 x float> [[TMP3]])2336; CHECK-NEXT: store <4 x i32> [[_MSPROP3]], ptr @__msan_retval_tls, align 82337; CHECK-NEXT: ret <4 x float> [[TMP4]]2338;2339 %temp1 = load <4 x float>, ptr %A2340 %temp2 = load <4 x float>, ptr %B2341 %temp3 = load <4 x float>, ptr %C2342 %temp4 = call <4 x float> @llvm.fma.v4f32(<4 x float> %temp1, <4 x float> %temp2, <4 x float> %temp3)2343 ret <4 x float> %temp42344}2345 2346define <2 x double> @fmla_2d(ptr %A, ptr %B, ptr %C) nounwind sanitize_memory {2347; CHECK-LABEL: define <2 x double> @fmla_2d(2348; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]]) #[[ATTR0]] {2349; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr @__msan_param_tls, align 82350; CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82351; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82352; CHECK-NEXT: call void @llvm.donothing()2353; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP5]], 02354; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]2355; CHECK: [[BB4]]:2356; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2357; CHECK-NEXT: unreachable2358; CHECK: [[BB5]]:2359; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[A]], align 162360; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i642361; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 1935140464885762362; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr2363; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP8]], align 162364; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP9]], 02365; CHECK-NEXT: br i1 [[_MSCMP4]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]2366; CHECK: [[BB9]]:2367; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2368; CHECK-NEXT: unreachable2369; CHECK: [[BB10]]:2370; CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr [[B]], align 162371; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i642372; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 1935140464885762373; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr2374; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP13]], align 162375; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i64 [[TMP10]], 02376; CHECK-NEXT: br i1 [[_MSCMP5]], label %[[BB14:.*]], label %[[BB15:.*]], !prof [[PROF1]]2377; CHECK: [[BB14]]:2378; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2379; CHECK-NEXT: unreachable2380; CHECK: [[BB15]]:2381; CHECK-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr [[C]], align 162382; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[C]] to i642383; CHECK-NEXT: [[TMP17:%.*]] = xor i64 [[TMP16]], 1935140464885762384; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr2385; CHECK-NEXT: [[_MSLD2:%.*]] = load <2 x i64>, ptr [[TMP18]], align 162386; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[_MSLD]], [[_MSLD1]]2387; CHECK-NEXT: [[_MSPROP3:%.*]] = or <2 x i64> [[_MSPROP]], [[_MSLD2]]2388; CHECK-NEXT: [[TMP4:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[TMP1]], <2 x double> [[TMP2]], <2 x double> [[TMP3]])2389; CHECK-NEXT: store <2 x i64> [[_MSPROP3]], ptr @__msan_retval_tls, align 82390; CHECK-NEXT: ret <2 x double> [[TMP4]]2391;2392 %temp1 = load <2 x double>, ptr %A2393 %temp2 = load <2 x double>, ptr %B2394 %temp3 = load <2 x double>, ptr %C2395 %temp4 = call <2 x double> @llvm.fma.v2f64(<2 x double> %temp1, <2 x double> %temp2, <2 x double> %temp3)2396 ret <2 x double> %temp42397}2398 2399declare <2 x float> @llvm.fma.v2f32(<2 x float>, <2 x float>, <2 x float>) nounwind readnone2400declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) nounwind readnone2401declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>) nounwind readnone2402 2403define <2 x float> @fmls_2s(ptr %A, ptr %B, ptr %C) nounwind sanitize_memory {2404; CHECK-LABEL: define <2 x float> @fmls_2s(2405; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]]) #[[ATTR0]] {2406; CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr @__msan_param_tls, align 82407; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82408; CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82409; CHECK-NEXT: call void @llvm.donothing()2410; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP9]], 02411; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]2412; CHECK: [[BB4]]:2413; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2414; CHECK-NEXT: unreachable2415; CHECK: [[BB5]]:2416; CHECK-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr [[A]], align 82417; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i642418; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 1935140464885762419; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr2420; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP8]], align 82421; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i64 [[TMP10]], 02422; CHECK-NEXT: br i1 [[_MSCMP5]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]2423; CHECK: [[BB9]]:2424; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2425; CHECK-NEXT: unreachable2426; CHECK: [[BB10]]:2427; CHECK-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr [[B]], align 82428; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i642429; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 1935140464885762430; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr2431; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP13]], align 82432; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i64 [[TMP14]], 02433; CHECK-NEXT: br i1 [[_MSCMP6]], label %[[BB14:.*]], label %[[BB15:.*]], !prof [[PROF1]]2434; CHECK: [[BB14]]:2435; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2436; CHECK-NEXT: unreachable2437; CHECK: [[BB15]]:2438; CHECK-NEXT: [[TMP3:%.*]] = load <2 x float>, ptr [[C]], align 82439; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[C]] to i642440; CHECK-NEXT: [[TMP17:%.*]] = xor i64 [[TMP16]], 1935140464885762441; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr2442; CHECK-NEXT: [[_MSLD2:%.*]] = load <2 x i32>, ptr [[TMP18]], align 82443; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> zeroinitializer, [[_MSLD1]]2444; CHECK-NEXT: [[TMP4:%.*]] = fsub <2 x float> splat (float -0.000000e+00), [[TMP2]]2445; CHECK-NEXT: [[_MSPROP3:%.*]] = or <2 x i32> [[_MSLD]], [[_MSPROP]]2446; CHECK-NEXT: [[_MSPROP4:%.*]] = or <2 x i32> [[_MSPROP3]], [[_MSLD2]]2447; CHECK-NEXT: [[TMP5:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float> [[TMP1]], <2 x float> [[TMP4]], <2 x float> [[TMP3]])2448; CHECK-NEXT: store <2 x i32> [[_MSPROP4]], ptr @__msan_retval_tls, align 82449; CHECK-NEXT: ret <2 x float> [[TMP5]]2450;2451 %temp1 = load <2 x float>, ptr %A2452 %temp2 = load <2 x float>, ptr %B2453 %temp3 = load <2 x float>, ptr %C2454 %temp4 = fsub <2 x float> <float -0.0, float -0.0>, %temp22455 %temp5 = call <2 x float> @llvm.fma.v2f32(<2 x float> %temp1, <2 x float> %temp4, <2 x float> %temp3)2456 ret <2 x float> %temp52457}2458 2459define <4 x float> @fmls_4s(ptr %A, ptr %B, ptr %C) nounwind sanitize_memory {2460; CHECK-LABEL: define <4 x float> @fmls_4s(2461; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]]) #[[ATTR0]] {2462; CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr @__msan_param_tls, align 82463; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82464; CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82465; CHECK-NEXT: call void @llvm.donothing()2466; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP9]], 02467; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]2468; CHECK: [[BB4]]:2469; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2470; CHECK-NEXT: unreachable2471; CHECK: [[BB5]]:2472; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[A]], align 162473; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i642474; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 1935140464885762475; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr2476; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP8]], align 162477; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i64 [[TMP10]], 02478; CHECK-NEXT: br i1 [[_MSCMP5]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]2479; CHECK: [[BB9]]:2480; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2481; CHECK-NEXT: unreachable2482; CHECK: [[BB10]]:2483; CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr [[B]], align 162484; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i642485; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 1935140464885762486; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr2487; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP13]], align 162488; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i64 [[TMP14]], 02489; CHECK-NEXT: br i1 [[_MSCMP6]], label %[[BB14:.*]], label %[[BB15:.*]], !prof [[PROF1]]2490; CHECK: [[BB14]]:2491; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2492; CHECK-NEXT: unreachable2493; CHECK: [[BB15]]:2494; CHECK-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr [[C]], align 162495; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[C]] to i642496; CHECK-NEXT: [[TMP17:%.*]] = xor i64 [[TMP16]], 1935140464885762497; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr2498; CHECK-NEXT: [[_MSLD2:%.*]] = load <4 x i32>, ptr [[TMP18]], align 162499; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> zeroinitializer, [[_MSLD1]]2500; CHECK-NEXT: [[TMP4:%.*]] = fsub <4 x float> splat (float -0.000000e+00), [[TMP2]]2501; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i32> [[_MSLD]], [[_MSPROP]]2502; CHECK-NEXT: [[_MSPROP4:%.*]] = or <4 x i32> [[_MSPROP3]], [[_MSLD2]]2503; CHECK-NEXT: [[TMP5:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[TMP1]], <4 x float> [[TMP4]], <4 x float> [[TMP3]])2504; CHECK-NEXT: store <4 x i32> [[_MSPROP4]], ptr @__msan_retval_tls, align 82505; CHECK-NEXT: ret <4 x float> [[TMP5]]2506;2507 %temp1 = load <4 x float>, ptr %A2508 %temp2 = load <4 x float>, ptr %B2509 %temp3 = load <4 x float>, ptr %C2510 %temp4 = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %temp22511 %temp5 = call <4 x float> @llvm.fma.v4f32(<4 x float> %temp1, <4 x float> %temp4, <4 x float> %temp3)2512 ret <4 x float> %temp52513}2514 2515define <2 x double> @fmls_2d(ptr %A, ptr %B, ptr %C) nounwind sanitize_memory {2516; CHECK-LABEL: define <2 x double> @fmls_2d(2517; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]]) #[[ATTR0]] {2518; CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr @__msan_param_tls, align 82519; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82520; CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82521; CHECK-NEXT: call void @llvm.donothing()2522; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP9]], 02523; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]2524; CHECK: [[BB4]]:2525; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2526; CHECK-NEXT: unreachable2527; CHECK: [[BB5]]:2528; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[A]], align 162529; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i642530; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 1935140464885762531; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr2532; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP8]], align 162533; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i64 [[TMP10]], 02534; CHECK-NEXT: br i1 [[_MSCMP5]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]2535; CHECK: [[BB9]]:2536; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2537; CHECK-NEXT: unreachable2538; CHECK: [[BB10]]:2539; CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr [[B]], align 162540; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i642541; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 1935140464885762542; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr2543; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP13]], align 162544; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i64 [[TMP14]], 02545; CHECK-NEXT: br i1 [[_MSCMP6]], label %[[BB14:.*]], label %[[BB15:.*]], !prof [[PROF1]]2546; CHECK: [[BB14]]:2547; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2548; CHECK-NEXT: unreachable2549; CHECK: [[BB15]]:2550; CHECK-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr [[C]], align 162551; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[C]] to i642552; CHECK-NEXT: [[TMP17:%.*]] = xor i64 [[TMP16]], 1935140464885762553; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr2554; CHECK-NEXT: [[_MSLD2:%.*]] = load <2 x i64>, ptr [[TMP18]], align 162555; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> zeroinitializer, [[_MSLD1]]2556; CHECK-NEXT: [[TMP4:%.*]] = fsub <2 x double> splat (double -0.000000e+00), [[TMP2]]2557; CHECK-NEXT: [[_MSPROP3:%.*]] = or <2 x i64> [[_MSLD]], [[_MSPROP]]2558; CHECK-NEXT: [[_MSPROP4:%.*]] = or <2 x i64> [[_MSPROP3]], [[_MSLD2]]2559; CHECK-NEXT: [[TMP5:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[TMP1]], <2 x double> [[TMP4]], <2 x double> [[TMP3]])2560; CHECK-NEXT: store <2 x i64> [[_MSPROP4]], ptr @__msan_retval_tls, align 82561; CHECK-NEXT: ret <2 x double> [[TMP5]]2562;2563 %temp1 = load <2 x double>, ptr %A2564 %temp2 = load <2 x double>, ptr %B2565 %temp3 = load <2 x double>, ptr %C2566 %temp4 = fsub <2 x double> <double -0.0, double -0.0>, %temp22567 %temp5 = call <2 x double> @llvm.fma.v2f64(<2 x double> %temp1, <2 x double> %temp4, <2 x double> %temp3)2568 ret <2 x double> %temp52569}2570 2571define <2 x float> @fmls_commuted_neg_2s(ptr %A, ptr %B, ptr %C) nounwind sanitize_memory {2572; CHECK-LABEL: define <2 x float> @fmls_commuted_neg_2s(2573; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]]) #[[ATTR0]] {2574; CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr @__msan_param_tls, align 82575; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82576; CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82577; CHECK-NEXT: call void @llvm.donothing()2578; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP9]], 02579; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]2580; CHECK: [[BB4]]:2581; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2582; CHECK-NEXT: unreachable2583; CHECK: [[BB5]]:2584; CHECK-NEXT: [[TMP1:%.*]] = load <2 x float>, ptr [[A]], align 82585; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i642586; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 1935140464885762587; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr2588; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP8]], align 82589; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i64 [[TMP10]], 02590; CHECK-NEXT: br i1 [[_MSCMP5]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]2591; CHECK: [[BB9]]:2592; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2593; CHECK-NEXT: unreachable2594; CHECK: [[BB10]]:2595; CHECK-NEXT: [[TMP2:%.*]] = load <2 x float>, ptr [[B]], align 82596; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i642597; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 1935140464885762598; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr2599; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP13]], align 82600; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i64 [[TMP14]], 02601; CHECK-NEXT: br i1 [[_MSCMP6]], label %[[BB14:.*]], label %[[BB15:.*]], !prof [[PROF1]]2602; CHECK: [[BB14]]:2603; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2604; CHECK-NEXT: unreachable2605; CHECK: [[BB15]]:2606; CHECK-NEXT: [[TMP3:%.*]] = load <2 x float>, ptr [[C]], align 82607; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[C]] to i642608; CHECK-NEXT: [[TMP17:%.*]] = xor i64 [[TMP16]], 1935140464885762609; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr2610; CHECK-NEXT: [[_MSLD2:%.*]] = load <2 x i32>, ptr [[TMP18]], align 82611; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> zeroinitializer, [[_MSLD1]]2612; CHECK-NEXT: [[TMP4:%.*]] = fsub <2 x float> splat (float -0.000000e+00), [[TMP2]]2613; CHECK-NEXT: [[_MSPROP3:%.*]] = or <2 x i32> [[_MSPROP]], [[_MSLD]]2614; CHECK-NEXT: [[_MSPROP4:%.*]] = or <2 x i32> [[_MSPROP3]], [[_MSLD2]]2615; CHECK-NEXT: [[TMP5:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float> [[TMP4]], <2 x float> [[TMP1]], <2 x float> [[TMP3]])2616; CHECK-NEXT: store <2 x i32> [[_MSPROP4]], ptr @__msan_retval_tls, align 82617; CHECK-NEXT: ret <2 x float> [[TMP5]]2618;2619 %temp1 = load <2 x float>, ptr %A2620 %temp2 = load <2 x float>, ptr %B2621 %temp3 = load <2 x float>, ptr %C2622 %temp4 = fsub <2 x float> <float -0.0, float -0.0>, %temp22623 %temp5 = call <2 x float> @llvm.fma.v2f32(<2 x float> %temp4, <2 x float> %temp1, <2 x float> %temp3)2624 ret <2 x float> %temp52625}2626 2627define <4 x float> @fmls_commuted_neg_4s(ptr %A, ptr %B, ptr %C) nounwind sanitize_memory {2628; CHECK-LABEL: define <4 x float> @fmls_commuted_neg_4s(2629; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]]) #[[ATTR0]] {2630; CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr @__msan_param_tls, align 82631; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82632; CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82633; CHECK-NEXT: call void @llvm.donothing()2634; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP9]], 02635; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]2636; CHECK: [[BB4]]:2637; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2638; CHECK-NEXT: unreachable2639; CHECK: [[BB5]]:2640; CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr [[A]], align 162641; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i642642; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 1935140464885762643; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr2644; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP8]], align 162645; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i64 [[TMP10]], 02646; CHECK-NEXT: br i1 [[_MSCMP5]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]2647; CHECK: [[BB9]]:2648; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2649; CHECK-NEXT: unreachable2650; CHECK: [[BB10]]:2651; CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr [[B]], align 162652; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i642653; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 1935140464885762654; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr2655; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP13]], align 162656; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i64 [[TMP14]], 02657; CHECK-NEXT: br i1 [[_MSCMP6]], label %[[BB14:.*]], label %[[BB15:.*]], !prof [[PROF1]]2658; CHECK: [[BB14]]:2659; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2660; CHECK-NEXT: unreachable2661; CHECK: [[BB15]]:2662; CHECK-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr [[C]], align 162663; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[C]] to i642664; CHECK-NEXT: [[TMP17:%.*]] = xor i64 [[TMP16]], 1935140464885762665; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr2666; CHECK-NEXT: [[_MSLD2:%.*]] = load <4 x i32>, ptr [[TMP18]], align 162667; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> zeroinitializer, [[_MSLD1]]2668; CHECK-NEXT: [[TMP4:%.*]] = fsub <4 x float> splat (float -0.000000e+00), [[TMP2]]2669; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i32> [[_MSPROP]], [[_MSLD]]2670; CHECK-NEXT: [[_MSPROP4:%.*]] = or <4 x i32> [[_MSPROP3]], [[_MSLD2]]2671; CHECK-NEXT: [[TMP5:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[TMP4]], <4 x float> [[TMP1]], <4 x float> [[TMP3]])2672; CHECK-NEXT: store <4 x i32> [[_MSPROP4]], ptr @__msan_retval_tls, align 82673; CHECK-NEXT: ret <4 x float> [[TMP5]]2674;2675 %temp1 = load <4 x float>, ptr %A2676 %temp2 = load <4 x float>, ptr %B2677 %temp3 = load <4 x float>, ptr %C2678 %temp4 = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %temp22679 %temp5 = call <4 x float> @llvm.fma.v4f32(<4 x float> %temp4, <4 x float> %temp1, <4 x float> %temp3)2680 ret <4 x float> %temp52681}2682 2683define <2 x double> @fmls_commuted_neg_2d(ptr %A, ptr %B, ptr %C) nounwind sanitize_memory {2684; CHECK-LABEL: define <2 x double> @fmls_commuted_neg_2d(2685; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]], ptr [[C:%.*]]) #[[ATTR0]] {2686; CHECK-NEXT: [[TMP9:%.*]] = load i64, ptr @__msan_param_tls, align 82687; CHECK-NEXT: [[TMP10:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82688; CHECK-NEXT: [[TMP14:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82689; CHECK-NEXT: call void @llvm.donothing()2690; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP9]], 02691; CHECK-NEXT: br i1 [[_MSCMP]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]2692; CHECK: [[BB4]]:2693; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2694; CHECK-NEXT: unreachable2695; CHECK: [[BB5]]:2696; CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr [[A]], align 162697; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[A]] to i642698; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 1935140464885762699; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr2700; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP8]], align 162701; CHECK-NEXT: [[_MSCMP5:%.*]] = icmp ne i64 [[TMP10]], 02702; CHECK-NEXT: br i1 [[_MSCMP5]], label %[[BB9:.*]], label %[[BB10:.*]], !prof [[PROF1]]2703; CHECK: [[BB9]]:2704; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2705; CHECK-NEXT: unreachable2706; CHECK: [[BB10]]:2707; CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr [[B]], align 162708; CHECK-NEXT: [[TMP11:%.*]] = ptrtoint ptr [[B]] to i642709; CHECK-NEXT: [[TMP12:%.*]] = xor i64 [[TMP11]], 1935140464885762710; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr2711; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP13]], align 162712; CHECK-NEXT: [[_MSCMP6:%.*]] = icmp ne i64 [[TMP14]], 02713; CHECK-NEXT: br i1 [[_MSCMP6]], label %[[BB14:.*]], label %[[BB15:.*]], !prof [[PROF1]]2714; CHECK: [[BB14]]:2715; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]2716; CHECK-NEXT: unreachable2717; CHECK: [[BB15]]:2718; CHECK-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr [[C]], align 162719; CHECK-NEXT: [[TMP16:%.*]] = ptrtoint ptr [[C]] to i642720; CHECK-NEXT: [[TMP17:%.*]] = xor i64 [[TMP16]], 1935140464885762721; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr2722; CHECK-NEXT: [[_MSLD2:%.*]] = load <2 x i64>, ptr [[TMP18]], align 162723; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> zeroinitializer, [[_MSLD1]]2724; CHECK-NEXT: [[TMP4:%.*]] = fsub <2 x double> splat (double -0.000000e+00), [[TMP2]]2725; CHECK-NEXT: [[_MSPROP3:%.*]] = or <2 x i64> [[_MSPROP]], [[_MSLD]]2726; CHECK-NEXT: [[_MSPROP4:%.*]] = or <2 x i64> [[_MSPROP3]], [[_MSLD2]]2727; CHECK-NEXT: [[TMP5:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[TMP4]], <2 x double> [[TMP1]], <2 x double> [[TMP3]])2728; CHECK-NEXT: store <2 x i64> [[_MSPROP4]], ptr @__msan_retval_tls, align 82729; CHECK-NEXT: ret <2 x double> [[TMP5]]2730;2731 %temp1 = load <2 x double>, ptr %A2732 %temp2 = load <2 x double>, ptr %B2733 %temp3 = load <2 x double>, ptr %C2734 %temp4 = fsub <2 x double> <double -0.0, double -0.0>, %temp22735 %temp5 = call <2 x double> @llvm.fma.v2f64(<2 x double> %temp4, <2 x double> %temp1, <2 x double> %temp3)2736 ret <2 x double> %temp52737}2738 2739define <2 x float> @fmls_indexed_2s(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind readnone ssp {2740; CHECK-LABEL: define <2 x float> @fmls_indexed_2s(2741; CHECK-SAME: <2 x float> [[A:%.*]], <2 x float> [[B:%.*]], <2 x float> [[C:%.*]]) #[[ATTR3:[0-9]+]] {2742; CHECK-NEXT: [[ENTRY:.*:]]2743; CHECK-NEXT: call void @llvm.donothing()2744; CHECK-NEXT: [[TMP0:%.*]] = fsub <2 x float> splat (float -0.000000e+00), [[C]]2745; CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x float> [[B]], <2 x float> undef, <2 x i32> zeroinitializer2746; CHECK-NEXT: [[FMLS1:%.*]] = tail call <2 x float> @llvm.fma.v2f32(<2 x float> [[TMP0]], <2 x float> [[LANE]], <2 x float> [[A]])2747; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr @__msan_retval_tls, align 82748; CHECK-NEXT: ret <2 x float> [[FMLS1]]2749;2750entry:2751 %0 = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %c2752 %lane = shufflevector <2 x float> %b, <2 x float> undef, <2 x i32> zeroinitializer2753 %fmls1 = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %0, <2 x float> %lane, <2 x float> %a)2754 ret <2 x float> %fmls12755}2756 2757define <4 x float> @fmls_indexed_4s(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind readnone ssp {2758; CHECK-LABEL: define <4 x float> @fmls_indexed_4s(2759; CHECK-SAME: <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> [[C:%.*]]) #[[ATTR3]] {2760; CHECK-NEXT: [[ENTRY:.*:]]2761; CHECK-NEXT: call void @llvm.donothing()2762; CHECK-NEXT: [[TMP0:%.*]] = fsub <4 x float> splat (float -0.000000e+00), [[C]]2763; CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x float> [[B]], <4 x float> undef, <4 x i32> zeroinitializer2764; CHECK-NEXT: [[FMLS1:%.*]] = tail call <4 x float> @llvm.fma.v4f32(<4 x float> [[TMP0]], <4 x float> [[LANE]], <4 x float> [[A]])2765; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 82766; CHECK-NEXT: ret <4 x float> [[FMLS1]]2767;2768entry:2769 %0 = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00>, %c2770 %lane = shufflevector <4 x float> %b, <4 x float> undef, <4 x i32> zeroinitializer2771 %fmls1 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %0, <4 x float> %lane, <4 x float> %a)2772 ret <4 x float> %fmls12773}2774 2775define <2 x double> @fmls_indexed_2d(<2 x double> %a, <2 x double> %b, <2 x double> %c) nounwind readnone ssp {2776; CHECK-LABEL: define <2 x double> @fmls_indexed_2d(2777; CHECK-SAME: <2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> [[C:%.*]]) #[[ATTR3]] {2778; CHECK-NEXT: [[ENTRY:.*:]]2779; CHECK-NEXT: call void @llvm.donothing()2780; CHECK-NEXT: [[TMP0:%.*]] = fsub <2 x double> splat (double -0.000000e+00), [[C]]2781; CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x double> [[B]], <2 x double> undef, <2 x i32> zeroinitializer2782; CHECK-NEXT: [[FMLS1:%.*]] = tail call <2 x double> @llvm.fma.v2f64(<2 x double> [[TMP0]], <2 x double> [[LANE]], <2 x double> [[A]])2783; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 82784; CHECK-NEXT: ret <2 x double> [[FMLS1]]2785;2786entry:2787 %0 = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %c2788 %lane = shufflevector <2 x double> %b, <2 x double> undef, <2 x i32> zeroinitializer2789 %fmls1 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %0, <2 x double> %lane, <2 x double> %a)2790 ret <2 x double> %fmls12791}2792 2793define <2 x float> @fmla_indexed_scalar_2s(<2 x float> %a, <2 x float> %b, float %c) nounwind readnone ssp {2794; CHECK-LABEL: define <2 x float> @fmla_indexed_scalar_2s(2795; CHECK-SAME: <2 x float> [[A:%.*]], <2 x float> [[B:%.*]], float [[C:%.*]]) #[[ATTR3]] {2796; CHECK-NEXT: [[ENTRY:.*:]]2797; CHECK-NEXT: call void @llvm.donothing()2798; CHECK-NEXT: [[V1:%.*]] = insertelement <2 x float> undef, float [[C]], i32 02799; CHECK-NEXT: [[V2:%.*]] = insertelement <2 x float> [[V1]], float [[C]], i32 12800; CHECK-NEXT: [[FMLA1:%.*]] = tail call <2 x float> @llvm.fma.v2f32(<2 x float> [[V1]], <2 x float> [[B]], <2 x float> [[A]]) #[[ATTR7:[0-9]+]]2801; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr @__msan_retval_tls, align 82802; CHECK-NEXT: ret <2 x float> [[FMLA1]]2803;2804entry:2805 %v1 = insertelement <2 x float> undef, float %c, i32 02806 %v2 = insertelement <2 x float> %v1, float %c, i32 12807 %fmla1 = tail call <2 x float> @llvm.fma.v2f32(<2 x float> %v1, <2 x float> %b, <2 x float> %a) nounwind2808 ret <2 x float> %fmla12809}2810 2811define <4 x float> @fmla_indexed_scalar_4s(<4 x float> %a, <4 x float> %b, float %c) nounwind readnone ssp {2812; CHECK-LABEL: define <4 x float> @fmla_indexed_scalar_4s(2813; CHECK-SAME: <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], float [[C:%.*]]) #[[ATTR3]] {2814; CHECK-NEXT: [[ENTRY:.*:]]2815; CHECK-NEXT: call void @llvm.donothing()2816; CHECK-NEXT: [[V1:%.*]] = insertelement <4 x float> undef, float [[C]], i32 02817; CHECK-NEXT: [[V2:%.*]] = insertelement <4 x float> [[V1]], float [[C]], i32 12818; CHECK-NEXT: [[V3:%.*]] = insertelement <4 x float> [[V2]], float [[C]], i32 22819; CHECK-NEXT: [[V4:%.*]] = insertelement <4 x float> [[V3]], float [[C]], i32 32820; CHECK-NEXT: [[FMLA1:%.*]] = tail call <4 x float> @llvm.fma.v4f32(<4 x float> [[V4]], <4 x float> [[B]], <4 x float> [[A]]) #[[ATTR7]]2821; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 82822; CHECK-NEXT: ret <4 x float> [[FMLA1]]2823;2824entry:2825 %v1 = insertelement <4 x float> undef, float %c, i32 02826 %v2 = insertelement <4 x float> %v1, float %c, i32 12827 %v3 = insertelement <4 x float> %v2, float %c, i32 22828 %v4 = insertelement <4 x float> %v3, float %c, i32 32829 %fmla1 = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %v4, <4 x float> %b, <4 x float> %a) nounwind2830 ret <4 x float> %fmla12831}2832 2833define <2 x double> @fmla_indexed_scalar_2d(<2 x double> %a, <2 x double> %b, double %c) nounwind readnone ssp {2834; CHECK-LABEL: define <2 x double> @fmla_indexed_scalar_2d(2835; CHECK-SAME: <2 x double> [[A:%.*]], <2 x double> [[B:%.*]], double [[C:%.*]]) #[[ATTR3]] {2836; CHECK-NEXT: [[ENTRY:.*:]]2837; CHECK-NEXT: call void @llvm.donothing()2838; CHECK-NEXT: [[V1:%.*]] = insertelement <2 x double> undef, double [[C]], i32 02839; CHECK-NEXT: [[V2:%.*]] = insertelement <2 x double> [[V1]], double [[C]], i32 12840; CHECK-NEXT: [[FMLA1:%.*]] = tail call <2 x double> @llvm.fma.v2f64(<2 x double> [[V2]], <2 x double> [[B]], <2 x double> [[A]]) #[[ATTR7]]2841; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 82842; CHECK-NEXT: ret <2 x double> [[FMLA1]]2843;2844entry:2845 %v1 = insertelement <2 x double> undef, double %c, i32 02846 %v2 = insertelement <2 x double> %v1, double %c, i32 12847 %fmla1 = tail call <2 x double> @llvm.fma.v2f64(<2 x double> %v2, <2 x double> %b, <2 x double> %a) nounwind2848 ret <2 x double> %fmla12849}2850 2851define <2 x float> @fmls_indexed_2s_strict(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind readnone ssp strictfp {2852; CHECK-LABEL: define <2 x float> @fmls_indexed_2s_strict(2853; CHECK-SAME: <2 x float> [[A:%.*]], <2 x float> [[B:%.*]], <2 x float> [[C:%.*]]) #[[ATTR4:[0-9]+]] {2854; CHECK-NEXT: [[ENTRY:.*:]]2855; CHECK-NEXT: call void @llvm.donothing()2856; CHECK-NEXT: [[TMP0:%.*]] = fneg <2 x float> [[C]]2857; CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x float> [[B]], <2 x float> undef, <2 x i32> zeroinitializer2858; CHECK-NEXT: [[FMLS1:%.*]] = tail call <2 x float> @llvm.experimental.constrained.fma.v2f32(<2 x float> [[TMP0]], <2 x float> [[LANE]], <2 x float> [[A]], metadata !"round.tonearest", metadata !"fpexcept.strict") #[[ATTR9:[0-9]+]]2859; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr @__msan_retval_tls, align 82860; CHECK-NEXT: ret <2 x float> [[FMLS1]]2861;2862entry:2863 %0 = fneg <2 x float> %c2864 %lane = shufflevector <2 x float> %b, <2 x float> undef, <2 x i32> zeroinitializer2865 %fmls1 = tail call <2 x float> @llvm.experimental.constrained.fma.v2f32(<2 x float> %0, <2 x float> %lane, <2 x float> %a, metadata !"round.tonearest", metadata !"fpexcept.strict") #02866 ret <2 x float> %fmls12867}2868 2869define <4 x float> @fmls_indexed_4s_strict(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind readnone ssp strictfp {2870; CHECK-LABEL: define <4 x float> @fmls_indexed_4s_strict(2871; CHECK-SAME: <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], <4 x float> [[C:%.*]]) #[[ATTR4]] {2872; CHECK-NEXT: [[ENTRY:.*:]]2873; CHECK-NEXT: call void @llvm.donothing()2874; CHECK-NEXT: [[TMP0:%.*]] = fneg <4 x float> [[C]]2875; CHECK-NEXT: [[LANE:%.*]] = shufflevector <4 x float> [[B]], <4 x float> undef, <4 x i32> zeroinitializer2876; CHECK-NEXT: [[FMLS1:%.*]] = tail call <4 x float> @llvm.experimental.constrained.fma.v4f32(<4 x float> [[TMP0]], <4 x float> [[LANE]], <4 x float> [[A]], metadata !"round.tonearest", metadata !"fpexcept.strict") #[[ATTR9]]2877; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 82878; CHECK-NEXT: ret <4 x float> [[FMLS1]]2879;2880entry:2881 %0 = fneg <4 x float> %c2882 %lane = shufflevector <4 x float> %b, <4 x float> undef, <4 x i32> zeroinitializer2883 %fmls1 = tail call <4 x float> @llvm.experimental.constrained.fma.v4f32(<4 x float> %0, <4 x float> %lane, <4 x float> %a, metadata !"round.tonearest", metadata !"fpexcept.strict") #02884 ret <4 x float> %fmls12885}2886 2887define <2 x double> @fmls_indexed_2d_strict(<2 x double> %a, <2 x double> %b, <2 x double> %c) nounwind readnone ssp strictfp {2888; CHECK-LABEL: define <2 x double> @fmls_indexed_2d_strict(2889; CHECK-SAME: <2 x double> [[A:%.*]], <2 x double> [[B:%.*]], <2 x double> [[C:%.*]]) #[[ATTR4]] {2890; CHECK-NEXT: [[ENTRY:.*:]]2891; CHECK-NEXT: call void @llvm.donothing()2892; CHECK-NEXT: [[TMP0:%.*]] = fneg <2 x double> [[C]]2893; CHECK-NEXT: [[LANE:%.*]] = shufflevector <2 x double> [[B]], <2 x double> undef, <2 x i32> zeroinitializer2894; CHECK-NEXT: [[FMLS1:%.*]] = tail call <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double> [[TMP0]], <2 x double> [[LANE]], <2 x double> [[A]], metadata !"round.tonearest", metadata !"fpexcept.strict") #[[ATTR9]]2895; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 82896; CHECK-NEXT: ret <2 x double> [[FMLS1]]2897;2898entry:2899 %0 = fneg <2 x double> %c2900 %lane = shufflevector <2 x double> %b, <2 x double> undef, <2 x i32> zeroinitializer2901 %fmls1 = tail call <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double> %0, <2 x double> %lane, <2 x double> %a, metadata !"round.tonearest", metadata !"fpexcept.strict") #02902 ret <2 x double> %fmls12903}2904 2905define <2 x float> @fmla_indexed_scalar_2s_strict(<2 x float> %a, <2 x float> %b, float %c) nounwind readnone ssp strictfp {2906; CHECK-LABEL: define <2 x float> @fmla_indexed_scalar_2s_strict(2907; CHECK-SAME: <2 x float> [[A:%.*]], <2 x float> [[B:%.*]], float [[C:%.*]]) #[[ATTR4]] {2908; CHECK-NEXT: [[ENTRY:.*:]]2909; CHECK-NEXT: call void @llvm.donothing()2910; CHECK-NEXT: [[V1:%.*]] = insertelement <2 x float> undef, float [[C]], i32 02911; CHECK-NEXT: [[V2:%.*]] = insertelement <2 x float> [[V1]], float [[C]], i32 12912; CHECK-NEXT: [[FMLA1:%.*]] = tail call <2 x float> @llvm.experimental.constrained.fma.v2f32(<2 x float> [[V2]], <2 x float> [[B]], <2 x float> [[A]], metadata !"round.tonearest", metadata !"fpexcept.strict") #[[ATTR9]]2913; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr @__msan_retval_tls, align 82914; CHECK-NEXT: ret <2 x float> [[FMLA1]]2915;2916entry:2917 %v1 = insertelement <2 x float> undef, float %c, i32 02918 %v2 = insertelement <2 x float> %v1, float %c, i32 12919 %fmla1 = tail call <2 x float> @llvm.experimental.constrained.fma.v2f32(<2 x float> %v2, <2 x float> %b, <2 x float> %a, metadata !"round.tonearest", metadata !"fpexcept.strict") #02920 ret <2 x float> %fmla12921}2922 2923define <4 x float> @fmla_indexed_scalar_4s_strict(<4 x float> %a, <4 x float> %b, float %c) nounwind readnone ssp strictfp {2924; CHECK-LABEL: define <4 x float> @fmla_indexed_scalar_4s_strict(2925; CHECK-SAME: <4 x float> [[A:%.*]], <4 x float> [[B:%.*]], float [[C:%.*]]) #[[ATTR4]] {2926; CHECK-NEXT: [[ENTRY:.*:]]2927; CHECK-NEXT: call void @llvm.donothing()2928; CHECK-NEXT: [[V1:%.*]] = insertelement <4 x float> undef, float [[C]], i32 02929; CHECK-NEXT: [[V2:%.*]] = insertelement <4 x float> [[V1]], float [[C]], i32 12930; CHECK-NEXT: [[V3:%.*]] = insertelement <4 x float> [[V2]], float [[C]], i32 22931; CHECK-NEXT: [[V4:%.*]] = insertelement <4 x float> [[V3]], float [[C]], i32 32932; CHECK-NEXT: [[FMLA1:%.*]] = tail call <4 x float> @llvm.experimental.constrained.fma.v4f32(<4 x float> [[V4]], <4 x float> [[B]], <4 x float> [[A]], metadata !"round.tonearest", metadata !"fpexcept.strict") #[[ATTR9]]2933; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 82934; CHECK-NEXT: ret <4 x float> [[FMLA1]]2935;2936entry:2937 %v1 = insertelement <4 x float> undef, float %c, i32 02938 %v2 = insertelement <4 x float> %v1, float %c, i32 12939 %v3 = insertelement <4 x float> %v2, float %c, i32 22940 %v4 = insertelement <4 x float> %v3, float %c, i32 32941 %fmla1 = tail call <4 x float> @llvm.experimental.constrained.fma.v4f32(<4 x float> %v4, <4 x float> %b, <4 x float> %a, metadata !"round.tonearest", metadata !"fpexcept.strict") #02942 ret <4 x float> %fmla12943}2944 2945define <2 x double> @fmla_indexed_scalar_2d_strict(<2 x double> %a, <2 x double> %b, double %c) nounwind readnone ssp strictfp {2946; CHECK-LABEL: define <2 x double> @fmla_indexed_scalar_2d_strict(2947; CHECK-SAME: <2 x double> [[A:%.*]], <2 x double> [[B:%.*]], double [[C:%.*]]) #[[ATTR4]] {2948; CHECK-NEXT: [[ENTRY:.*:]]2949; CHECK-NEXT: call void @llvm.donothing()2950; CHECK-NEXT: [[V1:%.*]] = insertelement <2 x double> undef, double [[C]], i32 02951; CHECK-NEXT: [[V2:%.*]] = insertelement <2 x double> [[V1]], double [[C]], i32 12952; CHECK-NEXT: [[FMLA1:%.*]] = tail call <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double> [[V2]], <2 x double> [[B]], <2 x double> [[A]], metadata !"round.tonearest", metadata !"fpexcept.strict") #[[ATTR9]]2953; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 82954; CHECK-NEXT: ret <2 x double> [[FMLA1]]2955;2956entry:2957 %v1 = insertelement <2 x double> undef, double %c, i32 02958 %v2 = insertelement <2 x double> %v1, double %c, i32 12959 %fmla1 = tail call <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double> %v2, <2 x double> %b, <2 x double> %a, metadata !"round.tonearest", metadata !"fpexcept.strict") #02960 ret <2 x double> %fmla12961}2962 2963attributes #0 = { strictfp }2964 2965declare <2 x float> @llvm.experimental.constrained.fma.v2f32(<2 x float>, <2 x float>, <2 x float>, metadata, metadata)2966declare <4 x float> @llvm.experimental.constrained.fma.v4f32(<4 x float>, <4 x float>, <4 x float>, metadata, metadata)2967declare <2 x double> @llvm.experimental.constrained.fma.v2f64(<2 x double>, <2 x double>, <2 x double>, metadata, metadata)2968 2969define <4 x i16> @mul_4h(<4 x i16> %A, <4 x i16> %B) nounwind sanitize_memory {2970; CHECK-LABEL: define <4 x i16> @mul_4h(2971; CHECK-SAME: <4 x i16> [[A:%.*]], <4 x i16> [[B:%.*]]) #[[ATTR0]] {2972; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82973; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr @__msan_param_tls, align 82974; CHECK-NEXT: call void @llvm.donothing()2975; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> splat (i16 -1), <4 x i32> <i32 1, i32 1, i32 1, i32 1>2976; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i16> [[B]], <4 x i16> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>2977; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i16> [[TMP2]], [[_MSPROP]]2978; CHECK-NEXT: [[TMP4:%.*]] = mul <4 x i16> [[A]], [[TMP3]]2979; CHECK-NEXT: store <4 x i16> [[_MSPROP1]], ptr @__msan_retval_tls, align 82980; CHECK-NEXT: ret <4 x i16> [[TMP4]]2981;2982 %temp3 = shufflevector <4 x i16> %B, <4 x i16> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>2983 %temp4 = mul <4 x i16> %A, %temp32984 ret <4 x i16> %temp42985}2986 2987define <8 x i16> @mul_8h(<8 x i16> %A, <8 x i16> %B) nounwind sanitize_memory {2988; CHECK-LABEL: define <8 x i16> @mul_8h(2989; CHECK-SAME: <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]]) #[[ATTR0]] {2990; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 82991; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 82992; CHECK-NEXT: call void @llvm.donothing()2993; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> splat (i16 -1), <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>2994; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> poison, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>2995; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i16> [[TMP2]], [[_MSPROP]]2996; CHECK-NEXT: [[TMP4:%.*]] = mul <8 x i16> [[A]], [[TMP3]]2997; CHECK-NEXT: store <8 x i16> [[_MSPROP1]], ptr @__msan_retval_tls, align 82998; CHECK-NEXT: ret <8 x i16> [[TMP4]]2999;3000 %temp3 = shufflevector <8 x i16> %B, <8 x i16> poison, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>3001 %temp4 = mul <8 x i16> %A, %temp33002 ret <8 x i16> %temp43003}3004 3005define <2 x i32> @mul_2s(<2 x i32> %A, <2 x i32> %B) nounwind sanitize_memory {3006; CHECK-LABEL: define <2 x i32> @mul_2s(3007; CHECK-SAME: <2 x i32> [[A:%.*]], <2 x i32> [[B:%.*]]) #[[ATTR0]] {3008; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83009; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 83010; CHECK-NEXT: call void @llvm.donothing()3011; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> splat (i32 -1), <2 x i32> <i32 1, i32 1>3012; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i32> [[B]], <2 x i32> poison, <2 x i32> <i32 1, i32 1>3013; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i32> [[TMP2]], [[_MSPROP]]3014; CHECK-NEXT: [[TMP4:%.*]] = mul <2 x i32> [[A]], [[TMP3]]3015; CHECK-NEXT: store <2 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 83016; CHECK-NEXT: ret <2 x i32> [[TMP4]]3017;3018 %temp3 = shufflevector <2 x i32> %B, <2 x i32> poison, <2 x i32> <i32 1, i32 1>3019 %temp4 = mul <2 x i32> %A, %temp33020 ret <2 x i32> %temp43021}3022 3023define <4 x i32> @mul_4s(<4 x i32> %A, <4 x i32> %B) nounwind sanitize_memory {3024; CHECK-LABEL: define <4 x i32> @mul_4s(3025; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) #[[ATTR0]] {3026; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83027; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 83028; CHECK-NEXT: call void @llvm.donothing()3029; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> splat (i32 -1), <4 x i32> <i32 1, i32 1, i32 1, i32 1>3030; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>3031; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[TMP2]], [[_MSPROP]]3032; CHECK-NEXT: [[TMP4:%.*]] = mul <4 x i32> [[A]], [[TMP3]]3033; CHECK-NEXT: store <4 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 83034; CHECK-NEXT: ret <4 x i32> [[TMP4]]3035;3036 %temp3 = shufflevector <4 x i32> %B, <4 x i32> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>3037 %temp4 = mul <4 x i32> %A, %temp33038 ret <4 x i32> %temp43039}3040 3041define <2 x i64> @mul_2d(<2 x i64> %A, <2 x i64> %B) nounwind sanitize_memory {3042; CHECK-LABEL: define <2 x i64> @mul_2d(3043; CHECK-SAME: <2 x i64> [[A:%.*]], <2 x i64> [[B:%.*]]) #[[ATTR0]] {3044; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 83045; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83046; CHECK-NEXT: call void @llvm.donothing()3047; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP3]], [[TMP2]]3048; CHECK-NEXT: [[TMP1:%.*]] = mul <2 x i64> [[A]], [[B]]3049; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 83050; CHECK-NEXT: ret <2 x i64> [[TMP1]]3051;3052 %temp1 = mul <2 x i64> %A, %B3053 ret <2 x i64> %temp13054}3055 3056define <2 x float> @fmul_lane_2s(<2 x float> %A, <2 x float> %B) nounwind sanitize_memory {3057; CHECK-LABEL: define <2 x float> @fmul_lane_2s(3058; CHECK-SAME: <2 x float> [[A:%.*]], <2 x float> [[B:%.*]]) #[[ATTR0]] {3059; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83060; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 83061; CHECK-NEXT: call void @llvm.donothing()3062; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> splat (i32 -1), <2 x i32> <i32 1, i32 1>3063; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x float> [[B]], <2 x float> poison, <2 x i32> <i32 1, i32 1>3064; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i32> [[TMP2]], [[_MSPROP]]3065; CHECK-NEXT: [[TMP4:%.*]] = fmul <2 x float> [[A]], [[TMP3]]3066; CHECK-NEXT: store <2 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 83067; CHECK-NEXT: ret <2 x float> [[TMP4]]3068;3069 %temp3 = shufflevector <2 x float> %B, <2 x float> poison, <2 x i32> <i32 1, i32 1>3070 %temp4 = fmul <2 x float> %A, %temp33071 ret <2 x float> %temp43072}3073 3074define <4 x float> @fmul_lane_4s(<4 x float> %A, <4 x float> %B) nounwind sanitize_memory {3075; CHECK-LABEL: define <4 x float> @fmul_lane_4s(3076; CHECK-SAME: <4 x float> [[A:%.*]], <4 x float> [[B:%.*]]) #[[ATTR0]] {3077; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83078; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 83079; CHECK-NEXT: call void @llvm.donothing()3080; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> splat (i32 -1), <4 x i32> <i32 1, i32 1, i32 1, i32 1>3081; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x float> [[B]], <4 x float> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>3082; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[TMP2]], [[_MSPROP]]3083; CHECK-NEXT: [[TMP4:%.*]] = fmul <4 x float> [[A]], [[TMP3]]3084; CHECK-NEXT: store <4 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 83085; CHECK-NEXT: ret <4 x float> [[TMP4]]3086;3087 %temp3 = shufflevector <4 x float> %B, <4 x float> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>3088 %temp4 = fmul <4 x float> %A, %temp33089 ret <4 x float> %temp43090}3091 3092define <2 x double> @fmul_lane_2d(<2 x double> %A, <2 x double> %B) nounwind sanitize_memory {3093; CHECK-LABEL: define <2 x double> @fmul_lane_2d(3094; CHECK-SAME: <2 x double> [[A:%.*]], <2 x double> [[B:%.*]]) #[[ATTR0]] {3095; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83096; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 83097; CHECK-NEXT: call void @llvm.donothing()3098; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> splat (i64 -1), <2 x i32> <i32 1, i32 1>3099; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[B]], <2 x double> poison, <2 x i32> <i32 1, i32 1>3100; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> [[TMP2]], [[_MSPROP]]3101; CHECK-NEXT: [[TMP4:%.*]] = fmul <2 x double> [[A]], [[TMP3]]3102; CHECK-NEXT: store <2 x i64> [[_MSPROP1]], ptr @__msan_retval_tls, align 83103; CHECK-NEXT: ret <2 x double> [[TMP4]]3104;3105 %temp3 = shufflevector <2 x double> %B, <2 x double> poison, <2 x i32> <i32 1, i32 1>3106 %temp4 = fmul <2 x double> %A, %temp33107 ret <2 x double> %temp43108}3109 3110define float @fmul_lane_s(float %A, <4 x float> %vec) nounwind sanitize_memory {3111; CHECK-LABEL: define float @fmul_lane_s(3112; CHECK-SAME: float [[A:%.*]], <4 x float> [[VEC:%.*]]) #[[ATTR0]] {3113; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83114; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_tls, align 83115; CHECK-NEXT: call void @llvm.donothing()3116; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <4 x i32> [[TMP1]], i32 33117; CHECK-NEXT: [[B:%.*]] = extractelement <4 x float> [[VEC]], i32 33118; CHECK-NEXT: [[_MSPROP1:%.*]] = or i32 [[TMP2]], [[_MSPROP]]3119; CHECK-NEXT: [[RES:%.*]] = fmul float [[A]], [[B]]3120; CHECK-NEXT: store i32 [[_MSPROP1]], ptr @__msan_retval_tls, align 83121; CHECK-NEXT: ret float [[RES]]3122;3123 %B = extractelement <4 x float> %vec, i32 33124 %res = fmul float %A, %B3125 ret float %res3126}3127 3128define double @fmul_lane_d(double %A, <2 x double> %vec) nounwind sanitize_memory {3129; CHECK-LABEL: define double @fmul_lane_d(3130; CHECK-SAME: double [[A:%.*]], <2 x double> [[VEC:%.*]]) #[[ATTR0]] {3131; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83132; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_param_tls, align 83133; CHECK-NEXT: call void @llvm.donothing()3134; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <2 x i64> [[TMP1]], i32 13135; CHECK-NEXT: [[B:%.*]] = extractelement <2 x double> [[VEC]], i32 13136; CHECK-NEXT: [[_MSPROP1:%.*]] = or i64 [[TMP2]], [[_MSPROP]]3137; CHECK-NEXT: [[RES:%.*]] = fmul double [[A]], [[B]]3138; CHECK-NEXT: store i64 [[_MSPROP1]], ptr @__msan_retval_tls, align 83139; CHECK-NEXT: ret double [[RES]]3140;3141 %B = extractelement <2 x double> %vec, i32 13142 %res = fmul double %A, %B3143 ret double %res3144}3145 3146 3147 3148define <2 x float> @fmulx_lane_2s(<2 x float> %A, <2 x float> %B) nounwind sanitize_memory {3149; CHECK-LABEL: define <2 x float> @fmulx_lane_2s(3150; CHECK-SAME: <2 x float> [[A:%.*]], <2 x float> [[B:%.*]]) #[[ATTR0]] {3151; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83152; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 83153; CHECK-NEXT: call void @llvm.donothing()3154; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> splat (i32 -1), <2 x i32> <i32 1, i32 1>3155; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x float> [[B]], <2 x float> poison, <2 x i32> <i32 1, i32 1>3156; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i32> [[TMP2]], [[_MSPROP]]3157; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i32> [[_MSPROP1]], zeroinitializer3158; CHECK-NEXT: [[TMP4:%.*]] = call <2 x float> @llvm.aarch64.neon.fmulx.v2f32(<2 x float> [[A]], <2 x float> [[TMP3]])3159; CHECK-NEXT: store <2 x i32> [[_MSPROP2]], ptr @__msan_retval_tls, align 83160; CHECK-NEXT: ret <2 x float> [[TMP4]]3161;3162 %temp3 = shufflevector <2 x float> %B, <2 x float> poison, <2 x i32> <i32 1, i32 1>3163 %temp4 = call <2 x float> @llvm.aarch64.neon.fmulx.v2f32(<2 x float> %A, <2 x float> %temp3)3164 ret <2 x float> %temp43165}3166 3167define <4 x float> @fmulx_lane_4s(<4 x float> %A, <4 x float> %B) nounwind sanitize_memory {3168; CHECK-LABEL: define <4 x float> @fmulx_lane_4s(3169; CHECK-SAME: <4 x float> [[A:%.*]], <4 x float> [[B:%.*]]) #[[ATTR0]] {3170; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83171; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 83172; CHECK-NEXT: call void @llvm.donothing()3173; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> splat (i32 -1), <4 x i32> <i32 1, i32 1, i32 1, i32 1>3174; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x float> [[B]], <4 x float> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>3175; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[TMP2]], [[_MSPROP]]3176; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i32> [[_MSPROP1]], zeroinitializer3177; CHECK-NEXT: [[TMP4:%.*]] = call <4 x float> @llvm.aarch64.neon.fmulx.v4f32(<4 x float> [[A]], <4 x float> [[TMP3]])3178; CHECK-NEXT: store <4 x i32> [[_MSPROP2]], ptr @__msan_retval_tls, align 83179; CHECK-NEXT: ret <4 x float> [[TMP4]]3180;3181 %temp3 = shufflevector <4 x float> %B, <4 x float> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>3182 %temp4 = call <4 x float> @llvm.aarch64.neon.fmulx.v4f32(<4 x float> %A, <4 x float> %temp3)3183 ret <4 x float> %temp43184}3185 3186define <2 x double> @fmulx_lane_2d(<2 x double> %A, <2 x double> %B) nounwind sanitize_memory {3187; CHECK-LABEL: define <2 x double> @fmulx_lane_2d(3188; CHECK-SAME: <2 x double> [[A:%.*]], <2 x double> [[B:%.*]]) #[[ATTR0]] {3189; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83190; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 83191; CHECK-NEXT: call void @llvm.donothing()3192; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i64> [[TMP1]], <2 x i64> splat (i64 -1), <2 x i32> <i32 1, i32 1>3193; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x double> [[B]], <2 x double> poison, <2 x i32> <i32 1, i32 1>3194; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> [[TMP2]], [[_MSPROP]]3195; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i64> [[_MSPROP1]], zeroinitializer3196; CHECK-NEXT: [[TMP4:%.*]] = call <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double> [[A]], <2 x double> [[TMP3]])3197; CHECK-NEXT: store <2 x i64> [[_MSPROP2]], ptr @__msan_retval_tls, align 83198; CHECK-NEXT: ret <2 x double> [[TMP4]]3199;3200 %temp3 = shufflevector <2 x double> %B, <2 x double> poison, <2 x i32> <i32 1, i32 1>3201 %temp4 = call <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double> %A, <2 x double> %temp3)3202 ret <2 x double> %temp43203}3204 3205define <4 x i16> @sqdmulh_lane_4h(<4 x i16> %A, <4 x i16> %B) nounwind sanitize_memory {3206; CHECK-LABEL: define <4 x i16> @sqdmulh_lane_4h(3207; CHECK-SAME: <4 x i16> [[A:%.*]], <4 x i16> [[B:%.*]]) #[[ATTR0]] {3208; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83209; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr @__msan_param_tls, align 83210; CHECK-NEXT: call void @llvm.donothing()3211; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> splat (i16 -1), <4 x i32> <i32 1, i32 1, i32 1, i32 1>3212; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i16> [[B]], <4 x i16> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>3213; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i16> [[TMP2]], [[_MSPROP]]3214; CHECK-NEXT: [[TMP4:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqdmulh.v4i16(<4 x i16> [[A]], <4 x i16> [[TMP3]])3215; CHECK-NEXT: store <4 x i16> [[_MSPROP1]], ptr @__msan_retval_tls, align 83216; CHECK-NEXT: ret <4 x i16> [[TMP4]]3217;3218 %temp3 = shufflevector <4 x i16> %B, <4 x i16> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>3219 %temp4 = call <4 x i16> @llvm.aarch64.neon.sqdmulh.v4i16(<4 x i16> %A, <4 x i16> %temp3)3220 ret <4 x i16> %temp43221}3222 3223define <8 x i16> @sqdmulh_lane_8h(<8 x i16> %A, <8 x i16> %B) nounwind sanitize_memory {3224; CHECK-LABEL: define <8 x i16> @sqdmulh_lane_8h(3225; CHECK-SAME: <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]]) #[[ATTR0]] {3226; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83227; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 83228; CHECK-NEXT: call void @llvm.donothing()3229; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> splat (i16 -1), <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>3230; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> poison, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>3231; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i16> [[TMP2]], [[_MSPROP]]3232; CHECK-NEXT: [[TMP4:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqdmulh.v8i16(<8 x i16> [[A]], <8 x i16> [[TMP3]])3233; CHECK-NEXT: store <8 x i16> [[_MSPROP1]], ptr @__msan_retval_tls, align 83234; CHECK-NEXT: ret <8 x i16> [[TMP4]]3235;3236 %temp3 = shufflevector <8 x i16> %B, <8 x i16> poison, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>3237 %temp4 = call <8 x i16> @llvm.aarch64.neon.sqdmulh.v8i16(<8 x i16> %A, <8 x i16> %temp3)3238 ret <8 x i16> %temp43239}3240 3241define <2 x i32> @sqdmulh_lane_2s(<2 x i32> %A, <2 x i32> %B) nounwind sanitize_memory {3242; CHECK-LABEL: define <2 x i32> @sqdmulh_lane_2s(3243; CHECK-SAME: <2 x i32> [[A:%.*]], <2 x i32> [[B:%.*]]) #[[ATTR0]] {3244; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83245; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 83246; CHECK-NEXT: call void @llvm.donothing()3247; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> splat (i32 -1), <2 x i32> <i32 1, i32 1>3248; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i32> [[B]], <2 x i32> poison, <2 x i32> <i32 1, i32 1>3249; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i32> [[TMP2]], [[_MSPROP]]3250; CHECK-NEXT: [[TMP4:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32> [[A]], <2 x i32> [[TMP3]])3251; CHECK-NEXT: store <2 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 83252; CHECK-NEXT: ret <2 x i32> [[TMP4]]3253;3254 %temp3 = shufflevector <2 x i32> %B, <2 x i32> poison, <2 x i32> <i32 1, i32 1>3255 %temp4 = call <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32> %A, <2 x i32> %temp3)3256 ret <2 x i32> %temp43257}3258 3259define <4 x i32> @sqdmulh_lane_4s(<4 x i32> %A, <4 x i32> %B) nounwind sanitize_memory {3260; CHECK-LABEL: define <4 x i32> @sqdmulh_lane_4s(3261; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) #[[ATTR0]] {3262; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83263; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 83264; CHECK-NEXT: call void @llvm.donothing()3265; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> splat (i32 -1), <4 x i32> <i32 1, i32 1, i32 1, i32 1>3266; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>3267; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[TMP2]], [[_MSPROP]]3268; CHECK-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmulh.v4i32(<4 x i32> [[A]], <4 x i32> [[TMP3]])3269; CHECK-NEXT: store <4 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 83270; CHECK-NEXT: ret <4 x i32> [[TMP4]]3271;3272 %temp3 = shufflevector <4 x i32> %B, <4 x i32> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>3273 %temp4 = call <4 x i32> @llvm.aarch64.neon.sqdmulh.v4i32(<4 x i32> %A, <4 x i32> %temp3)3274 ret <4 x i32> %temp43275}3276 3277define i32 @sqdmulh_lane_1s(i32 %A, <4 x i32> %B) nounwind sanitize_memory {3278; CHECK-LABEL: define i32 @sqdmulh_lane_1s(3279; CHECK-SAME: i32 [[A:%.*]], <4 x i32> [[B:%.*]]) #[[ATTR0]] {3280; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83281; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr @__msan_param_tls, align 83282; CHECK-NEXT: call void @llvm.donothing()3283; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <4 x i32> [[TMP3]], i32 13284; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i32> [[B]], i32 13285; CHECK-NEXT: [[_MSPROP1:%.*]] = or i32 [[TMP4]], [[_MSPROP]]3286; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.aarch64.neon.sqdmulh.i32(i32 [[A]], i32 [[TMP1]])3287; CHECK-NEXT: store i32 [[_MSPROP1]], ptr @__msan_retval_tls, align 83288; CHECK-NEXT: ret i32 [[TMP2]]3289;3290 %temp1 = extractelement <4 x i32> %B, i32 13291 %temp2 = call i32 @llvm.aarch64.neon.sqdmulh.i32(i32 %A, i32 %temp1)3292 ret i32 %temp23293}3294 3295define <4 x i16> @sqrdmulh_lane_4h(<4 x i16> %A, <4 x i16> %B) nounwind sanitize_memory {3296; CHECK-LABEL: define <4 x i16> @sqrdmulh_lane_4h(3297; CHECK-SAME: <4 x i16> [[A:%.*]], <4 x i16> [[B:%.*]]) #[[ATTR0]] {3298; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83299; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr @__msan_param_tls, align 83300; CHECK-NEXT: call void @llvm.donothing()3301; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> splat (i16 -1), <4 x i32> <i32 1, i32 1, i32 1, i32 1>3302; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i16> [[B]], <4 x i16> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>3303; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i16> [[TMP2]], [[_MSPROP]]3304; CHECK-NEXT: [[TMP4:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> [[A]], <4 x i16> [[TMP3]])3305; CHECK-NEXT: store <4 x i16> [[_MSPROP1]], ptr @__msan_retval_tls, align 83306; CHECK-NEXT: ret <4 x i16> [[TMP4]]3307;3308 %temp3 = shufflevector <4 x i16> %B, <4 x i16> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>3309 %temp4 = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %A, <4 x i16> %temp3)3310 ret <4 x i16> %temp43311}3312 3313define <8 x i16> @sqrdmulh_lane_8h(<8 x i16> %A, <8 x i16> %B) nounwind sanitize_memory {3314; CHECK-LABEL: define <8 x i16> @sqrdmulh_lane_8h(3315; CHECK-SAME: <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]]) #[[ATTR0]] {3316; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83317; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 83318; CHECK-NEXT: call void @llvm.donothing()3319; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> splat (i16 -1), <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>3320; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> poison, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>3321; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i16> [[TMP2]], [[_MSPROP]]3322; CHECK-NEXT: [[TMP4:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> [[A]], <8 x i16> [[TMP3]])3323; CHECK-NEXT: store <8 x i16> [[_MSPROP1]], ptr @__msan_retval_tls, align 83324; CHECK-NEXT: ret <8 x i16> [[TMP4]]3325;3326 %temp3 = shufflevector <8 x i16> %B, <8 x i16> poison, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>3327 %temp4 = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %A, <8 x i16> %temp3)3328 ret <8 x i16> %temp43329}3330 3331define <2 x i32> @sqrdmulh_lane_2s(<2 x i32> %A, <2 x i32> %B) nounwind sanitize_memory {3332; CHECK-LABEL: define <2 x i32> @sqrdmulh_lane_2s(3333; CHECK-SAME: <2 x i32> [[A:%.*]], <2 x i32> [[B:%.*]]) #[[ATTR0]] {3334; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83335; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 83336; CHECK-NEXT: call void @llvm.donothing()3337; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> splat (i32 -1), <2 x i32> <i32 1, i32 1>3338; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i32> [[B]], <2 x i32> poison, <2 x i32> <i32 1, i32 1>3339; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i32> [[TMP2]], [[_MSPROP]]3340; CHECK-NEXT: [[TMP4:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> [[A]], <2 x i32> [[TMP3]])3341; CHECK-NEXT: store <2 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 83342; CHECK-NEXT: ret <2 x i32> [[TMP4]]3343;3344 %temp3 = shufflevector <2 x i32> %B, <2 x i32> poison, <2 x i32> <i32 1, i32 1>3345 %temp4 = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> %A, <2 x i32> %temp3)3346 ret <2 x i32> %temp43347}3348 3349define <4 x i32> @sqrdmulh_lane_4s(<4 x i32> %A, <4 x i32> %B) nounwind sanitize_memory {3350; CHECK-LABEL: define <4 x i32> @sqrdmulh_lane_4s(3351; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) #[[ATTR0]] {3352; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83353; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 83354; CHECK-NEXT: call void @llvm.donothing()3355; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> splat (i32 -1), <4 x i32> <i32 1, i32 1, i32 1, i32 1>3356; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>3357; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[TMP2]], [[_MSPROP]]3358; CHECK-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> [[A]], <4 x i32> [[TMP3]])3359; CHECK-NEXT: store <4 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 83360; CHECK-NEXT: ret <4 x i32> [[TMP4]]3361;3362 %temp3 = shufflevector <4 x i32> %B, <4 x i32> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>3363 %temp4 = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %A, <4 x i32> %temp3)3364 ret <4 x i32> %temp43365}3366 3367define i32 @sqrdmulh_lane_1s(i32 %A, <4 x i32> %B) nounwind sanitize_memory {3368; CHECK-LABEL: define i32 @sqrdmulh_lane_1s(3369; CHECK-SAME: i32 [[A:%.*]], <4 x i32> [[B:%.*]]) #[[ATTR0]] {3370; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83371; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr @__msan_param_tls, align 83372; CHECK-NEXT: call void @llvm.donothing()3373; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <4 x i32> [[TMP3]], i32 13374; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i32> [[B]], i32 13375; CHECK-NEXT: [[_MSPROP1:%.*]] = or i32 [[TMP4]], [[_MSPROP]]3376; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.aarch64.neon.sqrdmulh.i32(i32 [[A]], i32 [[TMP1]])3377; CHECK-NEXT: store i32 [[_MSPROP1]], ptr @__msan_retval_tls, align 83378; CHECK-NEXT: ret i32 [[TMP2]]3379;3380 %temp1 = extractelement <4 x i32> %B, i32 13381 %temp2 = call i32 @llvm.aarch64.neon.sqrdmulh.i32(i32 %A, i32 %temp1)3382 ret i32 %temp23383}3384 3385define <4 x i32> @sqdmull_lane_4s(<4 x i16> %A, <4 x i16> %B) nounwind sanitize_memory {3386; CHECK-LABEL: define <4 x i32> @sqdmull_lane_4s(3387; CHECK-SAME: <4 x i16> [[A:%.*]], <4 x i16> [[B:%.*]]) #[[ATTR0]] {3388; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83389; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr @__msan_param_tls, align 83390; CHECK-NEXT: call void @llvm.donothing()3391; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> splat (i16 -1), <4 x i32> <i32 1, i32 1, i32 1, i32 1>3392; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i16> [[B]], <4 x i16> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>3393; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i16> [[TMP2]] to i643394; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP5]], 03395; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i16> [[_MSPROP]] to i643396; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP6]], 03397; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3398; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]3399; CHECK: [[BB5]]:3400; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]3401; CHECK-NEXT: unreachable3402; CHECK: [[BB6]]:3403; CHECK-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[A]], <4 x i16> [[TMP3]])3404; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 83405; CHECK-NEXT: ret <4 x i32> [[TMP4]]3406;3407 %temp3 = shufflevector <4 x i16> %B, <4 x i16> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>3408 %temp4 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %A, <4 x i16> %temp3)3409 ret <4 x i32> %temp43410}3411 3412define <2 x i64> @sqdmull_lane_2d(<2 x i32> %A, <2 x i32> %B) nounwind sanitize_memory {3413; CHECK-LABEL: define <2 x i64> @sqdmull_lane_2d(3414; CHECK-SAME: <2 x i32> [[A:%.*]], <2 x i32> [[B:%.*]]) #[[ATTR0]] {3415; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83416; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 83417; CHECK-NEXT: call void @llvm.donothing()3418; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> splat (i32 -1), <2 x i32> <i32 1, i32 1>3419; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i32> [[B]], <2 x i32> poison, <2 x i32> <i32 1, i32 1>3420; CHECK-NEXT: [[TMP5:%.*]] = bitcast <2 x i32> [[TMP2]] to i643421; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP5]], 03422; CHECK-NEXT: [[TMP6:%.*]] = bitcast <2 x i32> [[_MSPROP]] to i643423; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP6]], 03424; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3425; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]3426; CHECK: [[BB5]]:3427; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]3428; CHECK-NEXT: unreachable3429; CHECK: [[BB6]]:3430; CHECK-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[A]], <2 x i32> [[TMP3]])3431; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 83432; CHECK-NEXT: ret <2 x i64> [[TMP4]]3433;3434 %temp3 = shufflevector <2 x i32> %B, <2 x i32> poison, <2 x i32> <i32 1, i32 1>3435 %temp4 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %A, <2 x i32> %temp3)3436 ret <2 x i64> %temp43437}3438 3439define <4 x i32> @sqdmull2_lane_4s(<8 x i16> %A, <8 x i16> %B) nounwind sanitize_memory {3440; CHECK-LABEL: define <4 x i32> @sqdmull2_lane_4s(3441; CHECK-SAME: <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]]) #[[ATTR0]] {3442; CHECK-NEXT: [[TMP5:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 83443; CHECK-NEXT: [[TMP6:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83444; CHECK-NEXT: call void @llvm.donothing()3445; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i16> [[TMP5]], <8 x i16> splat (i16 -1), <4 x i32> <i32 4, i32 5, i32 6, i32 7>3446; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>3447; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <8 x i16> [[TMP6]], <8 x i16> splat (i16 -1), <4 x i32> <i32 1, i32 1, i32 1, i32 1>3448; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>3449; CHECK-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[_MSPROP]] to i643450; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP3]], 03451; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[_MSPROP1]] to i643452; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP7]], 03453; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP2]]3454; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]3455; CHECK: [[BB5]]:3456; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]3457; CHECK-NEXT: unreachable3458; CHECK: [[BB6]]:3459; CHECK-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[TMP1]], <4 x i16> [[TMP2]])3460; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 83461; CHECK-NEXT: ret <4 x i32> [[TMP4]]3462;3463 %temp1 = shufflevector <8 x i16> %A, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>3464 %temp2 = shufflevector <8 x i16> %B, <8 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>3465 %temp4 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %temp1, <4 x i16> %temp2)3466 ret <4 x i32> %temp43467}3468 3469define <2 x i64> @sqdmull2_lane_2d(<4 x i32> %A, <4 x i32> %B) nounwind sanitize_memory {3470; CHECK-LABEL: define <2 x i64> @sqdmull2_lane_2d(3471; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) #[[ATTR0]] {3472; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 83473; CHECK-NEXT: [[TMP6:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83474; CHECK-NEXT: call void @llvm.donothing()3475; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i32> [[TMP5]], <4 x i32> splat (i32 -1), <2 x i32> <i32 2, i32 3>3476; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> undef, <2 x i32> <i32 2, i32 3>3477; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <4 x i32> [[TMP6]], <4 x i32> splat (i32 -1), <2 x i32> <i32 1, i32 1>3478; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> undef, <2 x i32> <i32 1, i32 1>3479; CHECK-NEXT: [[TMP3:%.*]] = bitcast <2 x i32> [[_MSPROP]] to i643480; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP3]], 03481; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i32> [[_MSPROP1]] to i643482; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP7]], 03483; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP2]]3484; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB5:.*]], label %[[BB6:.*]], !prof [[PROF1]]3485; CHECK: [[BB5]]:3486; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]3487; CHECK-NEXT: unreachable3488; CHECK: [[BB6]]:3489; CHECK-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]])3490; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 83491; CHECK-NEXT: ret <2 x i64> [[TMP4]]3492;3493 %temp1 = shufflevector <4 x i32> %A, <4 x i32> undef, <2 x i32> <i32 2, i32 3>3494 %temp2 = shufflevector <4 x i32> %B, <4 x i32> undef, <2 x i32> <i32 1, i32 1>3495 %temp4 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %temp1, <2 x i32> %temp2)3496 ret <2 x i64> %temp43497}3498 3499define <4 x i32> @umull_lane_4s(<4 x i16> %A, <4 x i16> %B) nounwind sanitize_memory {3500; CHECK-LABEL: define <4 x i32> @umull_lane_4s(3501; CHECK-SAME: <4 x i16> [[A:%.*]], <4 x i16> [[B:%.*]]) #[[ATTR0]] {3502; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83503; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr @__msan_param_tls, align 83504; CHECK-NEXT: call void @llvm.donothing()3505; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> splat (i16 -1), <4 x i32> <i32 1, i32 1, i32 1, i32 1>3506; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i16> [[B]], <4 x i16> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>3507; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i16> [[TMP2]], [[_MSPROP]]3508; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i16> [[_MSPROP1]], zeroinitializer3509; CHECK-NEXT: [[TMP5:%.*]] = zext <4 x i16> [[_MSPROP2]] to <4 x i32>3510; CHECK-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[A]], <4 x i16> [[TMP3]])3511; CHECK-NEXT: store <4 x i32> [[TMP5]], ptr @__msan_retval_tls, align 83512; CHECK-NEXT: ret <4 x i32> [[TMP4]]3513;3514 %temp3 = shufflevector <4 x i16> %B, <4 x i16> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>3515 %temp4 = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %A, <4 x i16> %temp3)3516 ret <4 x i32> %temp43517}3518 3519define <2 x i64> @umull_lane_2d(<2 x i32> %A, <2 x i32> %B) nounwind sanitize_memory {3520; CHECK-LABEL: define <2 x i64> @umull_lane_2d(3521; CHECK-SAME: <2 x i32> [[A:%.*]], <2 x i32> [[B:%.*]]) #[[ATTR0]] {3522; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83523; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 83524; CHECK-NEXT: call void @llvm.donothing()3525; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> splat (i32 -1), <2 x i32> <i32 1, i32 1>3526; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i32> [[B]], <2 x i32> poison, <2 x i32> <i32 1, i32 1>3527; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i32> [[TMP2]], [[_MSPROP]]3528; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i32> [[_MSPROP1]], zeroinitializer3529; CHECK-NEXT: [[TMP5:%.*]] = zext <2 x i32> [[_MSPROP2]] to <2 x i64>3530; CHECK-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[A]], <2 x i32> [[TMP3]])3531; CHECK-NEXT: store <2 x i64> [[TMP5]], ptr @__msan_retval_tls, align 83532; CHECK-NEXT: ret <2 x i64> [[TMP4]]3533;3534 %temp3 = shufflevector <2 x i32> %B, <2 x i32> poison, <2 x i32> <i32 1, i32 1>3535 %temp4 = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %A, <2 x i32> %temp3)3536 ret <2 x i64> %temp43537}3538 3539define <4 x i32> @smull_lane_4s(<4 x i16> %A, <4 x i16> %B) nounwind sanitize_memory {3540; CHECK-LABEL: define <4 x i32> @smull_lane_4s(3541; CHECK-SAME: <4 x i16> [[A:%.*]], <4 x i16> [[B:%.*]]) #[[ATTR0]] {3542; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83543; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr @__msan_param_tls, align 83544; CHECK-NEXT: call void @llvm.donothing()3545; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> splat (i16 -1), <4 x i32> <i32 1, i32 1, i32 1, i32 1>3546; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <4 x i16> [[B]], <4 x i16> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>3547; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i16> [[TMP2]], [[_MSPROP]]3548; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i16> [[_MSPROP1]], zeroinitializer3549; CHECK-NEXT: [[TMP5:%.*]] = zext <4 x i16> [[_MSPROP2]] to <4 x i32>3550; CHECK-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[A]], <4 x i16> [[TMP3]])3551; CHECK-NEXT: store <4 x i32> [[TMP5]], ptr @__msan_retval_tls, align 83552; CHECK-NEXT: ret <4 x i32> [[TMP4]]3553;3554 %temp3 = shufflevector <4 x i16> %B, <4 x i16> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>3555 %temp4 = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %A, <4 x i16> %temp3)3556 ret <4 x i32> %temp43557}3558 3559define <2 x i64> @smull_lane_2d(<2 x i32> %A, <2 x i32> %B) nounwind sanitize_memory {3560; CHECK-LABEL: define <2 x i64> @smull_lane_2d(3561; CHECK-SAME: <2 x i32> [[A:%.*]], <2 x i32> [[B:%.*]]) #[[ATTR0]] {3562; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83563; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 83564; CHECK-NEXT: call void @llvm.donothing()3565; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> splat (i32 -1), <2 x i32> <i32 1, i32 1>3566; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i32> [[B]], <2 x i32> poison, <2 x i32> <i32 1, i32 1>3567; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i32> [[TMP2]], [[_MSPROP]]3568; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i32> [[_MSPROP1]], zeroinitializer3569; CHECK-NEXT: [[TMP5:%.*]] = zext <2 x i32> [[_MSPROP2]] to <2 x i64>3570; CHECK-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[A]], <2 x i32> [[TMP3]])3571; CHECK-NEXT: store <2 x i64> [[TMP5]], ptr @__msan_retval_tls, align 83572; CHECK-NEXT: ret <2 x i64> [[TMP4]]3573;3574 %temp3 = shufflevector <2 x i32> %B, <2 x i32> poison, <2 x i32> <i32 1, i32 1>3575 %temp4 = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %A, <2 x i32> %temp3)3576 ret <2 x i64> %temp43577}3578 3579define <4 x i32> @smlal_lane_4s(<4 x i16> %A, <4 x i16> %B, <4 x i32> %C) nounwind sanitize_memory {3580; CHECK-LABEL: define <4 x i32> @smlal_lane_4s(3581; CHECK-SAME: <4 x i16> [[A:%.*]], <4 x i16> [[B:%.*]], <4 x i32> [[C:%.*]]) #[[ATTR0]] {3582; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83583; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr @__msan_param_tls, align 83584; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83585; CHECK-NEXT: call void @llvm.donothing()3586; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> splat (i16 -1), <4 x i32> <i32 1, i32 1, i32 1, i32 1>3587; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i16> [[B]], <4 x i16> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>3588; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i16> [[TMP2]], [[_MSPROP]]3589; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i16> [[_MSPROP1]], zeroinitializer3590; CHECK-NEXT: [[TMP7:%.*]] = zext <4 x i16> [[_MSPROP2]] to <4 x i32>3591; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[A]], <4 x i16> [[TMP4]])3592; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i32> [[TMP3]], [[TMP7]]3593; CHECK-NEXT: [[TMP6:%.*]] = add <4 x i32> [[C]], [[TMP5]]3594; CHECK-NEXT: store <4 x i32> [[_MSPROP3]], ptr @__msan_retval_tls, align 83595; CHECK-NEXT: ret <4 x i32> [[TMP6]]3596;3597 %temp4 = shufflevector <4 x i16> %B, <4 x i16> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>3598 %temp5 = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %A, <4 x i16> %temp4)3599 %temp6 = add <4 x i32> %C, %temp53600 ret <4 x i32> %temp63601}3602 3603define <2 x i64> @smlal_lane_2d(<2 x i32> %A, <2 x i32> %B, <2 x i64> %C) nounwind sanitize_memory {3604; CHECK-LABEL: define <2 x i64> @smlal_lane_2d(3605; CHECK-SAME: <2 x i32> [[A:%.*]], <2 x i32> [[B:%.*]], <2 x i64> [[C:%.*]]) #[[ATTR0]] {3606; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83607; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 83608; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83609; CHECK-NEXT: call void @llvm.donothing()3610; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> splat (i32 -1), <2 x i32> <i32 1, i32 1>3611; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[B]], <2 x i32> poison, <2 x i32> <i32 1, i32 1>3612; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i32> [[TMP2]], [[_MSPROP]]3613; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i32> [[_MSPROP1]], zeroinitializer3614; CHECK-NEXT: [[TMP7:%.*]] = zext <2 x i32> [[_MSPROP2]] to <2 x i64>3615; CHECK-NEXT: [[TMP5:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[A]], <2 x i32> [[TMP4]])3616; CHECK-NEXT: [[_MSPROP3:%.*]] = or <2 x i64> [[TMP3]], [[TMP7]]3617; CHECK-NEXT: [[TMP6:%.*]] = add <2 x i64> [[C]], [[TMP5]]3618; CHECK-NEXT: store <2 x i64> [[_MSPROP3]], ptr @__msan_retval_tls, align 83619; CHECK-NEXT: ret <2 x i64> [[TMP6]]3620;3621 %temp4 = shufflevector <2 x i32> %B, <2 x i32> poison, <2 x i32> <i32 1, i32 1>3622 %temp5 = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %A, <2 x i32> %temp4)3623 %temp6 = add <2 x i64> %C, %temp53624 ret <2 x i64> %temp63625}3626 3627define <4 x i32> @sqdmlal_lane_4s(<4 x i16> %A, <4 x i16> %B, <4 x i32> %C) nounwind sanitize_memory {3628; CHECK-LABEL: define <4 x i32> @sqdmlal_lane_4s(3629; CHECK-SAME: <4 x i16> [[A:%.*]], <4 x i16> [[B:%.*]], <4 x i32> [[C:%.*]]) #[[ATTR0]] {3630; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83631; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr @__msan_param_tls, align 83632; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83633; CHECK-NEXT: call void @llvm.donothing()3634; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> splat (i16 -1), <4 x i32> <i32 1, i32 1, i32 1, i32 1>3635; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i16> [[B]], <4 x i16> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>3636; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP2]] to i643637; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP7]], 03638; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i16> [[_MSPROP]] to i643639; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP8]], 03640; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP2]]3641; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]3642; CHECK: [[BB6]]:3643; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]3644; CHECK-NEXT: unreachable3645; CHECK: [[BB7]]:3646; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[A]], <4 x i16> [[TMP4]])3647; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[TMP3]], zeroinitializer3648; CHECK-NEXT: [[TMP6:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> [[C]], <4 x i32> [[TMP5]])3649; CHECK-NEXT: store <4 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 83650; CHECK-NEXT: ret <4 x i32> [[TMP6]]3651;3652 %temp4 = shufflevector <4 x i16> %B, <4 x i16> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>3653 %temp5 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %A, <4 x i16> %temp4)3654 %temp6 = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %C, <4 x i32> %temp5)3655 ret <4 x i32> %temp63656}3657 3658define <2 x i64> @sqdmlal_lane_2d(<2 x i32> %A, <2 x i32> %B, <2 x i64> %C) nounwind sanitize_memory {3659; CHECK-LABEL: define <2 x i64> @sqdmlal_lane_2d(3660; CHECK-SAME: <2 x i32> [[A:%.*]], <2 x i32> [[B:%.*]], <2 x i64> [[C:%.*]]) #[[ATTR0]] {3661; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83662; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 83663; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83664; CHECK-NEXT: call void @llvm.donothing()3665; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> splat (i32 -1), <2 x i32> <i32 1, i32 1>3666; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[B]], <2 x i32> poison, <2 x i32> <i32 1, i32 1>3667; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i32> [[TMP2]] to i643668; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP7]], 03669; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x i32> [[_MSPROP]] to i643670; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP8]], 03671; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP2]]3672; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]3673; CHECK: [[BB6]]:3674; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]3675; CHECK-NEXT: unreachable3676; CHECK: [[BB7]]:3677; CHECK-NEXT: [[TMP5:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[A]], <2 x i32> [[TMP4]])3678; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> [[TMP3]], zeroinitializer3679; CHECK-NEXT: [[TMP6:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> [[C]], <2 x i64> [[TMP5]])3680; CHECK-NEXT: store <2 x i64> [[_MSPROP1]], ptr @__msan_retval_tls, align 83681; CHECK-NEXT: ret <2 x i64> [[TMP6]]3682;3683 %temp4 = shufflevector <2 x i32> %B, <2 x i32> poison, <2 x i32> <i32 1, i32 1>3684 %temp5 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %A, <2 x i32> %temp4)3685 %temp6 = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %C, <2 x i64> %temp5)3686 ret <2 x i64> %temp63687}3688 3689define <4 x i32> @sqdmlal2_lane_4s(<8 x i16> %A, <8 x i16> %B, <4 x i32> %C) nounwind sanitize_memory {3690; CHECK-LABEL: define <4 x i32> @sqdmlal2_lane_4s(3691; CHECK-SAME: <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <4 x i32> [[C:%.*]]) #[[ATTR0]] {3692; CHECK-NEXT: [[TMP7:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 83693; CHECK-NEXT: [[TMP8:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83694; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 83695; CHECK-NEXT: call void @llvm.donothing()3696; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i16> [[TMP7]], <8 x i16> splat (i16 -1), <4 x i32> <i32 4, i32 5, i32 6, i32 7>3697; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>3698; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <8 x i16> [[TMP8]], <8 x i16> splat (i16 -1), <4 x i32> <i32 1, i32 1, i32 1, i32 1>3699; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>3700; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[_MSPROP]] to i643701; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 03702; CHECK-NEXT: [[TMP9:%.*]] = bitcast <4 x i16> [[_MSPROP1]] to i643703; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP9]], 03704; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP3]]3705; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]3706; CHECK: [[BB6]]:3707; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]3708; CHECK-NEXT: unreachable3709; CHECK: [[BB7]]:3710; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[TMP1]], <4 x i16> [[TMP2]])3711; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i32> [[TMP3]], zeroinitializer3712; CHECK-NEXT: [[TMP6:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> [[C]], <4 x i32> [[TMP5]])3713; CHECK-NEXT: store <4 x i32> [[_MSPROP2]], ptr @__msan_retval_tls, align 83714; CHECK-NEXT: ret <4 x i32> [[TMP6]]3715;3716 %temp1 = shufflevector <8 x i16> %A, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>3717 %temp2 = shufflevector <8 x i16> %B, <8 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>3718 %temp5 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %temp1, <4 x i16> %temp2)3719 %temp6 = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %C, <4 x i32> %temp5)3720 ret <4 x i32> %temp63721}3722 3723define <2 x i64> @sqdmlal2_lane_2d(<4 x i32> %A, <4 x i32> %B, <2 x i64> %C) nounwind sanitize_memory {3724; CHECK-LABEL: define <2 x i64> @sqdmlal2_lane_2d(3725; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <2 x i64> [[C:%.*]]) #[[ATTR0]] {3726; CHECK-NEXT: [[TMP7:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 83727; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83728; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 83729; CHECK-NEXT: call void @llvm.donothing()3730; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i32> [[TMP7]], <4 x i32> splat (i32 -1), <2 x i32> <i32 2, i32 3>3731; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> undef, <2 x i32> <i32 2, i32 3>3732; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <4 x i32> [[TMP8]], <4 x i32> splat (i32 -1), <2 x i32> <i32 1, i32 1>3733; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> undef, <2 x i32> <i32 1, i32 1>3734; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[_MSPROP]] to i643735; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 03736; CHECK-NEXT: [[TMP9:%.*]] = bitcast <2 x i32> [[_MSPROP1]] to i643737; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP9]], 03738; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP3]]3739; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]3740; CHECK: [[BB6]]:3741; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]3742; CHECK-NEXT: unreachable3743; CHECK: [[BB7]]:3744; CHECK-NEXT: [[TMP5:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]])3745; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i64> [[TMP3]], zeroinitializer3746; CHECK-NEXT: [[TMP6:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> [[C]], <2 x i64> [[TMP5]])3747; CHECK-NEXT: store <2 x i64> [[_MSPROP2]], ptr @__msan_retval_tls, align 83748; CHECK-NEXT: ret <2 x i64> [[TMP6]]3749;3750 %temp1 = shufflevector <4 x i32> %A, <4 x i32> undef, <2 x i32> <i32 2, i32 3>3751 %temp2 = shufflevector <4 x i32> %B, <4 x i32> undef, <2 x i32> <i32 1, i32 1>3752 %temp5 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %temp1, <2 x i32> %temp2)3753 %temp6 = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %C, <2 x i64> %temp5)3754 ret <2 x i64> %temp63755}3756 3757define i32 @sqdmlal_lane_1s(i32 %A, i16 %B, <4 x i16> %C) nounwind sanitize_memory {3758; CHECK-LABEL: define i32 @sqdmlal_lane_1s(3759; CHECK-SAME: i32 [[A:%.*]], i16 [[B:%.*]], <4 x i16> [[C:%.*]]) #[[ATTR0]] {3760; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83761; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83762; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr @__msan_param_tls, align 83763; CHECK-NEXT: call void @llvm.donothing()3764; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <4 x i16> splat (i16 -1), i16 [[TMP1]], i32 03765; CHECK-NEXT: [[LHS:%.*]] = insertelement <4 x i16> undef, i16 [[B]], i32 03766; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <4 x i16> [[TMP2]], <4 x i16> splat (i16 -1), <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>3767; CHECK-NEXT: [[RHS:%.*]] = shufflevector <4 x i16> [[C]], <4 x i16> undef, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>3768; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[_MSPROP]] to i643769; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 03770; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i16> [[_MSPROP1]] to i643771; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP5]], 03772; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP3]]3773; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]3774; CHECK: [[BB6]]:3775; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]3776; CHECK-NEXT: unreachable3777; CHECK: [[BB7]]:3778; CHECK-NEXT: [[PROD_VEC:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[LHS]], <4 x i16> [[RHS]])3779; CHECK-NEXT: [[PROD:%.*]] = extractelement <4 x i32> [[PROD_VEC]], i32 03780; CHECK-NEXT: [[_MSPROP2:%.*]] = or i32 [[TMP3]], 03781; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.aarch64.neon.sqadd.i32(i32 [[A]], i32 [[PROD]])3782; CHECK-NEXT: store i32 [[_MSPROP2]], ptr @__msan_retval_tls, align 83783; CHECK-NEXT: ret i32 [[RES]]3784;3785 %lhs = insertelement <4 x i16> undef, i16 %B, i32 03786 %rhs = shufflevector <4 x i16> %C, <4 x i16> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>3787 %prod.vec = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %lhs, <4 x i16> %rhs)3788 %prod = extractelement <4 x i32> %prod.vec, i32 03789 %res = call i32 @llvm.aarch64.neon.sqadd.i32(i32 %A, i32 %prod)3790 ret i32 %res3791}3792declare i32 @llvm.aarch64.neon.sqadd.i32(i32, i32)3793 3794define i32 @sqdmlsl_lane_1s(i32 %A, i16 %B, <4 x i16> %C) nounwind sanitize_memory {3795; CHECK-LABEL: define i32 @sqdmlsl_lane_1s(3796; CHECK-SAME: i32 [[A:%.*]], i16 [[B:%.*]], <4 x i16> [[C:%.*]]) #[[ATTR0]] {3797; CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83798; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83799; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr @__msan_param_tls, align 83800; CHECK-NEXT: call void @llvm.donothing()3801; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <4 x i16> splat (i16 -1), i16 [[TMP1]], i32 03802; CHECK-NEXT: [[LHS:%.*]] = insertelement <4 x i16> undef, i16 [[B]], i32 03803; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <4 x i16> [[TMP2]], <4 x i16> splat (i16 -1), <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>3804; CHECK-NEXT: [[RHS:%.*]] = shufflevector <4 x i16> [[C]], <4 x i16> undef, <4 x i32> <i32 1, i32 poison, i32 poison, i32 poison>3805; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[_MSPROP]] to i643806; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 03807; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i16> [[_MSPROP1]] to i643808; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP5]], 03809; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP3]]3810; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]3811; CHECK: [[BB6]]:3812; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]3813; CHECK-NEXT: unreachable3814; CHECK: [[BB7]]:3815; CHECK-NEXT: [[PROD_VEC:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[LHS]], <4 x i16> [[RHS]])3816; CHECK-NEXT: [[PROD:%.*]] = extractelement <4 x i32> [[PROD_VEC]], i32 03817; CHECK-NEXT: [[_MSPROP2:%.*]] = or i32 [[TMP3]], 03818; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.aarch64.neon.sqsub.i32(i32 [[A]], i32 [[PROD]])3819; CHECK-NEXT: store i32 [[_MSPROP2]], ptr @__msan_retval_tls, align 83820; CHECK-NEXT: ret i32 [[RES]]3821;3822 %lhs = insertelement <4 x i16> undef, i16 %B, i32 03823 %rhs = shufflevector <4 x i16> %C, <4 x i16> undef, <4 x i32> <i32 1, i32 undef, i32 undef, i32 undef>3824 %prod.vec = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %lhs, <4 x i16> %rhs)3825 %prod = extractelement <4 x i32> %prod.vec, i32 03826 %res = call i32 @llvm.aarch64.neon.sqsub.i32(i32 %A, i32 %prod)3827 ret i32 %res3828}3829declare i32 @llvm.aarch64.neon.sqsub.i32(i32, i32)3830 3831define i32 @sqadd_lane1_sqdmull4s(i32 %A, <4 x i16> %B, <4 x i16> %C) nounwind sanitize_memory {3832; CHECK-LABEL: define i32 @sqadd_lane1_sqdmull4s(3833; CHECK-SAME: i32 [[A:%.*]], <4 x i16> [[B:%.*]], <4 x i16> [[C:%.*]]) #[[ATTR0]] {3834; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83835; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83836; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr @__msan_param_tls, align 83837; CHECK-NEXT: call void @llvm.donothing()3838; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP1]] to i643839; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 03840; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i16> [[TMP2]] to i643841; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP5]], 03842; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3843; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]3844; CHECK: [[BB6]]:3845; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]3846; CHECK-NEXT: unreachable3847; CHECK: [[BB7]]:3848; CHECK-NEXT: [[PROD_VEC:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[B]], <4 x i16> [[C]])3849; CHECK-NEXT: [[PROD:%.*]] = extractelement <4 x i32> [[PROD_VEC]], i32 13850; CHECK-NEXT: [[_MSPROP:%.*]] = or i32 [[TMP3]], 03851; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.aarch64.neon.sqadd.i32(i32 [[A]], i32 [[PROD]])3852; CHECK-NEXT: store i32 [[_MSPROP]], ptr @__msan_retval_tls, align 83853; CHECK-NEXT: ret i32 [[RES]]3854;3855 %prod.vec = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %B, <4 x i16> %C)3856 %prod = extractelement <4 x i32> %prod.vec, i32 13857 %res = call i32 @llvm.aarch64.neon.sqadd.i32(i32 %A, i32 %prod)3858 ret i32 %res3859}3860 3861define i32 @sqsub_lane1_sqdmull4s(i32 %A, <4 x i16> %B, <4 x i16> %C) nounwind sanitize_memory {3862; CHECK-LABEL: define i32 @sqsub_lane1_sqdmull4s(3863; CHECK-SAME: i32 [[A:%.*]], <4 x i16> [[B:%.*]], <4 x i16> [[C:%.*]]) #[[ATTR0]] {3864; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83865; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83866; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr @__msan_param_tls, align 83867; CHECK-NEXT: call void @llvm.donothing()3868; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[TMP1]] to i643869; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 03870; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i16> [[TMP2]] to i643871; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i64 [[TMP5]], 03872; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]3873; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]3874; CHECK: [[BB6]]:3875; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]3876; CHECK-NEXT: unreachable3877; CHECK: [[BB7]]:3878; CHECK-NEXT: [[PROD_VEC:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[B]], <4 x i16> [[C]])3879; CHECK-NEXT: [[PROD:%.*]] = extractelement <4 x i32> [[PROD_VEC]], i32 13880; CHECK-NEXT: [[_MSPROP:%.*]] = or i32 [[TMP3]], 03881; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.aarch64.neon.sqsub.i32(i32 [[A]], i32 [[PROD]])3882; CHECK-NEXT: store i32 [[_MSPROP]], ptr @__msan_retval_tls, align 83883; CHECK-NEXT: ret i32 [[RES]]3884;3885 %prod.vec = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %B, <4 x i16> %C)3886 %prod = extractelement <4 x i32> %prod.vec, i32 13887 %res = call i32 @llvm.aarch64.neon.sqsub.i32(i32 %A, i32 %prod)3888 ret i32 %res3889}3890 3891define i64 @sqdmlal_lane_1d(i64 %A, i32 %B, <2 x i32> %C) nounwind sanitize_memory {3892; CHECK-LABEL: define i64 @sqdmlal_lane_1d(3893; CHECK-SAME: i64 [[A:%.*]], i32 [[B:%.*]], <2 x i32> [[C:%.*]]) #[[ATTR0]] {3894; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83895; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83896; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__msan_param_tls, align 83897; CHECK-NEXT: call void @llvm.donothing()3898; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <2 x i32> [[TMP1]], i32 13899; CHECK-NEXT: [[RHS:%.*]] = extractelement <2 x i32> [[C]], i32 13900; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP2]], 03901; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i32 [[_MSPROP]], 03902; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP2]]3903; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]3904; CHECK: [[BB4]]:3905; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]3906; CHECK-NEXT: unreachable3907; CHECK: [[BB5]]:3908; CHECK-NEXT: [[PROD:%.*]] = call i64 @llvm.aarch64.neon.sqdmulls.scalar(i32 [[B]], i32 [[RHS]])3909; CHECK-NEXT: [[_MSPROP1:%.*]] = or i64 [[TMP3]], 03910; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.aarch64.neon.sqadd.i64(i64 [[A]], i64 [[PROD]])3911; CHECK-NEXT: store i64 [[_MSPROP1]], ptr @__msan_retval_tls, align 83912; CHECK-NEXT: ret i64 [[RES]]3913;3914 %rhs = extractelement <2 x i32> %C, i32 13915 %prod = call i64 @llvm.aarch64.neon.sqdmulls.scalar(i32 %B, i32 %rhs)3916 %res = call i64 @llvm.aarch64.neon.sqadd.i64(i64 %A, i64 %prod)3917 ret i64 %res3918}3919declare i64 @llvm.aarch64.neon.sqdmulls.scalar(i32, i32)3920declare i64 @llvm.aarch64.neon.sqadd.i64(i64, i64)3921 3922define i64 @sqdmlsl_lane_1d(i64 %A, i32 %B, <2 x i32> %C) nounwind sanitize_memory {3923; CHECK-LABEL: define i64 @sqdmlsl_lane_1d(3924; CHECK-SAME: i64 [[A:%.*]], i32 [[B:%.*]], <2 x i32> [[C:%.*]]) #[[ATTR0]] {3925; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83926; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83927; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr @__msan_param_tls, align 83928; CHECK-NEXT: call void @llvm.donothing()3929; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <2 x i32> [[TMP1]], i32 13930; CHECK-NEXT: [[RHS:%.*]] = extractelement <2 x i32> [[C]], i32 13931; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP2]], 03932; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i32 [[_MSPROP]], 03933; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP2]]3934; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]3935; CHECK: [[BB4]]:3936; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]3937; CHECK-NEXT: unreachable3938; CHECK: [[BB5]]:3939; CHECK-NEXT: [[PROD:%.*]] = call i64 @llvm.aarch64.neon.sqdmulls.scalar(i32 [[B]], i32 [[RHS]])3940; CHECK-NEXT: [[_MSPROP1:%.*]] = or i64 [[TMP3]], 03941; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.aarch64.neon.sqsub.i64(i64 [[A]], i64 [[PROD]])3942; CHECK-NEXT: store i64 [[_MSPROP1]], ptr @__msan_retval_tls, align 83943; CHECK-NEXT: ret i64 [[RES]]3944;3945 %rhs = extractelement <2 x i32> %C, i32 13946 %prod = call i64 @llvm.aarch64.neon.sqdmulls.scalar(i32 %B, i32 %rhs)3947 %res = call i64 @llvm.aarch64.neon.sqsub.i64(i64 %A, i64 %prod)3948 ret i64 %res3949}3950declare i64 @llvm.aarch64.neon.sqsub.i64(i64, i64)3951 3952 3953define <4 x i32> @umlal_lane_4s(<4 x i16> %A, <4 x i16> %B, <4 x i32> %C) nounwind sanitize_memory {3954; CHECK-LABEL: define <4 x i32> @umlal_lane_4s(3955; CHECK-SAME: <4 x i16> [[A:%.*]], <4 x i16> [[B:%.*]], <4 x i32> [[C:%.*]]) #[[ATTR0]] {3956; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83957; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr @__msan_param_tls, align 83958; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83959; CHECK-NEXT: call void @llvm.donothing()3960; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> splat (i16 -1), <4 x i32> <i32 1, i32 1, i32 1, i32 1>3961; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i16> [[B]], <4 x i16> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>3962; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i16> [[TMP2]], [[_MSPROP]]3963; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i16> [[_MSPROP1]], zeroinitializer3964; CHECK-NEXT: [[TMP7:%.*]] = zext <4 x i16> [[_MSPROP2]] to <4 x i32>3965; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[A]], <4 x i16> [[TMP4]])3966; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i32> [[TMP3]], [[TMP7]]3967; CHECK-NEXT: [[TMP6:%.*]] = add <4 x i32> [[C]], [[TMP5]]3968; CHECK-NEXT: store <4 x i32> [[_MSPROP3]], ptr @__msan_retval_tls, align 83969; CHECK-NEXT: ret <4 x i32> [[TMP6]]3970;3971 %temp4 = shufflevector <4 x i16> %B, <4 x i16> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>3972 %temp5 = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %A, <4 x i16> %temp4)3973 %temp6 = add <4 x i32> %C, %temp53974 ret <4 x i32> %temp63975}3976 3977define <2 x i64> @umlal_lane_2d(<2 x i32> %A, <2 x i32> %B, <2 x i64> %C) nounwind sanitize_memory {3978; CHECK-LABEL: define <2 x i64> @umlal_lane_2d(3979; CHECK-SAME: <2 x i32> [[A:%.*]], <2 x i32> [[B:%.*]], <2 x i64> [[C:%.*]]) #[[ATTR0]] {3980; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83981; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 83982; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 83983; CHECK-NEXT: call void @llvm.donothing()3984; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> splat (i32 -1), <2 x i32> <i32 1, i32 1>3985; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[B]], <2 x i32> poison, <2 x i32> <i32 1, i32 1>3986; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i32> [[TMP2]], [[_MSPROP]]3987; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i32> [[_MSPROP1]], zeroinitializer3988; CHECK-NEXT: [[TMP7:%.*]] = zext <2 x i32> [[_MSPROP2]] to <2 x i64>3989; CHECK-NEXT: [[TMP5:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[A]], <2 x i32> [[TMP4]])3990; CHECK-NEXT: [[_MSPROP3:%.*]] = or <2 x i64> [[TMP3]], [[TMP7]]3991; CHECK-NEXT: [[TMP6:%.*]] = add <2 x i64> [[C]], [[TMP5]]3992; CHECK-NEXT: store <2 x i64> [[_MSPROP3]], ptr @__msan_retval_tls, align 83993; CHECK-NEXT: ret <2 x i64> [[TMP6]]3994;3995 %temp4 = shufflevector <2 x i32> %B, <2 x i32> poison, <2 x i32> <i32 1, i32 1>3996 %temp5 = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %A, <2 x i32> %temp4)3997 %temp6 = add <2 x i64> %C, %temp53998 ret <2 x i64> %temp63999}4000 4001 4002define <4 x i32> @smlsl_lane_4s(<4 x i16> %A, <4 x i16> %B, <4 x i32> %C) nounwind sanitize_memory {4003; CHECK-LABEL: define <4 x i32> @smlsl_lane_4s(4004; CHECK-SAME: <4 x i16> [[A:%.*]], <4 x i16> [[B:%.*]], <4 x i32> [[C:%.*]]) #[[ATTR0]] {4005; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 84006; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr @__msan_param_tls, align 84007; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84008; CHECK-NEXT: call void @llvm.donothing()4009; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> splat (i16 -1), <4 x i32> <i32 1, i32 1, i32 1, i32 1>4010; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i16> [[B]], <4 x i16> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>4011; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i16> [[TMP2]], [[_MSPROP]]4012; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i16> [[_MSPROP1]], zeroinitializer4013; CHECK-NEXT: [[TMP7:%.*]] = zext <4 x i16> [[_MSPROP2]] to <4 x i32>4014; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[A]], <4 x i16> [[TMP4]])4015; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i32> [[TMP3]], [[TMP7]]4016; CHECK-NEXT: [[TMP6:%.*]] = sub <4 x i32> [[C]], [[TMP5]]4017; CHECK-NEXT: store <4 x i32> [[_MSPROP3]], ptr @__msan_retval_tls, align 84018; CHECK-NEXT: ret <4 x i32> [[TMP6]]4019;4020 %temp4 = shufflevector <4 x i16> %B, <4 x i16> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>4021 %temp5 = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %A, <4 x i16> %temp4)4022 %temp6 = sub <4 x i32> %C, %temp54023 ret <4 x i32> %temp64024}4025 4026define <2 x i64> @smlsl_lane_2d(<2 x i32> %A, <2 x i32> %B, <2 x i64> %C) nounwind sanitize_memory {4027; CHECK-LABEL: define <2 x i64> @smlsl_lane_2d(4028; CHECK-SAME: <2 x i32> [[A:%.*]], <2 x i32> [[B:%.*]], <2 x i64> [[C:%.*]]) #[[ATTR0]] {4029; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 84030; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 84031; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84032; CHECK-NEXT: call void @llvm.donothing()4033; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> splat (i32 -1), <2 x i32> <i32 1, i32 1>4034; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[B]], <2 x i32> poison, <2 x i32> <i32 1, i32 1>4035; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i32> [[TMP2]], [[_MSPROP]]4036; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i32> [[_MSPROP1]], zeroinitializer4037; CHECK-NEXT: [[TMP7:%.*]] = zext <2 x i32> [[_MSPROP2]] to <2 x i64>4038; CHECK-NEXT: [[TMP5:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[A]], <2 x i32> [[TMP4]])4039; CHECK-NEXT: [[_MSPROP3:%.*]] = or <2 x i64> [[TMP3]], [[TMP7]]4040; CHECK-NEXT: [[TMP6:%.*]] = sub <2 x i64> [[C]], [[TMP5]]4041; CHECK-NEXT: store <2 x i64> [[_MSPROP3]], ptr @__msan_retval_tls, align 84042; CHECK-NEXT: ret <2 x i64> [[TMP6]]4043;4044 %temp4 = shufflevector <2 x i32> %B, <2 x i32> poison, <2 x i32> <i32 1, i32 1>4045 %temp5 = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %A, <2 x i32> %temp4)4046 %temp6 = sub <2 x i64> %C, %temp54047 ret <2 x i64> %temp64048}4049 4050define <4 x i32> @sqdmlsl_lane_4s(<4 x i16> %A, <4 x i16> %B, <4 x i32> %C) nounwind sanitize_memory {4051; CHECK-LABEL: define <4 x i32> @sqdmlsl_lane_4s(4052; CHECK-SAME: <4 x i16> [[A:%.*]], <4 x i16> [[B:%.*]], <4 x i32> [[C:%.*]]) #[[ATTR0]] {4053; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 84054; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr @__msan_param_tls, align 84055; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84056; CHECK-NEXT: call void @llvm.donothing()4057; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> splat (i16 -1), <4 x i32> <i32 1, i32 1, i32 1, i32 1>4058; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i16> [[B]], <4 x i16> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>4059; CHECK-NEXT: [[TMP7:%.*]] = bitcast <4 x i16> [[TMP2]] to i644060; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP7]], 04061; CHECK-NEXT: [[TMP8:%.*]] = bitcast <4 x i16> [[_MSPROP]] to i644062; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP8]], 04063; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP2]]4064; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]4065; CHECK: [[BB6]]:4066; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]4067; CHECK-NEXT: unreachable4068; CHECK: [[BB7]]:4069; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[A]], <4 x i16> [[TMP4]])4070; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[TMP3]], zeroinitializer4071; CHECK-NEXT: [[TMP6:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> [[C]], <4 x i32> [[TMP5]])4072; CHECK-NEXT: store <4 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 84073; CHECK-NEXT: ret <4 x i32> [[TMP6]]4074;4075 %temp4 = shufflevector <4 x i16> %B, <4 x i16> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>4076 %temp5 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %A, <4 x i16> %temp4)4077 %temp6 = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %C, <4 x i32> %temp5)4078 ret <4 x i32> %temp64079}4080 4081define <2 x i64> @sqdmlsl_lane_2d(<2 x i32> %A, <2 x i32> %B, <2 x i64> %C) nounwind sanitize_memory {4082; CHECK-LABEL: define <2 x i64> @sqdmlsl_lane_2d(4083; CHECK-SAME: <2 x i32> [[A:%.*]], <2 x i32> [[B:%.*]], <2 x i64> [[C:%.*]]) #[[ATTR0]] {4084; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 84085; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 84086; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84087; CHECK-NEXT: call void @llvm.donothing()4088; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> splat (i32 -1), <2 x i32> <i32 1, i32 1>4089; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[B]], <2 x i32> poison, <2 x i32> <i32 1, i32 1>4090; CHECK-NEXT: [[TMP7:%.*]] = bitcast <2 x i32> [[TMP2]] to i644091; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP7]], 04092; CHECK-NEXT: [[TMP8:%.*]] = bitcast <2 x i32> [[_MSPROP]] to i644093; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP8]], 04094; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP2]]4095; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]4096; CHECK: [[BB6]]:4097; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]4098; CHECK-NEXT: unreachable4099; CHECK: [[BB7]]:4100; CHECK-NEXT: [[TMP5:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[A]], <2 x i32> [[TMP4]])4101; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> [[TMP3]], zeroinitializer4102; CHECK-NEXT: [[TMP6:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> [[C]], <2 x i64> [[TMP5]])4103; CHECK-NEXT: store <2 x i64> [[_MSPROP1]], ptr @__msan_retval_tls, align 84104; CHECK-NEXT: ret <2 x i64> [[TMP6]]4105;4106 %temp4 = shufflevector <2 x i32> %B, <2 x i32> poison, <2 x i32> <i32 1, i32 1>4107 %temp5 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %A, <2 x i32> %temp4)4108 %temp6 = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %C, <2 x i64> %temp5)4109 ret <2 x i64> %temp64110}4111 4112define <4 x i32> @sqdmlsl2_lane_4s(<8 x i16> %A, <8 x i16> %B, <4 x i32> %C) nounwind sanitize_memory {4113; CHECK-LABEL: define <4 x i32> @sqdmlsl2_lane_4s(4114; CHECK-SAME: <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <4 x i32> [[C:%.*]]) #[[ATTR0]] {4115; CHECK-NEXT: [[TMP7:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 84116; CHECK-NEXT: [[TMP8:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84117; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84118; CHECK-NEXT: call void @llvm.donothing()4119; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i16> [[TMP7]], <8 x i16> splat (i16 -1), <4 x i32> <i32 4, i32 5, i32 6, i32 7>4120; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>4121; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <8 x i16> [[TMP8]], <8 x i16> splat (i16 -1), <4 x i32> <i32 1, i32 1, i32 1, i32 1>4122; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>4123; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i16> [[_MSPROP]] to i644124; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 04125; CHECK-NEXT: [[TMP9:%.*]] = bitcast <4 x i16> [[_MSPROP1]] to i644126; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP9]], 04127; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP3]]4128; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]4129; CHECK: [[BB6]]:4130; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]4131; CHECK-NEXT: unreachable4132; CHECK: [[BB7]]:4133; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[TMP1]], <4 x i16> [[TMP2]])4134; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i32> [[TMP3]], zeroinitializer4135; CHECK-NEXT: [[TMP6:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> [[C]], <4 x i32> [[TMP5]])4136; CHECK-NEXT: store <4 x i32> [[_MSPROP2]], ptr @__msan_retval_tls, align 84137; CHECK-NEXT: ret <4 x i32> [[TMP6]]4138;4139 %temp1 = shufflevector <8 x i16> %A, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>4140 %temp2 = shufflevector <8 x i16> %B, <8 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>4141 %temp5 = call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %temp1, <4 x i16> %temp2)4142 %temp6 = call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %C, <4 x i32> %temp5)4143 ret <4 x i32> %temp64144}4145 4146define <2 x i64> @sqdmlsl2_lane_2d(<4 x i32> %A, <4 x i32> %B, <2 x i64> %C) nounwind sanitize_memory {4147; CHECK-LABEL: define <2 x i64> @sqdmlsl2_lane_2d(4148; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <2 x i64> [[C:%.*]]) #[[ATTR0]] {4149; CHECK-NEXT: [[TMP7:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 84150; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84151; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84152; CHECK-NEXT: call void @llvm.donothing()4153; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i32> [[TMP7]], <4 x i32> splat (i32 -1), <2 x i32> <i32 2, i32 3>4154; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> undef, <2 x i32> <i32 2, i32 3>4155; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <4 x i32> [[TMP8]], <4 x i32> splat (i32 -1), <2 x i32> <i32 1, i32 1>4156; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> undef, <2 x i32> <i32 1, i32 1>4157; CHECK-NEXT: [[TMP4:%.*]] = bitcast <2 x i32> [[_MSPROP]] to i644158; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP4]], 04159; CHECK-NEXT: [[TMP9:%.*]] = bitcast <2 x i32> [[_MSPROP1]] to i644160; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP9]], 04161; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP3]]4162; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]4163; CHECK: [[BB6]]:4164; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]4165; CHECK-NEXT: unreachable4166; CHECK: [[BB7]]:4167; CHECK-NEXT: [[TMP5:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]])4168; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i64> [[TMP3]], zeroinitializer4169; CHECK-NEXT: [[TMP6:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> [[C]], <2 x i64> [[TMP5]])4170; CHECK-NEXT: store <2 x i64> [[_MSPROP2]], ptr @__msan_retval_tls, align 84171; CHECK-NEXT: ret <2 x i64> [[TMP6]]4172;4173 %temp1 = shufflevector <4 x i32> %A, <4 x i32> undef, <2 x i32> <i32 2, i32 3>4174 %temp2 = shufflevector <4 x i32> %B, <4 x i32> undef, <2 x i32> <i32 1, i32 1>4175 %temp5 = call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %temp1, <2 x i32> %temp2)4176 %temp6 = call <2 x i64> @llvm.aarch64.neon.sqsub.v2i64(<2 x i64> %C, <2 x i64> %temp5)4177 ret <2 x i64> %temp64178}4179 4180define <4 x i32> @umlsl_lane_4s(<4 x i16> %A, <4 x i16> %B, <4 x i32> %C) nounwind sanitize_memory {4181; CHECK-LABEL: define <4 x i32> @umlsl_lane_4s(4182; CHECK-SAME: <4 x i16> [[A:%.*]], <4 x i16> [[B:%.*]], <4 x i32> [[C:%.*]]) #[[ATTR0]] {4183; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 84184; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr @__msan_param_tls, align 84185; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84186; CHECK-NEXT: call void @llvm.donothing()4187; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i16> [[TMP1]], <4 x i16> splat (i16 -1), <4 x i32> <i32 1, i32 1, i32 1, i32 1>4188; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i16> [[B]], <4 x i16> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>4189; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i16> [[TMP2]], [[_MSPROP]]4190; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i16> [[_MSPROP1]], zeroinitializer4191; CHECK-NEXT: [[TMP7:%.*]] = zext <4 x i16> [[_MSPROP2]] to <4 x i32>4192; CHECK-NEXT: [[TMP5:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[A]], <4 x i16> [[TMP4]])4193; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i32> [[TMP3]], [[TMP7]]4194; CHECK-NEXT: [[TMP6:%.*]] = sub <4 x i32> [[C]], [[TMP5]]4195; CHECK-NEXT: store <4 x i32> [[_MSPROP3]], ptr @__msan_retval_tls, align 84196; CHECK-NEXT: ret <4 x i32> [[TMP6]]4197;4198 %temp4 = shufflevector <4 x i16> %B, <4 x i16> poison, <4 x i32> <i32 1, i32 1, i32 1, i32 1>4199 %temp5 = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %A, <4 x i16> %temp4)4200 %temp6 = sub <4 x i32> %C, %temp54201 ret <4 x i32> %temp64202}4203 4204define <2 x i64> @umlsl_lane_2d(<2 x i32> %A, <2 x i32> %B, <2 x i64> %C) nounwind sanitize_memory {4205; CHECK-LABEL: define <2 x i64> @umlsl_lane_2d(4206; CHECK-SAME: <2 x i32> [[A:%.*]], <2 x i32> [[B:%.*]], <2 x i64> [[C:%.*]]) #[[ATTR0]] {4207; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 84208; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr @__msan_param_tls, align 84209; CHECK-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84210; CHECK-NEXT: call void @llvm.donothing()4211; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i32> [[TMP1]], <2 x i32> splat (i32 -1), <2 x i32> <i32 1, i32 1>4212; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[B]], <2 x i32> poison, <2 x i32> <i32 1, i32 1>4213; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i32> [[TMP2]], [[_MSPROP]]4214; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i32> [[_MSPROP1]], zeroinitializer4215; CHECK-NEXT: [[TMP7:%.*]] = zext <2 x i32> [[_MSPROP2]] to <2 x i64>4216; CHECK-NEXT: [[TMP5:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[A]], <2 x i32> [[TMP4]])4217; CHECK-NEXT: [[_MSPROP3:%.*]] = or <2 x i64> [[TMP3]], [[TMP7]]4218; CHECK-NEXT: [[TMP6:%.*]] = sub <2 x i64> [[C]], [[TMP5]]4219; CHECK-NEXT: store <2 x i64> [[_MSPROP3]], ptr @__msan_retval_tls, align 84220; CHECK-NEXT: ret <2 x i64> [[TMP6]]4221;4222 %temp4 = shufflevector <2 x i32> %B, <2 x i32> poison, <2 x i32> <i32 1, i32 1>4223 %temp5 = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %A, <2 x i32> %temp4)4224 %temp6 = sub <2 x i64> %C, %temp54225 ret <2 x i64> %temp64226}4227 4228; Scalar FMULX4229define float @fmulxs(float %a, float %b) nounwind sanitize_memory {4230; CHECK-LABEL: define float @fmulxs(4231; CHECK-SAME: float [[A:%.*]], float [[B:%.*]]) #[[ATTR0]] {4232; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 84233; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 84234; CHECK-NEXT: call void @llvm.donothing()4235; CHECK-NEXT: [[_MSPROP:%.*]] = or i32 [[TMP1]], [[TMP2]]4236; CHECK-NEXT: [[_MSPROP1:%.*]] = or i32 [[_MSPROP]], 04237; CHECK-NEXT: [[FMULX_I:%.*]] = tail call float @llvm.aarch64.neon.fmulx.f32(float [[A]], float [[B]]) #[[ATTR7]]4238; CHECK-NEXT: store i32 [[_MSPROP1]], ptr @__msan_retval_tls, align 84239; CHECK-NEXT: ret float [[FMULX_I]]4240;4241 %fmulx.i = tail call float @llvm.aarch64.neon.fmulx.f32(float %a, float %b) nounwind4242 ret float %fmulx.i4243}4244 4245define double @fmulxd(double %a, double %b) nounwind sanitize_memory {4246; CHECK-LABEL: define double @fmulxd(4247; CHECK-SAME: double [[A:%.*]], double [[B:%.*]]) #[[ATTR0]] {4248; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84249; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 84250; CHECK-NEXT: call void @llvm.donothing()4251; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]]4252; CHECK-NEXT: [[_MSPROP1:%.*]] = or i64 [[_MSPROP]], 04253; CHECK-NEXT: [[FMULX_I:%.*]] = tail call double @llvm.aarch64.neon.fmulx.f64(double [[A]], double [[B]]) #[[ATTR7]]4254; CHECK-NEXT: store i64 [[_MSPROP1]], ptr @__msan_retval_tls, align 84255; CHECK-NEXT: ret double [[FMULX_I]]4256;4257 %fmulx.i = tail call double @llvm.aarch64.neon.fmulx.f64(double %a, double %b) nounwind4258 ret double %fmulx.i4259}4260 4261define float @fmulxs_lane(float %a, <4 x float> %vec) nounwind sanitize_memory {4262; CHECK-LABEL: define float @fmulxs_lane(4263; CHECK-SAME: float [[A:%.*]], <4 x float> [[VEC:%.*]]) #[[ATTR0]] {4264; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 84265; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_tls, align 84266; CHECK-NEXT: call void @llvm.donothing()4267; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <4 x i32> [[TMP1]], i32 34268; CHECK-NEXT: [[B:%.*]] = extractelement <4 x float> [[VEC]], i32 34269; CHECK-NEXT: [[_MSPROP1:%.*]] = or i32 [[TMP2]], [[_MSPROP]]4270; CHECK-NEXT: [[_MSPROP2:%.*]] = or i32 [[_MSPROP1]], 04271; CHECK-NEXT: [[FMULX_I:%.*]] = tail call float @llvm.aarch64.neon.fmulx.f32(float [[A]], float [[B]]) #[[ATTR7]]4272; CHECK-NEXT: store i32 [[_MSPROP2]], ptr @__msan_retval_tls, align 84273; CHECK-NEXT: ret float [[FMULX_I]]4274;4275 %b = extractelement <4 x float> %vec, i32 34276 %fmulx.i = tail call float @llvm.aarch64.neon.fmulx.f32(float %a, float %b) nounwind4277 ret float %fmulx.i4278}4279 4280define double @fmulxd_lane(double %a, <2 x double> %vec) nounwind sanitize_memory {4281; CHECK-LABEL: define double @fmulxd_lane(4282; CHECK-SAME: double [[A:%.*]], <2 x double> [[VEC:%.*]]) #[[ATTR0]] {4283; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 84284; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_param_tls, align 84285; CHECK-NEXT: call void @llvm.donothing()4286; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <2 x i64> [[TMP1]], i32 14287; CHECK-NEXT: [[B:%.*]] = extractelement <2 x double> [[VEC]], i32 14288; CHECK-NEXT: [[_MSPROP1:%.*]] = or i64 [[TMP2]], [[_MSPROP]]4289; CHECK-NEXT: [[_MSPROP2:%.*]] = or i64 [[_MSPROP1]], 04290; CHECK-NEXT: [[FMULX_I:%.*]] = tail call double @llvm.aarch64.neon.fmulx.f64(double [[A]], double [[B]]) #[[ATTR7]]4291; CHECK-NEXT: store i64 [[_MSPROP2]], ptr @__msan_retval_tls, align 84292; CHECK-NEXT: ret double [[FMULX_I]]4293;4294 %b = extractelement <2 x double> %vec, i32 14295 %fmulx.i = tail call double @llvm.aarch64.neon.fmulx.f64(double %a, double %b) nounwind4296 ret double %fmulx.i4297}4298 4299declare double @llvm.aarch64.neon.fmulx.f64(double, double) nounwind readnone4300declare float @llvm.aarch64.neon.fmulx.f32(float, float) nounwind readnone4301 4302 4303define <8 x i16> @smull2_8h_simple(<16 x i8> %a, <16 x i8> %b) nounwind sanitize_memory {4304; CHECK-LABEL: define <8 x i16> @smull2_8h_simple(4305; CHECK-SAME: <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]]) #[[ATTR0]] {4306; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i8>, ptr @__msan_param_tls, align 84307; CHECK-NEXT: [[TMP6:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84308; CHECK-NEXT: call void @llvm.donothing()4309; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <16 x i8> [[TMP4]], <16 x i8> splat (i8 -1), <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>4310; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>4311; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <16 x i8> [[TMP6]], <16 x i8> splat (i8 -1), <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>4312; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <16 x i8> [[B]], <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>4313; CHECK-NEXT: [[_MSPROP2:%.*]] = or <8 x i8> [[_MSPROP]], [[_MSPROP1]]4314; CHECK-NEXT: [[_MSPROP3:%.*]] = or <8 x i8> [[_MSPROP2]], zeroinitializer4315; CHECK-NEXT: [[TMP5:%.*]] = zext <8 x i8> [[_MSPROP3]] to <8 x i16>4316; CHECK-NEXT: [[TMP3:%.*]] = tail call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> [[TMP1]], <8 x i8> [[TMP2]])4317; CHECK-NEXT: store <8 x i16> [[TMP5]], ptr @__msan_retval_tls, align 84318; CHECK-NEXT: ret <8 x i16> [[TMP3]]4319;4320 %1 = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>4321 %2 = shufflevector <16 x i8> %b, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>4322 %3 = tail call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> %1, <8 x i8> %2) #24323 ret <8 x i16> %34324}4325 4326define <8 x i16> @foo0(<16 x i8> %a, <16 x i8> %b) nounwind sanitize_memory {4327; CHECK-LABEL: define <8 x i16> @foo0(4328; CHECK-SAME: <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]]) #[[ATTR0]] {4329; CHECK-NEXT: [[TMP8:%.*]] = load <16 x i8>, ptr @__msan_param_tls, align 84330; CHECK-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84331; CHECK-NEXT: call void @llvm.donothing()4332; CHECK-NEXT: [[TMP10:%.*]] = bitcast <16 x i8> [[TMP8]] to <2 x i64>4333; CHECK-NEXT: [[TMP:%.*]] = bitcast <16 x i8> [[A]] to <2 x i64>4334; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i64> [[TMP10]], <2 x i64> splat (i64 -1), <1 x i32> <i32 1>4335; CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <2 x i64> [[TMP]], <2 x i64> undef, <1 x i32> <i32 1>4336; CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>4337; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I]] to <8 x i8>4338; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP9]] to <2 x i64>4339; CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[B]] to <2 x i64>4340; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <2 x i64> [[TMP5]], <2 x i64> splat (i64 -1), <1 x i32> <i32 1>4341; CHECK-NEXT: [[SHUFFLE_I3_I:%.*]] = shufflevector <2 x i64> [[TMP2]], <2 x i64> undef, <1 x i32> <i32 1>4342; CHECK-NEXT: [[TMP6:%.*]] = bitcast <1 x i64> [[_MSPROP1]] to <8 x i8>4343; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[SHUFFLE_I3_I]] to <8 x i8>4344; CHECK-NEXT: [[_MSPROP2:%.*]] = or <8 x i8> [[TMP4]], [[TMP6]]4345; CHECK-NEXT: [[_MSPROP3:%.*]] = or <8 x i8> [[_MSPROP2]], zeroinitializer4346; CHECK-NEXT: [[TMP7:%.*]] = zext <8 x i8> [[_MSPROP3]] to <8 x i16>4347; CHECK-NEXT: [[VMULL_I_I:%.*]] = tail call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> [[TMP1]], <8 x i8> [[TMP3]]) #[[ATTR7]]4348; CHECK-NEXT: store <8 x i16> [[TMP7]], ptr @__msan_retval_tls, align 84349; CHECK-NEXT: ret <8 x i16> [[VMULL_I_I]]4350;4351 %temp = bitcast <16 x i8> %a to <2 x i64>4352 %shuffle.i.i = shufflevector <2 x i64> %temp, <2 x i64> undef, <1 x i32> <i32 1>4353 %temp1 = bitcast <1 x i64> %shuffle.i.i to <8 x i8>4354 %temp2 = bitcast <16 x i8> %b to <2 x i64>4355 %shuffle.i3.i = shufflevector <2 x i64> %temp2, <2 x i64> undef, <1 x i32> <i32 1>4356 %temp3 = bitcast <1 x i64> %shuffle.i3.i to <8 x i8>4357 %vmull.i.i = tail call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> %temp1, <8 x i8> %temp3) nounwind4358 ret <8 x i16> %vmull.i.i4359}4360 4361define <4 x i32> @foo1(<8 x i16> %a, <8 x i16> %b) nounwind sanitize_memory {4362; CHECK-LABEL: define <4 x i32> @foo1(4363; CHECK-SAME: <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]]) #[[ATTR0]] {4364; CHECK-NEXT: [[TMP8:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 84365; CHECK-NEXT: [[TMP9:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84366; CHECK-NEXT: call void @llvm.donothing()4367; CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x i16> [[TMP8]] to <2 x i64>4368; CHECK-NEXT: [[TMP:%.*]] = bitcast <8 x i16> [[A]] to <2 x i64>4369; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i64> [[TMP10]], <2 x i64> splat (i64 -1), <1 x i32> <i32 1>4370; CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <2 x i64> [[TMP]], <2 x i64> undef, <1 x i32> <i32 1>4371; CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>4372; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I]] to <4 x i16>4373; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP9]] to <2 x i64>4374; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[B]] to <2 x i64>4375; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <2 x i64> [[TMP5]], <2 x i64> splat (i64 -1), <1 x i32> <i32 1>4376; CHECK-NEXT: [[SHUFFLE_I3_I:%.*]] = shufflevector <2 x i64> [[TMP2]], <2 x i64> undef, <1 x i32> <i32 1>4377; CHECK-NEXT: [[TMP6:%.*]] = bitcast <1 x i64> [[_MSPROP1]] to <4 x i16>4378; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[SHUFFLE_I3_I]] to <4 x i16>4379; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i16> [[TMP4]], [[TMP6]]4380; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i16> [[_MSPROP2]], zeroinitializer4381; CHECK-NEXT: [[TMP7:%.*]] = zext <4 x i16> [[_MSPROP3]] to <4 x i32>4382; CHECK-NEXT: [[VMULL2_I_I:%.*]] = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[TMP1]], <4 x i16> [[TMP3]]) #[[ATTR7]]4383; CHECK-NEXT: store <4 x i32> [[TMP7]], ptr @__msan_retval_tls, align 84384; CHECK-NEXT: ret <4 x i32> [[VMULL2_I_I]]4385;4386 %temp = bitcast <8 x i16> %a to <2 x i64>4387 %shuffle.i.i = shufflevector <2 x i64> %temp, <2 x i64> undef, <1 x i32> <i32 1>4388 %temp1 = bitcast <1 x i64> %shuffle.i.i to <4 x i16>4389 %temp2 = bitcast <8 x i16> %b to <2 x i64>4390 %shuffle.i3.i = shufflevector <2 x i64> %temp2, <2 x i64> undef, <1 x i32> <i32 1>4391 %temp3 = bitcast <1 x i64> %shuffle.i3.i to <4 x i16>4392 %vmull2.i.i = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %temp1, <4 x i16> %temp3) nounwind4393 ret <4 x i32> %vmull2.i.i4394}4395 4396define <2 x i64> @foo2(<4 x i32> %a, <4 x i32> %b) nounwind sanitize_memory {4397; CHECK-LABEL: define <2 x i64> @foo2(4398; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) #[[ATTR0]] {4399; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 84400; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84401; CHECK-NEXT: call void @llvm.donothing()4402; CHECK-NEXT: [[TMP10:%.*]] = bitcast <4 x i32> [[TMP8]] to <2 x i64>4403; CHECK-NEXT: [[TMP:%.*]] = bitcast <4 x i32> [[A]] to <2 x i64>4404; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i64> [[TMP10]], <2 x i64> splat (i64 -1), <1 x i32> <i32 1>4405; CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <2 x i64> [[TMP]], <2 x i64> undef, <1 x i32> <i32 1>4406; CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <2 x i32>4407; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I]] to <2 x i32>4408; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP9]] to <2 x i64>4409; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[B]] to <2 x i64>4410; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <2 x i64> [[TMP5]], <2 x i64> splat (i64 -1), <1 x i32> <i32 1>4411; CHECK-NEXT: [[SHUFFLE_I3_I:%.*]] = shufflevector <2 x i64> [[TMP2]], <2 x i64> undef, <1 x i32> <i32 1>4412; CHECK-NEXT: [[TMP6:%.*]] = bitcast <1 x i64> [[_MSPROP1]] to <2 x i32>4413; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[SHUFFLE_I3_I]] to <2 x i32>4414; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i32> [[TMP4]], [[TMP6]]4415; CHECK-NEXT: [[_MSPROP3:%.*]] = or <2 x i32> [[_MSPROP2]], zeroinitializer4416; CHECK-NEXT: [[TMP7:%.*]] = zext <2 x i32> [[_MSPROP3]] to <2 x i64>4417; CHECK-NEXT: [[VMULL2_I_I:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[TMP1]], <2 x i32> [[TMP3]]) #[[ATTR7]]4418; CHECK-NEXT: store <2 x i64> [[TMP7]], ptr @__msan_retval_tls, align 84419; CHECK-NEXT: ret <2 x i64> [[VMULL2_I_I]]4420;4421 %temp = bitcast <4 x i32> %a to <2 x i64>4422 %shuffle.i.i = shufflevector <2 x i64> %temp, <2 x i64> undef, <1 x i32> <i32 1>4423 %temp1 = bitcast <1 x i64> %shuffle.i.i to <2 x i32>4424 %temp2 = bitcast <4 x i32> %b to <2 x i64>4425 %shuffle.i3.i = shufflevector <2 x i64> %temp2, <2 x i64> undef, <1 x i32> <i32 1>4426 %temp3 = bitcast <1 x i64> %shuffle.i3.i to <2 x i32>4427 %vmull2.i.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %temp1, <2 x i32> %temp3) nounwind4428 ret <2 x i64> %vmull2.i.i4429}4430 4431define <8 x i16> @foo3(<16 x i8> %a, <16 x i8> %b) nounwind sanitize_memory {4432; CHECK-LABEL: define <8 x i16> @foo3(4433; CHECK-SAME: <16 x i8> [[A:%.*]], <16 x i8> [[B:%.*]]) #[[ATTR0]] {4434; CHECK-NEXT: [[TMP8:%.*]] = load <16 x i8>, ptr @__msan_param_tls, align 84435; CHECK-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84436; CHECK-NEXT: call void @llvm.donothing()4437; CHECK-NEXT: [[TMP10:%.*]] = bitcast <16 x i8> [[TMP8]] to <2 x i64>4438; CHECK-NEXT: [[TMP:%.*]] = bitcast <16 x i8> [[A]] to <2 x i64>4439; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i64> [[TMP10]], <2 x i64> splat (i64 -1), <1 x i32> <i32 1>4440; CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <2 x i64> [[TMP]], <2 x i64> undef, <1 x i32> <i32 1>4441; CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>4442; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I]] to <8 x i8>4443; CHECK-NEXT: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP9]] to <2 x i64>4444; CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[B]] to <2 x i64>4445; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <2 x i64> [[TMP5]], <2 x i64> splat (i64 -1), <1 x i32> <i32 1>4446; CHECK-NEXT: [[SHUFFLE_I3_I:%.*]] = shufflevector <2 x i64> [[TMP2]], <2 x i64> undef, <1 x i32> <i32 1>4447; CHECK-NEXT: [[TMP6:%.*]] = bitcast <1 x i64> [[_MSPROP1]] to <8 x i8>4448; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[SHUFFLE_I3_I]] to <8 x i8>4449; CHECK-NEXT: [[_MSPROP2:%.*]] = or <8 x i8> [[TMP4]], [[TMP6]]4450; CHECK-NEXT: [[_MSPROP3:%.*]] = or <8 x i8> [[_MSPROP2]], zeroinitializer4451; CHECK-NEXT: [[TMP7:%.*]] = zext <8 x i8> [[_MSPROP3]] to <8 x i16>4452; CHECK-NEXT: [[VMULL_I_I:%.*]] = tail call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> [[TMP1]], <8 x i8> [[TMP3]]) #[[ATTR7]]4453; CHECK-NEXT: store <8 x i16> [[TMP7]], ptr @__msan_retval_tls, align 84454; CHECK-NEXT: ret <8 x i16> [[VMULL_I_I]]4455;4456 %temp = bitcast <16 x i8> %a to <2 x i64>4457 %shuffle.i.i = shufflevector <2 x i64> %temp, <2 x i64> undef, <1 x i32> <i32 1>4458 %temp1 = bitcast <1 x i64> %shuffle.i.i to <8 x i8>4459 %temp2 = bitcast <16 x i8> %b to <2 x i64>4460 %shuffle.i3.i = shufflevector <2 x i64> %temp2, <2 x i64> undef, <1 x i32> <i32 1>4461 %temp3 = bitcast <1 x i64> %shuffle.i3.i to <8 x i8>4462 %vmull.i.i = tail call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> %temp1, <8 x i8> %temp3) nounwind4463 ret <8 x i16> %vmull.i.i4464}4465 4466define <4 x i32> @foo4(<8 x i16> %a, <8 x i16> %b) nounwind sanitize_memory {4467; CHECK-LABEL: define <4 x i32> @foo4(4468; CHECK-SAME: <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]]) #[[ATTR0]] {4469; CHECK-NEXT: [[TMP8:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 84470; CHECK-NEXT: [[TMP9:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84471; CHECK-NEXT: call void @llvm.donothing()4472; CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x i16> [[TMP8]] to <2 x i64>4473; CHECK-NEXT: [[TMP:%.*]] = bitcast <8 x i16> [[A]] to <2 x i64>4474; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i64> [[TMP10]], <2 x i64> splat (i64 -1), <1 x i32> <i32 1>4475; CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <2 x i64> [[TMP]], <2 x i64> undef, <1 x i32> <i32 1>4476; CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>4477; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I]] to <4 x i16>4478; CHECK-NEXT: [[TMP5:%.*]] = bitcast <8 x i16> [[TMP9]] to <2 x i64>4479; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[B]] to <2 x i64>4480; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <2 x i64> [[TMP5]], <2 x i64> splat (i64 -1), <1 x i32> <i32 1>4481; CHECK-NEXT: [[SHUFFLE_I3_I:%.*]] = shufflevector <2 x i64> [[TMP2]], <2 x i64> undef, <1 x i32> <i32 1>4482; CHECK-NEXT: [[TMP6:%.*]] = bitcast <1 x i64> [[_MSPROP1]] to <4 x i16>4483; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[SHUFFLE_I3_I]] to <4 x i16>4484; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i16> [[TMP4]], [[TMP6]]4485; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i16> [[_MSPROP2]], zeroinitializer4486; CHECK-NEXT: [[TMP7:%.*]] = zext <4 x i16> [[_MSPROP3]] to <4 x i32>4487; CHECK-NEXT: [[VMULL2_I_I:%.*]] = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[TMP1]], <4 x i16> [[TMP3]]) #[[ATTR7]]4488; CHECK-NEXT: store <4 x i32> [[TMP7]], ptr @__msan_retval_tls, align 84489; CHECK-NEXT: ret <4 x i32> [[VMULL2_I_I]]4490;4491 %temp = bitcast <8 x i16> %a to <2 x i64>4492 %shuffle.i.i = shufflevector <2 x i64> %temp, <2 x i64> undef, <1 x i32> <i32 1>4493 %temp1 = bitcast <1 x i64> %shuffle.i.i to <4 x i16>4494 %temp2 = bitcast <8 x i16> %b to <2 x i64>4495 %shuffle.i3.i = shufflevector <2 x i64> %temp2, <2 x i64> undef, <1 x i32> <i32 1>4496 %temp3 = bitcast <1 x i64> %shuffle.i3.i to <4 x i16>4497 %vmull2.i.i = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %temp1, <4 x i16> %temp3) nounwind4498 ret <4 x i32> %vmull2.i.i4499}4500 4501define <2 x i64> @foo5(<4 x i32> %a, <4 x i32> %b) nounwind sanitize_memory {4502; CHECK-LABEL: define <2 x i64> @foo5(4503; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) #[[ATTR0]] {4504; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 84505; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84506; CHECK-NEXT: call void @llvm.donothing()4507; CHECK-NEXT: [[TMP10:%.*]] = bitcast <4 x i32> [[TMP8]] to <2 x i64>4508; CHECK-NEXT: [[TMP:%.*]] = bitcast <4 x i32> [[A]] to <2 x i64>4509; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i64> [[TMP10]], <2 x i64> splat (i64 -1), <1 x i32> <i32 1>4510; CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <2 x i64> [[TMP]], <2 x i64> undef, <1 x i32> <i32 1>4511; CHECK-NEXT: [[TMP4:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <2 x i32>4512; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I]] to <2 x i32>4513; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP9]] to <2 x i64>4514; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[B]] to <2 x i64>4515; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <2 x i64> [[TMP5]], <2 x i64> splat (i64 -1), <1 x i32> <i32 1>4516; CHECK-NEXT: [[SHUFFLE_I3_I:%.*]] = shufflevector <2 x i64> [[TMP2]], <2 x i64> undef, <1 x i32> <i32 1>4517; CHECK-NEXT: [[TMP6:%.*]] = bitcast <1 x i64> [[_MSPROP1]] to <2 x i32>4518; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[SHUFFLE_I3_I]] to <2 x i32>4519; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i32> [[TMP4]], [[TMP6]]4520; CHECK-NEXT: [[_MSPROP3:%.*]] = or <2 x i32> [[_MSPROP2]], zeroinitializer4521; CHECK-NEXT: [[TMP7:%.*]] = zext <2 x i32> [[_MSPROP3]] to <2 x i64>4522; CHECK-NEXT: [[VMULL2_I_I:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[TMP1]], <2 x i32> [[TMP3]]) #[[ATTR7]]4523; CHECK-NEXT: store <2 x i64> [[TMP7]], ptr @__msan_retval_tls, align 84524; CHECK-NEXT: ret <2 x i64> [[VMULL2_I_I]]4525;4526 %temp = bitcast <4 x i32> %a to <2 x i64>4527 %shuffle.i.i = shufflevector <2 x i64> %temp, <2 x i64> undef, <1 x i32> <i32 1>4528 %temp1 = bitcast <1 x i64> %shuffle.i.i to <2 x i32>4529 %temp2 = bitcast <4 x i32> %b to <2 x i64>4530 %shuffle.i3.i = shufflevector <2 x i64> %temp2, <2 x i64> undef, <1 x i32> <i32 1>4531 %temp3 = bitcast <1 x i64> %shuffle.i3.i to <2 x i32>4532 %vmull2.i.i = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %temp1, <2 x i32> %temp3) nounwind4533 ret <2 x i64> %vmull2.i.i4534}4535 4536define <4 x i32> @foo6(<4 x i32> %a, <8 x i16> %b, <4 x i16> %c) nounwind readnone optsize ssp {4537; CHECK-LABEL: define <4 x i32> @foo6(4538; CHECK-SAME: <4 x i32> [[A:%.*]], <8 x i16> [[B:%.*]], <4 x i16> [[C:%.*]]) #[[ATTR6:[0-9]+]] {4539; CHECK-NEXT: [[ENTRY:.*:]]4540; CHECK-NEXT: call void @llvm.donothing()4541; CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B]] to <2 x i64>4542; CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> undef, <1 x i32> <i32 1>4543; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I]] to <4 x i16>4544; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i16> [[C]], <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>4545; CHECK-NEXT: [[VMULL2_I:%.*]] = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[TMP1]], <4 x i16> [[SHUFFLE]]) #[[ATTR7]]4546; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 84547; CHECK-NEXT: ret <4 x i32> [[VMULL2_I]]4548;4549entry:4550 %0 = bitcast <8 x i16> %b to <2 x i64>4551 %shuffle.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> <i32 1>4552 %1 = bitcast <1 x i64> %shuffle.i to <4 x i16>4553 %shuffle = shufflevector <4 x i16> %c, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>4554 %vmull2.i = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %1, <4 x i16> %shuffle) nounwind4555 ret <4 x i32> %vmull2.i4556}4557 4558define <4 x i32> @foo6a(<4 x i32> %a, <8 x i16> %b, <4 x i16> %c) nounwind readnone optsize ssp {4559; CHECK-LABEL: define <4 x i32> @foo6a(4560; CHECK-SAME: <4 x i32> [[A:%.*]], <8 x i16> [[B:%.*]], <4 x i16> [[C:%.*]]) #[[ATTR6]] {4561; CHECK-NEXT: [[ENTRY:.*:]]4562; CHECK-NEXT: call void @llvm.donothing()4563; CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B]] to <2 x i64>4564; CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> undef, <1 x i32> zeroinitializer4565; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I]] to <4 x i16>4566; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i16> [[C]], <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>4567; CHECK-NEXT: [[VMULL2_I:%.*]] = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[TMP1]], <4 x i16> [[SHUFFLE]]) #[[ATTR7]]4568; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 84569; CHECK-NEXT: ret <4 x i32> [[VMULL2_I]]4570;4571entry:4572 %0 = bitcast <8 x i16> %b to <2 x i64>4573 %shuffle.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> <i32 0>4574 %1 = bitcast <1 x i64> %shuffle.i to <4 x i16>4575 %shuffle = shufflevector <4 x i16> %c, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>4576 %vmull2.i = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %1, <4 x i16> %shuffle) nounwind4577 ret <4 x i32> %vmull2.i4578}4579 4580define <2 x i64> @foo7(<2 x i64> %a, <4 x i32> %b, <2 x i32> %c) nounwind readnone optsize ssp {4581; CHECK-LABEL: define <2 x i64> @foo7(4582; CHECK-SAME: <2 x i64> [[A:%.*]], <4 x i32> [[B:%.*]], <2 x i32> [[C:%.*]]) #[[ATTR6]] {4583; CHECK-NEXT: [[ENTRY:.*:]]4584; CHECK-NEXT: call void @llvm.donothing()4585; CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[B]] to <2 x i64>4586; CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> undef, <1 x i32> <i32 1>4587; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I]] to <2 x i32>4588; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[C]], <2 x i32> undef, <2 x i32> <i32 1, i32 1>4589; CHECK-NEXT: [[VMULL2_I:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[TMP1]], <2 x i32> [[SHUFFLE]]) #[[ATTR7]]4590; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 84591; CHECK-NEXT: ret <2 x i64> [[VMULL2_I]]4592;4593entry:4594 %0 = bitcast <4 x i32> %b to <2 x i64>4595 %shuffle.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> <i32 1>4596 %1 = bitcast <1 x i64> %shuffle.i to <2 x i32>4597 %shuffle = shufflevector <2 x i32> %c, <2 x i32> undef, <2 x i32> <i32 1, i32 1>4598 %vmull2.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %1, <2 x i32> %shuffle) nounwind4599 ret <2 x i64> %vmull2.i4600}4601 4602define <2 x i64> @foo7a(<2 x i64> %a, <4 x i32> %b, <2 x i32> %c) nounwind readnone optsize ssp {4603; CHECK-LABEL: define <2 x i64> @foo7a(4604; CHECK-SAME: <2 x i64> [[A:%.*]], <4 x i32> [[B:%.*]], <2 x i32> [[C:%.*]]) #[[ATTR6]] {4605; CHECK-NEXT: [[ENTRY:.*:]]4606; CHECK-NEXT: call void @llvm.donothing()4607; CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[B]] to <2 x i64>4608; CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> undef, <1 x i32> zeroinitializer4609; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I]] to <2 x i32>4610; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[C]], <2 x i32> undef, <2 x i32> <i32 1, i32 1>4611; CHECK-NEXT: [[VMULL2_I:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[TMP1]], <2 x i32> [[SHUFFLE]]) #[[ATTR7]]4612; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 84613; CHECK-NEXT: ret <2 x i64> [[VMULL2_I]]4614;4615entry:4616 %0 = bitcast <4 x i32> %b to <2 x i64>4617 %shuffle.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> <i32 0>4618 %1 = bitcast <1 x i64> %shuffle.i to <2 x i32>4619 %shuffle = shufflevector <2 x i32> %c, <2 x i32> undef, <2 x i32> <i32 1, i32 1>4620 %vmull2.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %1, <2 x i32> %shuffle) nounwind4621 ret <2 x i64> %vmull2.i4622}4623 4624 4625define <4 x i32> @foo8(<4 x i32> %a, <8 x i16> %b, <4 x i16> %c) nounwind readnone optsize ssp {4626; CHECK-LABEL: define <4 x i32> @foo8(4627; CHECK-SAME: <4 x i32> [[A:%.*]], <8 x i16> [[B:%.*]], <4 x i16> [[C:%.*]]) #[[ATTR6]] {4628; CHECK-NEXT: [[ENTRY:.*:]]4629; CHECK-NEXT: call void @llvm.donothing()4630; CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B]] to <2 x i64>4631; CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> undef, <1 x i32> <i32 1>4632; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I]] to <4 x i16>4633; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i16> [[C]], <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>4634; CHECK-NEXT: [[VMULL2_I:%.*]] = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[TMP1]], <4 x i16> [[SHUFFLE]]) #[[ATTR7]]4635; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 84636; CHECK-NEXT: ret <4 x i32> [[VMULL2_I]]4637;4638entry:4639 %0 = bitcast <8 x i16> %b to <2 x i64>4640 %shuffle.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> <i32 1>4641 %1 = bitcast <1 x i64> %shuffle.i to <4 x i16>4642 %shuffle = shufflevector <4 x i16> %c, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>4643 %vmull2.i = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %1, <4 x i16> %shuffle) nounwind4644 ret <4 x i32> %vmull2.i4645}4646 4647define <4 x i32> @foo8a(<4 x i32> %a, <8 x i16> %b, <4 x i16> %c) nounwind readnone optsize ssp {4648; CHECK-LABEL: define <4 x i32> @foo8a(4649; CHECK-SAME: <4 x i32> [[A:%.*]], <8 x i16> [[B:%.*]], <4 x i16> [[C:%.*]]) #[[ATTR6]] {4650; CHECK-NEXT: [[ENTRY:.*:]]4651; CHECK-NEXT: call void @llvm.donothing()4652; CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B]] to <2 x i64>4653; CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> undef, <1 x i32> zeroinitializer4654; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I]] to <4 x i16>4655; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i16> [[C]], <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>4656; CHECK-NEXT: [[VMULL2_I:%.*]] = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[TMP1]], <4 x i16> [[SHUFFLE]]) #[[ATTR7]]4657; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 84658; CHECK-NEXT: ret <4 x i32> [[VMULL2_I]]4659;4660entry:4661 %0 = bitcast <8 x i16> %b to <2 x i64>4662 %shuffle.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> <i32 0>4663 %1 = bitcast <1 x i64> %shuffle.i to <4 x i16>4664 %shuffle = shufflevector <4 x i16> %c, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>4665 %vmull2.i = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %1, <4 x i16> %shuffle) nounwind4666 ret <4 x i32> %vmull2.i4667}4668 4669define <2 x i64> @foo9(<2 x i64> %a, <4 x i32> %b, <2 x i32> %c) nounwind readnone optsize ssp {4670; CHECK-LABEL: define <2 x i64> @foo9(4671; CHECK-SAME: <2 x i64> [[A:%.*]], <4 x i32> [[B:%.*]], <2 x i32> [[C:%.*]]) #[[ATTR6]] {4672; CHECK-NEXT: [[ENTRY:.*:]]4673; CHECK-NEXT: call void @llvm.donothing()4674; CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[B]] to <2 x i64>4675; CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> undef, <1 x i32> <i32 1>4676; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I]] to <2 x i32>4677; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[C]], <2 x i32> undef, <2 x i32> <i32 1, i32 1>4678; CHECK-NEXT: [[VMULL2_I:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[TMP1]], <2 x i32> [[SHUFFLE]]) #[[ATTR7]]4679; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 84680; CHECK-NEXT: ret <2 x i64> [[VMULL2_I]]4681;4682entry:4683 %0 = bitcast <4 x i32> %b to <2 x i64>4684 %shuffle.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> <i32 1>4685 %1 = bitcast <1 x i64> %shuffle.i to <2 x i32>4686 %shuffle = shufflevector <2 x i32> %c, <2 x i32> undef, <2 x i32> <i32 1, i32 1>4687 %vmull2.i = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %1, <2 x i32> %shuffle) nounwind4688 ret <2 x i64> %vmull2.i4689}4690 4691define <2 x i64> @foo9a(<2 x i64> %a, <4 x i32> %b, <2 x i32> %c) nounwind readnone optsize ssp {4692; CHECK-LABEL: define <2 x i64> @foo9a(4693; CHECK-SAME: <2 x i64> [[A:%.*]], <4 x i32> [[B:%.*]], <2 x i32> [[C:%.*]]) #[[ATTR6]] {4694; CHECK-NEXT: [[ENTRY:.*:]]4695; CHECK-NEXT: call void @llvm.donothing()4696; CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[B]] to <2 x i64>4697; CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> undef, <1 x i32> zeroinitializer4698; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I]] to <2 x i32>4699; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[C]], <2 x i32> undef, <2 x i32> <i32 1, i32 1>4700; CHECK-NEXT: [[VMULL2_I:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[TMP1]], <2 x i32> [[SHUFFLE]]) #[[ATTR7]]4701; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 84702; CHECK-NEXT: ret <2 x i64> [[VMULL2_I]]4703;4704entry:4705 %0 = bitcast <4 x i32> %b to <2 x i64>4706 %shuffle.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> <i32 0>4707 %1 = bitcast <1 x i64> %shuffle.i to <2 x i32>4708 %shuffle = shufflevector <2 x i32> %c, <2 x i32> undef, <2 x i32> <i32 1, i32 1>4709 %vmull2.i = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %1, <2 x i32> %shuffle) nounwind4710 ret <2 x i64> %vmull2.i4711}4712 4713define <8 x i16> @bar0(<8 x i16> %a, <16 x i8> %b, <16 x i8> %c) nounwind sanitize_memory {4714; CHECK-LABEL: define <8 x i16> @bar0(4715; CHECK-SAME: <8 x i16> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i8> [[C:%.*]]) #[[ATTR0]] {4716; CHECK-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84717; CHECK-NEXT: [[TMP10:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84718; CHECK-NEXT: [[TMP11:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 84719; CHECK-NEXT: call void @llvm.donothing()4720; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP9]] to <2 x i64>4721; CHECK-NEXT: [[TMP:%.*]] = bitcast <16 x i8> [[B]] to <2 x i64>4722; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i64> [[TMP4]], <2 x i64> splat (i64 -1), <1 x i32> <i32 1>4723; CHECK-NEXT: [[SHUFFLE_I_I_I:%.*]] = shufflevector <2 x i64> [[TMP]], <2 x i64> undef, <1 x i32> <i32 1>4724; CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>4725; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I_I]] to <8 x i8>4726; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP10]] to <2 x i64>4727; CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[C]] to <2 x i64>4728; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <2 x i64> [[TMP6]], <2 x i64> splat (i64 -1), <1 x i32> <i32 1>4729; CHECK-NEXT: [[SHUFFLE_I3_I_I:%.*]] = shufflevector <2 x i64> [[TMP2]], <2 x i64> undef, <1 x i32> <i32 1>4730; CHECK-NEXT: [[TMP7:%.*]] = bitcast <1 x i64> [[_MSPROP1]] to <8 x i8>4731; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[SHUFFLE_I3_I_I]] to <8 x i8>4732; CHECK-NEXT: [[_MSPROP2:%.*]] = or <8 x i8> [[TMP5]], [[TMP7]]4733; CHECK-NEXT: [[_MSPROP3:%.*]] = or <8 x i8> [[_MSPROP2]], zeroinitializer4734; CHECK-NEXT: [[TMP8:%.*]] = zext <8 x i8> [[_MSPROP3]] to <8 x i16>4735; CHECK-NEXT: [[VMULL_I_I_I:%.*]] = tail call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> [[TMP1]], <8 x i8> [[TMP3]]) #[[ATTR7]]4736; CHECK-NEXT: [[_MSPROP4:%.*]] = or <8 x i16> [[TMP8]], [[TMP11]]4737; CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i16> [[VMULL_I_I_I]], [[A]]4738; CHECK-NEXT: store <8 x i16> [[_MSPROP4]], ptr @__msan_retval_tls, align 84739; CHECK-NEXT: ret <8 x i16> [[ADD_I]]4740;4741 %temp = bitcast <16 x i8> %b to <2 x i64>4742 %shuffle.i.i.i = shufflevector <2 x i64> %temp, <2 x i64> undef, <1 x i32> <i32 1>4743 %temp1 = bitcast <1 x i64> %shuffle.i.i.i to <8 x i8>4744 %temp2 = bitcast <16 x i8> %c to <2 x i64>4745 %shuffle.i3.i.i = shufflevector <2 x i64> %temp2, <2 x i64> undef, <1 x i32> <i32 1>4746 %temp3 = bitcast <1 x i64> %shuffle.i3.i.i to <8 x i8>4747 %vmull.i.i.i = tail call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> %temp1, <8 x i8> %temp3) nounwind4748 %add.i = add <8 x i16> %vmull.i.i.i, %a4749 ret <8 x i16> %add.i4750}4751 4752define <4 x i32> @bar1(<4 x i32> %a, <8 x i16> %b, <8 x i16> %c) nounwind sanitize_memory {4753; CHECK-LABEL: define <4 x i32> @bar1(4754; CHECK-SAME: <4 x i32> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i16> [[C:%.*]]) #[[ATTR0]] {4755; CHECK-NEXT: [[TMP9:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84756; CHECK-NEXT: [[TMP10:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84757; CHECK-NEXT: [[TMP11:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 84758; CHECK-NEXT: call void @llvm.donothing()4759; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP9]] to <2 x i64>4760; CHECK-NEXT: [[TMP:%.*]] = bitcast <8 x i16> [[B]] to <2 x i64>4761; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i64> [[TMP4]], <2 x i64> splat (i64 -1), <1 x i32> <i32 1>4762; CHECK-NEXT: [[SHUFFLE_I_I_I:%.*]] = shufflevector <2 x i64> [[TMP]], <2 x i64> undef, <1 x i32> <i32 1>4763; CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>4764; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I_I]] to <4 x i16>4765; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[TMP10]] to <2 x i64>4766; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[C]] to <2 x i64>4767; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <2 x i64> [[TMP6]], <2 x i64> splat (i64 -1), <1 x i32> <i32 1>4768; CHECK-NEXT: [[SHUFFLE_I3_I_I:%.*]] = shufflevector <2 x i64> [[TMP2]], <2 x i64> undef, <1 x i32> <i32 1>4769; CHECK-NEXT: [[TMP7:%.*]] = bitcast <1 x i64> [[_MSPROP1]] to <4 x i16>4770; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[SHUFFLE_I3_I_I]] to <4 x i16>4771; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i16> [[TMP5]], [[TMP7]]4772; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i16> [[_MSPROP2]], zeroinitializer4773; CHECK-NEXT: [[TMP8:%.*]] = zext <4 x i16> [[_MSPROP3]] to <4 x i32>4774; CHECK-NEXT: [[VMULL2_I_I_I:%.*]] = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[TMP1]], <4 x i16> [[TMP3]]) #[[ATTR7]]4775; CHECK-NEXT: [[_MSPROP4:%.*]] = or <4 x i32> [[TMP8]], [[TMP11]]4776; CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i32> [[VMULL2_I_I_I]], [[A]]4777; CHECK-NEXT: store <4 x i32> [[_MSPROP4]], ptr @__msan_retval_tls, align 84778; CHECK-NEXT: ret <4 x i32> [[ADD_I]]4779;4780 %temp = bitcast <8 x i16> %b to <2 x i64>4781 %shuffle.i.i.i = shufflevector <2 x i64> %temp, <2 x i64> undef, <1 x i32> <i32 1>4782 %temp1 = bitcast <1 x i64> %shuffle.i.i.i to <4 x i16>4783 %temp2 = bitcast <8 x i16> %c to <2 x i64>4784 %shuffle.i3.i.i = shufflevector <2 x i64> %temp2, <2 x i64> undef, <1 x i32> <i32 1>4785 %temp3 = bitcast <1 x i64> %shuffle.i3.i.i to <4 x i16>4786 %vmull2.i.i.i = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %temp1, <4 x i16> %temp3) nounwind4787 %add.i = add <4 x i32> %vmull2.i.i.i, %a4788 ret <4 x i32> %add.i4789}4790 4791define <2 x i64> @bar2(<2 x i64> %a, <4 x i32> %b, <4 x i32> %c) nounwind sanitize_memory {4792; CHECK-LABEL: define <2 x i64> @bar2(4793; CHECK-SAME: <2 x i64> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i32> [[C:%.*]]) #[[ATTR0]] {4794; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84795; CHECK-NEXT: [[TMP10:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84796; CHECK-NEXT: [[TMP11:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 84797; CHECK-NEXT: call void @llvm.donothing()4798; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP9]] to <2 x i64>4799; CHECK-NEXT: [[TMP:%.*]] = bitcast <4 x i32> [[B]] to <2 x i64>4800; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i64> [[TMP4]], <2 x i64> splat (i64 -1), <1 x i32> <i32 1>4801; CHECK-NEXT: [[SHUFFLE_I_I_I:%.*]] = shufflevector <2 x i64> [[TMP]], <2 x i64> undef, <1 x i32> <i32 1>4802; CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <2 x i32>4803; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I_I]] to <2 x i32>4804; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP10]] to <2 x i64>4805; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[C]] to <2 x i64>4806; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <2 x i64> [[TMP6]], <2 x i64> splat (i64 -1), <1 x i32> <i32 1>4807; CHECK-NEXT: [[SHUFFLE_I3_I_I:%.*]] = shufflevector <2 x i64> [[TMP2]], <2 x i64> undef, <1 x i32> <i32 1>4808; CHECK-NEXT: [[TMP7:%.*]] = bitcast <1 x i64> [[_MSPROP1]] to <2 x i32>4809; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[SHUFFLE_I3_I_I]] to <2 x i32>4810; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i32> [[TMP5]], [[TMP7]]4811; CHECK-NEXT: [[_MSPROP3:%.*]] = or <2 x i32> [[_MSPROP2]], zeroinitializer4812; CHECK-NEXT: [[TMP8:%.*]] = zext <2 x i32> [[_MSPROP3]] to <2 x i64>4813; CHECK-NEXT: [[VMULL2_I_I_I:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[TMP1]], <2 x i32> [[TMP3]]) #[[ATTR7]]4814; CHECK-NEXT: [[_MSPROP4:%.*]] = or <2 x i64> [[TMP8]], [[TMP11]]4815; CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i64> [[VMULL2_I_I_I]], [[A]]4816; CHECK-NEXT: store <2 x i64> [[_MSPROP4]], ptr @__msan_retval_tls, align 84817; CHECK-NEXT: ret <2 x i64> [[ADD_I]]4818;4819 %temp = bitcast <4 x i32> %b to <2 x i64>4820 %shuffle.i.i.i = shufflevector <2 x i64> %temp, <2 x i64> undef, <1 x i32> <i32 1>4821 %temp1 = bitcast <1 x i64> %shuffle.i.i.i to <2 x i32>4822 %temp2 = bitcast <4 x i32> %c to <2 x i64>4823 %shuffle.i3.i.i = shufflevector <2 x i64> %temp2, <2 x i64> undef, <1 x i32> <i32 1>4824 %temp3 = bitcast <1 x i64> %shuffle.i3.i.i to <2 x i32>4825 %vmull2.i.i.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %temp1, <2 x i32> %temp3) nounwind4826 %add.i = add <2 x i64> %vmull2.i.i.i, %a4827 ret <2 x i64> %add.i4828}4829 4830define <8 x i16> @bar3(<8 x i16> %a, <16 x i8> %b, <16 x i8> %c) nounwind sanitize_memory {4831; CHECK-LABEL: define <8 x i16> @bar3(4832; CHECK-SAME: <8 x i16> [[A:%.*]], <16 x i8> [[B:%.*]], <16 x i8> [[C:%.*]]) #[[ATTR0]] {4833; CHECK-NEXT: [[TMP9:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84834; CHECK-NEXT: [[TMP10:%.*]] = load <16 x i8>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84835; CHECK-NEXT: [[TMP11:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 84836; CHECK-NEXT: call void @llvm.donothing()4837; CHECK-NEXT: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP9]] to <2 x i64>4838; CHECK-NEXT: [[TMP:%.*]] = bitcast <16 x i8> [[B]] to <2 x i64>4839; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i64> [[TMP4]], <2 x i64> splat (i64 -1), <1 x i32> <i32 1>4840; CHECK-NEXT: [[SHUFFLE_I_I_I:%.*]] = shufflevector <2 x i64> [[TMP]], <2 x i64> undef, <1 x i32> <i32 1>4841; CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <8 x i8>4842; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I_I]] to <8 x i8>4843; CHECK-NEXT: [[TMP6:%.*]] = bitcast <16 x i8> [[TMP10]] to <2 x i64>4844; CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[C]] to <2 x i64>4845; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <2 x i64> [[TMP6]], <2 x i64> splat (i64 -1), <1 x i32> <i32 1>4846; CHECK-NEXT: [[SHUFFLE_I3_I_I:%.*]] = shufflevector <2 x i64> [[TMP2]], <2 x i64> undef, <1 x i32> <i32 1>4847; CHECK-NEXT: [[TMP7:%.*]] = bitcast <1 x i64> [[_MSPROP1]] to <8 x i8>4848; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[SHUFFLE_I3_I_I]] to <8 x i8>4849; CHECK-NEXT: [[_MSPROP2:%.*]] = or <8 x i8> [[TMP5]], [[TMP7]]4850; CHECK-NEXT: [[_MSPROP3:%.*]] = or <8 x i8> [[_MSPROP2]], zeroinitializer4851; CHECK-NEXT: [[TMP8:%.*]] = zext <8 x i8> [[_MSPROP3]] to <8 x i16>4852; CHECK-NEXT: [[VMULL_I_I_I:%.*]] = tail call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> [[TMP1]], <8 x i8> [[TMP3]]) #[[ATTR7]]4853; CHECK-NEXT: [[_MSPROP4:%.*]] = or <8 x i16> [[TMP8]], [[TMP11]]4854; CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i16> [[VMULL_I_I_I]], [[A]]4855; CHECK-NEXT: store <8 x i16> [[_MSPROP4]], ptr @__msan_retval_tls, align 84856; CHECK-NEXT: ret <8 x i16> [[ADD_I]]4857;4858 %temp = bitcast <16 x i8> %b to <2 x i64>4859 %shuffle.i.i.i = shufflevector <2 x i64> %temp, <2 x i64> undef, <1 x i32> <i32 1>4860 %temp1 = bitcast <1 x i64> %shuffle.i.i.i to <8 x i8>4861 %temp2 = bitcast <16 x i8> %c to <2 x i64>4862 %shuffle.i3.i.i = shufflevector <2 x i64> %temp2, <2 x i64> undef, <1 x i32> <i32 1>4863 %temp3 = bitcast <1 x i64> %shuffle.i3.i.i to <8 x i8>4864 %vmull.i.i.i = tail call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> %temp1, <8 x i8> %temp3) nounwind4865 %add.i = add <8 x i16> %vmull.i.i.i, %a4866 ret <8 x i16> %add.i4867}4868 4869define <4 x i32> @bar4(<4 x i32> %a, <8 x i16> %b, <8 x i16> %c) nounwind sanitize_memory {4870; CHECK-LABEL: define <4 x i32> @bar4(4871; CHECK-SAME: <4 x i32> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i16> [[C:%.*]]) #[[ATTR0]] {4872; CHECK-NEXT: [[TMP9:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84873; CHECK-NEXT: [[TMP10:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84874; CHECK-NEXT: [[TMP11:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 84875; CHECK-NEXT: call void @llvm.donothing()4876; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP9]] to <2 x i64>4877; CHECK-NEXT: [[TMP:%.*]] = bitcast <8 x i16> [[B]] to <2 x i64>4878; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i64> [[TMP4]], <2 x i64> splat (i64 -1), <1 x i32> <i32 1>4879; CHECK-NEXT: [[SHUFFLE_I_I_I:%.*]] = shufflevector <2 x i64> [[TMP]], <2 x i64> undef, <1 x i32> <i32 1>4880; CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <4 x i16>4881; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I_I]] to <4 x i16>4882; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[TMP10]] to <2 x i64>4883; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[C]] to <2 x i64>4884; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <2 x i64> [[TMP6]], <2 x i64> splat (i64 -1), <1 x i32> <i32 1>4885; CHECK-NEXT: [[SHUFFLE_I3_I_I:%.*]] = shufflevector <2 x i64> [[TMP2]], <2 x i64> undef, <1 x i32> <i32 1>4886; CHECK-NEXT: [[TMP7:%.*]] = bitcast <1 x i64> [[_MSPROP1]] to <4 x i16>4887; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[SHUFFLE_I3_I_I]] to <4 x i16>4888; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i16> [[TMP5]], [[TMP7]]4889; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i16> [[_MSPROP2]], zeroinitializer4890; CHECK-NEXT: [[TMP8:%.*]] = zext <4 x i16> [[_MSPROP3]] to <4 x i32>4891; CHECK-NEXT: [[VMULL2_I_I_I:%.*]] = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[TMP1]], <4 x i16> [[TMP3]]) #[[ATTR7]]4892; CHECK-NEXT: [[_MSPROP4:%.*]] = or <4 x i32> [[TMP8]], [[TMP11]]4893; CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i32> [[VMULL2_I_I_I]], [[A]]4894; CHECK-NEXT: store <4 x i32> [[_MSPROP4]], ptr @__msan_retval_tls, align 84895; CHECK-NEXT: ret <4 x i32> [[ADD_I]]4896;4897 %temp = bitcast <8 x i16> %b to <2 x i64>4898 %shuffle.i.i.i = shufflevector <2 x i64> %temp, <2 x i64> undef, <1 x i32> <i32 1>4899 %temp1 = bitcast <1 x i64> %shuffle.i.i.i to <4 x i16>4900 %temp2 = bitcast <8 x i16> %c to <2 x i64>4901 %shuffle.i3.i.i = shufflevector <2 x i64> %temp2, <2 x i64> undef, <1 x i32> <i32 1>4902 %temp3 = bitcast <1 x i64> %shuffle.i3.i.i to <4 x i16>4903 %vmull2.i.i.i = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %temp1, <4 x i16> %temp3) nounwind4904 %add.i = add <4 x i32> %vmull2.i.i.i, %a4905 ret <4 x i32> %add.i4906}4907 4908define <2 x i64> @bar5(<2 x i64> %a, <4 x i32> %b, <4 x i32> %c) nounwind sanitize_memory {4909; CHECK-LABEL: define <2 x i64> @bar5(4910; CHECK-SAME: <2 x i64> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i32> [[C:%.*]]) #[[ATTR0]] {4911; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84912; CHECK-NEXT: [[TMP10:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84913; CHECK-NEXT: [[TMP11:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 84914; CHECK-NEXT: call void @llvm.donothing()4915; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP9]] to <2 x i64>4916; CHECK-NEXT: [[TMP:%.*]] = bitcast <4 x i32> [[B]] to <2 x i64>4917; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i64> [[TMP4]], <2 x i64> splat (i64 -1), <1 x i32> <i32 1>4918; CHECK-NEXT: [[SHUFFLE_I_I_I:%.*]] = shufflevector <2 x i64> [[TMP]], <2 x i64> undef, <1 x i32> <i32 1>4919; CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[_MSPROP]] to <2 x i32>4920; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I_I]] to <2 x i32>4921; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[TMP10]] to <2 x i64>4922; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[C]] to <2 x i64>4923; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <2 x i64> [[TMP6]], <2 x i64> splat (i64 -1), <1 x i32> <i32 1>4924; CHECK-NEXT: [[SHUFFLE_I3_I_I:%.*]] = shufflevector <2 x i64> [[TMP2]], <2 x i64> undef, <1 x i32> <i32 1>4925; CHECK-NEXT: [[TMP7:%.*]] = bitcast <1 x i64> [[_MSPROP1]] to <2 x i32>4926; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[SHUFFLE_I3_I_I]] to <2 x i32>4927; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i32> [[TMP5]], [[TMP7]]4928; CHECK-NEXT: [[_MSPROP3:%.*]] = or <2 x i32> [[_MSPROP2]], zeroinitializer4929; CHECK-NEXT: [[TMP8:%.*]] = zext <2 x i32> [[_MSPROP3]] to <2 x i64>4930; CHECK-NEXT: [[VMULL2_I_I_I:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[TMP1]], <2 x i32> [[TMP3]]) #[[ATTR7]]4931; CHECK-NEXT: [[_MSPROP4:%.*]] = or <2 x i64> [[TMP8]], [[TMP11]]4932; CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i64> [[VMULL2_I_I_I]], [[A]]4933; CHECK-NEXT: store <2 x i64> [[_MSPROP4]], ptr @__msan_retval_tls, align 84934; CHECK-NEXT: ret <2 x i64> [[ADD_I]]4935;4936 %temp = bitcast <4 x i32> %b to <2 x i64>4937 %shuffle.i.i.i = shufflevector <2 x i64> %temp, <2 x i64> undef, <1 x i32> <i32 1>4938 %temp1 = bitcast <1 x i64> %shuffle.i.i.i to <2 x i32>4939 %temp2 = bitcast <4 x i32> %c to <2 x i64>4940 %shuffle.i3.i.i = shufflevector <2 x i64> %temp2, <2 x i64> undef, <1 x i32> <i32 1>4941 %temp3 = bitcast <1 x i64> %shuffle.i3.i.i to <2 x i32>4942 %vmull2.i.i.i = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %temp1, <2 x i32> %temp3) nounwind4943 %add.i = add <2 x i64> %vmull2.i.i.i, %a4944 ret <2 x i64> %add.i4945}4946 4947define <4 x i32> @mlal2_1(<4 x i32> %a, <8 x i16> %b, <4 x i16> %c) nounwind sanitize_memory {4948; CHECK-LABEL: define <4 x i32> @mlal2_1(4949; CHECK-SAME: <4 x i32> [[A:%.*]], <8 x i16> [[B:%.*]], <4 x i16> [[C:%.*]]) #[[ATTR0]] {4950; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84951; CHECK-NEXT: [[TMP10:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84952; CHECK-NEXT: [[TMP11:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 84953; CHECK-NEXT: call void @llvm.donothing()4954; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i16> [[TMP9]], <4 x i16> splat (i16 -1), <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>4955; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i16> [[C]], <4 x i16> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>4956; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP10]] to <2 x i64>4957; CHECK-NEXT: [[TMP:%.*]] = bitcast <8 x i16> [[B]] to <2 x i64>4958; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <2 x i64> [[TMP4]], <2 x i64> splat (i64 -1), <1 x i32> <i32 1>4959; CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <2 x i64> [[TMP]], <2 x i64> undef, <1 x i32> <i32 1>4960; CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[_MSPROP1]] to <4 x i16>4961; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I]] to <4 x i16>4962; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[_MSPROP]] to <2 x i64>4963; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[SHUFFLE]] to <2 x i64>4964; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <2 x i64> [[TMP6]], <2 x i64> splat (i64 -1), <1 x i32> <i32 1>4965; CHECK-NEXT: [[SHUFFLE_I3_I:%.*]] = shufflevector <2 x i64> [[TMP2]], <2 x i64> undef, <1 x i32> <i32 1>4966; CHECK-NEXT: [[TMP7:%.*]] = bitcast <1 x i64> [[_MSPROP2]] to <4 x i16>4967; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[SHUFFLE_I3_I]] to <4 x i16>4968; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i16> [[TMP5]], [[TMP7]]4969; CHECK-NEXT: [[_MSPROP4:%.*]] = or <4 x i16> [[_MSPROP3]], zeroinitializer4970; CHECK-NEXT: [[TMP8:%.*]] = zext <4 x i16> [[_MSPROP4]] to <4 x i32>4971; CHECK-NEXT: [[VMULL2_I_I:%.*]] = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[TMP1]], <4 x i16> [[TMP3]]) #[[ATTR7]]4972; CHECK-NEXT: [[_MSPROP5:%.*]] = or <4 x i32> [[TMP8]], [[TMP11]]4973; CHECK-NEXT: [[ADD:%.*]] = add <4 x i32> [[VMULL2_I_I]], [[A]]4974; CHECK-NEXT: store <4 x i32> [[_MSPROP5]], ptr @__msan_retval_tls, align 84975; CHECK-NEXT: ret <4 x i32> [[ADD]]4976;4977 %shuffle = shufflevector <4 x i16> %c, <4 x i16> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>4978 %temp = bitcast <8 x i16> %b to <2 x i64>4979 %shuffle.i.i = shufflevector <2 x i64> %temp, <2 x i64> undef, <1 x i32> <i32 1>4980 %temp1 = bitcast <1 x i64> %shuffle.i.i to <4 x i16>4981 %temp2 = bitcast <8 x i16> %shuffle to <2 x i64>4982 %shuffle.i3.i = shufflevector <2 x i64> %temp2, <2 x i64> undef, <1 x i32> <i32 1>4983 %temp3 = bitcast <1 x i64> %shuffle.i3.i to <4 x i16>4984 %vmull2.i.i = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %temp1, <4 x i16> %temp3) nounwind4985 %add = add <4 x i32> %vmull2.i.i, %a4986 ret <4 x i32> %add4987}4988 4989define <2 x i64> @mlal2_2(<2 x i64> %a, <4 x i32> %b, <2 x i32> %c) nounwind sanitize_memory {4990; CHECK-LABEL: define <2 x i64> @mlal2_2(4991; CHECK-SAME: <2 x i64> [[A:%.*]], <4 x i32> [[B:%.*]], <2 x i32> [[C:%.*]]) #[[ATTR0]] {4992; CHECK-NEXT: [[TMP9:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 84993; CHECK-NEXT: [[TMP10:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 84994; CHECK-NEXT: [[TMP11:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 84995; CHECK-NEXT: call void @llvm.donothing()4996; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i32> [[TMP9]], <2 x i32> splat (i32 -1), <4 x i32> <i32 1, i32 1, i32 1, i32 1>4997; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[C]], <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>4998; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP10]] to <2 x i64>4999; CHECK-NEXT: [[TMP:%.*]] = bitcast <4 x i32> [[B]] to <2 x i64>5000; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <2 x i64> [[TMP4]], <2 x i64> splat (i64 -1), <1 x i32> <i32 1>5001; CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <2 x i64> [[TMP]], <2 x i64> undef, <1 x i32> <i32 1>5002; CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[_MSPROP1]] to <2 x i32>5003; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I]] to <2 x i32>5004; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[_MSPROP]] to <2 x i64>5005; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[SHUFFLE]] to <2 x i64>5006; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <2 x i64> [[TMP6]], <2 x i64> splat (i64 -1), <1 x i32> <i32 1>5007; CHECK-NEXT: [[SHUFFLE_I3_I:%.*]] = shufflevector <2 x i64> [[TMP2]], <2 x i64> undef, <1 x i32> <i32 1>5008; CHECK-NEXT: [[TMP7:%.*]] = bitcast <1 x i64> [[_MSPROP2]] to <2 x i32>5009; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[SHUFFLE_I3_I]] to <2 x i32>5010; CHECK-NEXT: [[_MSPROP3:%.*]] = or <2 x i32> [[TMP5]], [[TMP7]]5011; CHECK-NEXT: [[_MSPROP4:%.*]] = or <2 x i32> [[_MSPROP3]], zeroinitializer5012; CHECK-NEXT: [[TMP8:%.*]] = zext <2 x i32> [[_MSPROP4]] to <2 x i64>5013; CHECK-NEXT: [[VMULL2_I_I:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[TMP1]], <2 x i32> [[TMP3]]) #[[ATTR7]]5014; CHECK-NEXT: [[_MSPROP5:%.*]] = or <2 x i64> [[TMP8]], [[TMP11]]5015; CHECK-NEXT: [[ADD:%.*]] = add <2 x i64> [[VMULL2_I_I]], [[A]]5016; CHECK-NEXT: store <2 x i64> [[_MSPROP5]], ptr @__msan_retval_tls, align 85017; CHECK-NEXT: ret <2 x i64> [[ADD]]5018;5019 %shuffle = shufflevector <2 x i32> %c, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>5020 %temp = bitcast <4 x i32> %b to <2 x i64>5021 %shuffle.i.i = shufflevector <2 x i64> %temp, <2 x i64> undef, <1 x i32> <i32 1>5022 %temp1 = bitcast <1 x i64> %shuffle.i.i to <2 x i32>5023 %temp2 = bitcast <4 x i32> %shuffle to <2 x i64>5024 %shuffle.i3.i = shufflevector <2 x i64> %temp2, <2 x i64> undef, <1 x i32> <i32 1>5025 %temp3 = bitcast <1 x i64> %shuffle.i3.i to <2 x i32>5026 %vmull2.i.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %temp1, <2 x i32> %temp3) nounwind5027 %add = add <2 x i64> %vmull2.i.i, %a5028 ret <2 x i64> %add5029}5030 5031define <4 x i32> @mlal2_4(<4 x i32> %a, <8 x i16> %b, <4 x i16> %c) nounwind sanitize_memory {5032; CHECK-LABEL: define <4 x i32> @mlal2_4(5033; CHECK-SAME: <4 x i32> [[A:%.*]], <8 x i16> [[B:%.*]], <4 x i16> [[C:%.*]]) #[[ATTR0]] {5034; CHECK-NEXT: [[TMP9:%.*]] = load <4 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 85035; CHECK-NEXT: [[TMP10:%.*]] = load <8 x i16>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 85036; CHECK-NEXT: [[TMP11:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 85037; CHECK-NEXT: call void @llvm.donothing()5038; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i16> [[TMP9]], <4 x i16> splat (i16 -1), <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>5039; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i16> [[C]], <4 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>5040; CHECK-NEXT: [[TMP4:%.*]] = bitcast <8 x i16> [[TMP10]] to <2 x i64>5041; CHECK-NEXT: [[TMP:%.*]] = bitcast <8 x i16> [[B]] to <2 x i64>5042; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <2 x i64> [[TMP4]], <2 x i64> splat (i64 -1), <1 x i32> <i32 1>5043; CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <2 x i64> [[TMP]], <2 x i64> undef, <1 x i32> <i32 1>5044; CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[_MSPROP1]] to <4 x i16>5045; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I]] to <4 x i16>5046; CHECK-NEXT: [[TMP6:%.*]] = bitcast <8 x i16> [[_MSPROP]] to <2 x i64>5047; CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i16> [[SHUFFLE]] to <2 x i64>5048; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <2 x i64> [[TMP6]], <2 x i64> splat (i64 -1), <1 x i32> <i32 1>5049; CHECK-NEXT: [[SHUFFLE_I3_I:%.*]] = shufflevector <2 x i64> [[TMP2]], <2 x i64> undef, <1 x i32> <i32 1>5050; CHECK-NEXT: [[TMP7:%.*]] = bitcast <1 x i64> [[_MSPROP2]] to <4 x i16>5051; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[SHUFFLE_I3_I]] to <4 x i16>5052; CHECK-NEXT: [[_MSPROP3:%.*]] = or <4 x i16> [[TMP5]], [[TMP7]]5053; CHECK-NEXT: [[_MSPROP4:%.*]] = or <4 x i16> [[_MSPROP3]], zeroinitializer5054; CHECK-NEXT: [[TMP8:%.*]] = zext <4 x i16> [[_MSPROP4]] to <4 x i32>5055; CHECK-NEXT: [[VMULL2_I_I:%.*]] = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[TMP1]], <4 x i16> [[TMP3]]) #[[ATTR7]]5056; CHECK-NEXT: [[_MSPROP5:%.*]] = or <4 x i32> [[TMP8]], [[TMP11]]5057; CHECK-NEXT: [[ADD:%.*]] = add <4 x i32> [[VMULL2_I_I]], [[A]]5058; CHECK-NEXT: store <4 x i32> [[_MSPROP5]], ptr @__msan_retval_tls, align 85059; CHECK-NEXT: ret <4 x i32> [[ADD]]5060;5061 %shuffle = shufflevector <4 x i16> %c, <4 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>5062 %temp = bitcast <8 x i16> %b to <2 x i64>5063 %shuffle.i.i = shufflevector <2 x i64> %temp, <2 x i64> undef, <1 x i32> <i32 1>5064 %temp1 = bitcast <1 x i64> %shuffle.i.i to <4 x i16>5065 %temp2 = bitcast <8 x i16> %shuffle to <2 x i64>5066 %shuffle.i3.i = shufflevector <2 x i64> %temp2, <2 x i64> undef, <1 x i32> <i32 1>5067 %temp3 = bitcast <1 x i64> %shuffle.i3.i to <4 x i16>5068 %vmull2.i.i = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %temp1, <4 x i16> %temp3) nounwind5069 %add = add <4 x i32> %vmull2.i.i, %a5070 ret <4 x i32> %add5071}5072 5073define <2 x i64> @mlal2_5(<2 x i64> %a, <4 x i32> %b, <2 x i32> %c) nounwind sanitize_memory {5074; CHECK-LABEL: define <2 x i64> @mlal2_5(5075; CHECK-SAME: <2 x i64> [[A:%.*]], <4 x i32> [[B:%.*]], <2 x i32> [[C:%.*]]) #[[ATTR0]] {5076; CHECK-NEXT: [[TMP9:%.*]] = load <2 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 85077; CHECK-NEXT: [[TMP10:%.*]] = load <4 x i32>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 85078; CHECK-NEXT: [[TMP11:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 85079; CHECK-NEXT: call void @llvm.donothing()5080; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i32> [[TMP9]], <2 x i32> splat (i32 -1), <4 x i32> zeroinitializer5081; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[C]], <2 x i32> undef, <4 x i32> zeroinitializer5082; CHECK-NEXT: [[TMP4:%.*]] = bitcast <4 x i32> [[TMP10]] to <2 x i64>5083; CHECK-NEXT: [[TMP:%.*]] = bitcast <4 x i32> [[B]] to <2 x i64>5084; CHECK-NEXT: [[_MSPROP1:%.*]] = shufflevector <2 x i64> [[TMP4]], <2 x i64> splat (i64 -1), <1 x i32> <i32 1>5085; CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <2 x i64> [[TMP]], <2 x i64> undef, <1 x i32> <i32 1>5086; CHECK-NEXT: [[TMP5:%.*]] = bitcast <1 x i64> [[_MSPROP1]] to <2 x i32>5087; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I]] to <2 x i32>5088; CHECK-NEXT: [[TMP6:%.*]] = bitcast <4 x i32> [[_MSPROP]] to <2 x i64>5089; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[SHUFFLE]] to <2 x i64>5090; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <2 x i64> [[TMP6]], <2 x i64> splat (i64 -1), <1 x i32> <i32 1>5091; CHECK-NEXT: [[SHUFFLE_I3_I:%.*]] = shufflevector <2 x i64> [[TMP2]], <2 x i64> undef, <1 x i32> <i32 1>5092; CHECK-NEXT: [[TMP7:%.*]] = bitcast <1 x i64> [[_MSPROP2]] to <2 x i32>5093; CHECK-NEXT: [[TMP3:%.*]] = bitcast <1 x i64> [[SHUFFLE_I3_I]] to <2 x i32>5094; CHECK-NEXT: [[_MSPROP3:%.*]] = or <2 x i32> [[TMP5]], [[TMP7]]5095; CHECK-NEXT: [[_MSPROP4:%.*]] = or <2 x i32> [[_MSPROP3]], zeroinitializer5096; CHECK-NEXT: [[TMP8:%.*]] = zext <2 x i32> [[_MSPROP4]] to <2 x i64>5097; CHECK-NEXT: [[VMULL2_I_I:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[TMP1]], <2 x i32> [[TMP3]]) #[[ATTR7]]5098; CHECK-NEXT: [[_MSPROP5:%.*]] = or <2 x i64> [[TMP8]], [[TMP11]]5099; CHECK-NEXT: [[ADD:%.*]] = add <2 x i64> [[VMULL2_I_I]], [[A]]5100; CHECK-NEXT: store <2 x i64> [[_MSPROP5]], ptr @__msan_retval_tls, align 85101; CHECK-NEXT: ret <2 x i64> [[ADD]]5102;5103 %shuffle = shufflevector <2 x i32> %c, <2 x i32> undef, <4 x i32> zeroinitializer5104 %temp = bitcast <4 x i32> %b to <2 x i64>5105 %shuffle.i.i = shufflevector <2 x i64> %temp, <2 x i64> undef, <1 x i32> <i32 1>5106 %temp1 = bitcast <1 x i64> %shuffle.i.i to <2 x i32>5107 %temp2 = bitcast <4 x i32> %shuffle to <2 x i64>5108 %shuffle.i3.i = shufflevector <2 x i64> %temp2, <2 x i64> undef, <1 x i32> <i32 1>5109 %temp3 = bitcast <1 x i64> %shuffle.i3.i to <2 x i32>5110 %vmull2.i.i = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %temp1, <2 x i32> %temp3) nounwind5111 %add = add <2 x i64> %vmull2.i.i, %a5112 ret <2 x i64> %add5113}5114 5115; rdar://123285025116define <2 x double> @vmulq_n_f64(<2 x double> %x, double %y) nounwind readnone ssp {5117; CHECK-LABEL: define <2 x double> @vmulq_n_f64(5118; CHECK-SAME: <2 x double> [[X:%.*]], double [[Y:%.*]]) #[[ATTR3]] {5119; CHECK-NEXT: [[ENTRY:.*:]]5120; CHECK-NEXT: call void @llvm.donothing()5121; CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double [[Y]], i32 05122; CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double [[Y]], i32 15123; CHECK-NEXT: [[MUL_I:%.*]] = fmul <2 x double> [[VECINIT1_I]], [[X]]5124; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 85125; CHECK-NEXT: ret <2 x double> [[MUL_I]]5126;5127entry:5128 %vecinit.i = insertelement <2 x double> undef, double %y, i32 05129 %vecinit1.i = insertelement <2 x double> %vecinit.i, double %y, i32 15130 %mul.i = fmul <2 x double> %vecinit1.i, %x5131 ret <2 x double> %mul.i5132}5133 5134define <4 x float> @vmulq_n_f32(<4 x float> %x, float %y) nounwind readnone ssp {5135; CHECK-LABEL: define <4 x float> @vmulq_n_f32(5136; CHECK-SAME: <4 x float> [[X:%.*]], float [[Y:%.*]]) #[[ATTR3]] {5137; CHECK-NEXT: [[ENTRY:.*:]]5138; CHECK-NEXT: call void @llvm.donothing()5139; CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float [[Y]], i32 05140; CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float [[Y]], i32 15141; CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float [[Y]], i32 25142; CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x float> [[VECINIT2_I]], float [[Y]], i32 35143; CHECK-NEXT: [[MUL_I:%.*]] = fmul <4 x float> [[VECINIT3_I]], [[X]]5144; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 85145; CHECK-NEXT: ret <4 x float> [[MUL_I]]5146;5147entry:5148 %vecinit.i = insertelement <4 x float> undef, float %y, i32 05149 %vecinit1.i = insertelement <4 x float> %vecinit.i, float %y, i32 15150 %vecinit2.i = insertelement <4 x float> %vecinit1.i, float %y, i32 25151 %vecinit3.i = insertelement <4 x float> %vecinit2.i, float %y, i32 35152 %mul.i = fmul <4 x float> %vecinit3.i, %x5153 ret <4 x float> %mul.i5154}5155 5156define <2 x float> @vmul_n_f32(<2 x float> %x, float %y) nounwind readnone ssp {5157; CHECK-LABEL: define <2 x float> @vmul_n_f32(5158; CHECK-SAME: <2 x float> [[X:%.*]], float [[Y:%.*]]) #[[ATTR3]] {5159; CHECK-NEXT: [[ENTRY:.*:]]5160; CHECK-NEXT: call void @llvm.donothing()5161; CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x float> undef, float [[Y]], i32 05162; CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x float> [[VECINIT_I]], float [[Y]], i32 15163; CHECK-NEXT: [[MUL_I:%.*]] = fmul <2 x float> [[VECINIT1_I]], [[X]]5164; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr @__msan_retval_tls, align 85165; CHECK-NEXT: ret <2 x float> [[MUL_I]]5166;5167entry:5168 %vecinit.i = insertelement <2 x float> undef, float %y, i32 05169 %vecinit1.i = insertelement <2 x float> %vecinit.i, float %y, i32 15170 %mul.i = fmul <2 x float> %vecinit1.i, %x5171 ret <2 x float> %mul.i5172}5173 5174define <4 x i16> @vmla_laneq_s16_test(<4 x i16> %a, <4 x i16> %b, <8 x i16> %c) nounwind readnone ssp {5175; CHECK-LABEL: define <4 x i16> @vmla_laneq_s16_test(5176; CHECK-SAME: <4 x i16> [[A:%.*]], <4 x i16> [[B:%.*]], <8 x i16> [[C:%.*]]) #[[ATTR3]] {5177; CHECK-NEXT: [[ENTRY:.*:]]5178; CHECK-NEXT: call void @llvm.donothing()5179; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <8 x i16> [[C]], <8 x i16> undef, <4 x i32> <i32 6, i32 6, i32 6, i32 6>5180; CHECK-NEXT: [[MUL:%.*]] = mul <4 x i16> [[SHUFFLE]], [[B]]5181; CHECK-NEXT: [[ADD:%.*]] = add <4 x i16> [[MUL]], [[A]]5182; CHECK-NEXT: store <4 x i16> zeroinitializer, ptr @__msan_retval_tls, align 85183; CHECK-NEXT: ret <4 x i16> [[ADD]]5184;5185entry:5186 %shuffle = shufflevector <8 x i16> %c, <8 x i16> undef, <4 x i32> <i32 6, i32 6, i32 6, i32 6>5187 %mul = mul <4 x i16> %shuffle, %b5188 %add = add <4 x i16> %mul, %a5189 ret <4 x i16> %add5190}5191 5192define <2 x i32> @vmla_laneq_s32_test(<2 x i32> %a, <2 x i32> %b, <4 x i32> %c) nounwind readnone ssp {5193; CHECK-LABEL: define <2 x i32> @vmla_laneq_s32_test(5194; CHECK-SAME: <2 x i32> [[A:%.*]], <2 x i32> [[B:%.*]], <4 x i32> [[C:%.*]]) #[[ATTR3]] {5195; CHECK-NEXT: [[ENTRY:.*:]]5196; CHECK-NEXT: call void @llvm.donothing()5197; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[C]], <4 x i32> undef, <2 x i32> <i32 3, i32 3>5198; CHECK-NEXT: [[MUL:%.*]] = mul <2 x i32> [[SHUFFLE]], [[B]]5199; CHECK-NEXT: [[ADD:%.*]] = add <2 x i32> [[MUL]], [[A]]5200; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr @__msan_retval_tls, align 85201; CHECK-NEXT: ret <2 x i32> [[ADD]]5202;5203entry:5204 %shuffle = shufflevector <4 x i32> %c, <4 x i32> undef, <2 x i32> <i32 3, i32 3>5205 %mul = mul <2 x i32> %shuffle, %b5206 %add = add <2 x i32> %mul, %a5207 ret <2 x i32> %add5208}5209 5210define <8 x i16> @not_really_vmlaq_laneq_s16_test(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) nounwind readnone ssp {5211; CHECK-LABEL: define <8 x i16> @not_really_vmlaq_laneq_s16_test(5212; CHECK-SAME: <8 x i16> [[A:%.*]], <8 x i16> [[B:%.*]], <8 x i16> [[C:%.*]]) #[[ATTR3]] {5213; CHECK-NEXT: [[ENTRY:.*:]]5214; CHECK-NEXT: call void @llvm.donothing()5215; CHECK-NEXT: [[SHUFFLE1:%.*]] = shufflevector <8 x i16> [[C]], <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>5216; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <4 x i16> [[SHUFFLE1]], <4 x i16> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>5217; CHECK-NEXT: [[MUL:%.*]] = mul <8 x i16> [[SHUFFLE2]], [[B]]5218; CHECK-NEXT: [[ADD:%.*]] = add <8 x i16> [[MUL]], [[A]]5219; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 85220; CHECK-NEXT: ret <8 x i16> [[ADD]]5221;5222entry:5223 %shuffle1 = shufflevector <8 x i16> %c, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>5224 %shuffle2 = shufflevector <4 x i16> %shuffle1, <4 x i16> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>5225 %mul = mul <8 x i16> %shuffle2, %b5226 %add = add <8 x i16> %mul, %a5227 ret <8 x i16> %add5228}5229 5230define <4 x i32> @not_really_vmlaq_laneq_s32_test(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) nounwind readnone ssp {5231; CHECK-LABEL: define <4 x i32> @not_really_vmlaq_laneq_s32_test(5232; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]], <4 x i32> [[C:%.*]]) #[[ATTR3]] {5233; CHECK-NEXT: [[ENTRY:.*:]]5234; CHECK-NEXT: call void @llvm.donothing()5235; CHECK-NEXT: [[SHUFFLE1:%.*]] = shufflevector <4 x i32> [[C]], <4 x i32> undef, <2 x i32> <i32 2, i32 3>5236; CHECK-NEXT: [[SHUFFLE2:%.*]] = shufflevector <2 x i32> [[SHUFFLE1]], <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>5237; CHECK-NEXT: [[MUL:%.*]] = mul <4 x i32> [[SHUFFLE2]], [[B]]5238; CHECK-NEXT: [[ADD:%.*]] = add <4 x i32> [[MUL]], [[A]]5239; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 85240; CHECK-NEXT: ret <4 x i32> [[ADD]]5241;5242entry:5243 %shuffle1 = shufflevector <4 x i32> %c, <4 x i32> undef, <2 x i32> <i32 2, i32 3>5244 %shuffle2 = shufflevector <2 x i32> %shuffle1, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>5245 %mul = mul <4 x i32> %shuffle2, %b5246 %add = add <4 x i32> %mul, %a5247 ret <4 x i32> %add5248}5249 5250define <4 x i32> @vmull_laneq_s16_test(<4 x i16> %a, <8 x i16> %b) nounwind readnone ssp {5251; CHECK-LABEL: define <4 x i32> @vmull_laneq_s16_test(5252; CHECK-SAME: <4 x i16> [[A:%.*]], <8 x i16> [[B:%.*]]) #[[ATTR3]] {5253; CHECK-NEXT: [[ENTRY:.*:]]5254; CHECK-NEXT: call void @llvm.donothing()5255; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> undef, <4 x i32> <i32 6, i32 6, i32 6, i32 6>5256; CHECK-NEXT: [[VMULL2_I:%.*]] = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[A]], <4 x i16> [[SHUFFLE]])5257; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 85258; CHECK-NEXT: ret <4 x i32> [[VMULL2_I]]5259;5260entry:5261 %shuffle = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 6, i32 6, i32 6, i32 6>5262 %vmull2.i = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %a, <4 x i16> %shuffle) #25263 ret <4 x i32> %vmull2.i5264}5265 5266define <2 x i64> @vmull_laneq_s32_test(<2 x i32> %a, <4 x i32> %b) nounwind readnone ssp {5267; CHECK-LABEL: define <2 x i64> @vmull_laneq_s32_test(5268; CHECK-SAME: <2 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) #[[ATTR3]] {5269; CHECK-NEXT: [[ENTRY:.*:]]5270; CHECK-NEXT: call void @llvm.donothing()5271; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> undef, <2 x i32> <i32 2, i32 2>5272; CHECK-NEXT: [[VMULL2_I:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[A]], <2 x i32> [[SHUFFLE]])5273; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 85274; CHECK-NEXT: ret <2 x i64> [[VMULL2_I]]5275;5276entry:5277 %shuffle = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 2>5278 %vmull2.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %a, <2 x i32> %shuffle) #25279 ret <2 x i64> %vmull2.i5280}5281define <4 x i32> @vmull_laneq_u16_test(<4 x i16> %a, <8 x i16> %b) nounwind readnone ssp {5282; CHECK-LABEL: define <4 x i32> @vmull_laneq_u16_test(5283; CHECK-SAME: <4 x i16> [[A:%.*]], <8 x i16> [[B:%.*]]) #[[ATTR3]] {5284; CHECK-NEXT: [[ENTRY:.*:]]5285; CHECK-NEXT: call void @llvm.donothing()5286; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> undef, <4 x i32> <i32 6, i32 6, i32 6, i32 6>5287; CHECK-NEXT: [[VMULL2_I:%.*]] = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[A]], <4 x i16> [[SHUFFLE]])5288; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 85289; CHECK-NEXT: ret <4 x i32> [[VMULL2_I]]5290;5291entry:5292 %shuffle = shufflevector <8 x i16> %b, <8 x i16> undef, <4 x i32> <i32 6, i32 6, i32 6, i32 6>5293 %vmull2.i = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %a, <4 x i16> %shuffle) #25294 ret <4 x i32> %vmull2.i5295}5296 5297define <2 x i64> @vmull_laneq_u32_test(<2 x i32> %a, <4 x i32> %b) nounwind readnone ssp {5298; CHECK-LABEL: define <2 x i64> @vmull_laneq_u32_test(5299; CHECK-SAME: <2 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) #[[ATTR3]] {5300; CHECK-NEXT: [[ENTRY:.*:]]5301; CHECK-NEXT: call void @llvm.donothing()5302; CHECK-NEXT: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> undef, <2 x i32> <i32 2, i32 2>5303; CHECK-NEXT: [[VMULL2_I:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[A]], <2 x i32> [[SHUFFLE]])5304; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 85305; CHECK-NEXT: ret <2 x i64> [[VMULL2_I]]5306;5307entry:5308 %shuffle = shufflevector <4 x i32> %b, <4 x i32> undef, <2 x i32> <i32 2, i32 2>5309 %vmull2.i = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %a, <2 x i32> %shuffle) #25310 ret <2 x i64> %vmull2.i5311}5312 5313define <4 x i32> @vmull_low_n_s16_test(<4 x i32> %a, <8 x i16> %b, <4 x i16> %c, i32 %d) nounwind readnone optsize ssp {5314; CHECK-LABEL: define <4 x i32> @vmull_low_n_s16_test(5315; CHECK-SAME: <4 x i32> [[A:%.*]], <8 x i16> [[B:%.*]], <4 x i16> [[C:%.*]], i32 [[D:%.*]]) #[[ATTR6]] {5316; CHECK-NEXT: [[ENTRY:.*:]]5317; CHECK-NEXT: call void @llvm.donothing()5318; CHECK-NEXT: [[CONV:%.*]] = trunc i32 [[D]] to i165319; CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B]] to <2 x i64>5320; CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> undef, <1 x i32> zeroinitializer5321; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I]] to <4 x i16>5322; CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> undef, i16 [[CONV]], i32 05323; CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[CONV]], i32 15324; CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[CONV]], i32 25325; CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[CONV]], i32 35326; CHECK-NEXT: [[VMULL2_I_I:%.*]] = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[TMP1]], <4 x i16> [[VECINIT3_I]]) #[[ATTR7]]5327; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 85328; CHECK-NEXT: ret <4 x i32> [[VMULL2_I_I]]5329;5330entry:5331 %conv = trunc i32 %d to i165332 %0 = bitcast <8 x i16> %b to <2 x i64>5333 %shuffle.i.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> <i32 0>5334 %1 = bitcast <1 x i64> %shuffle.i.i to <4 x i16>5335 %vecinit.i = insertelement <4 x i16> undef, i16 %conv, i32 05336 %vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %conv, i32 15337 %vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %conv, i32 25338 %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %conv, i32 35339 %vmull2.i.i = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %1, <4 x i16> %vecinit3.i) nounwind5340 ret <4 x i32> %vmull2.i.i5341}5342 5343define <4 x i32> @vmull_high_n_s16_test(<4 x i32> %a, <8 x i16> %b, <4 x i16> %c, i32 %d) nounwind readnone optsize ssp {5344; CHECK-LABEL: define <4 x i32> @vmull_high_n_s16_test(5345; CHECK-SAME: <4 x i32> [[A:%.*]], <8 x i16> [[B:%.*]], <4 x i16> [[C:%.*]], i32 [[D:%.*]]) #[[ATTR6]] {5346; CHECK-NEXT: [[ENTRY:.*:]]5347; CHECK-NEXT: call void @llvm.donothing()5348; CHECK-NEXT: [[CONV:%.*]] = trunc i32 [[D]] to i165349; CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B]] to <2 x i64>5350; CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> undef, <1 x i32> <i32 1>5351; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I]] to <4 x i16>5352; CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> undef, i16 [[CONV]], i32 05353; CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[CONV]], i32 15354; CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[CONV]], i32 25355; CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[CONV]], i32 35356; CHECK-NEXT: [[VMULL2_I_I:%.*]] = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[TMP1]], <4 x i16> [[VECINIT3_I]]) #[[ATTR7]]5357; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 85358; CHECK-NEXT: ret <4 x i32> [[VMULL2_I_I]]5359;5360entry:5361 %conv = trunc i32 %d to i165362 %0 = bitcast <8 x i16> %b to <2 x i64>5363 %shuffle.i.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> <i32 1>5364 %1 = bitcast <1 x i64> %shuffle.i.i to <4 x i16>5365 %vecinit.i = insertelement <4 x i16> undef, i16 %conv, i32 05366 %vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %conv, i32 15367 %vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %conv, i32 25368 %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %conv, i32 35369 %vmull2.i.i = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %1, <4 x i16> %vecinit3.i) nounwind5370 ret <4 x i32> %vmull2.i.i5371}5372 5373define <2 x i64> @vmull_high_n_s32_test(<2 x i64> %a, <4 x i32> %b, <2 x i32> %c, i32 %d) nounwind readnone optsize ssp {5374; CHECK-LABEL: define <2 x i64> @vmull_high_n_s32_test(5375; CHECK-SAME: <2 x i64> [[A:%.*]], <4 x i32> [[B:%.*]], <2 x i32> [[C:%.*]], i32 [[D:%.*]]) #[[ATTR6]] {5376; CHECK-NEXT: [[ENTRY:.*:]]5377; CHECK-NEXT: call void @llvm.donothing()5378; CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[B]] to <2 x i64>5379; CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> undef, <1 x i32> <i32 1>5380; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I]] to <2 x i32>5381; CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> undef, i32 [[D]], i32 05382; CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 [[D]], i32 15383; CHECK-NEXT: [[VMULL2_I_I:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[TMP1]], <2 x i32> [[VECINIT1_I]]) #[[ATTR7]]5384; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 85385; CHECK-NEXT: ret <2 x i64> [[VMULL2_I_I]]5386;5387entry:5388 %0 = bitcast <4 x i32> %b to <2 x i64>5389 %shuffle.i.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> <i32 1>5390 %1 = bitcast <1 x i64> %shuffle.i.i to <2 x i32>5391 %vecinit.i = insertelement <2 x i32> undef, i32 %d, i32 05392 %vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %d, i32 15393 %vmull2.i.i = tail call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> %1, <2 x i32> %vecinit1.i) nounwind5394 ret <2 x i64> %vmull2.i.i5395}5396 5397define <4 x i32> @vmull_high_n_u16_test(<4 x i32> %a, <8 x i16> %b, <4 x i16> %c, i32 %d) nounwind readnone optsize ssp {5398; CHECK-LABEL: define <4 x i32> @vmull_high_n_u16_test(5399; CHECK-SAME: <4 x i32> [[A:%.*]], <8 x i16> [[B:%.*]], <4 x i16> [[C:%.*]], i32 [[D:%.*]]) #[[ATTR6]] {5400; CHECK-NEXT: [[ENTRY:.*:]]5401; CHECK-NEXT: call void @llvm.donothing()5402; CHECK-NEXT: [[CONV:%.*]] = trunc i32 [[D]] to i165403; CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[B]] to <2 x i64>5404; CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> undef, <1 x i32> <i32 1>5405; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I]] to <4 x i16>5406; CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> undef, i16 [[CONV]], i32 05407; CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[CONV]], i32 15408; CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[CONV]], i32 25409; CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[CONV]], i32 35410; CHECK-NEXT: [[VMULL2_I_I:%.*]] = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[TMP1]], <4 x i16> [[VECINIT3_I]]) #[[ATTR7]]5411; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 85412; CHECK-NEXT: ret <4 x i32> [[VMULL2_I_I]]5413;5414entry:5415 %conv = trunc i32 %d to i165416 %0 = bitcast <8 x i16> %b to <2 x i64>5417 %shuffle.i.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> <i32 1>5418 %1 = bitcast <1 x i64> %shuffle.i.i to <4 x i16>5419 %vecinit.i = insertelement <4 x i16> undef, i16 %conv, i32 05420 %vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %conv, i32 15421 %vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %conv, i32 25422 %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %conv, i32 35423 %vmull2.i.i = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %1, <4 x i16> %vecinit3.i) nounwind5424 ret <4 x i32> %vmull2.i.i5425}5426 5427define <2 x i64> @vmull_high_n_u32_test(<2 x i64> %a, <4 x i32> %b, <2 x i32> %c, i32 %d) nounwind readnone optsize ssp {5428; CHECK-LABEL: define <2 x i64> @vmull_high_n_u32_test(5429; CHECK-SAME: <2 x i64> [[A:%.*]], <4 x i32> [[B:%.*]], <2 x i32> [[C:%.*]], i32 [[D:%.*]]) #[[ATTR6]] {5430; CHECK-NEXT: [[ENTRY:.*:]]5431; CHECK-NEXT: call void @llvm.donothing()5432; CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[B]] to <2 x i64>5433; CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> undef, <1 x i32> <i32 1>5434; CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[SHUFFLE_I_I]] to <2 x i32>5435; CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <2 x i32> undef, i32 [[D]], i32 05436; CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <2 x i32> [[VECINIT_I]], i32 [[D]], i32 15437; CHECK-NEXT: [[VMULL2_I_I:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[TMP1]], <2 x i32> [[VECINIT1_I]]) #[[ATTR7]]5438; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 85439; CHECK-NEXT: ret <2 x i64> [[VMULL2_I_I]]5440;5441entry:5442 %0 = bitcast <4 x i32> %b to <2 x i64>5443 %shuffle.i.i = shufflevector <2 x i64> %0, <2 x i64> undef, <1 x i32> <i32 1>5444 %1 = bitcast <1 x i64> %shuffle.i.i to <2 x i32>5445 %vecinit.i = insertelement <2 x i32> undef, i32 %d, i32 05446 %vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %d, i32 15447 %vmull2.i.i = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %1, <2 x i32> %vecinit1.i) nounwind5448 ret <2 x i64> %vmull2.i.i5449}5450 5451define <4 x i32> @vmul_built_dup_test(<4 x i32> %a, <4 x i32> %b) {5452; CHECK-LABEL: define <4 x i32> @vmul_built_dup_test(5453; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) {5454; CHECK-NEXT: call void @llvm.donothing()5455; CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <4 x i32> [[B]], i32 15456; CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i32> undef, i32 [[VGET_LANE]], i32 05457; CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i32> [[VECINIT_I]], i32 [[VGET_LANE]], i32 15458; CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i32> [[VECINIT1_I]], i32 [[VGET_LANE]], i32 25459; CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i32> [[VECINIT2_I]], i32 [[VGET_LANE]], i32 35460; CHECK-NEXT: [[PROD:%.*]] = mul <4 x i32> [[A]], [[VECINIT3_I]]5461; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 85462; CHECK-NEXT: ret <4 x i32> [[PROD]]5463;5464 %vget_lane = extractelement <4 x i32> %b, i32 15465 %vecinit.i = insertelement <4 x i32> undef, i32 %vget_lane, i32 05466 %vecinit1.i = insertelement <4 x i32> %vecinit.i, i32 %vget_lane, i32 15467 %vecinit2.i = insertelement <4 x i32> %vecinit1.i, i32 %vget_lane, i32 25468 %vecinit3.i = insertelement <4 x i32> %vecinit2.i, i32 %vget_lane, i32 35469 %prod = mul <4 x i32> %a, %vecinit3.i5470 ret <4 x i32> %prod5471}5472 5473define <4 x i16> @vmul_built_dup_fromsmall_test(<4 x i16> %a, <4 x i16> %b) {5474; CHECK-LABEL: define <4 x i16> @vmul_built_dup_fromsmall_test(5475; CHECK-SAME: <4 x i16> [[A:%.*]], <4 x i16> [[B:%.*]]) {5476; CHECK-NEXT: call void @llvm.donothing()5477; CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <4 x i16> [[B]], i32 35478; CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <4 x i16> undef, i16 [[VGET_LANE]], i32 05479; CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <4 x i16> [[VECINIT_I]], i16 [[VGET_LANE]], i32 15480; CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <4 x i16> [[VECINIT1_I]], i16 [[VGET_LANE]], i32 25481; CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <4 x i16> [[VECINIT2_I]], i16 [[VGET_LANE]], i32 35482; CHECK-NEXT: [[PROD:%.*]] = mul <4 x i16> [[A]], [[VECINIT3_I]]5483; CHECK-NEXT: store <4 x i16> zeroinitializer, ptr @__msan_retval_tls, align 85484; CHECK-NEXT: ret <4 x i16> [[PROD]]5485;5486 %vget_lane = extractelement <4 x i16> %b, i32 35487 %vecinit.i = insertelement <4 x i16> undef, i16 %vget_lane, i32 05488 %vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %vget_lane, i32 15489 %vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %vget_lane, i32 25490 %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %vget_lane, i32 35491 %prod = mul <4 x i16> %a, %vecinit3.i5492 ret <4 x i16> %prod5493}5494 5495define <8 x i16> @vmulq_built_dup_fromsmall_test(<8 x i16> %a, <4 x i16> %b) {5496; CHECK-LABEL: define <8 x i16> @vmulq_built_dup_fromsmall_test(5497; CHECK-SAME: <8 x i16> [[A:%.*]], <4 x i16> [[B:%.*]]) {5498; CHECK-NEXT: call void @llvm.donothing()5499; CHECK-NEXT: [[VGET_LANE:%.*]] = extractelement <4 x i16> [[B]], i32 05500; CHECK-NEXT: [[VECINIT_I:%.*]] = insertelement <8 x i16> undef, i16 [[VGET_LANE]], i32 05501; CHECK-NEXT: [[VECINIT1_I:%.*]] = insertelement <8 x i16> [[VECINIT_I]], i16 [[VGET_LANE]], i32 15502; CHECK-NEXT: [[VECINIT2_I:%.*]] = insertelement <8 x i16> [[VECINIT1_I]], i16 [[VGET_LANE]], i32 25503; CHECK-NEXT: [[VECINIT3_I:%.*]] = insertelement <8 x i16> [[VECINIT2_I]], i16 [[VGET_LANE]], i32 35504; CHECK-NEXT: [[VECINIT4_I:%.*]] = insertelement <8 x i16> [[VECINIT3_I]], i16 [[VGET_LANE]], i32 45505; CHECK-NEXT: [[VECINIT5_I:%.*]] = insertelement <8 x i16> [[VECINIT4_I]], i16 [[VGET_LANE]], i32 55506; CHECK-NEXT: [[VECINIT6_I:%.*]] = insertelement <8 x i16> [[VECINIT5_I]], i16 [[VGET_LANE]], i32 65507; CHECK-NEXT: [[VECINIT7_I:%.*]] = insertelement <8 x i16> [[VECINIT6_I]], i16 [[VGET_LANE]], i32 75508; CHECK-NEXT: [[PROD:%.*]] = mul <8 x i16> [[A]], [[VECINIT7_I]]5509; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 85510; CHECK-NEXT: ret <8 x i16> [[PROD]]5511;5512 %vget_lane = extractelement <4 x i16> %b, i32 05513 %vecinit.i = insertelement <8 x i16> undef, i16 %vget_lane, i32 05514 %vecinit1.i = insertelement <8 x i16> %vecinit.i, i16 %vget_lane, i32 15515 %vecinit2.i = insertelement <8 x i16> %vecinit1.i, i16 %vget_lane, i32 25516 %vecinit3.i = insertelement <8 x i16> %vecinit2.i, i16 %vget_lane, i32 35517 %vecinit4.i = insertelement <8 x i16> %vecinit3.i, i16 %vget_lane, i32 45518 %vecinit5.i = insertelement <8 x i16> %vecinit4.i, i16 %vget_lane, i32 55519 %vecinit6.i = insertelement <8 x i16> %vecinit5.i, i16 %vget_lane, i32 65520 %vecinit7.i = insertelement <8 x i16> %vecinit6.i, i16 %vget_lane, i32 75521 %prod = mul <8 x i16> %a, %vecinit7.i5522 ret <8 x i16> %prod5523}5524 5525define <2 x i64> @mull_from_two_extracts(<4 x i32> %lhs, <4 x i32> %rhs) {5526; CHECK-LABEL: define <2 x i64> @mull_from_two_extracts(5527; CHECK-SAME: <4 x i32> [[LHS:%.*]], <4 x i32> [[RHS:%.*]]) {5528; CHECK-NEXT: call void @llvm.donothing()5529; CHECK-NEXT: [[LHS_HIGH:%.*]] = shufflevector <4 x i32> [[LHS]], <4 x i32> undef, <2 x i32> <i32 2, i32 3>5530; CHECK-NEXT: [[RHS_HIGH:%.*]] = shufflevector <4 x i32> [[RHS]], <4 x i32> undef, <2 x i32> <i32 2, i32 3>5531; CHECK-NEXT: [[RES:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[LHS_HIGH]], <2 x i32> [[RHS_HIGH]]) #[[ATTR7]]5532; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 85533; CHECK-NEXT: ret <2 x i64> [[RES]]5534;5535 %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>5536 %rhs.high = shufflevector <4 x i32> %rhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>5537 5538 %res = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %lhs.high, <2 x i32> %rhs.high) nounwind5539 ret <2 x i64> %res5540}5541 5542define <2 x i64> @mlal_from_two_extracts(<2 x i64> %accum, <4 x i32> %lhs, <4 x i32> %rhs) {5543; CHECK-LABEL: define <2 x i64> @mlal_from_two_extracts(5544; CHECK-SAME: <2 x i64> [[ACCUM:%.*]], <4 x i32> [[LHS:%.*]], <4 x i32> [[RHS:%.*]]) {5545; CHECK-NEXT: call void @llvm.donothing()5546; CHECK-NEXT: [[LHS_HIGH:%.*]] = shufflevector <4 x i32> [[LHS]], <4 x i32> undef, <2 x i32> <i32 2, i32 3>5547; CHECK-NEXT: [[RHS_HIGH:%.*]] = shufflevector <4 x i32> [[RHS]], <4 x i32> undef, <2 x i32> <i32 2, i32 3>5548; CHECK-NEXT: [[RES:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[LHS_HIGH]], <2 x i32> [[RHS_HIGH]]) #[[ATTR7]]5549; CHECK-NEXT: [[SUM:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> [[ACCUM]], <2 x i64> [[RES]])5550; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 85551; CHECK-NEXT: ret <2 x i64> [[SUM]]5552;5553 %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>5554 %rhs.high = shufflevector <4 x i32> %rhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>5555 5556 %res = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %lhs.high, <2 x i32> %rhs.high) nounwind5557 %sum = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %accum, <2 x i64> %res)5558 ret <2 x i64> %sum5559}5560 5561define <2 x i64> @mull_from_extract_dup_low(<4 x i32> %lhs, i32 %rhs) {5562; CHECK-LABEL: define <2 x i64> @mull_from_extract_dup_low(5563; CHECK-SAME: <4 x i32> [[LHS:%.*]], i32 [[RHS:%.*]]) {5564; CHECK-NEXT: call void @llvm.donothing()5565; CHECK-NEXT: [[RHSVEC_TMP:%.*]] = insertelement <2 x i32> undef, i32 [[RHS]], i32 05566; CHECK-NEXT: [[RHSVEC:%.*]] = insertelement <2 x i32> [[RHSVEC_TMP]], i32 [[RHS]], i32 15567; CHECK-NEXT: [[LHS_HIGH:%.*]] = shufflevector <4 x i32> [[LHS]], <4 x i32> undef, <2 x i32> <i32 0, i32 1>5568; CHECK-NEXT: [[RES:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[LHS_HIGH]], <2 x i32> [[RHSVEC]]) #[[ATTR7]]5569; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 85570; CHECK-NEXT: ret <2 x i64> [[RES]]5571;5572 %rhsvec.tmp = insertelement <2 x i32> undef, i32 %rhs, i32 05573 %rhsvec = insertelement <2 x i32> %rhsvec.tmp, i32 %rhs, i32 15574 5575 %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 0, i32 1>5576 5577 %res = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %lhs.high, <2 x i32> %rhsvec) nounwind5578 ret <2 x i64> %res5579}5580 5581define <2 x i64> @mull_from_extract_dup_high(<4 x i32> %lhs, i32 %rhs) {5582; CHECK-LABEL: define <2 x i64> @mull_from_extract_dup_high(5583; CHECK-SAME: <4 x i32> [[LHS:%.*]], i32 [[RHS:%.*]]) {5584; CHECK-NEXT: call void @llvm.donothing()5585; CHECK-NEXT: [[RHSVEC_TMP:%.*]] = insertelement <2 x i32> undef, i32 [[RHS]], i32 05586; CHECK-NEXT: [[RHSVEC:%.*]] = insertelement <2 x i32> [[RHSVEC_TMP]], i32 [[RHS]], i32 15587; CHECK-NEXT: [[LHS_HIGH:%.*]] = shufflevector <4 x i32> [[LHS]], <4 x i32> undef, <2 x i32> <i32 2, i32 3>5588; CHECK-NEXT: [[RES:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[LHS_HIGH]], <2 x i32> [[RHSVEC]]) #[[ATTR7]]5589; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 85590; CHECK-NEXT: ret <2 x i64> [[RES]]5591;5592 %rhsvec.tmp = insertelement <2 x i32> undef, i32 %rhs, i32 05593 %rhsvec = insertelement <2 x i32> %rhsvec.tmp, i32 %rhs, i32 15594 5595 %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>5596 5597 %res = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %lhs.high, <2 x i32> %rhsvec) nounwind5598 ret <2 x i64> %res5599}5600 5601define <8 x i16> @pmull_from_extract_dup_low(<16 x i8> %lhs, i8 %rhs) {5602; CHECK-LABEL: define <8 x i16> @pmull_from_extract_dup_low(5603; CHECK-SAME: <16 x i8> [[LHS:%.*]], i8 [[RHS:%.*]]) {5604; CHECK-NEXT: call void @llvm.donothing()5605; CHECK-NEXT: [[RHSVEC_0:%.*]] = insertelement <8 x i8> undef, i8 [[RHS]], i32 05606; CHECK-NEXT: [[RHSVEC:%.*]] = shufflevector <8 x i8> [[RHSVEC_0]], <8 x i8> undef, <8 x i32> zeroinitializer5607; CHECK-NEXT: [[LHS_HIGH:%.*]] = shufflevector <16 x i8> [[LHS]], <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>5608; CHECK-NEXT: [[RES:%.*]] = tail call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> [[LHS_HIGH]], <8 x i8> [[RHSVEC]]) #[[ATTR7]]5609; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 85610; CHECK-NEXT: ret <8 x i16> [[RES]]5611;5612 %rhsvec.0 = insertelement <8 x i8> undef, i8 %rhs, i32 05613 %rhsvec = shufflevector <8 x i8> %rhsvec.0, <8 x i8> undef, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>5614 5615 %lhs.high = shufflevector <16 x i8> %lhs, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>5616 5617 %res = tail call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> %lhs.high, <8 x i8> %rhsvec) nounwind5618 ret <8 x i16> %res5619}5620 5621define <8 x i16> @pmull_from_extract_dup_high(<16 x i8> %lhs, i8 %rhs) {5622; CHECK-LABEL: define <8 x i16> @pmull_from_extract_dup_high(5623; CHECK-SAME: <16 x i8> [[LHS:%.*]], i8 [[RHS:%.*]]) {5624; CHECK-NEXT: call void @llvm.donothing()5625; CHECK-NEXT: [[RHSVEC_0:%.*]] = insertelement <8 x i8> undef, i8 [[RHS]], i32 05626; CHECK-NEXT: [[RHSVEC:%.*]] = shufflevector <8 x i8> [[RHSVEC_0]], <8 x i8> undef, <8 x i32> zeroinitializer5627; CHECK-NEXT: [[LHS_HIGH:%.*]] = shufflevector <16 x i8> [[LHS]], <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>5628; CHECK-NEXT: [[RES:%.*]] = tail call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> [[LHS_HIGH]], <8 x i8> [[RHSVEC]]) #[[ATTR7]]5629; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 85630; CHECK-NEXT: ret <8 x i16> [[RES]]5631;5632 %rhsvec.0 = insertelement <8 x i8> undef, i8 %rhs, i32 05633 %rhsvec = shufflevector <8 x i8> %rhsvec.0, <8 x i8> undef, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>5634 5635 %lhs.high = shufflevector <16 x i8> %lhs, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>5636 5637 %res = tail call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> %lhs.high, <8 x i8> %rhsvec) nounwind5638 ret <8 x i16> %res5639}5640 5641define <8 x i16> @pmull_from_extract_duplane_low(<16 x i8> %lhs, <8 x i8> %rhs) {5642; CHECK-LABEL: define <8 x i16> @pmull_from_extract_duplane_low(5643; CHECK-SAME: <16 x i8> [[LHS:%.*]], <8 x i8> [[RHS:%.*]]) {5644; CHECK-NEXT: call void @llvm.donothing()5645; CHECK-NEXT: [[LHS_HIGH:%.*]] = shufflevector <16 x i8> [[LHS]], <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>5646; CHECK-NEXT: [[RHS_HIGH:%.*]] = shufflevector <8 x i8> [[RHS]], <8 x i8> undef, <8 x i32> zeroinitializer5647; CHECK-NEXT: [[RES:%.*]] = tail call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> [[LHS_HIGH]], <8 x i8> [[RHS_HIGH]]) #[[ATTR7]]5648; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 85649; CHECK-NEXT: ret <8 x i16> [[RES]]5650;5651 %lhs.high = shufflevector <16 x i8> %lhs, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>5652 %rhs.high = shufflevector <8 x i8> %rhs, <8 x i8> undef, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>5653 5654 %res = tail call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> %lhs.high, <8 x i8> %rhs.high) nounwind5655 ret <8 x i16> %res5656}5657 5658define <8 x i16> @pmull_from_extract_duplane_high(<16 x i8> %lhs, <8 x i8> %rhs) {5659; CHECK-LABEL: define <8 x i16> @pmull_from_extract_duplane_high(5660; CHECK-SAME: <16 x i8> [[LHS:%.*]], <8 x i8> [[RHS:%.*]]) {5661; CHECK-NEXT: call void @llvm.donothing()5662; CHECK-NEXT: [[LHS_HIGH:%.*]] = shufflevector <16 x i8> [[LHS]], <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>5663; CHECK-NEXT: [[RHS_HIGH:%.*]] = shufflevector <8 x i8> [[RHS]], <8 x i8> undef, <8 x i32> zeroinitializer5664; CHECK-NEXT: [[RES:%.*]] = tail call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> [[LHS_HIGH]], <8 x i8> [[RHS_HIGH]]) #[[ATTR7]]5665; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 85666; CHECK-NEXT: ret <8 x i16> [[RES]]5667;5668 %lhs.high = shufflevector <16 x i8> %lhs, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>5669 %rhs.high = shufflevector <8 x i8> %rhs, <8 x i8> undef, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>5670 5671 %res = tail call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> %lhs.high, <8 x i8> %rhs.high) nounwind5672 ret <8 x i16> %res5673}5674 5675define <2 x i64> @sqdmull_from_extract_duplane_low(<4 x i32> %lhs, <4 x i32> %rhs) {5676; CHECK-LABEL: define <2 x i64> @sqdmull_from_extract_duplane_low(5677; CHECK-SAME: <4 x i32> [[LHS:%.*]], <4 x i32> [[RHS:%.*]]) {5678; CHECK-NEXT: call void @llvm.donothing()5679; CHECK-NEXT: [[LHS_HIGH:%.*]] = shufflevector <4 x i32> [[LHS]], <4 x i32> undef, <2 x i32> <i32 0, i32 1>5680; CHECK-NEXT: [[RHS_HIGH:%.*]] = shufflevector <4 x i32> [[RHS]], <4 x i32> undef, <2 x i32> zeroinitializer5681; CHECK-NEXT: [[RES:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[LHS_HIGH]], <2 x i32> [[RHS_HIGH]]) #[[ATTR7]]5682; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 85683; CHECK-NEXT: ret <2 x i64> [[RES]]5684;5685 %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 0, i32 1>5686 %rhs.high = shufflevector <4 x i32> %rhs, <4 x i32> undef, <2 x i32> <i32 0, i32 0>5687 5688 %res = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %lhs.high, <2 x i32> %rhs.high) nounwind5689 ret <2 x i64> %res5690}5691 5692define <2 x i64> @sqdmull_from_extract_duplane_high(<4 x i32> %lhs, <4 x i32> %rhs) {5693; CHECK-LABEL: define <2 x i64> @sqdmull_from_extract_duplane_high(5694; CHECK-SAME: <4 x i32> [[LHS:%.*]], <4 x i32> [[RHS:%.*]]) {5695; CHECK-NEXT: call void @llvm.donothing()5696; CHECK-NEXT: [[LHS_HIGH:%.*]] = shufflevector <4 x i32> [[LHS]], <4 x i32> undef, <2 x i32> <i32 2, i32 3>5697; CHECK-NEXT: [[RHS_HIGH:%.*]] = shufflevector <4 x i32> [[RHS]], <4 x i32> undef, <2 x i32> zeroinitializer5698; CHECK-NEXT: [[RES:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[LHS_HIGH]], <2 x i32> [[RHS_HIGH]]) #[[ATTR7]]5699; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 85700; CHECK-NEXT: ret <2 x i64> [[RES]]5701;5702 %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>5703 %rhs.high = shufflevector <4 x i32> %rhs, <4 x i32> undef, <2 x i32> <i32 0, i32 0>5704 5705 %res = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %lhs.high, <2 x i32> %rhs.high) nounwind5706 ret <2 x i64> %res5707}5708 5709define <2 x i64> @sqdmlal_from_extract_duplane_low(<2 x i64> %accum, <4 x i32> %lhs, <4 x i32> %rhs) {5710; CHECK-LABEL: define <2 x i64> @sqdmlal_from_extract_duplane_low(5711; CHECK-SAME: <2 x i64> [[ACCUM:%.*]], <4 x i32> [[LHS:%.*]], <4 x i32> [[RHS:%.*]]) {5712; CHECK-NEXT: call void @llvm.donothing()5713; CHECK-NEXT: [[LHS_HIGH:%.*]] = shufflevector <4 x i32> [[LHS]], <4 x i32> undef, <2 x i32> <i32 0, i32 1>5714; CHECK-NEXT: [[RHS_HIGH:%.*]] = shufflevector <4 x i32> [[RHS]], <4 x i32> undef, <2 x i32> zeroinitializer5715; CHECK-NEXT: [[RES:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[LHS_HIGH]], <2 x i32> [[RHS_HIGH]]) #[[ATTR7]]5716; CHECK-NEXT: [[SUM:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> [[ACCUM]], <2 x i64> [[RES]])5717; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 85718; CHECK-NEXT: ret <2 x i64> [[SUM]]5719;5720 %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 0, i32 1>5721 %rhs.high = shufflevector <4 x i32> %rhs, <4 x i32> undef, <2 x i32> <i32 0, i32 0>5722 5723 %res = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %lhs.high, <2 x i32> %rhs.high) nounwind5724 %sum = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %accum, <2 x i64> %res)5725 ret <2 x i64> %sum5726}5727 5728define <2 x i64> @sqdmlal_from_extract_duplane_high(<2 x i64> %accum, <4 x i32> %lhs, <4 x i32> %rhs) {5729; CHECK-LABEL: define <2 x i64> @sqdmlal_from_extract_duplane_high(5730; CHECK-SAME: <2 x i64> [[ACCUM:%.*]], <4 x i32> [[LHS:%.*]], <4 x i32> [[RHS:%.*]]) {5731; CHECK-NEXT: call void @llvm.donothing()5732; CHECK-NEXT: [[LHS_HIGH:%.*]] = shufflevector <4 x i32> [[LHS]], <4 x i32> undef, <2 x i32> <i32 2, i32 3>5733; CHECK-NEXT: [[RHS_HIGH:%.*]] = shufflevector <4 x i32> [[RHS]], <4 x i32> undef, <2 x i32> zeroinitializer5734; CHECK-NEXT: [[RES:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> [[LHS_HIGH]], <2 x i32> [[RHS_HIGH]]) #[[ATTR7]]5735; CHECK-NEXT: [[SUM:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> [[ACCUM]], <2 x i64> [[RES]])5736; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 85737; CHECK-NEXT: ret <2 x i64> [[SUM]]5738;5739 %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>5740 %rhs.high = shufflevector <4 x i32> %rhs, <4 x i32> undef, <2 x i32> <i32 0, i32 0>5741 5742 %res = tail call <2 x i64> @llvm.aarch64.neon.sqdmull.v2i64(<2 x i32> %lhs.high, <2 x i32> %rhs.high) nounwind5743 %sum = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %accum, <2 x i64> %res)5744 ret <2 x i64> %sum5745}5746 5747define <2 x i64> @umlal_from_extract_duplane_low(<2 x i64> %accum, <4 x i32> %lhs, <4 x i32> %rhs) {5748; CHECK-LABEL: define <2 x i64> @umlal_from_extract_duplane_low(5749; CHECK-SAME: <2 x i64> [[ACCUM:%.*]], <4 x i32> [[LHS:%.*]], <4 x i32> [[RHS:%.*]]) {5750; CHECK-NEXT: call void @llvm.donothing()5751; CHECK-NEXT: [[LHS_HIGH:%.*]] = shufflevector <4 x i32> [[LHS]], <4 x i32> undef, <2 x i32> <i32 0, i32 1>5752; CHECK-NEXT: [[RHS_HIGH:%.*]] = shufflevector <4 x i32> [[RHS]], <4 x i32> undef, <2 x i32> zeroinitializer5753; CHECK-NEXT: [[RES:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[LHS_HIGH]], <2 x i32> [[RHS_HIGH]]) #[[ATTR7]]5754; CHECK-NEXT: [[SUM:%.*]] = add <2 x i64> [[ACCUM]], [[RES]]5755; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 85756; CHECK-NEXT: ret <2 x i64> [[SUM]]5757;5758 %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 0, i32 1>5759 %rhs.high = shufflevector <4 x i32> %rhs, <4 x i32> undef, <2 x i32> <i32 0, i32 0>5760 5761 %res = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %lhs.high, <2 x i32> %rhs.high) nounwind5762 %sum = add <2 x i64> %accum, %res5763 ret <2 x i64> %sum5764}5765 5766define <2 x i64> @umlal_from_extract_duplane_high(<2 x i64> %accum, <4 x i32> %lhs, <4 x i32> %rhs) {5767; CHECK-LABEL: define <2 x i64> @umlal_from_extract_duplane_high(5768; CHECK-SAME: <2 x i64> [[ACCUM:%.*]], <4 x i32> [[LHS:%.*]], <4 x i32> [[RHS:%.*]]) {5769; CHECK-NEXT: call void @llvm.donothing()5770; CHECK-NEXT: [[LHS_HIGH:%.*]] = shufflevector <4 x i32> [[LHS]], <4 x i32> undef, <2 x i32> <i32 2, i32 3>5771; CHECK-NEXT: [[RHS_HIGH:%.*]] = shufflevector <4 x i32> [[RHS]], <4 x i32> undef, <2 x i32> zeroinitializer5772; CHECK-NEXT: [[RES:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[LHS_HIGH]], <2 x i32> [[RHS_HIGH]]) #[[ATTR7]]5773; CHECK-NEXT: [[SUM:%.*]] = add <2 x i64> [[ACCUM]], [[RES]]5774; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 85775; CHECK-NEXT: ret <2 x i64> [[SUM]]5776;5777 %lhs.high = shufflevector <4 x i32> %lhs, <4 x i32> undef, <2 x i32> <i32 2, i32 3>5778 %rhs.high = shufflevector <4 x i32> %rhs, <4 x i32> undef, <2 x i32> <i32 0, i32 0>5779 5780 %res = tail call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> %lhs.high, <2 x i32> %rhs.high) nounwind5781 %sum = add <2 x i64> %accum, %res5782 ret <2 x i64> %sum5783}5784 5785define float @scalar_fmla_from_extract_v4f32(float %accum, float %lhs, <4 x float> %rvec) {5786; CHECK-LABEL: define float @scalar_fmla_from_extract_v4f32(5787; CHECK-SAME: float [[ACCUM:%.*]], float [[LHS:%.*]], <4 x float> [[RVEC:%.*]]) {5788; CHECK-NEXT: call void @llvm.donothing()5789; CHECK-NEXT: [[RHS:%.*]] = extractelement <4 x float> [[RVEC]], i32 35790; CHECK-NEXT: [[RES:%.*]] = call float @llvm.fma.f32(float [[LHS]], float [[RHS]], float [[ACCUM]])5791; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 85792; CHECK-NEXT: ret float [[RES]]5793;5794 %rhs = extractelement <4 x float> %rvec, i32 35795 %res = call float @llvm.fma.f32(float %lhs, float %rhs, float %accum)5796 ret float %res5797}5798 5799define float @scalar_fmla_from_extract_v2f32(float %accum, float %lhs, <2 x float> %rvec) {5800; CHECK-LABEL: define float @scalar_fmla_from_extract_v2f32(5801; CHECK-SAME: float [[ACCUM:%.*]], float [[LHS:%.*]], <2 x float> [[RVEC:%.*]]) {5802; CHECK-NEXT: call void @llvm.donothing()5803; CHECK-NEXT: [[RHS:%.*]] = extractelement <2 x float> [[RVEC]], i32 15804; CHECK-NEXT: [[RES:%.*]] = call float @llvm.fma.f32(float [[LHS]], float [[RHS]], float [[ACCUM]])5805; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 85806; CHECK-NEXT: ret float [[RES]]5807;5808 %rhs = extractelement <2 x float> %rvec, i32 15809 %res = call float @llvm.fma.f32(float %lhs, float %rhs, float %accum)5810 ret float %res5811}5812 5813define float @scalar_fmls_from_extract_v4f32(float %accum, float %lhs, <4 x float> %rvec) {5814; CHECK-LABEL: define float @scalar_fmls_from_extract_v4f32(5815; CHECK-SAME: float [[ACCUM:%.*]], float [[LHS:%.*]], <4 x float> [[RVEC:%.*]]) {5816; CHECK-NEXT: call void @llvm.donothing()5817; CHECK-NEXT: [[RHS_SCAL:%.*]] = extractelement <4 x float> [[RVEC]], i32 35818; CHECK-NEXT: [[RHS:%.*]] = fsub float -0.000000e+00, [[RHS_SCAL]]5819; CHECK-NEXT: [[RES:%.*]] = call float @llvm.fma.f32(float [[LHS]], float [[RHS]], float [[ACCUM]])5820; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 85821; CHECK-NEXT: ret float [[RES]]5822;5823 %rhs.scal = extractelement <4 x float> %rvec, i32 35824 %rhs = fsub float -0.0, %rhs.scal5825 %res = call float @llvm.fma.f32(float %lhs, float %rhs, float %accum)5826 ret float %res5827}5828 5829define float @scalar_fmls_from_extract_v2f32(float %accum, float %lhs, <2 x float> %rvec) {5830; CHECK-LABEL: define float @scalar_fmls_from_extract_v2f32(5831; CHECK-SAME: float [[ACCUM:%.*]], float [[LHS:%.*]], <2 x float> [[RVEC:%.*]]) {5832; CHECK-NEXT: call void @llvm.donothing()5833; CHECK-NEXT: [[RHS_SCAL:%.*]] = extractelement <2 x float> [[RVEC]], i32 15834; CHECK-NEXT: [[RHS:%.*]] = fsub float -0.000000e+00, [[RHS_SCAL]]5835; CHECK-NEXT: [[RES:%.*]] = call float @llvm.fma.f32(float [[LHS]], float [[RHS]], float [[ACCUM]])5836; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 85837; CHECK-NEXT: ret float [[RES]]5838;5839 %rhs.scal = extractelement <2 x float> %rvec, i32 15840 %rhs = fsub float -0.0, %rhs.scal5841 %res = call float @llvm.fma.f32(float %lhs, float %rhs, float %accum)5842 ret float %res5843}5844 5845declare float @llvm.fma.f32(float, float, float)5846 5847define double @scalar_fmla_from_extract_v2f64(double %accum, double %lhs, <2 x double> %rvec) {5848; CHECK-LABEL: define double @scalar_fmla_from_extract_v2f64(5849; CHECK-SAME: double [[ACCUM:%.*]], double [[LHS:%.*]], <2 x double> [[RVEC:%.*]]) {5850; CHECK-NEXT: call void @llvm.donothing()5851; CHECK-NEXT: [[RHS:%.*]] = extractelement <2 x double> [[RVEC]], i32 15852; CHECK-NEXT: [[RES:%.*]] = call double @llvm.fma.f64(double [[LHS]], double [[RHS]], double [[ACCUM]])5853; CHECK-NEXT: store i64 0, ptr @__msan_retval_tls, align 85854; CHECK-NEXT: ret double [[RES]]5855;5856 %rhs = extractelement <2 x double> %rvec, i32 15857 %res = call double @llvm.fma.f64(double %lhs, double %rhs, double %accum)5858 ret double %res5859}5860 5861define double @scalar_fmls_from_extract_v2f64(double %accum, double %lhs, <2 x double> %rvec) {5862; CHECK-LABEL: define double @scalar_fmls_from_extract_v2f64(5863; CHECK-SAME: double [[ACCUM:%.*]], double [[LHS:%.*]], <2 x double> [[RVEC:%.*]]) {5864; CHECK-NEXT: call void @llvm.donothing()5865; CHECK-NEXT: [[RHS_SCAL:%.*]] = extractelement <2 x double> [[RVEC]], i32 15866; CHECK-NEXT: [[RHS:%.*]] = fsub double -0.000000e+00, [[RHS_SCAL]]5867; CHECK-NEXT: [[RES:%.*]] = call double @llvm.fma.f64(double [[LHS]], double [[RHS]], double [[ACCUM]])5868; CHECK-NEXT: store i64 0, ptr @__msan_retval_tls, align 85869; CHECK-NEXT: ret double [[RES]]5870;5871 %rhs.scal = extractelement <2 x double> %rvec, i32 15872 %rhs = fsub double -0.0, %rhs.scal5873 %res = call double @llvm.fma.f64(double %lhs, double %rhs, double %accum)5874 ret double %res5875}5876 5877declare double @llvm.fma.f64(double, double, double)5878 5879define <2 x float> @fmls_with_fneg_before_extract_v2f32(<2 x float> %accum, <2 x float> %lhs, <4 x float> %rhs) {5880; CHECK-LABEL: define <2 x float> @fmls_with_fneg_before_extract_v2f32(5881; CHECK-SAME: <2 x float> [[ACCUM:%.*]], <2 x float> [[LHS:%.*]], <4 x float> [[RHS:%.*]]) {5882; CHECK-NEXT: call void @llvm.donothing()5883; CHECK-NEXT: [[RHS_NEG:%.*]] = fsub <4 x float> splat (float -0.000000e+00), [[RHS]]5884; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x float> [[RHS_NEG]], <4 x float> undef, <2 x i32> <i32 3, i32 3>5885; CHECK-NEXT: [[RES:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float> [[LHS]], <2 x float> [[SPLAT]], <2 x float> [[ACCUM]])5886; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr @__msan_retval_tls, align 85887; CHECK-NEXT: ret <2 x float> [[RES]]5888;5889 %rhs_neg = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %rhs5890 %splat = shufflevector <4 x float> %rhs_neg, <4 x float> undef, <2 x i32> <i32 3, i32 3>5891 %res = call <2 x float> @llvm.fma.v2f32(<2 x float> %lhs, <2 x float> %splat, <2 x float> %accum)5892 ret <2 x float> %res5893}5894 5895define <2 x float> @fmls_with_fneg_before_extract_v2f32_1(<2 x float> %accum, <2 x float> %lhs, <2 x float> %rhs) {5896; CHECK-LABEL: define <2 x float> @fmls_with_fneg_before_extract_v2f32_1(5897; CHECK-SAME: <2 x float> [[ACCUM:%.*]], <2 x float> [[LHS:%.*]], <2 x float> [[RHS:%.*]]) {5898; CHECK-NEXT: call void @llvm.donothing()5899; CHECK-NEXT: [[RHS_NEG:%.*]] = fsub <2 x float> splat (float -0.000000e+00), [[RHS]]5900; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <2 x float> [[RHS_NEG]], <2 x float> undef, <2 x i32> <i32 1, i32 1>5901; CHECK-NEXT: [[RES:%.*]] = call <2 x float> @llvm.fma.v2f32(<2 x float> [[LHS]], <2 x float> [[SPLAT]], <2 x float> [[ACCUM]])5902; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr @__msan_retval_tls, align 85903; CHECK-NEXT: ret <2 x float> [[RES]]5904;5905 %rhs_neg = fsub <2 x float> <float -0.0, float -0.0>, %rhs5906 %splat = shufflevector <2 x float> %rhs_neg, <2 x float> undef, <2 x i32> <i32 1, i32 1>5907 %res = call <2 x float> @llvm.fma.v2f32(<2 x float> %lhs, <2 x float> %splat, <2 x float> %accum)5908 ret <2 x float> %res5909}5910 5911define <4 x float> @fmls_with_fneg_before_extract_v4f32(<4 x float> %accum, <4 x float> %lhs, <4 x float> %rhs) {5912; CHECK-LABEL: define <4 x float> @fmls_with_fneg_before_extract_v4f32(5913; CHECK-SAME: <4 x float> [[ACCUM:%.*]], <4 x float> [[LHS:%.*]], <4 x float> [[RHS:%.*]]) {5914; CHECK-NEXT: call void @llvm.donothing()5915; CHECK-NEXT: [[RHS_NEG:%.*]] = fsub <4 x float> splat (float -0.000000e+00), [[RHS]]5916; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <4 x float> [[RHS_NEG]], <4 x float> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>5917; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[LHS]], <4 x float> [[SPLAT]], <4 x float> [[ACCUM]])5918; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 85919; CHECK-NEXT: ret <4 x float> [[RES]]5920;5921 %rhs_neg = fsub <4 x float> <float -0.0, float -0.0, float -0.0, float -0.0>, %rhs5922 %splat = shufflevector <4 x float> %rhs_neg, <4 x float> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>5923 %res = call <4 x float> @llvm.fma.v4f32(<4 x float> %lhs, <4 x float> %splat, <4 x float> %accum)5924 ret <4 x float> %res5925}5926 5927define <4 x float> @fmls_with_fneg_before_extract_v4f32_1(<4 x float> %accum, <4 x float> %lhs, <2 x float> %rhs) {5928; CHECK-LABEL: define <4 x float> @fmls_with_fneg_before_extract_v4f32_1(5929; CHECK-SAME: <4 x float> [[ACCUM:%.*]], <4 x float> [[LHS:%.*]], <2 x float> [[RHS:%.*]]) {5930; CHECK-NEXT: call void @llvm.donothing()5931; CHECK-NEXT: [[RHS_NEG:%.*]] = fsub <2 x float> splat (float -0.000000e+00), [[RHS]]5932; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <2 x float> [[RHS_NEG]], <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>5933; CHECK-NEXT: [[RES:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[LHS]], <4 x float> [[SPLAT]], <4 x float> [[ACCUM]])5934; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 85935; CHECK-NEXT: ret <4 x float> [[RES]]5936;5937 %rhs_neg = fsub <2 x float> <float -0.0, float -0.0>, %rhs5938 %splat = shufflevector <2 x float> %rhs_neg, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>5939 %res = call <4 x float> @llvm.fma.v4f32(<4 x float> %lhs, <4 x float> %splat, <4 x float> %accum)5940 ret <4 x float> %res5941}5942 5943define <2 x double> @fmls_with_fneg_before_extract_v2f64(<2 x double> %accum, <2 x double> %lhs, <2 x double> %rhs) {5944; CHECK-LABEL: define <2 x double> @fmls_with_fneg_before_extract_v2f64(5945; CHECK-SAME: <2 x double> [[ACCUM:%.*]], <2 x double> [[LHS:%.*]], <2 x double> [[RHS:%.*]]) {5946; CHECK-NEXT: call void @llvm.donothing()5947; CHECK-NEXT: [[RHS_NEG:%.*]] = fsub <2 x double> splat (double -0.000000e+00), [[RHS]]5948; CHECK-NEXT: [[SPLAT:%.*]] = shufflevector <2 x double> [[RHS_NEG]], <2 x double> undef, <2 x i32> <i32 1, i32 1>5949; CHECK-NEXT: [[RES:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[LHS]], <2 x double> [[SPLAT]], <2 x double> [[ACCUM]])5950; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 85951; CHECK-NEXT: ret <2 x double> [[RES]]5952;5953 %rhs_neg = fsub <2 x double> <double -0.0, double -0.0>, %rhs5954 %splat = shufflevector <2 x double> %rhs_neg, <2 x double> undef, <2 x i32> <i32 1, i32 1>5955 %res = call <2 x double> @llvm.fma.v2f64(<2 x double> %lhs, <2 x double> %splat, <2 x double> %accum)5956 ret <2 x double> %res5957}5958 5959define <1 x double> @test_fmul_v1f64(<1 x double> %L, <1 x double> %R) nounwind sanitize_memory {5960; CHECK-LABEL: define <1 x double> @test_fmul_v1f64(5961; CHECK-SAME: <1 x double> [[L:%.*]], <1 x double> [[R:%.*]]) #[[ATTR0]] {5962; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 85963; CHECK-NEXT: [[TMP2:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 85964; CHECK-NEXT: call void @llvm.donothing()5965; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP1]], [[TMP2]]5966; CHECK-NEXT: [[PROD:%.*]] = fmul <1 x double> [[L]], [[R]]5967; CHECK-NEXT: store <1 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 85968; CHECK-NEXT: ret <1 x double> [[PROD]]5969;5970 %prod = fmul <1 x double> %L, %R5971 ret <1 x double> %prod5972}5973 5974define <1 x double> @test_fdiv_v1f64(<1 x double> %L, <1 x double> %R) nounwind sanitize_memory {5975; CHECK-LABEL: define <1 x double> @test_fdiv_v1f64(5976; CHECK-SAME: <1 x double> [[L:%.*]], <1 x double> [[R:%.*]]) #[[ATTR0]] {5977; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 85978; CHECK-NEXT: [[TMP2:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 85979; CHECK-NEXT: call void @llvm.donothing()5980; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP1]], [[TMP2]]5981; CHECK-NEXT: [[PROD:%.*]] = fdiv <1 x double> [[L]], [[R]]5982; CHECK-NEXT: store <1 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 85983; CHECK-NEXT: ret <1 x double> [[PROD]]5984;5985 %prod = fdiv <1 x double> %L, %R5986 ret <1 x double> %prod5987}5988 5989define i32 @sqdmlal_s(i16 %A, i16 %B, i32 %C) nounwind sanitize_memory {5990; CHECK-LABEL: define i32 @sqdmlal_s(5991; CHECK-SAME: i16 [[A:%.*]], i16 [[B:%.*]], i32 [[C:%.*]]) #[[ATTR0]] {5992; CHECK-NEXT: [[TMP6:%.*]] = load i16, ptr @__msan_param_tls, align 85993; CHECK-NEXT: [[TMP7:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 85994; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 85995; CHECK-NEXT: call void @llvm.donothing()5996; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <4 x i16> splat (i16 -1), i16 [[TMP6]], i64 05997; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> undef, i16 [[A]], i64 05998; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <4 x i16> splat (i16 -1), i16 [[TMP7]], i64 05999; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i16> undef, i16 [[B]], i64 06000; CHECK-NEXT: [[TMP9:%.*]] = bitcast <4 x i16> [[_MSPROP]] to i646001; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP9]], 06002; CHECK-NEXT: [[TMP10:%.*]] = bitcast <4 x i16> [[_MSPROP1]] to i646003; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP10]], 06004; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP3]]6005; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]6006; CHECK: [[BB6]]:6007; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]6008; CHECK-NEXT: unreachable6009; CHECK: [[BB7]]:6010; CHECK-NEXT: [[TMP3:%.*]] = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[TMP1]], <4 x i16> [[TMP2]])6011; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i64 06012; CHECK-NEXT: [[_MSPROP2:%.*]] = or i32 [[TMP8]], 06013; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.sqadd.i32(i32 [[C]], i32 [[TMP4]])6014; CHECK-NEXT: store i32 [[_MSPROP2]], ptr @__msan_retval_tls, align 86015; CHECK-NEXT: ret i32 [[TMP5]]6016;6017 %temp1 = insertelement <4 x i16> undef, i16 %A, i64 06018 %temp2 = insertelement <4 x i16> undef, i16 %B, i64 06019 %temp3 = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %temp1, <4 x i16> %temp2)6020 %temp4 = extractelement <4 x i32> %temp3, i64 06021 %temp5 = tail call i32 @llvm.aarch64.neon.sqadd.i32(i32 %C, i32 %temp4)6022 ret i32 %temp56023}6024 6025define i64 @sqdmlal_d(i32 %A, i32 %B, i64 %C) nounwind sanitize_memory {6026; CHECK-LABEL: define i64 @sqdmlal_d(6027; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]], i64 [[C:%.*]]) #[[ATTR0]] {6028; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 86029; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 86030; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 86031; CHECK-NEXT: call void @llvm.donothing()6032; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 06033; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i32 [[TMP2]], 06034; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6035; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]6036; CHECK: [[BB4]]:6037; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]6038; CHECK-NEXT: unreachable6039; CHECK: [[BB5]]:6040; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.aarch64.neon.sqdmulls.scalar(i32 [[A]], i32 [[B]])6041; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP3]], 06042; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.aarch64.neon.sqadd.i64(i64 [[C]], i64 [[TMP4]])6043; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 86044; CHECK-NEXT: ret i64 [[TMP5]]6045;6046 %temp4 = call i64 @llvm.aarch64.neon.sqdmulls.scalar(i32 %A, i32 %B)6047 %temp5 = call i64 @llvm.aarch64.neon.sqadd.i64(i64 %C, i64 %temp4)6048 ret i64 %temp56049}6050 6051define i32 @sqdmlsl_s(i16 %A, i16 %B, i32 %C) nounwind sanitize_memory {6052; CHECK-LABEL: define i32 @sqdmlsl_s(6053; CHECK-SAME: i16 [[A:%.*]], i16 [[B:%.*]], i32 [[C:%.*]]) #[[ATTR0]] {6054; CHECK-NEXT: [[TMP6:%.*]] = load i16, ptr @__msan_param_tls, align 86055; CHECK-NEXT: [[TMP7:%.*]] = load i16, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 86056; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 86057; CHECK-NEXT: call void @llvm.donothing()6058; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <4 x i16> splat (i16 -1), i16 [[TMP6]], i64 06059; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i16> undef, i16 [[A]], i64 06060; CHECK-NEXT: [[_MSPROP1:%.*]] = insertelement <4 x i16> splat (i16 -1), i16 [[TMP7]], i64 06061; CHECK-NEXT: [[TMP2:%.*]] = insertelement <4 x i16> undef, i16 [[B]], i64 06062; CHECK-NEXT: [[TMP9:%.*]] = bitcast <4 x i16> [[_MSPROP]] to i646063; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP9]], 06064; CHECK-NEXT: [[TMP10:%.*]] = bitcast <4 x i16> [[_MSPROP1]] to i646065; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP10]], 06066; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP3]]6067; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB6:.*]], label %[[BB7:.*]], !prof [[PROF1]]6068; CHECK: [[BB6]]:6069; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]6070; CHECK-NEXT: unreachable6071; CHECK: [[BB7]]:6072; CHECK-NEXT: [[TMP3:%.*]] = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> [[TMP1]], <4 x i16> [[TMP2]])6073; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[TMP3]], i64 06074; CHECK-NEXT: [[_MSPROP2:%.*]] = or i32 [[TMP8]], 06075; CHECK-NEXT: [[TMP5:%.*]] = tail call i32 @llvm.aarch64.neon.sqsub.i32(i32 [[C]], i32 [[TMP4]])6076; CHECK-NEXT: store i32 [[_MSPROP2]], ptr @__msan_retval_tls, align 86077; CHECK-NEXT: ret i32 [[TMP5]]6078;6079 %temp1 = insertelement <4 x i16> undef, i16 %A, i64 06080 %temp2 = insertelement <4 x i16> undef, i16 %B, i64 06081 %temp3 = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %temp1, <4 x i16> %temp2)6082 %temp4 = extractelement <4 x i32> %temp3, i64 06083 %temp5 = tail call i32 @llvm.aarch64.neon.sqsub.i32(i32 %C, i32 %temp4)6084 ret i32 %temp56085}6086 6087define i64 @sqdmlsl_d(i32 %A, i32 %B, i64 %C) nounwind sanitize_memory {6088; CHECK-LABEL: define i64 @sqdmlsl_d(6089; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]], i64 [[C:%.*]]) #[[ATTR0]] {6090; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_tls, align 86091; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 86092; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 86093; CHECK-NEXT: call void @llvm.donothing()6094; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP1]], 06095; CHECK-NEXT: [[_MSCMP1:%.*]] = icmp ne i32 [[TMP2]], 06096; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP]], [[_MSCMP1]]6097; CHECK-NEXT: br i1 [[_MSOR]], label %[[BB4:.*]], label %[[BB5:.*]], !prof [[PROF1]]6098; CHECK: [[BB4]]:6099; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR8]]6100; CHECK-NEXT: unreachable6101; CHECK: [[BB5]]:6102; CHECK-NEXT: [[TMP4:%.*]] = call i64 @llvm.aarch64.neon.sqdmulls.scalar(i32 [[A]], i32 [[B]])6103; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP3]], 06104; CHECK-NEXT: [[TMP5:%.*]] = call i64 @llvm.aarch64.neon.sqsub.i64(i64 [[C]], i64 [[TMP4]])6105; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 86106; CHECK-NEXT: ret i64 [[TMP5]]6107;6108 %temp4 = call i64 @llvm.aarch64.neon.sqdmulls.scalar(i32 %A, i32 %B)6109 %temp5 = call i64 @llvm.aarch64.neon.sqsub.i64(i64 %C, i64 %temp4)6110 ret i64 %temp56111}6112 6113define <16 x i8> @test_pmull_64(i64 %l, i64 %r) nounwind sanitize_memory {6114; CHECK-LABEL: define <16 x i8> @test_pmull_64(6115; CHECK-SAME: i64 [[L:%.*]], i64 [[R:%.*]]) #[[ATTR0]] {6116; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86117; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 86118; CHECK-NEXT: call void @llvm.donothing()6119; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP1]], [[TMP2]]6120; CHECK-NEXT: [[_MSPROP1:%.*]] = or i64 [[_MSPROP]], 06121; CHECK-NEXT: [[TMP3:%.*]] = zext i64 [[_MSPROP1]] to i1286122; CHECK-NEXT: [[TMP4:%.*]] = bitcast i128 [[TMP3]] to <16 x i8>6123; CHECK-NEXT: [[VAL:%.*]] = call <16 x i8> @llvm.aarch64.neon.pmull64(i64 [[L]], i64 [[R]])6124; CHECK-NEXT: store <16 x i8> [[TMP4]], ptr @__msan_retval_tls, align 86125; CHECK-NEXT: ret <16 x i8> [[VAL]]6126;6127 %val = call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %l, i64 %r)6128 ret <16 x i8> %val6129}6130 6131define <16 x i8> @test_pmull_high_64(<2 x i64> %l, <2 x i64> %r) nounwind sanitize_memory {6132; CHECK-LABEL: define <16 x i8> @test_pmull_high_64(6133; CHECK-SAME: <2 x i64> [[L:%.*]], <2 x i64> [[R:%.*]]) #[[ATTR0]] {6134; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 86135; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 86136; CHECK-NEXT: call void @llvm.donothing()6137; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <2 x i64> [[TMP1]], i32 16138; CHECK-NEXT: [[L_HI:%.*]] = extractelement <2 x i64> [[L]], i32 16139; CHECK-NEXT: [[_MSPROP1:%.*]] = extractelement <2 x i64> [[TMP2]], i32 16140; CHECK-NEXT: [[R_HI:%.*]] = extractelement <2 x i64> [[R]], i32 16141; CHECK-NEXT: [[_MSPROP2:%.*]] = or i64 [[_MSPROP]], [[_MSPROP1]]6142; CHECK-NEXT: [[_MSPROP3:%.*]] = or i64 [[_MSPROP2]], 06143; CHECK-NEXT: [[TMP3:%.*]] = zext i64 [[_MSPROP3]] to i1286144; CHECK-NEXT: [[TMP4:%.*]] = bitcast i128 [[TMP3]] to <16 x i8>6145; CHECK-NEXT: [[VAL:%.*]] = call <16 x i8> @llvm.aarch64.neon.pmull64(i64 [[L_HI]], i64 [[R_HI]])6146; CHECK-NEXT: store <16 x i8> [[TMP4]], ptr @__msan_retval_tls, align 86147; CHECK-NEXT: ret <16 x i8> [[VAL]]6148;6149 %l_hi = extractelement <2 x i64> %l, i32 16150 %r_hi = extractelement <2 x i64> %r, i32 16151 %val = call <16 x i8> @llvm.aarch64.neon.pmull64(i64 %l_hi, i64 %r_hi)6152 ret <16 x i8> %val6153}6154 6155declare <16 x i8> @llvm.aarch64.neon.pmull64(i64, i64)6156 6157define <1 x i64> @test_mul_v1i64(<1 x i64> %lhs, <1 x i64> %rhs) nounwind sanitize_memory {6158; CHECK-LABEL: define <1 x i64> @test_mul_v1i64(6159; CHECK-SAME: <1 x i64> [[LHS:%.*]], <1 x i64> [[RHS:%.*]]) #[[ATTR0]] {6160; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 86161; CHECK-NEXT: [[TMP2:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 86162; CHECK-NEXT: call void @llvm.donothing()6163; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP1]], [[TMP2]]6164; CHECK-NEXT: [[PROD:%.*]] = mul <1 x i64> [[LHS]], [[RHS]]6165; CHECK-NEXT: store <1 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 86166; CHECK-NEXT: ret <1 x i64> [[PROD]]6167;6168 %prod = mul <1 x i64> %lhs, %rhs6169 ret <1 x i64> %prod6170}6171;.6172; CHECK: [[PROF1]] = !{!"branch_weights", i32 1, i32 1048575}6173;.6174