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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42;3; RUN: opt < %s -passes=msan -S | FileCheck %s4;5; Forked from llvm/test/CodeGen/AArch64/arm64-vshift.ll6 7target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"8target triple = "aarch64--linux-android9001"9 10define <8 x i8> @sqshl8b(ptr %A, ptr %B) nounwind sanitize_memory {11; CHECK-LABEL: define <8 x i8> @sqshl8b(12; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] {13; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 814; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 815; CHECK-NEXT: call void @llvm.donothing()16; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 017; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1:![0-9]+]]18; CHECK: 3:19; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5:[0-9]+]]20; CHECK-NEXT: unreachable21; CHECK: 4:22; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[A]], align 823; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i6424; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 19351404648857625; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr26; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 827; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 028; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]29; CHECK: 8:30; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]31; CHECK-NEXT: unreachable32; CHECK: 9:33; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i8>, ptr [[B]], align 834; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i6435; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 19351404648857636; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr37; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP12]], align 838; CHECK-NEXT: [[TMP13:%.*]] = bitcast <8 x i8> [[_MSLD1]] to i6439; CHECK-NEXT: [[TMP14:%.*]] = icmp ne i64 [[TMP13]], 040; CHECK-NEXT: [[TMP15:%.*]] = sext i1 [[TMP14]] to i6441; CHECK-NEXT: [[TMP16:%.*]] = bitcast i64 [[TMP15]] to <8 x i8>42; CHECK-NEXT: [[TMP17:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8> [[_MSLD]], <8 x i8> [[TMP2]])43; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i8> [[TMP17]], [[TMP16]]44; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8> [[TMP1]], <8 x i8> [[TMP2]])45; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 846; CHECK-NEXT: ret <8 x i8> [[TMP3]]47;48 %tmp1 = load <8 x i8>, ptr %A49 %tmp2 = load <8 x i8>, ptr %B50 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)51 ret <8 x i8> %tmp352}53 54define <4 x i16> @sqshl4h(ptr %A, ptr %B) nounwind sanitize_memory {55; CHECK-LABEL: define <4 x i16> @sqshl4h(56; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {57; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 858; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 859; CHECK-NEXT: call void @llvm.donothing()60; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 061; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]62; CHECK: 3:63; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]64; CHECK-NEXT: unreachable65; CHECK: 4:66; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 867; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i6468; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 19351404648857669; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr70; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 871; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 072; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]73; CHECK: 8:74; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]75; CHECK-NEXT: unreachable76; CHECK: 9:77; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr [[B]], align 878; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i6479; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 19351404648857680; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr81; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 882; CHECK-NEXT: [[TMP13:%.*]] = bitcast <4 x i16> [[_MSLD1]] to i6483; CHECK-NEXT: [[TMP14:%.*]] = icmp ne i64 [[TMP13]], 084; CHECK-NEXT: [[TMP15:%.*]] = sext i1 [[TMP14]] to i6485; CHECK-NEXT: [[TMP16:%.*]] = bitcast i64 [[TMP15]] to <4 x i16>86; CHECK-NEXT: [[TMP17:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> [[_MSLD]], <4 x i16> [[TMP2]])87; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[TMP17]], [[TMP16]]88; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> [[TMP1]], <4 x i16> [[TMP2]])89; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 890; CHECK-NEXT: ret <4 x i16> [[TMP3]]91;92 %tmp1 = load <4 x i16>, ptr %A93 %tmp2 = load <4 x i16>, ptr %B94 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)95 ret <4 x i16> %tmp396}97 98define <2 x i32> @sqshl2s(ptr %A, ptr %B) nounwind sanitize_memory {99; CHECK-LABEL: define <2 x i32> @sqshl2s(100; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {101; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8102; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8103; CHECK-NEXT: call void @llvm.donothing()104; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0105; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]106; CHECK: 3:107; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]108; CHECK-NEXT: unreachable109; CHECK: 4:110; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 8111; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64112; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576113; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr114; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 8115; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0116; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]117; CHECK: 8:118; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]119; CHECK-NEXT: unreachable120; CHECK: 9:121; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr [[B]], align 8122; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64123; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576124; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr125; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 8126; CHECK-NEXT: [[TMP13:%.*]] = bitcast <2 x i32> [[_MSLD1]] to i64127; CHECK-NEXT: [[TMP14:%.*]] = icmp ne i64 [[TMP13]], 0128; CHECK-NEXT: [[TMP15:%.*]] = sext i1 [[TMP14]] to i64129; CHECK-NEXT: [[TMP16:%.*]] = bitcast i64 [[TMP15]] to <2 x i32>130; CHECK-NEXT: [[TMP17:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshl.v2i32(<2 x i32> [[_MSLD]], <2 x i32> [[TMP2]])131; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[TMP17]], [[TMP16]]132; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshl.v2i32(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]])133; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8134; CHECK-NEXT: ret <2 x i32> [[TMP3]]135;136 %tmp1 = load <2 x i32>, ptr %A137 %tmp2 = load <2 x i32>, ptr %B138 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)139 ret <2 x i32> %tmp3140}141 142define <1 x i64> @sqshl1d(ptr %A, ptr %B) nounwind sanitize_memory {143; CHECK-LABEL: define <1 x i64> @sqshl1d(144; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {145; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8146; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8147; CHECK-NEXT: call void @llvm.donothing()148; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0149; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]150; CHECK: 3:151; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]152; CHECK-NEXT: unreachable153; CHECK: 4:154; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr [[A]], align 8155; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64156; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576157; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr158; CHECK-NEXT: [[_MSLD:%.*]] = load <1 x i64>, ptr [[TMP7]], align 8159; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0160; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]161; CHECK: 8:162; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]163; CHECK-NEXT: unreachable164; CHECK: 9:165; CHECK-NEXT: [[TMP2:%.*]] = load <1 x i64>, ptr [[B]], align 8166; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64167; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576168; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr169; CHECK-NEXT: [[_MSLD1:%.*]] = load <1 x i64>, ptr [[TMP12]], align 8170; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[_MSLD1]] to i64171; CHECK-NEXT: [[TMP14:%.*]] = icmp ne i64 [[TMP13]], 0172; CHECK-NEXT: [[TMP15:%.*]] = sext i1 [[TMP14]] to i64173; CHECK-NEXT: [[TMP16:%.*]] = bitcast i64 [[TMP15]] to <1 x i64>174; CHECK-NEXT: [[TMP17:%.*]] = call <1 x i64> @llvm.aarch64.neon.sqshl.v1i64(<1 x i64> [[_MSLD]], <1 x i64> [[TMP2]])175; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP17]], [[TMP16]]176; CHECK-NEXT: [[TMP3:%.*]] = call <1 x i64> @llvm.aarch64.neon.sqshl.v1i64(<1 x i64> [[TMP1]], <1 x i64> [[TMP2]])177; CHECK-NEXT: store <1 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 8178; CHECK-NEXT: ret <1 x i64> [[TMP3]]179;180 %tmp1 = load <1 x i64>, ptr %A181 %tmp2 = load <1 x i64>, ptr %B182 %tmp3 = call <1 x i64> @llvm.aarch64.neon.sqshl.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)183 ret <1 x i64> %tmp3184}185 186define <1 x i64> @sqshl1d_constant(ptr %A) nounwind sanitize_memory {187; CHECK-LABEL: define <1 x i64> @sqshl1d_constant(188; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {189; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8190; CHECK-NEXT: call void @llvm.donothing()191; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0192; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]193; CHECK: 2:194; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]195; CHECK-NEXT: unreachable196; CHECK: 3:197; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr [[A]], align 8198; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i64199; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 193514046488576200; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr201; CHECK-NEXT: [[_MSLD:%.*]] = load <1 x i64>, ptr [[TMP6]], align 8202; CHECK-NEXT: [[TMP7:%.*]] = call <1 x i64> @llvm.aarch64.neon.sqshl.v1i64(<1 x i64> [[_MSLD]], <1 x i64> splat (i64 1))203; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP7]], zeroinitializer204; CHECK-NEXT: [[TMP3:%.*]] = call <1 x i64> @llvm.aarch64.neon.sqshl.v1i64(<1 x i64> [[TMP1]], <1 x i64> splat (i64 1))205; CHECK-NEXT: store <1 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 8206; CHECK-NEXT: ret <1 x i64> [[TMP3]]207;208 %tmp1 = load <1 x i64>, ptr %A209 %tmp3 = call <1 x i64> @llvm.aarch64.neon.sqshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 1>)210 ret <1 x i64> %tmp3211}212 213define i64 @sqshl_scalar(ptr %A, ptr %B) nounwind sanitize_memory {214; CHECK-LABEL: define i64 @sqshl_scalar(215; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {216; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8217; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8218; CHECK-NEXT: call void @llvm.donothing()219; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0220; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]221; CHECK: 3:222; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]223; CHECK-NEXT: unreachable224; CHECK: 4:225; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[A]], align 8226; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64227; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576228; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr229; CHECK-NEXT: [[_MSLD:%.*]] = load i64, ptr [[TMP7]], align 8230; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0231; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]232; CHECK: 8:233; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]234; CHECK-NEXT: unreachable235; CHECK: 9:236; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[B]], align 8237; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64238; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576239; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr240; CHECK-NEXT: [[_MSLD1:%.*]] = load i64, ptr [[TMP12]], align 8241; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[_MSLD1]], 0242; CHECK-NEXT: [[TMP14:%.*]] = sext i1 [[TMP13]] to i64243; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.aarch64.neon.sqshl.i64(i64 [[_MSLD]], i64 [[TMP2]])244; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP15]], [[TMP14]]245; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.sqshl.i64(i64 [[TMP1]], i64 [[TMP2]])246; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8247; CHECK-NEXT: ret i64 [[TMP3]]248;249 %tmp1 = load i64, ptr %A250 %tmp2 = load i64, ptr %B251 %tmp3 = call i64 @llvm.aarch64.neon.sqshl.i64(i64 %tmp1, i64 %tmp2)252 ret i64 %tmp3253}254 255define i64 @sqshl_scalar_constant(ptr %A) nounwind sanitize_memory {256; CHECK-LABEL: define i64 @sqshl_scalar_constant(257; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {258; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8259; CHECK-NEXT: call void @llvm.donothing()260; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0261; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]262; CHECK: 2:263; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]264; CHECK-NEXT: unreachable265; CHECK: 3:266; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[A]], align 8267; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i64268; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 193514046488576269; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr270; CHECK-NEXT: [[_MSLD:%.*]] = load i64, ptr [[TMP6]], align 8271; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.aarch64.neon.sqshl.i64(i64 [[_MSLD]], i64 1)272; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP7]], 0273; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.sqshl.i64(i64 [[TMP1]], i64 1)274; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8275; CHECK-NEXT: ret i64 [[TMP3]]276;277 %tmp1 = load i64, ptr %A278 %tmp3 = call i64 @llvm.aarch64.neon.sqshl.i64(i64 %tmp1, i64 1)279 ret i64 %tmp3280}281 282define <8 x i8> @uqshl8b(ptr %A, ptr %B) nounwind sanitize_memory {283; CHECK-LABEL: define <8 x i8> @uqshl8b(284; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {285; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8286; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8287; CHECK-NEXT: call void @llvm.donothing()288; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0289; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]290; CHECK: 3:291; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]292; CHECK-NEXT: unreachable293; CHECK: 4:294; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[A]], align 8295; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64296; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576297; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr298; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 8299; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0300; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]301; CHECK: 8:302; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]303; CHECK-NEXT: unreachable304; CHECK: 9:305; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i8>, ptr [[B]], align 8306; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64307; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576308; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr309; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP12]], align 8310; CHECK-NEXT: [[TMP13:%.*]] = bitcast <8 x i8> [[_MSLD1]] to i64311; CHECK-NEXT: [[TMP14:%.*]] = icmp ne i64 [[TMP13]], 0312; CHECK-NEXT: [[TMP15:%.*]] = sext i1 [[TMP14]] to i64313; CHECK-NEXT: [[TMP16:%.*]] = bitcast i64 [[TMP15]] to <8 x i8>314; CHECK-NEXT: [[TMP17:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> [[_MSLD]], <8 x i8> [[TMP2]])315; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i8> [[TMP17]], [[TMP16]]316; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> [[TMP1]], <8 x i8> [[TMP2]])317; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8318; CHECK-NEXT: ret <8 x i8> [[TMP3]]319;320 %tmp1 = load <8 x i8>, ptr %A321 %tmp2 = load <8 x i8>, ptr %B322 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)323 ret <8 x i8> %tmp3324}325 326define <4 x i16> @uqshl4h(ptr %A, ptr %B) nounwind sanitize_memory {327; CHECK-LABEL: define <4 x i16> @uqshl4h(328; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {329; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8330; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8331; CHECK-NEXT: call void @llvm.donothing()332; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0333; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]334; CHECK: 3:335; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]336; CHECK-NEXT: unreachable337; CHECK: 4:338; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 8339; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64340; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576341; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr342; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 8343; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0344; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]345; CHECK: 8:346; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]347; CHECK-NEXT: unreachable348; CHECK: 9:349; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr [[B]], align 8350; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64351; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576352; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr353; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 8354; CHECK-NEXT: [[TMP13:%.*]] = bitcast <4 x i16> [[_MSLD1]] to i64355; CHECK-NEXT: [[TMP14:%.*]] = icmp ne i64 [[TMP13]], 0356; CHECK-NEXT: [[TMP15:%.*]] = sext i1 [[TMP14]] to i64357; CHECK-NEXT: [[TMP16:%.*]] = bitcast i64 [[TMP15]] to <4 x i16>358; CHECK-NEXT: [[TMP17:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16> [[_MSLD]], <4 x i16> [[TMP2]])359; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[TMP17]], [[TMP16]]360; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16> [[TMP1]], <4 x i16> [[TMP2]])361; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8362; CHECK-NEXT: ret <4 x i16> [[TMP3]]363;364 %tmp1 = load <4 x i16>, ptr %A365 %tmp2 = load <4 x i16>, ptr %B366 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)367 ret <4 x i16> %tmp3368}369 370define <2 x i32> @uqshl2s(ptr %A, ptr %B) nounwind sanitize_memory {371; CHECK-LABEL: define <2 x i32> @uqshl2s(372; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {373; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8374; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8375; CHECK-NEXT: call void @llvm.donothing()376; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0377; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]378; CHECK: 3:379; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]380; CHECK-NEXT: unreachable381; CHECK: 4:382; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 8383; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64384; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576385; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr386; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 8387; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0388; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]389; CHECK: 8:390; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]391; CHECK-NEXT: unreachable392; CHECK: 9:393; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr [[B]], align 8394; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64395; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576396; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr397; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 8398; CHECK-NEXT: [[TMP13:%.*]] = bitcast <2 x i32> [[_MSLD1]] to i64399; CHECK-NEXT: [[TMP14:%.*]] = icmp ne i64 [[TMP13]], 0400; CHECK-NEXT: [[TMP15:%.*]] = sext i1 [[TMP14]] to i64401; CHECK-NEXT: [[TMP16:%.*]] = bitcast i64 [[TMP15]] to <2 x i32>402; CHECK-NEXT: [[TMP17:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqshl.v2i32(<2 x i32> [[_MSLD]], <2 x i32> [[TMP2]])403; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[TMP17]], [[TMP16]]404; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqshl.v2i32(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]])405; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8406; CHECK-NEXT: ret <2 x i32> [[TMP3]]407;408 %tmp1 = load <2 x i32>, ptr %A409 %tmp2 = load <2 x i32>, ptr %B410 %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)411 ret <2 x i32> %tmp3412}413 414define <16 x i8> @sqshl16b(ptr %A, ptr %B) nounwind sanitize_memory {415; CHECK-LABEL: define <16 x i8> @sqshl16b(416; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {417; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8418; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8419; CHECK-NEXT: call void @llvm.donothing()420; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0421; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]422; CHECK: 3:423; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]424; CHECK-NEXT: unreachable425; CHECK: 4:426; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[A]], align 16427; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64428; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576429; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr430; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP7]], align 16431; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0432; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]433; CHECK: 8:434; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]435; CHECK-NEXT: unreachable436; CHECK: 9:437; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr [[B]], align 16438; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64439; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576440; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr441; CHECK-NEXT: [[_MSLD1:%.*]] = load <16 x i8>, ptr [[TMP12]], align 16442; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[_MSLD1]] to i128443; CHECK-NEXT: [[TMP14:%.*]] = trunc i128 [[TMP13]] to i64444; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[TMP14]], 0445; CHECK-NEXT: [[TMP16:%.*]] = sext i1 [[TMP15]] to i128446; CHECK-NEXT: [[TMP17:%.*]] = bitcast i128 [[TMP16]] to <16 x i8>447; CHECK-NEXT: [[TMP18:%.*]] = call <16 x i8> @llvm.aarch64.neon.sqshl.v16i8(<16 x i8> [[_MSLD]], <16 x i8> [[TMP2]])448; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP18]], [[TMP17]]449; CHECK-NEXT: [[TMP3:%.*]] = call <16 x i8> @llvm.aarch64.neon.sqshl.v16i8(<16 x i8> [[TMP1]], <16 x i8> [[TMP2]])450; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8451; CHECK-NEXT: ret <16 x i8> [[TMP3]]452;453 %tmp1 = load <16 x i8>, ptr %A454 %tmp2 = load <16 x i8>, ptr %B455 %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)456 ret <16 x i8> %tmp3457}458 459define <8 x i16> @sqshl8h(ptr %A, ptr %B) nounwind sanitize_memory {460; CHECK-LABEL: define <8 x i16> @sqshl8h(461; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {462; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8463; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8464; CHECK-NEXT: call void @llvm.donothing()465; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0466; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]467; CHECK: 3:468; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]469; CHECK-NEXT: unreachable470; CHECK: 4:471; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 16472; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64473; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576474; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr475; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 16476; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0477; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]478; CHECK: 8:479; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]480; CHECK-NEXT: unreachable481; CHECK: 9:482; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr [[B]], align 16483; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64484; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576485; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr486; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 16487; CHECK-NEXT: [[TMP13:%.*]] = bitcast <8 x i16> [[_MSLD1]] to i128488; CHECK-NEXT: [[TMP14:%.*]] = trunc i128 [[TMP13]] to i64489; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[TMP14]], 0490; CHECK-NEXT: [[TMP16:%.*]] = sext i1 [[TMP15]] to i128491; CHECK-NEXT: [[TMP17:%.*]] = bitcast i128 [[TMP16]] to <8 x i16>492; CHECK-NEXT: [[TMP18:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqshl.v8i16(<8 x i16> [[_MSLD]], <8 x i16> [[TMP2]])493; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP18]], [[TMP17]]494; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqshl.v8i16(<8 x i16> [[TMP1]], <8 x i16> [[TMP2]])495; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8496; CHECK-NEXT: ret <8 x i16> [[TMP3]]497;498 %tmp1 = load <8 x i16>, ptr %A499 %tmp2 = load <8 x i16>, ptr %B500 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)501 ret <8 x i16> %tmp3502}503 504define <4 x i32> @sqshl4s(ptr %A, ptr %B) nounwind sanitize_memory {505; CHECK-LABEL: define <4 x i32> @sqshl4s(506; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {507; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8508; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8509; CHECK-NEXT: call void @llvm.donothing()510; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0511; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]512; CHECK: 3:513; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]514; CHECK-NEXT: unreachable515; CHECK: 4:516; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 16517; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64518; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576519; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr520; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 16521; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0522; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]523; CHECK: 8:524; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]525; CHECK-NEXT: unreachable526; CHECK: 9:527; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr [[B]], align 16528; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64529; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576530; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr531; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 16532; CHECK-NEXT: [[TMP13:%.*]] = bitcast <4 x i32> [[_MSLD1]] to i128533; CHECK-NEXT: [[TMP14:%.*]] = trunc i128 [[TMP13]] to i64534; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[TMP14]], 0535; CHECK-NEXT: [[TMP16:%.*]] = sext i1 [[TMP15]] to i128536; CHECK-NEXT: [[TMP17:%.*]] = bitcast i128 [[TMP16]] to <4 x i32>537; CHECK-NEXT: [[TMP18:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqshl.v4i32(<4 x i32> [[_MSLD]], <4 x i32> [[TMP2]])538; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP18]], [[TMP17]]539; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqshl.v4i32(<4 x i32> [[TMP1]], <4 x i32> [[TMP2]])540; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8541; CHECK-NEXT: ret <4 x i32> [[TMP3]]542;543 %tmp1 = load <4 x i32>, ptr %A544 %tmp2 = load <4 x i32>, ptr %B545 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)546 ret <4 x i32> %tmp3547}548 549define <2 x i64> @sqshl2d(ptr %A, ptr %B) nounwind sanitize_memory {550; CHECK-LABEL: define <2 x i64> @sqshl2d(551; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {552; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8553; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8554; CHECK-NEXT: call void @llvm.donothing()555; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0556; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]557; CHECK: 3:558; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]559; CHECK-NEXT: unreachable560; CHECK: 4:561; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 16562; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64563; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576564; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr565; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 16566; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0567; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]568; CHECK: 8:569; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]570; CHECK-NEXT: unreachable571; CHECK: 9:572; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr [[B]], align 16573; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64574; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576575; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr576; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 16577; CHECK-NEXT: [[TMP13:%.*]] = bitcast <2 x i64> [[_MSLD1]] to i128578; CHECK-NEXT: [[TMP14:%.*]] = trunc i128 [[TMP13]] to i64579; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[TMP14]], 0580; CHECK-NEXT: [[TMP16:%.*]] = sext i1 [[TMP15]] to i128581; CHECK-NEXT: [[TMP17:%.*]] = bitcast i128 [[TMP16]] to <2 x i64>582; CHECK-NEXT: [[TMP18:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqshl.v2i64(<2 x i64> [[_MSLD]], <2 x i64> [[TMP2]])583; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP18]], [[TMP17]]584; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqshl.v2i64(<2 x i64> [[TMP1]], <2 x i64> [[TMP2]])585; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 8586; CHECK-NEXT: ret <2 x i64> [[TMP3]]587;588 %tmp1 = load <2 x i64>, ptr %A589 %tmp2 = load <2 x i64>, ptr %B590 %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)591 ret <2 x i64> %tmp3592}593 594define <16 x i8> @uqshl16b(ptr %A, ptr %B) nounwind sanitize_memory {595; CHECK-LABEL: define <16 x i8> @uqshl16b(596; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {597; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8598; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8599; CHECK-NEXT: call void @llvm.donothing()600; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0601; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]602; CHECK: 3:603; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]604; CHECK-NEXT: unreachable605; CHECK: 4:606; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[A]], align 16607; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64608; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576609; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr610; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP7]], align 16611; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0612; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]613; CHECK: 8:614; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]615; CHECK-NEXT: unreachable616; CHECK: 9:617; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr [[B]], align 16618; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64619; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576620; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr621; CHECK-NEXT: [[_MSLD1:%.*]] = load <16 x i8>, ptr [[TMP12]], align 16622; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[_MSLD1]] to i128623; CHECK-NEXT: [[TMP14:%.*]] = trunc i128 [[TMP13]] to i64624; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[TMP14]], 0625; CHECK-NEXT: [[TMP16:%.*]] = sext i1 [[TMP15]] to i128626; CHECK-NEXT: [[TMP17:%.*]] = bitcast i128 [[TMP16]] to <16 x i8>627; CHECK-NEXT: [[TMP18:%.*]] = call <16 x i8> @llvm.aarch64.neon.uqshl.v16i8(<16 x i8> [[_MSLD]], <16 x i8> [[TMP2]])628; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP18]], [[TMP17]]629; CHECK-NEXT: [[TMP3:%.*]] = call <16 x i8> @llvm.aarch64.neon.uqshl.v16i8(<16 x i8> [[TMP1]], <16 x i8> [[TMP2]])630; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8631; CHECK-NEXT: ret <16 x i8> [[TMP3]]632;633 %tmp1 = load <16 x i8>, ptr %A634 %tmp2 = load <16 x i8>, ptr %B635 %tmp3 = call <16 x i8> @llvm.aarch64.neon.uqshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)636 ret <16 x i8> %tmp3637}638 639define <8 x i16> @uqshl8h(ptr %A, ptr %B) nounwind sanitize_memory {640; CHECK-LABEL: define <8 x i16> @uqshl8h(641; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {642; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8643; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8644; CHECK-NEXT: call void @llvm.donothing()645; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0646; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]647; CHECK: 3:648; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]649; CHECK-NEXT: unreachable650; CHECK: 4:651; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 16652; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64653; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576654; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr655; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 16656; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0657; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]658; CHECK: 8:659; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]660; CHECK-NEXT: unreachable661; CHECK: 9:662; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr [[B]], align 16663; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64664; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576665; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr666; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 16667; CHECK-NEXT: [[TMP13:%.*]] = bitcast <8 x i16> [[_MSLD1]] to i128668; CHECK-NEXT: [[TMP14:%.*]] = trunc i128 [[TMP13]] to i64669; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[TMP14]], 0670; CHECK-NEXT: [[TMP16:%.*]] = sext i1 [[TMP15]] to i128671; CHECK-NEXT: [[TMP17:%.*]] = bitcast i128 [[TMP16]] to <8 x i16>672; CHECK-NEXT: [[TMP18:%.*]] = call <8 x i16> @llvm.aarch64.neon.uqshl.v8i16(<8 x i16> [[_MSLD]], <8 x i16> [[TMP2]])673; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP18]], [[TMP17]]674; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i16> @llvm.aarch64.neon.uqshl.v8i16(<8 x i16> [[TMP1]], <8 x i16> [[TMP2]])675; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 8676; CHECK-NEXT: ret <8 x i16> [[TMP3]]677;678 %tmp1 = load <8 x i16>, ptr %A679 %tmp2 = load <8 x i16>, ptr %B680 %tmp3 = call <8 x i16> @llvm.aarch64.neon.uqshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)681 ret <8 x i16> %tmp3682}683 684define <4 x i32> @uqshl4s(ptr %A, ptr %B) nounwind sanitize_memory {685; CHECK-LABEL: define <4 x i32> @uqshl4s(686; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {687; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8688; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8689; CHECK-NEXT: call void @llvm.donothing()690; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0691; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]692; CHECK: 3:693; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]694; CHECK-NEXT: unreachable695; CHECK: 4:696; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 16697; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64698; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576699; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr700; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 16701; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0702; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]703; CHECK: 8:704; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]705; CHECK-NEXT: unreachable706; CHECK: 9:707; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr [[B]], align 16708; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64709; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576710; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr711; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 16712; CHECK-NEXT: [[TMP13:%.*]] = bitcast <4 x i32> [[_MSLD1]] to i128713; CHECK-NEXT: [[TMP14:%.*]] = trunc i128 [[TMP13]] to i64714; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[TMP14]], 0715; CHECK-NEXT: [[TMP16:%.*]] = sext i1 [[TMP15]] to i128716; CHECK-NEXT: [[TMP17:%.*]] = bitcast i128 [[TMP16]] to <4 x i32>717; CHECK-NEXT: [[TMP18:%.*]] = call <4 x i32> @llvm.aarch64.neon.uqshl.v4i32(<4 x i32> [[_MSLD]], <4 x i32> [[TMP2]])718; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP18]], [[TMP17]]719; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.uqshl.v4i32(<4 x i32> [[TMP1]], <4 x i32> [[TMP2]])720; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8721; CHECK-NEXT: ret <4 x i32> [[TMP3]]722;723 %tmp1 = load <4 x i32>, ptr %A724 %tmp2 = load <4 x i32>, ptr %B725 %tmp3 = call <4 x i32> @llvm.aarch64.neon.uqshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)726 ret <4 x i32> %tmp3727}728 729define <2 x i64> @uqshl2d(ptr %A, ptr %B) nounwind sanitize_memory {730; CHECK-LABEL: define <2 x i64> @uqshl2d(731; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {732; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8733; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8734; CHECK-NEXT: call void @llvm.donothing()735; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0736; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]737; CHECK: 3:738; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]739; CHECK-NEXT: unreachable740; CHECK: 4:741; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 16742; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64743; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576744; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr745; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 16746; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0747; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]748; CHECK: 8:749; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]750; CHECK-NEXT: unreachable751; CHECK: 9:752; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr [[B]], align 16753; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64754; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576755; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr756; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 16757; CHECK-NEXT: [[TMP13:%.*]] = bitcast <2 x i64> [[_MSLD1]] to i128758; CHECK-NEXT: [[TMP14:%.*]] = trunc i128 [[TMP13]] to i64759; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[TMP14]], 0760; CHECK-NEXT: [[TMP16:%.*]] = sext i1 [[TMP15]] to i128761; CHECK-NEXT: [[TMP17:%.*]] = bitcast i128 [[TMP16]] to <2 x i64>762; CHECK-NEXT: [[TMP18:%.*]] = call <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64> [[_MSLD]], <2 x i64> [[TMP2]])763; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP18]], [[TMP17]]764; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64> [[TMP1]], <2 x i64> [[TMP2]])765; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 8766; CHECK-NEXT: ret <2 x i64> [[TMP3]]767;768 %tmp1 = load <2 x i64>, ptr %A769 %tmp2 = load <2 x i64>, ptr %B770 %tmp3 = call <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)771 ret <2 x i64> %tmp3772}773 774define <1 x i64> @uqshl1d(ptr %A, ptr %B) nounwind sanitize_memory {775; CHECK-LABEL: define <1 x i64> @uqshl1d(776; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {777; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8778; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8779; CHECK-NEXT: call void @llvm.donothing()780; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0781; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]782; CHECK: 3:783; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]784; CHECK-NEXT: unreachable785; CHECK: 4:786; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr [[A]], align 8787; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64788; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576789; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr790; CHECK-NEXT: [[_MSLD:%.*]] = load <1 x i64>, ptr [[TMP7]], align 8791; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0792; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]793; CHECK: 8:794; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]795; CHECK-NEXT: unreachable796; CHECK: 9:797; CHECK-NEXT: [[TMP2:%.*]] = load <1 x i64>, ptr [[B]], align 8798; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64799; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576800; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr801; CHECK-NEXT: [[_MSLD1:%.*]] = load <1 x i64>, ptr [[TMP12]], align 8802; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[_MSLD1]] to i64803; CHECK-NEXT: [[TMP14:%.*]] = icmp ne i64 [[TMP13]], 0804; CHECK-NEXT: [[TMP15:%.*]] = sext i1 [[TMP14]] to i64805; CHECK-NEXT: [[TMP16:%.*]] = bitcast i64 [[TMP15]] to <1 x i64>806; CHECK-NEXT: [[TMP17:%.*]] = call <1 x i64> @llvm.aarch64.neon.uqshl.v1i64(<1 x i64> [[_MSLD]], <1 x i64> [[TMP2]])807; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP17]], [[TMP16]]808; CHECK-NEXT: [[TMP3:%.*]] = call <1 x i64> @llvm.aarch64.neon.uqshl.v1i64(<1 x i64> [[TMP1]], <1 x i64> [[TMP2]])809; CHECK-NEXT: store <1 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 8810; CHECK-NEXT: ret <1 x i64> [[TMP3]]811;812 %tmp1 = load <1 x i64>, ptr %A813 %tmp2 = load <1 x i64>, ptr %B814 %tmp3 = call <1 x i64> @llvm.aarch64.neon.uqshl.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)815 ret <1 x i64> %tmp3816}817 818define <1 x i64> @uqshl1d_constant(ptr %A) nounwind sanitize_memory {819; CHECK-LABEL: define <1 x i64> @uqshl1d_constant(820; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {821; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8822; CHECK-NEXT: call void @llvm.donothing()823; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0824; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]825; CHECK: 2:826; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]827; CHECK-NEXT: unreachable828; CHECK: 3:829; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr [[A]], align 8830; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i64831; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 193514046488576832; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr833; CHECK-NEXT: [[_MSLD:%.*]] = load <1 x i64>, ptr [[TMP6]], align 8834; CHECK-NEXT: [[TMP7:%.*]] = call <1 x i64> @llvm.aarch64.neon.uqshl.v1i64(<1 x i64> [[_MSLD]], <1 x i64> splat (i64 1))835; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP7]], zeroinitializer836; CHECK-NEXT: [[TMP3:%.*]] = call <1 x i64> @llvm.aarch64.neon.uqshl.v1i64(<1 x i64> [[TMP1]], <1 x i64> splat (i64 1))837; CHECK-NEXT: store <1 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 8838; CHECK-NEXT: ret <1 x i64> [[TMP3]]839;840 %tmp1 = load <1 x i64>, ptr %A841 %tmp3 = call <1 x i64> @llvm.aarch64.neon.uqshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 1>)842 ret <1 x i64> %tmp3843}844 845define i64 @uqshl_scalar(ptr %A, ptr %B) nounwind sanitize_memory {846; CHECK-LABEL: define i64 @uqshl_scalar(847; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {848; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8849; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8850; CHECK-NEXT: call void @llvm.donothing()851; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0852; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]853; CHECK: 3:854; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]855; CHECK-NEXT: unreachable856; CHECK: 4:857; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[A]], align 8858; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64859; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576860; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr861; CHECK-NEXT: [[_MSLD:%.*]] = load i64, ptr [[TMP7]], align 8862; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0863; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]864; CHECK: 8:865; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]866; CHECK-NEXT: unreachable867; CHECK: 9:868; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[B]], align 8869; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64870; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576871; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr872; CHECK-NEXT: [[_MSLD1:%.*]] = load i64, ptr [[TMP12]], align 8873; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[_MSLD1]], 0874; CHECK-NEXT: [[TMP14:%.*]] = sext i1 [[TMP13]] to i64875; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.aarch64.neon.uqshl.i64(i64 [[_MSLD]], i64 [[TMP2]])876; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP15]], [[TMP14]]877; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.uqshl.i64(i64 [[TMP1]], i64 [[TMP2]])878; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8879; CHECK-NEXT: ret i64 [[TMP3]]880;881 %tmp1 = load i64, ptr %A882 %tmp2 = load i64, ptr %B883 %tmp3 = call i64 @llvm.aarch64.neon.uqshl.i64(i64 %tmp1, i64 %tmp2)884 ret i64 %tmp3885}886 887define i64 @uqshl_scalar_constant(ptr %A) nounwind sanitize_memory {888; CHECK-LABEL: define i64 @uqshl_scalar_constant(889; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {890; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8891; CHECK-NEXT: call void @llvm.donothing()892; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0893; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]894; CHECK: 2:895; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]896; CHECK-NEXT: unreachable897; CHECK: 3:898; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[A]], align 8899; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i64900; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 193514046488576901; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr902; CHECK-NEXT: [[_MSLD:%.*]] = load i64, ptr [[TMP6]], align 8903; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.aarch64.neon.uqshl.i64(i64 [[_MSLD]], i64 1)904; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP7]], 0905; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.uqshl.i64(i64 [[TMP1]], i64 1)906; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 8907; CHECK-NEXT: ret i64 [[TMP3]]908;909 %tmp1 = load i64, ptr %A910 %tmp3 = call i64 @llvm.aarch64.neon.uqshl.i64(i64 %tmp1, i64 1)911 ret i64 %tmp3912}913 914declare <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8>, <8 x i8>) nounwind readnone915declare <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16>, <4 x i16>) nounwind readnone916declare <2 x i32> @llvm.aarch64.neon.sqshl.v2i32(<2 x i32>, <2 x i32>) nounwind readnone917declare <1 x i64> @llvm.aarch64.neon.sqshl.v1i64(<1 x i64>, <1 x i64>) nounwind readnone918declare i64 @llvm.aarch64.neon.sqshl.i64(i64, i64) nounwind readnone919 920 921declare <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8>, <8 x i8>) nounwind readnone922declare <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16>, <4 x i16>) nounwind readnone923declare <2 x i32> @llvm.aarch64.neon.uqshl.v2i32(<2 x i32>, <2 x i32>) nounwind readnone924declare <1 x i64> @llvm.aarch64.neon.uqshl.v1i64(<1 x i64>, <1 x i64>) nounwind readnone925declare i64 @llvm.aarch64.neon.uqshl.i64(i64, i64) nounwind readnone926 927declare <16 x i8> @llvm.aarch64.neon.sqshl.v16i8(<16 x i8>, <16 x i8>) nounwind readnone928declare <8 x i16> @llvm.aarch64.neon.sqshl.v8i16(<8 x i16>, <8 x i16>) nounwind readnone929declare <4 x i32> @llvm.aarch64.neon.sqshl.v4i32(<4 x i32>, <4 x i32>) nounwind readnone930declare <2 x i64> @llvm.aarch64.neon.sqshl.v2i64(<2 x i64>, <2 x i64>) nounwind readnone931 932declare <16 x i8> @llvm.aarch64.neon.uqshl.v16i8(<16 x i8>, <16 x i8>) nounwind readnone933declare <8 x i16> @llvm.aarch64.neon.uqshl.v8i16(<8 x i16>, <8 x i16>) nounwind readnone934declare <4 x i32> @llvm.aarch64.neon.uqshl.v4i32(<4 x i32>, <4 x i32>) nounwind readnone935declare <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64>, <2 x i64>) nounwind readnone936 937define <8 x i8> @srshl8b(ptr %A, ptr %B) nounwind sanitize_memory {938; CHECK-LABEL: define <8 x i8> @srshl8b(939; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {940; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8941; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8942; CHECK-NEXT: call void @llvm.donothing()943; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0944; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]945; CHECK: 3:946; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]947; CHECK-NEXT: unreachable948; CHECK: 4:949; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[A]], align 8950; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64951; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576952; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr953; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 8954; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0955; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]956; CHECK: 8:957; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]958; CHECK-NEXT: unreachable959; CHECK: 9:960; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i8>, ptr [[B]], align 8961; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64962; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 193514046488576963; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr964; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP12]], align 8965; CHECK-NEXT: [[TMP13:%.*]] = bitcast <8 x i8> [[_MSLD1]] to i64966; CHECK-NEXT: [[TMP14:%.*]] = icmp ne i64 [[TMP13]], 0967; CHECK-NEXT: [[TMP15:%.*]] = sext i1 [[TMP14]] to i64968; CHECK-NEXT: [[TMP16:%.*]] = bitcast i64 [[TMP15]] to <8 x i8>969; CHECK-NEXT: [[TMP17:%.*]] = call <8 x i8> @llvm.aarch64.neon.srshl.v8i8(<8 x i8> [[_MSLD]], <8 x i8> [[TMP2]])970; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i8> [[TMP17]], [[TMP16]]971; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.srshl.v8i8(<8 x i8> [[TMP1]], <8 x i8> [[TMP2]])972; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 8973; CHECK-NEXT: ret <8 x i8> [[TMP3]]974;975 %tmp1 = load <8 x i8>, ptr %A976 %tmp2 = load <8 x i8>, ptr %B977 %tmp3 = call <8 x i8> @llvm.aarch64.neon.srshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)978 ret <8 x i8> %tmp3979}980 981define <4 x i16> @srshl4h(ptr %A, ptr %B) nounwind sanitize_memory {982; CHECK-LABEL: define <4 x i16> @srshl4h(983; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {984; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8985; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 8986; CHECK-NEXT: call void @llvm.donothing()987; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 0988; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]989; CHECK: 3:990; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]991; CHECK-NEXT: unreachable992; CHECK: 4:993; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 8994; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i64995; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 193514046488576996; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr997; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 8998; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 0999; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1000; CHECK: 8:1001; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1002; CHECK-NEXT: unreachable1003; CHECK: 9:1004; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr [[B]], align 81005; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641006; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761007; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1008; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 81009; CHECK-NEXT: [[TMP13:%.*]] = bitcast <4 x i16> [[_MSLD1]] to i641010; CHECK-NEXT: [[TMP14:%.*]] = icmp ne i64 [[TMP13]], 01011; CHECK-NEXT: [[TMP15:%.*]] = sext i1 [[TMP14]] to i641012; CHECK-NEXT: [[TMP16:%.*]] = bitcast i64 [[TMP15]] to <4 x i16>1013; CHECK-NEXT: [[TMP17:%.*]] = call <4 x i16> @llvm.aarch64.neon.srshl.v4i16(<4 x i16> [[_MSLD]], <4 x i16> [[TMP2]])1014; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[TMP17]], [[TMP16]]1015; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.srshl.v4i16(<4 x i16> [[TMP1]], <4 x i16> [[TMP2]])1016; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 81017; CHECK-NEXT: ret <4 x i16> [[TMP3]]1018;1019 %tmp1 = load <4 x i16>, ptr %A1020 %tmp2 = load <4 x i16>, ptr %B1021 %tmp3 = call <4 x i16> @llvm.aarch64.neon.srshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)1022 ret <4 x i16> %tmp31023}1024 1025define <2 x i32> @srshl2s(ptr %A, ptr %B) nounwind sanitize_memory {1026; CHECK-LABEL: define <2 x i32> @srshl2s(1027; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1028; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81029; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81030; CHECK-NEXT: call void @llvm.donothing()1031; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01032; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1033; CHECK: 3:1034; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1035; CHECK-NEXT: unreachable1036; CHECK: 4:1037; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 81038; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641039; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761040; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1041; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 81042; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01043; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1044; CHECK: 8:1045; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1046; CHECK-NEXT: unreachable1047; CHECK: 9:1048; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr [[B]], align 81049; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641050; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761051; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1052; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 81053; CHECK-NEXT: [[TMP13:%.*]] = bitcast <2 x i32> [[_MSLD1]] to i641054; CHECK-NEXT: [[TMP14:%.*]] = icmp ne i64 [[TMP13]], 01055; CHECK-NEXT: [[TMP15:%.*]] = sext i1 [[TMP14]] to i641056; CHECK-NEXT: [[TMP16:%.*]] = bitcast i64 [[TMP15]] to <2 x i32>1057; CHECK-NEXT: [[TMP17:%.*]] = call <2 x i32> @llvm.aarch64.neon.srshl.v2i32(<2 x i32> [[_MSLD]], <2 x i32> [[TMP2]])1058; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[TMP17]], [[TMP16]]1059; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.srshl.v2i32(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]])1060; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 81061; CHECK-NEXT: ret <2 x i32> [[TMP3]]1062;1063 %tmp1 = load <2 x i32>, ptr %A1064 %tmp2 = load <2 x i32>, ptr %B1065 %tmp3 = call <2 x i32> @llvm.aarch64.neon.srshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)1066 ret <2 x i32> %tmp31067}1068 1069define <1 x i64> @srshl1d(ptr %A, ptr %B) nounwind sanitize_memory {1070; CHECK-LABEL: define <1 x i64> @srshl1d(1071; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1072; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81073; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81074; CHECK-NEXT: call void @llvm.donothing()1075; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01076; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1077; CHECK: 3:1078; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1079; CHECK-NEXT: unreachable1080; CHECK: 4:1081; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr [[A]], align 81082; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641083; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761084; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1085; CHECK-NEXT: [[_MSLD:%.*]] = load <1 x i64>, ptr [[TMP7]], align 81086; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01087; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1088; CHECK: 8:1089; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1090; CHECK-NEXT: unreachable1091; CHECK: 9:1092; CHECK-NEXT: [[TMP2:%.*]] = load <1 x i64>, ptr [[B]], align 81093; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641094; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761095; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1096; CHECK-NEXT: [[_MSLD1:%.*]] = load <1 x i64>, ptr [[TMP12]], align 81097; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[_MSLD1]] to i641098; CHECK-NEXT: [[TMP14:%.*]] = icmp ne i64 [[TMP13]], 01099; CHECK-NEXT: [[TMP15:%.*]] = sext i1 [[TMP14]] to i641100; CHECK-NEXT: [[TMP16:%.*]] = bitcast i64 [[TMP15]] to <1 x i64>1101; CHECK-NEXT: [[TMP17:%.*]] = call <1 x i64> @llvm.aarch64.neon.srshl.v1i64(<1 x i64> [[_MSLD]], <1 x i64> [[TMP2]])1102; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP17]], [[TMP16]]1103; CHECK-NEXT: [[TMP3:%.*]] = call <1 x i64> @llvm.aarch64.neon.srshl.v1i64(<1 x i64> [[TMP1]], <1 x i64> [[TMP2]])1104; CHECK-NEXT: store <1 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 81105; CHECK-NEXT: ret <1 x i64> [[TMP3]]1106;1107 %tmp1 = load <1 x i64>, ptr %A1108 %tmp2 = load <1 x i64>, ptr %B1109 %tmp3 = call <1 x i64> @llvm.aarch64.neon.srshl.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)1110 ret <1 x i64> %tmp31111}1112 1113define <1 x i64> @srshl1d_constant(ptr %A) nounwind sanitize_memory {1114; CHECK-LABEL: define <1 x i64> @srshl1d_constant(1115; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {1116; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81117; CHECK-NEXT: call void @llvm.donothing()1118; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01119; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]1120; CHECK: 2:1121; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1122; CHECK-NEXT: unreachable1123; CHECK: 3:1124; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr [[A]], align 81125; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i641126; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885761127; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr1128; CHECK-NEXT: [[_MSLD:%.*]] = load <1 x i64>, ptr [[TMP6]], align 81129; CHECK-NEXT: [[TMP7:%.*]] = call <1 x i64> @llvm.aarch64.neon.srshl.v1i64(<1 x i64> [[_MSLD]], <1 x i64> splat (i64 1))1130; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP7]], zeroinitializer1131; CHECK-NEXT: [[TMP3:%.*]] = call <1 x i64> @llvm.aarch64.neon.srshl.v1i64(<1 x i64> [[TMP1]], <1 x i64> splat (i64 1))1132; CHECK-NEXT: store <1 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 81133; CHECK-NEXT: ret <1 x i64> [[TMP3]]1134;1135 %tmp1 = load <1 x i64>, ptr %A1136 %tmp3 = call <1 x i64> @llvm.aarch64.neon.srshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 1>)1137 ret <1 x i64> %tmp31138}1139 1140define i64 @srshl_scalar(ptr %A, ptr %B) nounwind sanitize_memory {1141; CHECK-LABEL: define i64 @srshl_scalar(1142; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1143; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81144; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81145; CHECK-NEXT: call void @llvm.donothing()1146; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01147; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1148; CHECK: 3:1149; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1150; CHECK-NEXT: unreachable1151; CHECK: 4:1152; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[A]], align 81153; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641154; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761155; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1156; CHECK-NEXT: [[_MSLD:%.*]] = load i64, ptr [[TMP7]], align 81157; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01158; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1159; CHECK: 8:1160; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1161; CHECK-NEXT: unreachable1162; CHECK: 9:1163; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[B]], align 81164; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641165; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761166; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1167; CHECK-NEXT: [[_MSLD1:%.*]] = load i64, ptr [[TMP12]], align 81168; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[_MSLD1]], 01169; CHECK-NEXT: [[TMP14:%.*]] = sext i1 [[TMP13]] to i641170; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.aarch64.neon.srshl.i64(i64 [[_MSLD]], i64 [[TMP2]])1171; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP15]], [[TMP14]]1172; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.srshl.i64(i64 [[TMP1]], i64 [[TMP2]])1173; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 81174; CHECK-NEXT: ret i64 [[TMP3]]1175;1176 %tmp1 = load i64, ptr %A1177 %tmp2 = load i64, ptr %B1178 %tmp3 = call i64 @llvm.aarch64.neon.srshl.i64(i64 %tmp1, i64 %tmp2)1179 ret i64 %tmp31180}1181 1182define i64 @srshl_scalar_constant(ptr %A) nounwind sanitize_memory {1183; CHECK-LABEL: define i64 @srshl_scalar_constant(1184; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {1185; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81186; CHECK-NEXT: call void @llvm.donothing()1187; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01188; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]1189; CHECK: 2:1190; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1191; CHECK-NEXT: unreachable1192; CHECK: 3:1193; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[A]], align 81194; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i641195; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885761196; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr1197; CHECK-NEXT: [[_MSLD:%.*]] = load i64, ptr [[TMP6]], align 81198; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.aarch64.neon.srshl.i64(i64 [[_MSLD]], i64 1)1199; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP7]], 01200; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.srshl.i64(i64 [[TMP1]], i64 1)1201; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 81202; CHECK-NEXT: ret i64 [[TMP3]]1203;1204 %tmp1 = load i64, ptr %A1205 %tmp3 = call i64 @llvm.aarch64.neon.srshl.i64(i64 %tmp1, i64 1)1206 ret i64 %tmp31207}1208 1209define <8 x i8> @urshl8b(ptr %A, ptr %B) nounwind sanitize_memory {1210; CHECK-LABEL: define <8 x i8> @urshl8b(1211; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1212; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81213; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81214; CHECK-NEXT: call void @llvm.donothing()1215; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01216; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1217; CHECK: 3:1218; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1219; CHECK-NEXT: unreachable1220; CHECK: 4:1221; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[A]], align 81222; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641223; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761224; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1225; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 81226; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01227; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1228; CHECK: 8:1229; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1230; CHECK-NEXT: unreachable1231; CHECK: 9:1232; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i8>, ptr [[B]], align 81233; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641234; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761235; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1236; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP12]], align 81237; CHECK-NEXT: [[TMP13:%.*]] = bitcast <8 x i8> [[_MSLD1]] to i641238; CHECK-NEXT: [[TMP14:%.*]] = icmp ne i64 [[TMP13]], 01239; CHECK-NEXT: [[TMP15:%.*]] = sext i1 [[TMP14]] to i641240; CHECK-NEXT: [[TMP16:%.*]] = bitcast i64 [[TMP15]] to <8 x i8>1241; CHECK-NEXT: [[TMP17:%.*]] = call <8 x i8> @llvm.aarch64.neon.urshl.v8i8(<8 x i8> [[_MSLD]], <8 x i8> [[TMP2]])1242; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i8> [[TMP17]], [[TMP16]]1243; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.urshl.v8i8(<8 x i8> [[TMP1]], <8 x i8> [[TMP2]])1244; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 81245; CHECK-NEXT: ret <8 x i8> [[TMP3]]1246;1247 %tmp1 = load <8 x i8>, ptr %A1248 %tmp2 = load <8 x i8>, ptr %B1249 %tmp3 = call <8 x i8> @llvm.aarch64.neon.urshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)1250 ret <8 x i8> %tmp31251}1252 1253define <4 x i16> @urshl4h(ptr %A, ptr %B) nounwind sanitize_memory {1254; CHECK-LABEL: define <4 x i16> @urshl4h(1255; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1256; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81257; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81258; CHECK-NEXT: call void @llvm.donothing()1259; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01260; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1261; CHECK: 3:1262; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1263; CHECK-NEXT: unreachable1264; CHECK: 4:1265; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 81266; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641267; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761268; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1269; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 81270; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01271; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1272; CHECK: 8:1273; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1274; CHECK-NEXT: unreachable1275; CHECK: 9:1276; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr [[B]], align 81277; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641278; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761279; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1280; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 81281; CHECK-NEXT: [[TMP13:%.*]] = bitcast <4 x i16> [[_MSLD1]] to i641282; CHECK-NEXT: [[TMP14:%.*]] = icmp ne i64 [[TMP13]], 01283; CHECK-NEXT: [[TMP15:%.*]] = sext i1 [[TMP14]] to i641284; CHECK-NEXT: [[TMP16:%.*]] = bitcast i64 [[TMP15]] to <4 x i16>1285; CHECK-NEXT: [[TMP17:%.*]] = call <4 x i16> @llvm.aarch64.neon.urshl.v4i16(<4 x i16> [[_MSLD]], <4 x i16> [[TMP2]])1286; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[TMP17]], [[TMP16]]1287; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.urshl.v4i16(<4 x i16> [[TMP1]], <4 x i16> [[TMP2]])1288; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 81289; CHECK-NEXT: ret <4 x i16> [[TMP3]]1290;1291 %tmp1 = load <4 x i16>, ptr %A1292 %tmp2 = load <4 x i16>, ptr %B1293 %tmp3 = call <4 x i16> @llvm.aarch64.neon.urshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)1294 ret <4 x i16> %tmp31295}1296 1297define <2 x i32> @urshl2s(ptr %A, ptr %B) nounwind sanitize_memory {1298; CHECK-LABEL: define <2 x i32> @urshl2s(1299; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1300; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81301; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81302; CHECK-NEXT: call void @llvm.donothing()1303; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01304; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1305; CHECK: 3:1306; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1307; CHECK-NEXT: unreachable1308; CHECK: 4:1309; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 81310; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641311; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761312; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1313; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 81314; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01315; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1316; CHECK: 8:1317; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1318; CHECK-NEXT: unreachable1319; CHECK: 9:1320; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr [[B]], align 81321; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641322; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761323; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1324; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 81325; CHECK-NEXT: [[TMP13:%.*]] = bitcast <2 x i32> [[_MSLD1]] to i641326; CHECK-NEXT: [[TMP14:%.*]] = icmp ne i64 [[TMP13]], 01327; CHECK-NEXT: [[TMP15:%.*]] = sext i1 [[TMP14]] to i641328; CHECK-NEXT: [[TMP16:%.*]] = bitcast i64 [[TMP15]] to <2 x i32>1329; CHECK-NEXT: [[TMP17:%.*]] = call <2 x i32> @llvm.aarch64.neon.urshl.v2i32(<2 x i32> [[_MSLD]], <2 x i32> [[TMP2]])1330; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[TMP17]], [[TMP16]]1331; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.urshl.v2i32(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]])1332; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 81333; CHECK-NEXT: ret <2 x i32> [[TMP3]]1334;1335 %tmp1 = load <2 x i32>, ptr %A1336 %tmp2 = load <2 x i32>, ptr %B1337 %tmp3 = call <2 x i32> @llvm.aarch64.neon.urshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)1338 ret <2 x i32> %tmp31339}1340 1341define <1 x i64> @urshl1d(ptr %A, ptr %B) nounwind sanitize_memory {1342; CHECK-LABEL: define <1 x i64> @urshl1d(1343; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1344; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81345; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81346; CHECK-NEXT: call void @llvm.donothing()1347; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01348; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1349; CHECK: 3:1350; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1351; CHECK-NEXT: unreachable1352; CHECK: 4:1353; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr [[A]], align 81354; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641355; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761356; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1357; CHECK-NEXT: [[_MSLD:%.*]] = load <1 x i64>, ptr [[TMP7]], align 81358; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01359; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1360; CHECK: 8:1361; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1362; CHECK-NEXT: unreachable1363; CHECK: 9:1364; CHECK-NEXT: [[TMP2:%.*]] = load <1 x i64>, ptr [[B]], align 81365; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641366; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761367; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1368; CHECK-NEXT: [[_MSLD1:%.*]] = load <1 x i64>, ptr [[TMP12]], align 81369; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[_MSLD1]] to i641370; CHECK-NEXT: [[TMP14:%.*]] = icmp ne i64 [[TMP13]], 01371; CHECK-NEXT: [[TMP15:%.*]] = sext i1 [[TMP14]] to i641372; CHECK-NEXT: [[TMP16:%.*]] = bitcast i64 [[TMP15]] to <1 x i64>1373; CHECK-NEXT: [[TMP17:%.*]] = call <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64> [[_MSLD]], <1 x i64> [[TMP2]])1374; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP17]], [[TMP16]]1375; CHECK-NEXT: [[TMP3:%.*]] = call <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64> [[TMP1]], <1 x i64> [[TMP2]])1376; CHECK-NEXT: store <1 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 81377; CHECK-NEXT: ret <1 x i64> [[TMP3]]1378;1379 %tmp1 = load <1 x i64>, ptr %A1380 %tmp2 = load <1 x i64>, ptr %B1381 %tmp3 = call <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)1382 ret <1 x i64> %tmp31383}1384 1385define <1 x i64> @urshl1d_constant(ptr %A) nounwind sanitize_memory {1386; CHECK-LABEL: define <1 x i64> @urshl1d_constant(1387; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {1388; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81389; CHECK-NEXT: call void @llvm.donothing()1390; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01391; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]1392; CHECK: 2:1393; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1394; CHECK-NEXT: unreachable1395; CHECK: 3:1396; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr [[A]], align 81397; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i641398; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885761399; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr1400; CHECK-NEXT: [[_MSLD:%.*]] = load <1 x i64>, ptr [[TMP6]], align 81401; CHECK-NEXT: [[TMP7:%.*]] = call <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64> [[_MSLD]], <1 x i64> splat (i64 1))1402; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP7]], zeroinitializer1403; CHECK-NEXT: [[TMP3:%.*]] = call <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64> [[TMP1]], <1 x i64> splat (i64 1))1404; CHECK-NEXT: store <1 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 81405; CHECK-NEXT: ret <1 x i64> [[TMP3]]1406;1407 %tmp1 = load <1 x i64>, ptr %A1408 %tmp3 = call <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 1>)1409 ret <1 x i64> %tmp31410}1411 1412define i64 @urshl_scalar(ptr %A, ptr %B) nounwind sanitize_memory {1413; CHECK-LABEL: define i64 @urshl_scalar(1414; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1415; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81416; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81417; CHECK-NEXT: call void @llvm.donothing()1418; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01419; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1420; CHECK: 3:1421; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1422; CHECK-NEXT: unreachable1423; CHECK: 4:1424; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[A]], align 81425; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641426; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761427; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1428; CHECK-NEXT: [[_MSLD:%.*]] = load i64, ptr [[TMP7]], align 81429; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01430; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1431; CHECK: 8:1432; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1433; CHECK-NEXT: unreachable1434; CHECK: 9:1435; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[B]], align 81436; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641437; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761438; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1439; CHECK-NEXT: [[_MSLD1:%.*]] = load i64, ptr [[TMP12]], align 81440; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[_MSLD1]], 01441; CHECK-NEXT: [[TMP14:%.*]] = sext i1 [[TMP13]] to i641442; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.aarch64.neon.urshl.i64(i64 [[_MSLD]], i64 [[TMP2]])1443; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP15]], [[TMP14]]1444; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.urshl.i64(i64 [[TMP1]], i64 [[TMP2]])1445; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 81446; CHECK-NEXT: ret i64 [[TMP3]]1447;1448 %tmp1 = load i64, ptr %A1449 %tmp2 = load i64, ptr %B1450 %tmp3 = call i64 @llvm.aarch64.neon.urshl.i64(i64 %tmp1, i64 %tmp2)1451 ret i64 %tmp31452}1453 1454define i64 @urshl_scalar_constant(ptr %A) nounwind sanitize_memory {1455; CHECK-LABEL: define i64 @urshl_scalar_constant(1456; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {1457; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81458; CHECK-NEXT: call void @llvm.donothing()1459; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01460; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]1461; CHECK: 2:1462; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1463; CHECK-NEXT: unreachable1464; CHECK: 3:1465; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[A]], align 81466; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i641467; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885761468; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr1469; CHECK-NEXT: [[_MSLD:%.*]] = load i64, ptr [[TMP6]], align 81470; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.aarch64.neon.urshl.i64(i64 [[_MSLD]], i64 1)1471; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP7]], 01472; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.urshl.i64(i64 [[TMP1]], i64 1)1473; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 81474; CHECK-NEXT: ret i64 [[TMP3]]1475;1476 %tmp1 = load i64, ptr %A1477 %tmp3 = call i64 @llvm.aarch64.neon.urshl.i64(i64 %tmp1, i64 1)1478 ret i64 %tmp31479}1480 1481define <16 x i8> @srshl16b(ptr %A, ptr %B) nounwind sanitize_memory {1482; CHECK-LABEL: define <16 x i8> @srshl16b(1483; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1484; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81485; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81486; CHECK-NEXT: call void @llvm.donothing()1487; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01488; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1489; CHECK: 3:1490; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1491; CHECK-NEXT: unreachable1492; CHECK: 4:1493; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[A]], align 161494; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641495; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761496; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1497; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP7]], align 161498; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01499; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1500; CHECK: 8:1501; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1502; CHECK-NEXT: unreachable1503; CHECK: 9:1504; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr [[B]], align 161505; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641506; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761507; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1508; CHECK-NEXT: [[_MSLD1:%.*]] = load <16 x i8>, ptr [[TMP12]], align 161509; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[_MSLD1]] to i1281510; CHECK-NEXT: [[TMP14:%.*]] = trunc i128 [[TMP13]] to i641511; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[TMP14]], 01512; CHECK-NEXT: [[TMP16:%.*]] = sext i1 [[TMP15]] to i1281513; CHECK-NEXT: [[TMP17:%.*]] = bitcast i128 [[TMP16]] to <16 x i8>1514; CHECK-NEXT: [[TMP18:%.*]] = call <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8> [[_MSLD]], <16 x i8> [[TMP2]])1515; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP18]], [[TMP17]]1516; CHECK-NEXT: [[TMP3:%.*]] = call <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8> [[TMP1]], <16 x i8> [[TMP2]])1517; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 81518; CHECK-NEXT: ret <16 x i8> [[TMP3]]1519;1520 %tmp1 = load <16 x i8>, ptr %A1521 %tmp2 = load <16 x i8>, ptr %B1522 %tmp3 = call <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)1523 ret <16 x i8> %tmp31524}1525 1526define <8 x i16> @srshl8h(ptr %A, ptr %B) nounwind sanitize_memory {1527; CHECK-LABEL: define <8 x i16> @srshl8h(1528; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1529; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81530; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81531; CHECK-NEXT: call void @llvm.donothing()1532; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01533; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1534; CHECK: 3:1535; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1536; CHECK-NEXT: unreachable1537; CHECK: 4:1538; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 161539; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641540; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761541; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1542; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 161543; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01544; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1545; CHECK: 8:1546; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1547; CHECK-NEXT: unreachable1548; CHECK: 9:1549; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr [[B]], align 161550; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641551; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761552; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1553; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 161554; CHECK-NEXT: [[TMP13:%.*]] = bitcast <8 x i16> [[_MSLD1]] to i1281555; CHECK-NEXT: [[TMP14:%.*]] = trunc i128 [[TMP13]] to i641556; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[TMP14]], 01557; CHECK-NEXT: [[TMP16:%.*]] = sext i1 [[TMP15]] to i1281558; CHECK-NEXT: [[TMP17:%.*]] = bitcast i128 [[TMP16]] to <8 x i16>1559; CHECK-NEXT: [[TMP18:%.*]] = call <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16> [[_MSLD]], <8 x i16> [[TMP2]])1560; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP18]], [[TMP17]]1561; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16> [[TMP1]], <8 x i16> [[TMP2]])1562; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 81563; CHECK-NEXT: ret <8 x i16> [[TMP3]]1564;1565 %tmp1 = load <8 x i16>, ptr %A1566 %tmp2 = load <8 x i16>, ptr %B1567 %tmp3 = call <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)1568 ret <8 x i16> %tmp31569}1570 1571define <4 x i32> @srshl4s(ptr %A, ptr %B) nounwind sanitize_memory {1572; CHECK-LABEL: define <4 x i32> @srshl4s(1573; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1574; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81575; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81576; CHECK-NEXT: call void @llvm.donothing()1577; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01578; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1579; CHECK: 3:1580; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1581; CHECK-NEXT: unreachable1582; CHECK: 4:1583; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 161584; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641585; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761586; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1587; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 161588; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01589; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1590; CHECK: 8:1591; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1592; CHECK-NEXT: unreachable1593; CHECK: 9:1594; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr [[B]], align 161595; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641596; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761597; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1598; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 161599; CHECK-NEXT: [[TMP13:%.*]] = bitcast <4 x i32> [[_MSLD1]] to i1281600; CHECK-NEXT: [[TMP14:%.*]] = trunc i128 [[TMP13]] to i641601; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[TMP14]], 01602; CHECK-NEXT: [[TMP16:%.*]] = sext i1 [[TMP15]] to i1281603; CHECK-NEXT: [[TMP17:%.*]] = bitcast i128 [[TMP16]] to <4 x i32>1604; CHECK-NEXT: [[TMP18:%.*]] = call <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32> [[_MSLD]], <4 x i32> [[TMP2]])1605; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP18]], [[TMP17]]1606; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32> [[TMP1]], <4 x i32> [[TMP2]])1607; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 81608; CHECK-NEXT: ret <4 x i32> [[TMP3]]1609;1610 %tmp1 = load <4 x i32>, ptr %A1611 %tmp2 = load <4 x i32>, ptr %B1612 %tmp3 = call <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)1613 ret <4 x i32> %tmp31614}1615 1616define <2 x i64> @srshl2d(ptr %A, ptr %B) nounwind sanitize_memory {1617; CHECK-LABEL: define <2 x i64> @srshl2d(1618; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1619; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81620; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81621; CHECK-NEXT: call void @llvm.donothing()1622; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01623; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1624; CHECK: 3:1625; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1626; CHECK-NEXT: unreachable1627; CHECK: 4:1628; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 161629; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641630; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761631; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1632; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 161633; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01634; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1635; CHECK: 8:1636; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1637; CHECK-NEXT: unreachable1638; CHECK: 9:1639; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr [[B]], align 161640; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641641; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761642; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1643; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 161644; CHECK-NEXT: [[TMP13:%.*]] = bitcast <2 x i64> [[_MSLD1]] to i1281645; CHECK-NEXT: [[TMP14:%.*]] = trunc i128 [[TMP13]] to i641646; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[TMP14]], 01647; CHECK-NEXT: [[TMP16:%.*]] = sext i1 [[TMP15]] to i1281648; CHECK-NEXT: [[TMP17:%.*]] = bitcast i128 [[TMP16]] to <2 x i64>1649; CHECK-NEXT: [[TMP18:%.*]] = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> [[_MSLD]], <2 x i64> [[TMP2]])1650; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP18]], [[TMP17]]1651; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> [[TMP1]], <2 x i64> [[TMP2]])1652; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 81653; CHECK-NEXT: ret <2 x i64> [[TMP3]]1654;1655 %tmp1 = load <2 x i64>, ptr %A1656 %tmp2 = load <2 x i64>, ptr %B1657 %tmp3 = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)1658 ret <2 x i64> %tmp31659}1660 1661define <16 x i8> @urshl16b(ptr %A, ptr %B) nounwind sanitize_memory {1662; CHECK-LABEL: define <16 x i8> @urshl16b(1663; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1664; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81665; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81666; CHECK-NEXT: call void @llvm.donothing()1667; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01668; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1669; CHECK: 3:1670; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1671; CHECK-NEXT: unreachable1672; CHECK: 4:1673; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[A]], align 161674; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641675; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761676; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1677; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP7]], align 161678; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01679; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1680; CHECK: 8:1681; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1682; CHECK-NEXT: unreachable1683; CHECK: 9:1684; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr [[B]], align 161685; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641686; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761687; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1688; CHECK-NEXT: [[_MSLD1:%.*]] = load <16 x i8>, ptr [[TMP12]], align 161689; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[_MSLD1]] to i1281690; CHECK-NEXT: [[TMP14:%.*]] = trunc i128 [[TMP13]] to i641691; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[TMP14]], 01692; CHECK-NEXT: [[TMP16:%.*]] = sext i1 [[TMP15]] to i1281693; CHECK-NEXT: [[TMP17:%.*]] = bitcast i128 [[TMP16]] to <16 x i8>1694; CHECK-NEXT: [[TMP18:%.*]] = call <16 x i8> @llvm.aarch64.neon.urshl.v16i8(<16 x i8> [[_MSLD]], <16 x i8> [[TMP2]])1695; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP18]], [[TMP17]]1696; CHECK-NEXT: [[TMP3:%.*]] = call <16 x i8> @llvm.aarch64.neon.urshl.v16i8(<16 x i8> [[TMP1]], <16 x i8> [[TMP2]])1697; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 81698; CHECK-NEXT: ret <16 x i8> [[TMP3]]1699;1700 %tmp1 = load <16 x i8>, ptr %A1701 %tmp2 = load <16 x i8>, ptr %B1702 %tmp3 = call <16 x i8> @llvm.aarch64.neon.urshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)1703 ret <16 x i8> %tmp31704}1705 1706define <8 x i16> @urshl8h(ptr %A, ptr %B) nounwind sanitize_memory {1707; CHECK-LABEL: define <8 x i16> @urshl8h(1708; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1709; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81710; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81711; CHECK-NEXT: call void @llvm.donothing()1712; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01713; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1714; CHECK: 3:1715; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1716; CHECK-NEXT: unreachable1717; CHECK: 4:1718; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 161719; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641720; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761721; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1722; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 161723; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01724; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1725; CHECK: 8:1726; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1727; CHECK-NEXT: unreachable1728; CHECK: 9:1729; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr [[B]], align 161730; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641731; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761732; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1733; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 161734; CHECK-NEXT: [[TMP13:%.*]] = bitcast <8 x i16> [[_MSLD1]] to i1281735; CHECK-NEXT: [[TMP14:%.*]] = trunc i128 [[TMP13]] to i641736; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[TMP14]], 01737; CHECK-NEXT: [[TMP16:%.*]] = sext i1 [[TMP15]] to i1281738; CHECK-NEXT: [[TMP17:%.*]] = bitcast i128 [[TMP16]] to <8 x i16>1739; CHECK-NEXT: [[TMP18:%.*]] = call <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16> [[_MSLD]], <8 x i16> [[TMP2]])1740; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP18]], [[TMP17]]1741; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16> [[TMP1]], <8 x i16> [[TMP2]])1742; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 81743; CHECK-NEXT: ret <8 x i16> [[TMP3]]1744;1745 %tmp1 = load <8 x i16>, ptr %A1746 %tmp2 = load <8 x i16>, ptr %B1747 %tmp3 = call <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)1748 ret <8 x i16> %tmp31749}1750 1751define <4 x i32> @urshl4s(ptr %A, ptr %B) nounwind sanitize_memory {1752; CHECK-LABEL: define <4 x i32> @urshl4s(1753; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1754; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81755; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81756; CHECK-NEXT: call void @llvm.donothing()1757; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01758; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1759; CHECK: 3:1760; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1761; CHECK-NEXT: unreachable1762; CHECK: 4:1763; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 161764; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641765; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761766; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1767; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 161768; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01769; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1770; CHECK: 8:1771; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1772; CHECK-NEXT: unreachable1773; CHECK: 9:1774; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr [[B]], align 161775; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641776; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761777; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1778; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 161779; CHECK-NEXT: [[TMP13:%.*]] = bitcast <4 x i32> [[_MSLD1]] to i1281780; CHECK-NEXT: [[TMP14:%.*]] = trunc i128 [[TMP13]] to i641781; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[TMP14]], 01782; CHECK-NEXT: [[TMP16:%.*]] = sext i1 [[TMP15]] to i1281783; CHECK-NEXT: [[TMP17:%.*]] = bitcast i128 [[TMP16]] to <4 x i32>1784; CHECK-NEXT: [[TMP18:%.*]] = call <4 x i32> @llvm.aarch64.neon.urshl.v4i32(<4 x i32> [[_MSLD]], <4 x i32> [[TMP2]])1785; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP18]], [[TMP17]]1786; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.urshl.v4i32(<4 x i32> [[TMP1]], <4 x i32> [[TMP2]])1787; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 81788; CHECK-NEXT: ret <4 x i32> [[TMP3]]1789;1790 %tmp1 = load <4 x i32>, ptr %A1791 %tmp2 = load <4 x i32>, ptr %B1792 %tmp3 = call <4 x i32> @llvm.aarch64.neon.urshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)1793 ret <4 x i32> %tmp31794}1795 1796define <2 x i64> @urshl2d(ptr %A, ptr %B) nounwind sanitize_memory {1797; CHECK-LABEL: define <2 x i64> @urshl2d(1798; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1799; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81800; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81801; CHECK-NEXT: call void @llvm.donothing()1802; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01803; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1804; CHECK: 3:1805; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1806; CHECK-NEXT: unreachable1807; CHECK: 4:1808; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 161809; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641810; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761811; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1812; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 161813; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01814; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1815; CHECK: 8:1816; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1817; CHECK-NEXT: unreachable1818; CHECK: 9:1819; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr [[B]], align 161820; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641821; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761822; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1823; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 161824; CHECK-NEXT: [[TMP13:%.*]] = bitcast <2 x i64> [[_MSLD1]] to i1281825; CHECK-NEXT: [[TMP14:%.*]] = trunc i128 [[TMP13]] to i641826; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[TMP14]], 01827; CHECK-NEXT: [[TMP16:%.*]] = sext i1 [[TMP15]] to i1281828; CHECK-NEXT: [[TMP17:%.*]] = bitcast i128 [[TMP16]] to <2 x i64>1829; CHECK-NEXT: [[TMP18:%.*]] = call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> [[_MSLD]], <2 x i64> [[TMP2]])1830; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP18]], [[TMP17]]1831; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> [[TMP1]], <2 x i64> [[TMP2]])1832; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 81833; CHECK-NEXT: ret <2 x i64> [[TMP3]]1834;1835 %tmp1 = load <2 x i64>, ptr %A1836 %tmp2 = load <2 x i64>, ptr %B1837 %tmp3 = call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)1838 ret <2 x i64> %tmp31839}1840 1841declare <8 x i8> @llvm.aarch64.neon.srshl.v8i8(<8 x i8>, <8 x i8>) nounwind readnone1842declare <4 x i16> @llvm.aarch64.neon.srshl.v4i16(<4 x i16>, <4 x i16>) nounwind readnone1843declare <2 x i32> @llvm.aarch64.neon.srshl.v2i32(<2 x i32>, <2 x i32>) nounwind readnone1844declare <1 x i64> @llvm.aarch64.neon.srshl.v1i64(<1 x i64>, <1 x i64>) nounwind readnone1845declare i64 @llvm.aarch64.neon.srshl.i64(i64, i64) nounwind readnone1846 1847declare <8 x i8> @llvm.aarch64.neon.urshl.v8i8(<8 x i8>, <8 x i8>) nounwind readnone1848declare <4 x i16> @llvm.aarch64.neon.urshl.v4i16(<4 x i16>, <4 x i16>) nounwind readnone1849declare <2 x i32> @llvm.aarch64.neon.urshl.v2i32(<2 x i32>, <2 x i32>) nounwind readnone1850declare <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64>, <1 x i64>) nounwind readnone1851declare i64 @llvm.aarch64.neon.urshl.i64(i64, i64) nounwind readnone1852 1853declare <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8>, <16 x i8>) nounwind readnone1854declare <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16>, <8 x i16>) nounwind readnone1855declare <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32>, <4 x i32>) nounwind readnone1856declare <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64>, <2 x i64>) nounwind readnone1857 1858declare <16 x i8> @llvm.aarch64.neon.urshl.v16i8(<16 x i8>, <16 x i8>) nounwind readnone1859declare <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16>, <8 x i16>) nounwind readnone1860declare <4 x i32> @llvm.aarch64.neon.urshl.v4i32(<4 x i32>, <4 x i32>) nounwind readnone1861declare <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64>, <2 x i64>) nounwind readnone1862 1863define <8 x i8> @sqrshl8b(ptr %A, ptr %B) nounwind sanitize_memory {1864; CHECK-LABEL: define <8 x i8> @sqrshl8b(1865; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1866; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81867; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81868; CHECK-NEXT: call void @llvm.donothing()1869; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01870; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1871; CHECK: 3:1872; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1873; CHECK-NEXT: unreachable1874; CHECK: 4:1875; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[A]], align 81876; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641877; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761878; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1879; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 81880; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01881; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1882; CHECK: 8:1883; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1884; CHECK-NEXT: unreachable1885; CHECK: 9:1886; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i8>, ptr [[B]], align 81887; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641888; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761889; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1890; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP12]], align 81891; CHECK-NEXT: [[TMP13:%.*]] = bitcast <8 x i8> [[_MSLD1]] to i641892; CHECK-NEXT: [[TMP14:%.*]] = icmp ne i64 [[TMP13]], 01893; CHECK-NEXT: [[TMP15:%.*]] = sext i1 [[TMP14]] to i641894; CHECK-NEXT: [[TMP16:%.*]] = bitcast i64 [[TMP15]] to <8 x i8>1895; CHECK-NEXT: [[TMP17:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqrshl.v8i8(<8 x i8> [[_MSLD]], <8 x i8> [[TMP2]])1896; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i8> [[TMP17]], [[TMP16]]1897; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqrshl.v8i8(<8 x i8> [[TMP1]], <8 x i8> [[TMP2]])1898; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 81899; CHECK-NEXT: ret <8 x i8> [[TMP3]]1900;1901 %tmp1 = load <8 x i8>, ptr %A1902 %tmp2 = load <8 x i8>, ptr %B1903 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqrshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)1904 ret <8 x i8> %tmp31905}1906 1907define <4 x i16> @sqrshl4h(ptr %A, ptr %B) nounwind sanitize_memory {1908; CHECK-LABEL: define <4 x i16> @sqrshl4h(1909; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1910; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81911; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81912; CHECK-NEXT: call void @llvm.donothing()1913; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01914; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1915; CHECK: 3:1916; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1917; CHECK-NEXT: unreachable1918; CHECK: 4:1919; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 81920; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641921; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761922; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1923; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 81924; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01925; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1926; CHECK: 8:1927; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1928; CHECK-NEXT: unreachable1929; CHECK: 9:1930; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr [[B]], align 81931; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641932; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761933; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1934; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 81935; CHECK-NEXT: [[TMP13:%.*]] = bitcast <4 x i16> [[_MSLD1]] to i641936; CHECK-NEXT: [[TMP14:%.*]] = icmp ne i64 [[TMP13]], 01937; CHECK-NEXT: [[TMP15:%.*]] = sext i1 [[TMP14]] to i641938; CHECK-NEXT: [[TMP16:%.*]] = bitcast i64 [[TMP15]] to <4 x i16>1939; CHECK-NEXT: [[TMP17:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqrshl.v4i16(<4 x i16> [[_MSLD]], <4 x i16> [[TMP2]])1940; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[TMP17]], [[TMP16]]1941; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqrshl.v4i16(<4 x i16> [[TMP1]], <4 x i16> [[TMP2]])1942; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 81943; CHECK-NEXT: ret <4 x i16> [[TMP3]]1944;1945 %tmp1 = load <4 x i16>, ptr %A1946 %tmp2 = load <4 x i16>, ptr %B1947 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqrshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)1948 ret <4 x i16> %tmp31949}1950 1951define <2 x i32> @sqrshl2s(ptr %A, ptr %B) nounwind sanitize_memory {1952; CHECK-LABEL: define <2 x i32> @sqrshl2s(1953; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1954; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81955; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 81956; CHECK-NEXT: call void @llvm.donothing()1957; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 01958; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]1959; CHECK: 3:1960; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1961; CHECK-NEXT: unreachable1962; CHECK: 4:1963; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 81964; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i641965; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885761966; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr1967; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 81968; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 01969; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]1970; CHECK: 8:1971; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]1972; CHECK-NEXT: unreachable1973; CHECK: 9:1974; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr [[B]], align 81975; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i641976; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885761977; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr1978; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 81979; CHECK-NEXT: [[TMP13:%.*]] = bitcast <2 x i32> [[_MSLD1]] to i641980; CHECK-NEXT: [[TMP14:%.*]] = icmp ne i64 [[TMP13]], 01981; CHECK-NEXT: [[TMP15:%.*]] = sext i1 [[TMP14]] to i641982; CHECK-NEXT: [[TMP16:%.*]] = bitcast i64 [[TMP15]] to <2 x i32>1983; CHECK-NEXT: [[TMP17:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqrshl.v2i32(<2 x i32> [[_MSLD]], <2 x i32> [[TMP2]])1984; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[TMP17]], [[TMP16]]1985; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqrshl.v2i32(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]])1986; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 81987; CHECK-NEXT: ret <2 x i32> [[TMP3]]1988;1989 %tmp1 = load <2 x i32>, ptr %A1990 %tmp2 = load <2 x i32>, ptr %B1991 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqrshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)1992 ret <2 x i32> %tmp31993}1994 1995define <8 x i8> @uqrshl8b(ptr %A, ptr %B) nounwind sanitize_memory {1996; CHECK-LABEL: define <8 x i8> @uqrshl8b(1997; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {1998; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 81999; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82000; CHECK-NEXT: call void @llvm.donothing()2001; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02002; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]2003; CHECK: 3:2004; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2005; CHECK-NEXT: unreachable2006; CHECK: 4:2007; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[A]], align 82008; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642009; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762010; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2011; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 82012; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02013; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2014; CHECK: 8:2015; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2016; CHECK-NEXT: unreachable2017; CHECK: 9:2018; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i8>, ptr [[B]], align 82019; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642020; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762021; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2022; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP12]], align 82023; CHECK-NEXT: [[TMP13:%.*]] = bitcast <8 x i8> [[_MSLD1]] to i642024; CHECK-NEXT: [[TMP14:%.*]] = icmp ne i64 [[TMP13]], 02025; CHECK-NEXT: [[TMP15:%.*]] = sext i1 [[TMP14]] to i642026; CHECK-NEXT: [[TMP16:%.*]] = bitcast i64 [[TMP15]] to <8 x i8>2027; CHECK-NEXT: [[TMP17:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqrshl.v8i8(<8 x i8> [[_MSLD]], <8 x i8> [[TMP2]])2028; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i8> [[TMP17]], [[TMP16]]2029; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqrshl.v8i8(<8 x i8> [[TMP1]], <8 x i8> [[TMP2]])2030; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 82031; CHECK-NEXT: ret <8 x i8> [[TMP3]]2032;2033 %tmp1 = load <8 x i8>, ptr %A2034 %tmp2 = load <8 x i8>, ptr %B2035 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqrshl.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)2036 ret <8 x i8> %tmp32037}2038 2039define <4 x i16> @uqrshl4h(ptr %A, ptr %B) nounwind sanitize_memory {2040; CHECK-LABEL: define <4 x i16> @uqrshl4h(2041; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2042; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82043; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82044; CHECK-NEXT: call void @llvm.donothing()2045; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02046; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]2047; CHECK: 3:2048; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2049; CHECK-NEXT: unreachable2050; CHECK: 4:2051; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 82052; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642053; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762054; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2055; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 82056; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02057; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2058; CHECK: 8:2059; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2060; CHECK-NEXT: unreachable2061; CHECK: 9:2062; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr [[B]], align 82063; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642064; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762065; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2066; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 82067; CHECK-NEXT: [[TMP13:%.*]] = bitcast <4 x i16> [[_MSLD1]] to i642068; CHECK-NEXT: [[TMP14:%.*]] = icmp ne i64 [[TMP13]], 02069; CHECK-NEXT: [[TMP15:%.*]] = sext i1 [[TMP14]] to i642070; CHECK-NEXT: [[TMP16:%.*]] = bitcast i64 [[TMP15]] to <4 x i16>2071; CHECK-NEXT: [[TMP17:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqrshl.v4i16(<4 x i16> [[_MSLD]], <4 x i16> [[TMP2]])2072; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[TMP17]], [[TMP16]]2073; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqrshl.v4i16(<4 x i16> [[TMP1]], <4 x i16> [[TMP2]])2074; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 82075; CHECK-NEXT: ret <4 x i16> [[TMP3]]2076;2077 %tmp1 = load <4 x i16>, ptr %A2078 %tmp2 = load <4 x i16>, ptr %B2079 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqrshl.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)2080 ret <4 x i16> %tmp32081}2082 2083define <2 x i32> @uqrshl2s(ptr %A, ptr %B) nounwind sanitize_memory {2084; CHECK-LABEL: define <2 x i32> @uqrshl2s(2085; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2086; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82087; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82088; CHECK-NEXT: call void @llvm.donothing()2089; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02090; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]2091; CHECK: 3:2092; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2093; CHECK-NEXT: unreachable2094; CHECK: 4:2095; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 82096; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642097; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762098; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2099; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 82100; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02101; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2102; CHECK: 8:2103; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2104; CHECK-NEXT: unreachable2105; CHECK: 9:2106; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr [[B]], align 82107; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642108; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762109; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2110; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 82111; CHECK-NEXT: [[TMP13:%.*]] = bitcast <2 x i32> [[_MSLD1]] to i642112; CHECK-NEXT: [[TMP14:%.*]] = icmp ne i64 [[TMP13]], 02113; CHECK-NEXT: [[TMP15:%.*]] = sext i1 [[TMP14]] to i642114; CHECK-NEXT: [[TMP16:%.*]] = bitcast i64 [[TMP15]] to <2 x i32>2115; CHECK-NEXT: [[TMP17:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqrshl.v2i32(<2 x i32> [[_MSLD]], <2 x i32> [[TMP2]])2116; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[TMP17]], [[TMP16]]2117; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqrshl.v2i32(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]])2118; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 82119; CHECK-NEXT: ret <2 x i32> [[TMP3]]2120;2121 %tmp1 = load <2 x i32>, ptr %A2122 %tmp2 = load <2 x i32>, ptr %B2123 %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqrshl.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)2124 ret <2 x i32> %tmp32125}2126 2127define <16 x i8> @sqrshl16b(ptr %A, ptr %B) nounwind sanitize_memory {2128; CHECK-LABEL: define <16 x i8> @sqrshl16b(2129; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2130; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82131; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82132; CHECK-NEXT: call void @llvm.donothing()2133; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02134; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]2135; CHECK: 3:2136; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2137; CHECK-NEXT: unreachable2138; CHECK: 4:2139; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[A]], align 162140; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642141; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762142; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2143; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP7]], align 162144; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02145; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2146; CHECK: 8:2147; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2148; CHECK-NEXT: unreachable2149; CHECK: 9:2150; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr [[B]], align 162151; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642152; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762153; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2154; CHECK-NEXT: [[_MSLD1:%.*]] = load <16 x i8>, ptr [[TMP12]], align 162155; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[_MSLD1]] to i1282156; CHECK-NEXT: [[TMP14:%.*]] = trunc i128 [[TMP13]] to i642157; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[TMP14]], 02158; CHECK-NEXT: [[TMP16:%.*]] = sext i1 [[TMP15]] to i1282159; CHECK-NEXT: [[TMP17:%.*]] = bitcast i128 [[TMP16]] to <16 x i8>2160; CHECK-NEXT: [[TMP18:%.*]] = call <16 x i8> @llvm.aarch64.neon.sqrshl.v16i8(<16 x i8> [[_MSLD]], <16 x i8> [[TMP2]])2161; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP18]], [[TMP17]]2162; CHECK-NEXT: [[TMP3:%.*]] = call <16 x i8> @llvm.aarch64.neon.sqrshl.v16i8(<16 x i8> [[TMP1]], <16 x i8> [[TMP2]])2163; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 82164; CHECK-NEXT: ret <16 x i8> [[TMP3]]2165;2166 %tmp1 = load <16 x i8>, ptr %A2167 %tmp2 = load <16 x i8>, ptr %B2168 %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqrshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)2169 ret <16 x i8> %tmp32170}2171 2172define <8 x i16> @sqrshl8h(ptr %A, ptr %B) nounwind sanitize_memory {2173; CHECK-LABEL: define <8 x i16> @sqrshl8h(2174; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2175; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82176; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82177; CHECK-NEXT: call void @llvm.donothing()2178; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02179; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]2180; CHECK: 3:2181; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2182; CHECK-NEXT: unreachable2183; CHECK: 4:2184; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 162185; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642186; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762187; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2188; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 162189; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02190; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2191; CHECK: 8:2192; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2193; CHECK-NEXT: unreachable2194; CHECK: 9:2195; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr [[B]], align 162196; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642197; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762198; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2199; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 162200; CHECK-NEXT: [[TMP13:%.*]] = bitcast <8 x i16> [[_MSLD1]] to i1282201; CHECK-NEXT: [[TMP14:%.*]] = trunc i128 [[TMP13]] to i642202; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[TMP14]], 02203; CHECK-NEXT: [[TMP16:%.*]] = sext i1 [[TMP15]] to i1282204; CHECK-NEXT: [[TMP17:%.*]] = bitcast i128 [[TMP16]] to <8 x i16>2205; CHECK-NEXT: [[TMP18:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqrshl.v8i16(<8 x i16> [[_MSLD]], <8 x i16> [[TMP2]])2206; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP18]], [[TMP17]]2207; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqrshl.v8i16(<8 x i16> [[TMP1]], <8 x i16> [[TMP2]])2208; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 82209; CHECK-NEXT: ret <8 x i16> [[TMP3]]2210;2211 %tmp1 = load <8 x i16>, ptr %A2212 %tmp2 = load <8 x i16>, ptr %B2213 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqrshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)2214 ret <8 x i16> %tmp32215}2216 2217define <4 x i32> @sqrshl4s(ptr %A, ptr %B) nounwind sanitize_memory {2218; CHECK-LABEL: define <4 x i32> @sqrshl4s(2219; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2220; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82221; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82222; CHECK-NEXT: call void @llvm.donothing()2223; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02224; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]2225; CHECK: 3:2226; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2227; CHECK-NEXT: unreachable2228; CHECK: 4:2229; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 162230; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642231; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762232; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2233; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 162234; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02235; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2236; CHECK: 8:2237; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2238; CHECK-NEXT: unreachable2239; CHECK: 9:2240; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr [[B]], align 162241; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642242; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762243; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2244; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 162245; CHECK-NEXT: [[TMP13:%.*]] = bitcast <4 x i32> [[_MSLD1]] to i1282246; CHECK-NEXT: [[TMP14:%.*]] = trunc i128 [[TMP13]] to i642247; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[TMP14]], 02248; CHECK-NEXT: [[TMP16:%.*]] = sext i1 [[TMP15]] to i1282249; CHECK-NEXT: [[TMP17:%.*]] = bitcast i128 [[TMP16]] to <4 x i32>2250; CHECK-NEXT: [[TMP18:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqrshl.v4i32(<4 x i32> [[_MSLD]], <4 x i32> [[TMP2]])2251; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP18]], [[TMP17]]2252; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqrshl.v4i32(<4 x i32> [[TMP1]], <4 x i32> [[TMP2]])2253; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 82254; CHECK-NEXT: ret <4 x i32> [[TMP3]]2255;2256 %tmp1 = load <4 x i32>, ptr %A2257 %tmp2 = load <4 x i32>, ptr %B2258 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqrshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)2259 ret <4 x i32> %tmp32260}2261 2262define <2 x i64> @sqrshl2d(ptr %A, ptr %B) nounwind sanitize_memory {2263; CHECK-LABEL: define <2 x i64> @sqrshl2d(2264; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2265; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82266; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82267; CHECK-NEXT: call void @llvm.donothing()2268; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02269; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]2270; CHECK: 3:2271; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2272; CHECK-NEXT: unreachable2273; CHECK: 4:2274; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 162275; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642276; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762277; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2278; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 162279; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02280; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2281; CHECK: 8:2282; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2283; CHECK-NEXT: unreachable2284; CHECK: 9:2285; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr [[B]], align 162286; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642287; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762288; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2289; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 162290; CHECK-NEXT: [[TMP13:%.*]] = bitcast <2 x i64> [[_MSLD1]] to i1282291; CHECK-NEXT: [[TMP14:%.*]] = trunc i128 [[TMP13]] to i642292; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[TMP14]], 02293; CHECK-NEXT: [[TMP16:%.*]] = sext i1 [[TMP15]] to i1282294; CHECK-NEXT: [[TMP17:%.*]] = bitcast i128 [[TMP16]] to <2 x i64>2295; CHECK-NEXT: [[TMP18:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqrshl.v2i64(<2 x i64> [[_MSLD]], <2 x i64> [[TMP2]])2296; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP18]], [[TMP17]]2297; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqrshl.v2i64(<2 x i64> [[TMP1]], <2 x i64> [[TMP2]])2298; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 82299; CHECK-NEXT: ret <2 x i64> [[TMP3]]2300;2301 %tmp1 = load <2 x i64>, ptr %A2302 %tmp2 = load <2 x i64>, ptr %B2303 %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqrshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)2304 ret <2 x i64> %tmp32305}2306 2307define <1 x i64> @sqrshl1d(ptr %A, ptr %B) nounwind sanitize_memory {2308; CHECK-LABEL: define <1 x i64> @sqrshl1d(2309; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2310; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82311; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82312; CHECK-NEXT: call void @llvm.donothing()2313; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02314; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]2315; CHECK: 3:2316; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2317; CHECK-NEXT: unreachable2318; CHECK: 4:2319; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr [[A]], align 82320; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642321; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762322; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2323; CHECK-NEXT: [[_MSLD:%.*]] = load <1 x i64>, ptr [[TMP7]], align 82324; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02325; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2326; CHECK: 8:2327; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2328; CHECK-NEXT: unreachable2329; CHECK: 9:2330; CHECK-NEXT: [[TMP2:%.*]] = load <1 x i64>, ptr [[B]], align 82331; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642332; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762333; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2334; CHECK-NEXT: [[_MSLD1:%.*]] = load <1 x i64>, ptr [[TMP12]], align 82335; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[_MSLD1]] to i642336; CHECK-NEXT: [[TMP14:%.*]] = icmp ne i64 [[TMP13]], 02337; CHECK-NEXT: [[TMP15:%.*]] = sext i1 [[TMP14]] to i642338; CHECK-NEXT: [[TMP16:%.*]] = bitcast i64 [[TMP15]] to <1 x i64>2339; CHECK-NEXT: [[TMP17:%.*]] = call <1 x i64> @llvm.aarch64.neon.sqrshl.v1i64(<1 x i64> [[_MSLD]], <1 x i64> [[TMP2]])2340; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP17]], [[TMP16]]2341; CHECK-NEXT: [[TMP3:%.*]] = call <1 x i64> @llvm.aarch64.neon.sqrshl.v1i64(<1 x i64> [[TMP1]], <1 x i64> [[TMP2]])2342; CHECK-NEXT: store <1 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 82343; CHECK-NEXT: ret <1 x i64> [[TMP3]]2344;2345 %tmp1 = load <1 x i64>, ptr %A2346 %tmp2 = load <1 x i64>, ptr %B2347 %tmp3 = call <1 x i64> @llvm.aarch64.neon.sqrshl.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)2348 ret <1 x i64> %tmp32349}2350 2351define <1 x i64> @sqrshl1d_constant(ptr %A) nounwind sanitize_memory {2352; CHECK-LABEL: define <1 x i64> @sqrshl1d_constant(2353; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {2354; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82355; CHECK-NEXT: call void @llvm.donothing()2356; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02357; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]2358; CHECK: 2:2359; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2360; CHECK-NEXT: unreachable2361; CHECK: 3:2362; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr [[A]], align 82363; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i642364; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885762365; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr2366; CHECK-NEXT: [[_MSLD:%.*]] = load <1 x i64>, ptr [[TMP6]], align 82367; CHECK-NEXT: [[TMP7:%.*]] = call <1 x i64> @llvm.aarch64.neon.sqrshl.v1i64(<1 x i64> [[_MSLD]], <1 x i64> splat (i64 1))2368; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP7]], zeroinitializer2369; CHECK-NEXT: [[TMP3:%.*]] = call <1 x i64> @llvm.aarch64.neon.sqrshl.v1i64(<1 x i64> [[TMP1]], <1 x i64> splat (i64 1))2370; CHECK-NEXT: store <1 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 82371; CHECK-NEXT: ret <1 x i64> [[TMP3]]2372;2373 %tmp1 = load <1 x i64>, ptr %A2374 %tmp3 = call <1 x i64> @llvm.aarch64.neon.sqrshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 1>)2375 ret <1 x i64> %tmp32376}2377 2378define i64 @sqrshl_scalar(ptr %A, ptr %B) nounwind sanitize_memory {2379; CHECK-LABEL: define i64 @sqrshl_scalar(2380; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2381; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82382; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82383; CHECK-NEXT: call void @llvm.donothing()2384; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02385; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]2386; CHECK: 3:2387; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2388; CHECK-NEXT: unreachable2389; CHECK: 4:2390; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[A]], align 82391; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642392; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762393; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2394; CHECK-NEXT: [[_MSLD:%.*]] = load i64, ptr [[TMP7]], align 82395; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02396; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2397; CHECK: 8:2398; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2399; CHECK-NEXT: unreachable2400; CHECK: 9:2401; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[B]], align 82402; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642403; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762404; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2405; CHECK-NEXT: [[_MSLD1:%.*]] = load i64, ptr [[TMP12]], align 82406; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[_MSLD1]], 02407; CHECK-NEXT: [[TMP14:%.*]] = sext i1 [[TMP13]] to i642408; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.aarch64.neon.sqrshl.i64(i64 [[_MSLD]], i64 [[TMP2]])2409; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP15]], [[TMP14]]2410; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.sqrshl.i64(i64 [[TMP1]], i64 [[TMP2]])2411; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 82412; CHECK-NEXT: ret i64 [[TMP3]]2413;2414 %tmp1 = load i64, ptr %A2415 %tmp2 = load i64, ptr %B2416 %tmp3 = call i64 @llvm.aarch64.neon.sqrshl.i64(i64 %tmp1, i64 %tmp2)2417 ret i64 %tmp32418}2419 2420define i64 @sqrshl_scalar_constant(ptr %A) nounwind sanitize_memory {2421; CHECK-LABEL: define i64 @sqrshl_scalar_constant(2422; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {2423; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82424; CHECK-NEXT: call void @llvm.donothing()2425; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02426; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]2427; CHECK: 2:2428; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2429; CHECK-NEXT: unreachable2430; CHECK: 3:2431; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[A]], align 82432; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i642433; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885762434; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr2435; CHECK-NEXT: [[_MSLD:%.*]] = load i64, ptr [[TMP6]], align 82436; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.aarch64.neon.sqrshl.i64(i64 [[_MSLD]], i64 1)2437; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP7]], 02438; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.sqrshl.i64(i64 [[TMP1]], i64 1)2439; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 82440; CHECK-NEXT: ret i64 [[TMP3]]2441;2442 %tmp1 = load i64, ptr %A2443 %tmp3 = call i64 @llvm.aarch64.neon.sqrshl.i64(i64 %tmp1, i64 1)2444 ret i64 %tmp32445}2446 2447define <16 x i8> @uqrshl16b(ptr %A, ptr %B) nounwind sanitize_memory {2448; CHECK-LABEL: define <16 x i8> @uqrshl16b(2449; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2450; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82451; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82452; CHECK-NEXT: call void @llvm.donothing()2453; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02454; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]2455; CHECK: 3:2456; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2457; CHECK-NEXT: unreachable2458; CHECK: 4:2459; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[A]], align 162460; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642461; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762462; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2463; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP7]], align 162464; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02465; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2466; CHECK: 8:2467; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2468; CHECK-NEXT: unreachable2469; CHECK: 9:2470; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr [[B]], align 162471; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642472; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762473; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2474; CHECK-NEXT: [[_MSLD1:%.*]] = load <16 x i8>, ptr [[TMP12]], align 162475; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[_MSLD1]] to i1282476; CHECK-NEXT: [[TMP14:%.*]] = trunc i128 [[TMP13]] to i642477; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[TMP14]], 02478; CHECK-NEXT: [[TMP16:%.*]] = sext i1 [[TMP15]] to i1282479; CHECK-NEXT: [[TMP17:%.*]] = bitcast i128 [[TMP16]] to <16 x i8>2480; CHECK-NEXT: [[TMP18:%.*]] = call <16 x i8> @llvm.aarch64.neon.uqrshl.v16i8(<16 x i8> [[_MSLD]], <16 x i8> [[TMP2]])2481; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP18]], [[TMP17]]2482; CHECK-NEXT: [[TMP3:%.*]] = call <16 x i8> @llvm.aarch64.neon.uqrshl.v16i8(<16 x i8> [[TMP1]], <16 x i8> [[TMP2]])2483; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 82484; CHECK-NEXT: ret <16 x i8> [[TMP3]]2485;2486 %tmp1 = load <16 x i8>, ptr %A2487 %tmp2 = load <16 x i8>, ptr %B2488 %tmp3 = call <16 x i8> @llvm.aarch64.neon.uqrshl.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)2489 ret <16 x i8> %tmp32490}2491 2492define <8 x i16> @uqrshl8h(ptr %A, ptr %B) nounwind sanitize_memory {2493; CHECK-LABEL: define <8 x i16> @uqrshl8h(2494; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2495; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82496; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82497; CHECK-NEXT: call void @llvm.donothing()2498; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02499; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]2500; CHECK: 3:2501; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2502; CHECK-NEXT: unreachable2503; CHECK: 4:2504; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 162505; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642506; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762507; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2508; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 162509; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02510; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2511; CHECK: 8:2512; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2513; CHECK-NEXT: unreachable2514; CHECK: 9:2515; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr [[B]], align 162516; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642517; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762518; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2519; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 162520; CHECK-NEXT: [[TMP13:%.*]] = bitcast <8 x i16> [[_MSLD1]] to i1282521; CHECK-NEXT: [[TMP14:%.*]] = trunc i128 [[TMP13]] to i642522; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[TMP14]], 02523; CHECK-NEXT: [[TMP16:%.*]] = sext i1 [[TMP15]] to i1282524; CHECK-NEXT: [[TMP17:%.*]] = bitcast i128 [[TMP16]] to <8 x i16>2525; CHECK-NEXT: [[TMP18:%.*]] = call <8 x i16> @llvm.aarch64.neon.uqrshl.v8i16(<8 x i16> [[_MSLD]], <8 x i16> [[TMP2]])2526; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP18]], [[TMP17]]2527; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i16> @llvm.aarch64.neon.uqrshl.v8i16(<8 x i16> [[TMP1]], <8 x i16> [[TMP2]])2528; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 82529; CHECK-NEXT: ret <8 x i16> [[TMP3]]2530;2531 %tmp1 = load <8 x i16>, ptr %A2532 %tmp2 = load <8 x i16>, ptr %B2533 %tmp3 = call <8 x i16> @llvm.aarch64.neon.uqrshl.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)2534 ret <8 x i16> %tmp32535}2536 2537define <4 x i32> @uqrshl4s(ptr %A, ptr %B) nounwind sanitize_memory {2538; CHECK-LABEL: define <4 x i32> @uqrshl4s(2539; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2540; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82541; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82542; CHECK-NEXT: call void @llvm.donothing()2543; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02544; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]2545; CHECK: 3:2546; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2547; CHECK-NEXT: unreachable2548; CHECK: 4:2549; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 162550; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642551; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762552; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2553; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 162554; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02555; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2556; CHECK: 8:2557; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2558; CHECK-NEXT: unreachable2559; CHECK: 9:2560; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr [[B]], align 162561; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642562; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762563; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2564; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 162565; CHECK-NEXT: [[TMP13:%.*]] = bitcast <4 x i32> [[_MSLD1]] to i1282566; CHECK-NEXT: [[TMP14:%.*]] = trunc i128 [[TMP13]] to i642567; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[TMP14]], 02568; CHECK-NEXT: [[TMP16:%.*]] = sext i1 [[TMP15]] to i1282569; CHECK-NEXT: [[TMP17:%.*]] = bitcast i128 [[TMP16]] to <4 x i32>2570; CHECK-NEXT: [[TMP18:%.*]] = call <4 x i32> @llvm.aarch64.neon.uqrshl.v4i32(<4 x i32> [[_MSLD]], <4 x i32> [[TMP2]])2571; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP18]], [[TMP17]]2572; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.uqrshl.v4i32(<4 x i32> [[TMP1]], <4 x i32> [[TMP2]])2573; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 82574; CHECK-NEXT: ret <4 x i32> [[TMP3]]2575;2576 %tmp1 = load <4 x i32>, ptr %A2577 %tmp2 = load <4 x i32>, ptr %B2578 %tmp3 = call <4 x i32> @llvm.aarch64.neon.uqrshl.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)2579 ret <4 x i32> %tmp32580}2581 2582define <2 x i64> @uqrshl2d(ptr %A, ptr %B) nounwind sanitize_memory {2583; CHECK-LABEL: define <2 x i64> @uqrshl2d(2584; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2585; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82586; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82587; CHECK-NEXT: call void @llvm.donothing()2588; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02589; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]2590; CHECK: 3:2591; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2592; CHECK-NEXT: unreachable2593; CHECK: 4:2594; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 162595; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642596; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762597; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2598; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 162599; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02600; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2601; CHECK: 8:2602; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2603; CHECK-NEXT: unreachable2604; CHECK: 9:2605; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr [[B]], align 162606; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642607; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762608; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2609; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 162610; CHECK-NEXT: [[TMP13:%.*]] = bitcast <2 x i64> [[_MSLD1]] to i1282611; CHECK-NEXT: [[TMP14:%.*]] = trunc i128 [[TMP13]] to i642612; CHECK-NEXT: [[TMP15:%.*]] = icmp ne i64 [[TMP14]], 02613; CHECK-NEXT: [[TMP16:%.*]] = sext i1 [[TMP15]] to i1282614; CHECK-NEXT: [[TMP17:%.*]] = bitcast i128 [[TMP16]] to <2 x i64>2615; CHECK-NEXT: [[TMP18:%.*]] = call <2 x i64> @llvm.aarch64.neon.uqrshl.v2i64(<2 x i64> [[_MSLD]], <2 x i64> [[TMP2]])2616; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP18]], [[TMP17]]2617; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.uqrshl.v2i64(<2 x i64> [[TMP1]], <2 x i64> [[TMP2]])2618; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 82619; CHECK-NEXT: ret <2 x i64> [[TMP3]]2620;2621 %tmp1 = load <2 x i64>, ptr %A2622 %tmp2 = load <2 x i64>, ptr %B2623 %tmp3 = call <2 x i64> @llvm.aarch64.neon.uqrshl.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)2624 ret <2 x i64> %tmp32625}2626 2627define <1 x i64> @uqrshl1d(ptr %A, ptr %B) nounwind sanitize_memory {2628; CHECK-LABEL: define <1 x i64> @uqrshl1d(2629; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2630; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82631; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82632; CHECK-NEXT: call void @llvm.donothing()2633; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02634; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]2635; CHECK: 3:2636; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2637; CHECK-NEXT: unreachable2638; CHECK: 4:2639; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr [[A]], align 82640; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642641; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762642; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2643; CHECK-NEXT: [[_MSLD:%.*]] = load <1 x i64>, ptr [[TMP7]], align 82644; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02645; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2646; CHECK: 8:2647; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2648; CHECK-NEXT: unreachable2649; CHECK: 9:2650; CHECK-NEXT: [[TMP2:%.*]] = load <1 x i64>, ptr [[B]], align 82651; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642652; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762653; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2654; CHECK-NEXT: [[_MSLD1:%.*]] = load <1 x i64>, ptr [[TMP12]], align 82655; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[_MSLD1]] to i642656; CHECK-NEXT: [[TMP14:%.*]] = icmp ne i64 [[TMP13]], 02657; CHECK-NEXT: [[TMP15:%.*]] = sext i1 [[TMP14]] to i642658; CHECK-NEXT: [[TMP16:%.*]] = bitcast i64 [[TMP15]] to <1 x i64>2659; CHECK-NEXT: [[TMP17:%.*]] = call <1 x i64> @llvm.aarch64.neon.uqrshl.v1i64(<1 x i64> [[_MSLD]], <1 x i64> [[TMP2]])2660; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP17]], [[TMP16]]2661; CHECK-NEXT: [[TMP3:%.*]] = call <1 x i64> @llvm.aarch64.neon.uqrshl.v1i64(<1 x i64> [[TMP1]], <1 x i64> [[TMP2]])2662; CHECK-NEXT: store <1 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 82663; CHECK-NEXT: ret <1 x i64> [[TMP3]]2664;2665 %tmp1 = load <1 x i64>, ptr %A2666 %tmp2 = load <1 x i64>, ptr %B2667 %tmp3 = call <1 x i64> @llvm.aarch64.neon.uqrshl.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2)2668 ret <1 x i64> %tmp32669}2670 2671define <1 x i64> @uqrshl1d_constant(ptr %A) nounwind sanitize_memory {2672; CHECK-LABEL: define <1 x i64> @uqrshl1d_constant(2673; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {2674; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82675; CHECK-NEXT: call void @llvm.donothing()2676; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02677; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]2678; CHECK: 2:2679; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2680; CHECK-NEXT: unreachable2681; CHECK: 3:2682; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr [[A]], align 82683; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i642684; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885762685; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr2686; CHECK-NEXT: [[_MSLD:%.*]] = load <1 x i64>, ptr [[TMP6]], align 82687; CHECK-NEXT: [[TMP7:%.*]] = call <1 x i64> @llvm.aarch64.neon.uqrshl.v1i64(<1 x i64> [[_MSLD]], <1 x i64> splat (i64 1))2688; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP7]], zeroinitializer2689; CHECK-NEXT: [[TMP3:%.*]] = call <1 x i64> @llvm.aarch64.neon.uqrshl.v1i64(<1 x i64> [[TMP1]], <1 x i64> splat (i64 1))2690; CHECK-NEXT: store <1 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 82691; CHECK-NEXT: ret <1 x i64> [[TMP3]]2692;2693 %tmp1 = load <1 x i64>, ptr %A2694 %tmp3 = call <1 x i64> @llvm.aarch64.neon.uqrshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 1>)2695 ret <1 x i64> %tmp32696}2697 2698define i64 @uqrshl_scalar(ptr %A, ptr %B) nounwind sanitize_memory {2699; CHECK-LABEL: define i64 @uqrshl_scalar(2700; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {2701; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82702; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 82703; CHECK-NEXT: call void @llvm.donothing()2704; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02705; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]2706; CHECK: 3:2707; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2708; CHECK-NEXT: unreachable2709; CHECK: 4:2710; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[A]], align 82711; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i642712; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885762713; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr2714; CHECK-NEXT: [[_MSLD:%.*]] = load i64, ptr [[TMP7]], align 82715; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 02716; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]2717; CHECK: 8:2718; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2719; CHECK-NEXT: unreachable2720; CHECK: 9:2721; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[B]], align 82722; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i642723; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885762724; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr2725; CHECK-NEXT: [[_MSLD1:%.*]] = load i64, ptr [[TMP12]], align 82726; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i64 [[_MSLD1]], 02727; CHECK-NEXT: [[TMP14:%.*]] = sext i1 [[TMP13]] to i642728; CHECK-NEXT: [[TMP15:%.*]] = call i64 @llvm.aarch64.neon.uqrshl.i64(i64 [[_MSLD]], i64 [[TMP2]])2729; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP15]], [[TMP14]]2730; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.uqrshl.i64(i64 [[TMP1]], i64 [[TMP2]])2731; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 82732; CHECK-NEXT: ret i64 [[TMP3]]2733;2734 %tmp1 = load i64, ptr %A2735 %tmp2 = load i64, ptr %B2736 %tmp3 = call i64 @llvm.aarch64.neon.uqrshl.i64(i64 %tmp1, i64 %tmp2)2737 ret i64 %tmp32738}2739 2740define i64 @uqrshl_scalar_constant(ptr %A) nounwind sanitize_memory {2741; CHECK-LABEL: define i64 @uqrshl_scalar_constant(2742; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {2743; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82744; CHECK-NEXT: call void @llvm.donothing()2745; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02746; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]2747; CHECK: 2:2748; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2749; CHECK-NEXT: unreachable2750; CHECK: 3:2751; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[A]], align 82752; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i642753; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885762754; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr2755; CHECK-NEXT: [[_MSLD:%.*]] = load i64, ptr [[TMP6]], align 82756; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.aarch64.neon.uqrshl.i64(i64 [[_MSLD]], i64 1)2757; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP7]], 02758; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.uqrshl.i64(i64 [[TMP1]], i64 1)2759; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 82760; CHECK-NEXT: ret i64 [[TMP3]]2761;2762 %tmp1 = load i64, ptr %A2763 %tmp3 = call i64 @llvm.aarch64.neon.uqrshl.i64(i64 %tmp1, i64 1)2764 ret i64 %tmp32765}2766 2767declare <8 x i8> @llvm.aarch64.neon.sqrshl.v8i8(<8 x i8>, <8 x i8>) nounwind readnone2768declare <4 x i16> @llvm.aarch64.neon.sqrshl.v4i16(<4 x i16>, <4 x i16>) nounwind readnone2769declare <2 x i32> @llvm.aarch64.neon.sqrshl.v2i32(<2 x i32>, <2 x i32>) nounwind readnone2770declare <1 x i64> @llvm.aarch64.neon.sqrshl.v1i64(<1 x i64>, <1 x i64>) nounwind readnone2771declare i64 @llvm.aarch64.neon.sqrshl.i64(i64, i64) nounwind readnone2772 2773declare <8 x i8> @llvm.aarch64.neon.uqrshl.v8i8(<8 x i8>, <8 x i8>) nounwind readnone2774declare <4 x i16> @llvm.aarch64.neon.uqrshl.v4i16(<4 x i16>, <4 x i16>) nounwind readnone2775declare <2 x i32> @llvm.aarch64.neon.uqrshl.v2i32(<2 x i32>, <2 x i32>) nounwind readnone2776declare <1 x i64> @llvm.aarch64.neon.uqrshl.v1i64(<1 x i64>, <1 x i64>) nounwind readnone2777declare i64 @llvm.aarch64.neon.uqrshl.i64(i64, i64) nounwind readnone2778 2779declare <16 x i8> @llvm.aarch64.neon.sqrshl.v16i8(<16 x i8>, <16 x i8>) nounwind readnone2780declare <8 x i16> @llvm.aarch64.neon.sqrshl.v8i16(<8 x i16>, <8 x i16>) nounwind readnone2781declare <4 x i32> @llvm.aarch64.neon.sqrshl.v4i32(<4 x i32>, <4 x i32>) nounwind readnone2782declare <2 x i64> @llvm.aarch64.neon.sqrshl.v2i64(<2 x i64>, <2 x i64>) nounwind readnone2783 2784declare <16 x i8> @llvm.aarch64.neon.uqrshl.v16i8(<16 x i8>, <16 x i8>) nounwind readnone2785declare <8 x i16> @llvm.aarch64.neon.uqrshl.v8i16(<8 x i16>, <8 x i16>) nounwind readnone2786declare <4 x i32> @llvm.aarch64.neon.uqrshl.v4i32(<4 x i32>, <4 x i32>) nounwind readnone2787declare <2 x i64> @llvm.aarch64.neon.uqrshl.v2i64(<2 x i64>, <2 x i64>) nounwind readnone2788 2789define <8 x i8> @urshr8b(ptr %A) nounwind sanitize_memory {2790; CHECK-LABEL: define <8 x i8> @urshr8b(2791; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {2792; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82793; CHECK-NEXT: call void @llvm.donothing()2794; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02795; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]2796; CHECK: 2:2797; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2798; CHECK-NEXT: unreachable2799; CHECK: 3:2800; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[A]], align 82801; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i642802; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885762803; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr2804; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP6]], align 82805; CHECK-NEXT: [[TMP7:%.*]] = call <8 x i8> @llvm.aarch64.neon.urshl.v8i8(<8 x i8> [[_MSLD]], <8 x i8> splat (i8 -1))2806; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i8> [[TMP7]], zeroinitializer2807; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.urshl.v8i8(<8 x i8> [[TMP1]], <8 x i8> splat (i8 -1))2808; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 82809; CHECK-NEXT: ret <8 x i8> [[TMP3]]2810;2811 %tmp1 = load <8 x i8>, ptr %A2812 %tmp3 = call <8 x i8> @llvm.aarch64.neon.urshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)2813 ret <8 x i8> %tmp32814}2815 2816define <4 x i16> @urshr4h(ptr %A) nounwind sanitize_memory {2817; CHECK-LABEL: define <4 x i16> @urshr4h(2818; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {2819; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82820; CHECK-NEXT: call void @llvm.donothing()2821; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02822; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]2823; CHECK: 2:2824; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2825; CHECK-NEXT: unreachable2826; CHECK: 3:2827; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 82828; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i642829; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885762830; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr2831; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP6]], align 82832; CHECK-NEXT: [[TMP7:%.*]] = call <4 x i16> @llvm.aarch64.neon.urshl.v4i16(<4 x i16> [[_MSLD]], <4 x i16> splat (i16 -1))2833; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[TMP7]], zeroinitializer2834; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.urshl.v4i16(<4 x i16> [[TMP1]], <4 x i16> splat (i16 -1))2835; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 82836; CHECK-NEXT: ret <4 x i16> [[TMP3]]2837;2838 %tmp1 = load <4 x i16>, ptr %A2839 %tmp3 = call <4 x i16> @llvm.aarch64.neon.urshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>)2840 ret <4 x i16> %tmp32841}2842 2843define <2 x i32> @urshr2s(ptr %A) nounwind sanitize_memory {2844; CHECK-LABEL: define <2 x i32> @urshr2s(2845; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {2846; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82847; CHECK-NEXT: call void @llvm.donothing()2848; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02849; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]2850; CHECK: 2:2851; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2852; CHECK-NEXT: unreachable2853; CHECK: 3:2854; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 82855; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i642856; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885762857; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr2858; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP6]], align 82859; CHECK-NEXT: [[TMP7:%.*]] = call <2 x i32> @llvm.aarch64.neon.urshl.v2i32(<2 x i32> [[_MSLD]], <2 x i32> splat (i32 -1))2860; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[TMP7]], zeroinitializer2861; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.urshl.v2i32(<2 x i32> [[TMP1]], <2 x i32> splat (i32 -1))2862; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 82863; CHECK-NEXT: ret <2 x i32> [[TMP3]]2864;2865 %tmp1 = load <2 x i32>, ptr %A2866 %tmp3 = call <2 x i32> @llvm.aarch64.neon.urshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 -1, i32 -1>)2867 ret <2 x i32> %tmp32868}2869 2870define <16 x i8> @urshr16b(ptr %A) nounwind sanitize_memory {2871; CHECK-LABEL: define <16 x i8> @urshr16b(2872; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {2873; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82874; CHECK-NEXT: call void @llvm.donothing()2875; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02876; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]2877; CHECK: 2:2878; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2879; CHECK-NEXT: unreachable2880; CHECK: 3:2881; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[A]], align 162882; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i642883; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885762884; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr2885; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP6]], align 162886; CHECK-NEXT: [[TMP7:%.*]] = call <16 x i8> @llvm.aarch64.neon.urshl.v16i8(<16 x i8> [[_MSLD]], <16 x i8> splat (i8 -1))2887; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP7]], zeroinitializer2888; CHECK-NEXT: [[TMP3:%.*]] = call <16 x i8> @llvm.aarch64.neon.urshl.v16i8(<16 x i8> [[TMP1]], <16 x i8> splat (i8 -1))2889; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 82890; CHECK-NEXT: ret <16 x i8> [[TMP3]]2891;2892 %tmp1 = load <16 x i8>, ptr %A2893 %tmp3 = call <16 x i8> @llvm.aarch64.neon.urshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)2894 ret <16 x i8> %tmp32895}2896 2897define <8 x i16> @urshr8h(ptr %A) nounwind sanitize_memory {2898; CHECK-LABEL: define <8 x i16> @urshr8h(2899; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {2900; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82901; CHECK-NEXT: call void @llvm.donothing()2902; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02903; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]2904; CHECK: 2:2905; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2906; CHECK-NEXT: unreachable2907; CHECK: 3:2908; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 162909; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i642910; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885762911; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr2912; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP6]], align 162913; CHECK-NEXT: [[TMP7:%.*]] = call <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16> [[_MSLD]], <8 x i16> splat (i16 -1))2914; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP7]], zeroinitializer2915; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16> [[TMP1]], <8 x i16> splat (i16 -1))2916; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 82917; CHECK-NEXT: ret <8 x i16> [[TMP3]]2918;2919 %tmp1 = load <8 x i16>, ptr %A2920 %tmp3 = call <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>)2921 ret <8 x i16> %tmp32922}2923 2924define <4 x i32> @urshr4s(ptr %A) nounwind sanitize_memory {2925; CHECK-LABEL: define <4 x i32> @urshr4s(2926; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {2927; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82928; CHECK-NEXT: call void @llvm.donothing()2929; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02930; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]2931; CHECK: 2:2932; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2933; CHECK-NEXT: unreachable2934; CHECK: 3:2935; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 162936; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i642937; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885762938; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr2939; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP6]], align 162940; CHECK-NEXT: [[TMP7:%.*]] = call <4 x i32> @llvm.aarch64.neon.urshl.v4i32(<4 x i32> [[_MSLD]], <4 x i32> splat (i32 -1))2941; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP7]], zeroinitializer2942; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.urshl.v4i32(<4 x i32> [[TMP1]], <4 x i32> splat (i32 -1))2943; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 82944; CHECK-NEXT: ret <4 x i32> [[TMP3]]2945;2946 %tmp1 = load <4 x i32>, ptr %A2947 %tmp3 = call <4 x i32> @llvm.aarch64.neon.urshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)2948 ret <4 x i32> %tmp32949}2950 2951define <2 x i64> @urshr2d(ptr %A) nounwind sanitize_memory {2952; CHECK-LABEL: define <2 x i64> @urshr2d(2953; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {2954; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82955; CHECK-NEXT: call void @llvm.donothing()2956; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02957; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]2958; CHECK: 2:2959; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2960; CHECK-NEXT: unreachable2961; CHECK: 3:2962; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 162963; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i642964; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885762965; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr2966; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP6]], align 162967; CHECK-NEXT: [[TMP7:%.*]] = call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> [[_MSLD]], <2 x i64> splat (i64 -1))2968; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP7]], zeroinitializer2969; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> [[TMP1]], <2 x i64> splat (i64 -1))2970; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 82971; CHECK-NEXT: ret <2 x i64> [[TMP3]]2972;2973 %tmp1 = load <2 x i64>, ptr %A2974 %tmp3 = call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 -1, i64 -1>)2975 ret <2 x i64> %tmp32976}2977 2978define <1 x i64> @urshr1d(ptr %A) nounwind sanitize_memory {2979; CHECK-LABEL: define <1 x i64> @urshr1d(2980; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {2981; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 82982; CHECK-NEXT: call void @llvm.donothing()2983; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 02984; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]2985; CHECK: 2:2986; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]2987; CHECK-NEXT: unreachable2988; CHECK: 3:2989; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr [[A]], align 82990; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i642991; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885762992; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr2993; CHECK-NEXT: [[_MSLD:%.*]] = load <1 x i64>, ptr [[TMP6]], align 82994; CHECK-NEXT: [[TMP7:%.*]] = call <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64> [[_MSLD]], <1 x i64> splat (i64 -1))2995; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP7]], zeroinitializer2996; CHECK-NEXT: [[TMP3:%.*]] = call <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64> [[TMP1]], <1 x i64> splat (i64 -1))2997; CHECK-NEXT: store <1 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 82998; CHECK-NEXT: ret <1 x i64> [[TMP3]]2999;3000 %tmp1 = load <1 x i64>, ptr %A3001 %tmp3 = call <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 -1>)3002 ret <1 x i64> %tmp33003}3004 3005define i64 @urshr_scalar(ptr %A) nounwind sanitize_memory {3006; CHECK-LABEL: define i64 @urshr_scalar(3007; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {3008; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83009; CHECK-NEXT: call void @llvm.donothing()3010; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03011; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]3012; CHECK: 2:3013; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3014; CHECK-NEXT: unreachable3015; CHECK: 3:3016; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[A]], align 83017; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i643018; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885763019; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr3020; CHECK-NEXT: [[_MSLD:%.*]] = load i64, ptr [[TMP6]], align 83021; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.aarch64.neon.urshl.i64(i64 [[_MSLD]], i64 -1)3022; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP7]], 03023; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.urshl.i64(i64 [[TMP1]], i64 -1)3024; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 83025; CHECK-NEXT: ret i64 [[TMP3]]3026;3027 %tmp1 = load i64, ptr %A3028 %tmp3 = call i64 @llvm.aarch64.neon.urshl.i64(i64 %tmp1, i64 -1)3029 ret i64 %tmp33030}3031 3032define <8 x i8> @srshr8b(ptr %A) nounwind sanitize_memory {3033; CHECK-LABEL: define <8 x i8> @srshr8b(3034; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {3035; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83036; CHECK-NEXT: call void @llvm.donothing()3037; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03038; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]3039; CHECK: 2:3040; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3041; CHECK-NEXT: unreachable3042; CHECK: 3:3043; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[A]], align 83044; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i643045; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885763046; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr3047; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP6]], align 83048; CHECK-NEXT: [[TMP7:%.*]] = call <8 x i8> @llvm.aarch64.neon.srshl.v8i8(<8 x i8> [[_MSLD]], <8 x i8> splat (i8 -1))3049; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i8> [[TMP7]], zeroinitializer3050; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.srshl.v8i8(<8 x i8> [[TMP1]], <8 x i8> splat (i8 -1))3051; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 83052; CHECK-NEXT: ret <8 x i8> [[TMP3]]3053;3054 %tmp1 = load <8 x i8>, ptr %A3055 %tmp3 = call <8 x i8> @llvm.aarch64.neon.srshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)3056 ret <8 x i8> %tmp33057}3058 3059define <4 x i16> @srshr4h(ptr %A) nounwind sanitize_memory {3060; CHECK-LABEL: define <4 x i16> @srshr4h(3061; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {3062; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83063; CHECK-NEXT: call void @llvm.donothing()3064; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03065; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]3066; CHECK: 2:3067; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3068; CHECK-NEXT: unreachable3069; CHECK: 3:3070; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 83071; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i643072; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885763073; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr3074; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP6]], align 83075; CHECK-NEXT: [[TMP7:%.*]] = call <4 x i16> @llvm.aarch64.neon.srshl.v4i16(<4 x i16> [[_MSLD]], <4 x i16> splat (i16 -1))3076; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[TMP7]], zeroinitializer3077; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.srshl.v4i16(<4 x i16> [[TMP1]], <4 x i16> splat (i16 -1))3078; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 83079; CHECK-NEXT: ret <4 x i16> [[TMP3]]3080;3081 %tmp1 = load <4 x i16>, ptr %A3082 %tmp3 = call <4 x i16> @llvm.aarch64.neon.srshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>)3083 ret <4 x i16> %tmp33084}3085 3086define <2 x i32> @srshr2s(ptr %A) nounwind sanitize_memory {3087; CHECK-LABEL: define <2 x i32> @srshr2s(3088; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {3089; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83090; CHECK-NEXT: call void @llvm.donothing()3091; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03092; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]3093; CHECK: 2:3094; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3095; CHECK-NEXT: unreachable3096; CHECK: 3:3097; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 83098; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i643099; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885763100; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr3101; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP6]], align 83102; CHECK-NEXT: [[TMP7:%.*]] = call <2 x i32> @llvm.aarch64.neon.srshl.v2i32(<2 x i32> [[_MSLD]], <2 x i32> splat (i32 -1))3103; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[TMP7]], zeroinitializer3104; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.srshl.v2i32(<2 x i32> [[TMP1]], <2 x i32> splat (i32 -1))3105; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 83106; CHECK-NEXT: ret <2 x i32> [[TMP3]]3107;3108 %tmp1 = load <2 x i32>, ptr %A3109 %tmp3 = call <2 x i32> @llvm.aarch64.neon.srshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 -1, i32 -1>)3110 ret <2 x i32> %tmp33111}3112 3113define <16 x i8> @srshr16b(ptr %A) nounwind sanitize_memory {3114; CHECK-LABEL: define <16 x i8> @srshr16b(3115; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {3116; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83117; CHECK-NEXT: call void @llvm.donothing()3118; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03119; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]3120; CHECK: 2:3121; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3122; CHECK-NEXT: unreachable3123; CHECK: 3:3124; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[A]], align 163125; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i643126; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885763127; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr3128; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP6]], align 163129; CHECK-NEXT: [[TMP7:%.*]] = call <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8> [[_MSLD]], <16 x i8> splat (i8 -1))3130; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP7]], zeroinitializer3131; CHECK-NEXT: [[TMP3:%.*]] = call <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8> [[TMP1]], <16 x i8> splat (i8 -1))3132; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 83133; CHECK-NEXT: ret <16 x i8> [[TMP3]]3134;3135 %tmp1 = load <16 x i8>, ptr %A3136 %tmp3 = call <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)3137 ret <16 x i8> %tmp33138}3139 3140define <8 x i16> @srshr8h(ptr %A) nounwind sanitize_memory {3141; CHECK-LABEL: define <8 x i16> @srshr8h(3142; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {3143; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83144; CHECK-NEXT: call void @llvm.donothing()3145; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03146; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]3147; CHECK: 2:3148; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3149; CHECK-NEXT: unreachable3150; CHECK: 3:3151; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 163152; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i643153; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885763154; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr3155; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP6]], align 163156; CHECK-NEXT: [[TMP7:%.*]] = call <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16> [[_MSLD]], <8 x i16> splat (i16 -1))3157; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP7]], zeroinitializer3158; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16> [[TMP1]], <8 x i16> splat (i16 -1))3159; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 83160; CHECK-NEXT: ret <8 x i16> [[TMP3]]3161;3162 %tmp1 = load <8 x i16>, ptr %A3163 %tmp3 = call <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>)3164 ret <8 x i16> %tmp33165}3166 3167define <4 x i32> @srshr4s(ptr %A) nounwind sanitize_memory {3168; CHECK-LABEL: define <4 x i32> @srshr4s(3169; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {3170; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83171; CHECK-NEXT: call void @llvm.donothing()3172; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03173; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]3174; CHECK: 2:3175; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3176; CHECK-NEXT: unreachable3177; CHECK: 3:3178; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 163179; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i643180; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885763181; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr3182; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP6]], align 163183; CHECK-NEXT: [[TMP7:%.*]] = call <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32> [[_MSLD]], <4 x i32> splat (i32 -1))3184; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP7]], zeroinitializer3185; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32> [[TMP1]], <4 x i32> splat (i32 -1))3186; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 83187; CHECK-NEXT: ret <4 x i32> [[TMP3]]3188;3189 %tmp1 = load <4 x i32>, ptr %A3190 %tmp3 = call <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)3191 ret <4 x i32> %tmp33192}3193 3194define <2 x i64> @srshr2d(ptr %A) nounwind sanitize_memory {3195; CHECK-LABEL: define <2 x i64> @srshr2d(3196; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {3197; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83198; CHECK-NEXT: call void @llvm.donothing()3199; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03200; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]3201; CHECK: 2:3202; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3203; CHECK-NEXT: unreachable3204; CHECK: 3:3205; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 163206; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i643207; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885763208; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr3209; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP6]], align 163210; CHECK-NEXT: [[TMP7:%.*]] = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> [[_MSLD]], <2 x i64> splat (i64 -1))3211; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP7]], zeroinitializer3212; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> [[TMP1]], <2 x i64> splat (i64 -1))3213; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 83214; CHECK-NEXT: ret <2 x i64> [[TMP3]]3215;3216 %tmp1 = load <2 x i64>, ptr %A3217 %tmp3 = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 -1, i64 -1>)3218 ret <2 x i64> %tmp33219}3220 3221define <1 x i64> @srshr1d(ptr %A) nounwind sanitize_memory {3222; CHECK-LABEL: define <1 x i64> @srshr1d(3223; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {3224; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83225; CHECK-NEXT: call void @llvm.donothing()3226; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03227; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]3228; CHECK: 2:3229; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3230; CHECK-NEXT: unreachable3231; CHECK: 3:3232; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr [[A]], align 83233; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i643234; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885763235; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr3236; CHECK-NEXT: [[_MSLD:%.*]] = load <1 x i64>, ptr [[TMP6]], align 83237; CHECK-NEXT: [[TMP7:%.*]] = call <1 x i64> @llvm.aarch64.neon.srshl.v1i64(<1 x i64> [[_MSLD]], <1 x i64> splat (i64 -1))3238; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP7]], zeroinitializer3239; CHECK-NEXT: [[TMP3:%.*]] = call <1 x i64> @llvm.aarch64.neon.srshl.v1i64(<1 x i64> [[TMP1]], <1 x i64> splat (i64 -1))3240; CHECK-NEXT: store <1 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 83241; CHECK-NEXT: ret <1 x i64> [[TMP3]]3242;3243 %tmp1 = load <1 x i64>, ptr %A3244 %tmp3 = call <1 x i64> @llvm.aarch64.neon.srshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 -1>)3245 ret <1 x i64> %tmp33246}3247 3248define i64 @srshr_scalar(ptr %A) nounwind sanitize_memory {3249; CHECK-LABEL: define i64 @srshr_scalar(3250; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {3251; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83252; CHECK-NEXT: call void @llvm.donothing()3253; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03254; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]3255; CHECK: 2:3256; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3257; CHECK-NEXT: unreachable3258; CHECK: 3:3259; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[A]], align 83260; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i643261; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885763262; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr3263; CHECK-NEXT: [[_MSLD:%.*]] = load i64, ptr [[TMP6]], align 83264; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.aarch64.neon.srshl.i64(i64 [[_MSLD]], i64 -1)3265; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP7]], 03266; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.srshl.i64(i64 [[TMP1]], i64 -1)3267; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 83268; CHECK-NEXT: ret i64 [[TMP3]]3269;3270 %tmp1 = load i64, ptr %A3271 %tmp3 = call i64 @llvm.aarch64.neon.srshl.i64(i64 %tmp1, i64 -1)3272 ret i64 %tmp33273}3274 3275define <8 x i8> @sqshlu8b(ptr %A) nounwind sanitize_memory {3276; CHECK-LABEL: define <8 x i8> @sqshlu8b(3277; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {3278; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83279; CHECK-NEXT: call void @llvm.donothing()3280; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03281; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]3282; CHECK: 2:3283; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3284; CHECK-NEXT: unreachable3285; CHECK: 3:3286; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[A]], align 83287; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i643288; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885763289; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr3290; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP6]], align 83291; CHECK-NEXT: [[TMP7:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshlu.v8i8(<8 x i8> [[_MSLD]], <8 x i8> splat (i8 1))3292; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i8> [[TMP7]], zeroinitializer3293; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshlu.v8i8(<8 x i8> [[TMP1]], <8 x i8> splat (i8 1))3294; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 83295; CHECK-NEXT: ret <8 x i8> [[TMP3]]3296;3297 %tmp1 = load <8 x i8>, ptr %A3298 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshlu.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)3299 ret <8 x i8> %tmp33300}3301 3302define <4 x i16> @sqshlu4h(ptr %A) nounwind sanitize_memory {3303; CHECK-LABEL: define <4 x i16> @sqshlu4h(3304; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {3305; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83306; CHECK-NEXT: call void @llvm.donothing()3307; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03308; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]3309; CHECK: 2:3310; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3311; CHECK-NEXT: unreachable3312; CHECK: 3:3313; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 83314; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i643315; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885763316; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr3317; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP6]], align 83318; CHECK-NEXT: [[TMP7:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshlu.v4i16(<4 x i16> [[_MSLD]], <4 x i16> splat (i16 1))3319; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[TMP7]], zeroinitializer3320; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshlu.v4i16(<4 x i16> [[TMP1]], <4 x i16> splat (i16 1))3321; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 83322; CHECK-NEXT: ret <4 x i16> [[TMP3]]3323;3324 %tmp1 = load <4 x i16>, ptr %A3325 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshlu.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 1, i16 1, i16 1, i16 1>)3326 ret <4 x i16> %tmp33327}3328 3329define <2 x i32> @sqshlu2s(ptr %A) nounwind sanitize_memory {3330; CHECK-LABEL: define <2 x i32> @sqshlu2s(3331; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {3332; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83333; CHECK-NEXT: call void @llvm.donothing()3334; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03335; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]3336; CHECK: 2:3337; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3338; CHECK-NEXT: unreachable3339; CHECK: 3:3340; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 83341; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i643342; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885763343; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr3344; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP6]], align 83345; CHECK-NEXT: [[TMP7:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshlu.v2i32(<2 x i32> [[_MSLD]], <2 x i32> splat (i32 1))3346; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[TMP7]], zeroinitializer3347; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshlu.v2i32(<2 x i32> [[TMP1]], <2 x i32> splat (i32 1))3348; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 83349; CHECK-NEXT: ret <2 x i32> [[TMP3]]3350;3351 %tmp1 = load <2 x i32>, ptr %A3352 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshlu.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 1, i32 1>)3353 ret <2 x i32> %tmp33354}3355 3356define <16 x i8> @sqshlu16b(ptr %A) nounwind sanitize_memory {3357; CHECK-LABEL: define <16 x i8> @sqshlu16b(3358; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {3359; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83360; CHECK-NEXT: call void @llvm.donothing()3361; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03362; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]3363; CHECK: 2:3364; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3365; CHECK-NEXT: unreachable3366; CHECK: 3:3367; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[A]], align 163368; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i643369; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885763370; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr3371; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP6]], align 163372; CHECK-NEXT: [[TMP7:%.*]] = call <16 x i8> @llvm.aarch64.neon.sqshlu.v16i8(<16 x i8> [[_MSLD]], <16 x i8> splat (i8 1))3373; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP7]], zeroinitializer3374; CHECK-NEXT: [[TMP3:%.*]] = call <16 x i8> @llvm.aarch64.neon.sqshlu.v16i8(<16 x i8> [[TMP1]], <16 x i8> splat (i8 1))3375; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 83376; CHECK-NEXT: ret <16 x i8> [[TMP3]]3377;3378 %tmp1 = load <16 x i8>, ptr %A3379 %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqshlu.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)3380 ret <16 x i8> %tmp33381}3382 3383define <8 x i16> @sqshlu8h(ptr %A) nounwind sanitize_memory {3384; CHECK-LABEL: define <8 x i16> @sqshlu8h(3385; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {3386; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83387; CHECK-NEXT: call void @llvm.donothing()3388; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03389; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]3390; CHECK: 2:3391; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3392; CHECK-NEXT: unreachable3393; CHECK: 3:3394; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 163395; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i643396; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885763397; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr3398; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP6]], align 163399; CHECK-NEXT: [[TMP7:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqshlu.v8i16(<8 x i16> [[_MSLD]], <8 x i16> splat (i16 1))3400; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP7]], zeroinitializer3401; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqshlu.v8i16(<8 x i16> [[TMP1]], <8 x i16> splat (i16 1))3402; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 83403; CHECK-NEXT: ret <8 x i16> [[TMP3]]3404;3405 %tmp1 = load <8 x i16>, ptr %A3406 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqshlu.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)3407 ret <8 x i16> %tmp33408}3409 3410define <4 x i32> @sqshlu4s(ptr %A) nounwind sanitize_memory {3411; CHECK-LABEL: define <4 x i32> @sqshlu4s(3412; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {3413; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83414; CHECK-NEXT: call void @llvm.donothing()3415; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03416; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]3417; CHECK: 2:3418; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3419; CHECK-NEXT: unreachable3420; CHECK: 3:3421; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 163422; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i643423; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885763424; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr3425; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP6]], align 163426; CHECK-NEXT: [[TMP7:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqshlu.v4i32(<4 x i32> [[_MSLD]], <4 x i32> splat (i32 1))3427; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP7]], zeroinitializer3428; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqshlu.v4i32(<4 x i32> [[TMP1]], <4 x i32> splat (i32 1))3429; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 83430; CHECK-NEXT: ret <4 x i32> [[TMP3]]3431;3432 %tmp1 = load <4 x i32>, ptr %A3433 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqshlu.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)3434 ret <4 x i32> %tmp33435}3436 3437define <2 x i64> @sqshlu2d(ptr %A) nounwind sanitize_memory {3438; CHECK-LABEL: define <2 x i64> @sqshlu2d(3439; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {3440; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83441; CHECK-NEXT: call void @llvm.donothing()3442; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03443; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]3444; CHECK: 2:3445; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3446; CHECK-NEXT: unreachable3447; CHECK: 3:3448; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 163449; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i643450; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885763451; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr3452; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP6]], align 163453; CHECK-NEXT: [[TMP7:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqshlu.v2i64(<2 x i64> [[_MSLD]], <2 x i64> splat (i64 1))3454; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP7]], zeroinitializer3455; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqshlu.v2i64(<2 x i64> [[TMP1]], <2 x i64> splat (i64 1))3456; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 83457; CHECK-NEXT: ret <2 x i64> [[TMP3]]3458;3459 %tmp1 = load <2 x i64>, ptr %A3460 %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqshlu.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 1, i64 1>)3461 ret <2 x i64> %tmp33462}3463 3464define <1 x i64> @sqshlu1d_constant(ptr %A) nounwind sanitize_memory {3465; CHECK-LABEL: define <1 x i64> @sqshlu1d_constant(3466; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {3467; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83468; CHECK-NEXT: call void @llvm.donothing()3469; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03470; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]3471; CHECK: 2:3472; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3473; CHECK-NEXT: unreachable3474; CHECK: 3:3475; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr [[A]], align 83476; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i643477; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885763478; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr3479; CHECK-NEXT: [[_MSLD:%.*]] = load <1 x i64>, ptr [[TMP6]], align 83480; CHECK-NEXT: [[TMP7:%.*]] = call <1 x i64> @llvm.aarch64.neon.sqshlu.v1i64(<1 x i64> [[_MSLD]], <1 x i64> splat (i64 1))3481; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP7]], zeroinitializer3482; CHECK-NEXT: [[TMP3:%.*]] = call <1 x i64> @llvm.aarch64.neon.sqshlu.v1i64(<1 x i64> [[TMP1]], <1 x i64> splat (i64 1))3483; CHECK-NEXT: store <1 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 83484; CHECK-NEXT: ret <1 x i64> [[TMP3]]3485;3486 %tmp1 = load <1 x i64>, ptr %A3487 %tmp3 = call <1 x i64> @llvm.aarch64.neon.sqshlu.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 1>)3488 ret <1 x i64> %tmp33489}3490 3491define i64 @sqshlu_i64_constant(ptr %A) nounwind sanitize_memory {3492; CHECK-LABEL: define i64 @sqshlu_i64_constant(3493; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {3494; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83495; CHECK-NEXT: call void @llvm.donothing()3496; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03497; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]3498; CHECK: 2:3499; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3500; CHECK-NEXT: unreachable3501; CHECK: 3:3502; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[A]], align 83503; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i643504; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885763505; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr3506; CHECK-NEXT: [[_MSLD:%.*]] = load i64, ptr [[TMP6]], align 83507; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.aarch64.neon.sqshlu.i64(i64 [[_MSLD]], i64 1)3508; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP7]], 03509; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.sqshlu.i64(i64 [[TMP1]], i64 1)3510; CHECK-NEXT: store i64 [[_MSPROP]], ptr @__msan_retval_tls, align 83511; CHECK-NEXT: ret i64 [[TMP3]]3512;3513 %tmp1 = load i64, ptr %A3514 %tmp3 = call i64 @llvm.aarch64.neon.sqshlu.i64(i64 %tmp1, i64 1)3515 ret i64 %tmp33516}3517 3518define i32 @sqshlu_i32_constant(ptr %A) nounwind sanitize_memory {3519; CHECK-LABEL: define i32 @sqshlu_i32_constant(3520; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {3521; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83522; CHECK-NEXT: call void @llvm.donothing()3523; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03524; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]3525; CHECK: 2:3526; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3527; CHECK-NEXT: unreachable3528; CHECK: 3:3529; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 43530; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i643531; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885763532; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr3533; CHECK-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP6]], align 43534; CHECK-NEXT: [[TMP7:%.*]] = call i32 @llvm.aarch64.neon.sqshlu.i32(i32 [[_MSLD]], i32 1)3535; CHECK-NEXT: [[_MSPROP:%.*]] = or i32 [[TMP7]], 03536; CHECK-NEXT: [[TMP3:%.*]] = call i32 @llvm.aarch64.neon.sqshlu.i32(i32 [[TMP1]], i32 1)3537; CHECK-NEXT: store i32 [[_MSPROP]], ptr @__msan_retval_tls, align 83538; CHECK-NEXT: ret i32 [[TMP3]]3539;3540 %tmp1 = load i32, ptr %A3541 %tmp3 = call i32 @llvm.aarch64.neon.sqshlu.i32(i32 %tmp1, i32 1)3542 ret i32 %tmp33543}3544 3545declare <8 x i8> @llvm.aarch64.neon.sqshlu.v8i8(<8 x i8>, <8 x i8>) nounwind readnone3546declare <4 x i16> @llvm.aarch64.neon.sqshlu.v4i16(<4 x i16>, <4 x i16>) nounwind readnone3547declare <2 x i32> @llvm.aarch64.neon.sqshlu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone3548declare <1 x i64> @llvm.aarch64.neon.sqshlu.v1i64(<1 x i64>, <1 x i64>) nounwind readnone3549declare i64 @llvm.aarch64.neon.sqshlu.i64(i64, i64) nounwind readnone3550declare i32 @llvm.aarch64.neon.sqshlu.i32(i32, i32) nounwind readnone3551 3552declare <16 x i8> @llvm.aarch64.neon.sqshlu.v16i8(<16 x i8>, <16 x i8>) nounwind readnone3553declare <8 x i16> @llvm.aarch64.neon.sqshlu.v8i16(<8 x i16>, <8 x i16>) nounwind readnone3554declare <4 x i32> @llvm.aarch64.neon.sqshlu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone3555declare <2 x i64> @llvm.aarch64.neon.sqshlu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone3556 3557define <8 x i8> @rshrn8b(ptr %A) nounwind sanitize_memory {3558; CHECK-LABEL: define <8 x i8> @rshrn8b(3559; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {3560; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83561; CHECK-NEXT: call void @llvm.donothing()3562; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03563; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]3564; CHECK: 2:3565; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3566; CHECK-NEXT: unreachable3567; CHECK: 3:3568; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 163569; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i643570; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885763571; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr3572; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP6]], align 163573; CHECK-NEXT: [[TMP7:%.*]] = call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> [[_MSLD]], i32 1)3574; CHECK-NEXT: [[TMP8:%.*]] = or <8 x i8> [[TMP7]], zeroinitializer3575; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> [[TMP1]], i32 1)3576; CHECK-NEXT: store <8 x i8> [[TMP8]], ptr @__msan_retval_tls, align 83577; CHECK-NEXT: ret <8 x i8> [[TMP3]]3578;3579 %tmp1 = load <8 x i16>, ptr %A3580 %tmp3 = call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> %tmp1, i32 1)3581 ret <8 x i8> %tmp33582}3583 3584define <4 x i16> @rshrn4h(ptr %A) nounwind sanitize_memory {3585; CHECK-LABEL: define <4 x i16> @rshrn4h(3586; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {3587; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83588; CHECK-NEXT: call void @llvm.donothing()3589; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03590; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]3591; CHECK: 2:3592; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3593; CHECK-NEXT: unreachable3594; CHECK: 3:3595; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 163596; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i643597; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885763598; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr3599; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP6]], align 163600; CHECK-NEXT: [[TMP7:%.*]] = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> [[_MSLD]], i32 1)3601; CHECK-NEXT: [[TMP8:%.*]] = or <4 x i16> [[TMP7]], zeroinitializer3602; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> [[TMP1]], i32 1)3603; CHECK-NEXT: store <4 x i16> [[TMP8]], ptr @__msan_retval_tls, align 83604; CHECK-NEXT: ret <4 x i16> [[TMP3]]3605;3606 %tmp1 = load <4 x i32>, ptr %A3607 %tmp3 = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> %tmp1, i32 1)3608 ret <4 x i16> %tmp33609}3610 3611define <2 x i32> @rshrn2s(ptr %A) nounwind sanitize_memory {3612; CHECK-LABEL: define <2 x i32> @rshrn2s(3613; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {3614; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83615; CHECK-NEXT: call void @llvm.donothing()3616; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03617; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]3618; CHECK: 2:3619; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3620; CHECK-NEXT: unreachable3621; CHECK: 3:3622; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 163623; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i643624; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885763625; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr3626; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP6]], align 163627; CHECK-NEXT: [[TMP7:%.*]] = call <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64> [[_MSLD]], i32 1)3628; CHECK-NEXT: [[TMP8:%.*]] = or <2 x i32> [[TMP7]], zeroinitializer3629; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64> [[TMP1]], i32 1)3630; CHECK-NEXT: store <2 x i32> [[TMP8]], ptr @__msan_retval_tls, align 83631; CHECK-NEXT: ret <2 x i32> [[TMP3]]3632;3633 %tmp1 = load <2 x i64>, ptr %A3634 %tmp3 = call <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64> %tmp1, i32 1)3635 ret <2 x i32> %tmp33636}3637 3638define <16 x i8> @rshrn16b(ptr %ret, ptr %A) nounwind sanitize_memory {3639; CHECK-LABEL: define <16 x i8> @rshrn16b(3640; CHECK-SAME: ptr [[RET:%.*]], ptr [[A:%.*]]) #[[ATTR0]] {3641; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83642; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83643; CHECK-NEXT: call void @llvm.donothing()3644; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03645; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]3646; CHECK: 3:3647; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3648; CHECK-NEXT: unreachable3649; CHECK: 4:3650; CHECK-NEXT: [[OUT:%.*]] = load <8 x i8>, ptr [[RET]], align 83651; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[RET]] to i643652; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885763653; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr3654; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 83655; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 03656; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]3657; CHECK: 8:3658; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3659; CHECK-NEXT: unreachable3660; CHECK: 9:3661; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 163662; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[A]] to i643663; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885763664; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr3665; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 163666; CHECK-NEXT: [[TMP13:%.*]] = call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> [[_MSLD1]], i32 1)3667; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i8> [[TMP13]], zeroinitializer3668; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> [[TMP1]], i32 1)3669; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i8> [[_MSLD]], <8 x i8> [[TMP14]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>3670; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x i8> [[OUT]], <8 x i8> [[TMP3]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>3671; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 83672; CHECK-NEXT: ret <16 x i8> [[TMP4]]3673;3674 %out = load <8 x i8>, ptr %ret3675 %tmp1 = load <8 x i16>, ptr %A3676 %tmp3 = call <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16> %tmp1, i32 1)3677 %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>3678 ret <16 x i8> %tmp43679}3680 3681define <8 x i16> @rshrn8h(ptr %ret, ptr %A) nounwind sanitize_memory {3682; CHECK-LABEL: define <8 x i16> @rshrn8h(3683; CHECK-SAME: ptr [[RET:%.*]], ptr [[A:%.*]]) #[[ATTR0]] {3684; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83685; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83686; CHECK-NEXT: call void @llvm.donothing()3687; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03688; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]3689; CHECK: 3:3690; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3691; CHECK-NEXT: unreachable3692; CHECK: 4:3693; CHECK-NEXT: [[OUT:%.*]] = load <4 x i16>, ptr [[RET]], align 83694; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[RET]] to i643695; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885763696; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr3697; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 83698; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 03699; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]3700; CHECK: 8:3701; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3702; CHECK-NEXT: unreachable3703; CHECK: 9:3704; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 163705; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[A]] to i643706; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885763707; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr3708; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 163709; CHECK-NEXT: [[TMP13:%.*]] = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> [[_MSLD1]], i32 1)3710; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i16> [[TMP13]], zeroinitializer3711; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> [[TMP1]], i32 1)3712; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i16> [[_MSLD]], <4 x i16> [[TMP14]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>3713; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i16> [[OUT]], <4 x i16> [[TMP3]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>3714; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 83715; CHECK-NEXT: ret <8 x i16> [[TMP4]]3716;3717 %out = load <4 x i16>, ptr %ret3718 %tmp1 = load <4 x i32>, ptr %A3719 %tmp3 = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> %tmp1, i32 1)3720 %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>3721 ret <8 x i16> %tmp43722}3723 3724define <4 x i32> @rshrn4s(ptr %ret, ptr %A) nounwind sanitize_memory {3725; CHECK-LABEL: define <4 x i32> @rshrn4s(3726; CHECK-SAME: ptr [[RET:%.*]], ptr [[A:%.*]]) #[[ATTR0]] {3727; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83728; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83729; CHECK-NEXT: call void @llvm.donothing()3730; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03731; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]3732; CHECK: 3:3733; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3734; CHECK-NEXT: unreachable3735; CHECK: 4:3736; CHECK-NEXT: [[OUT:%.*]] = load <2 x i32>, ptr [[RET]], align 83737; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[RET]] to i643738; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885763739; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr3740; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 83741; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 03742; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]3743; CHECK: 8:3744; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3745; CHECK-NEXT: unreachable3746; CHECK: 9:3747; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 163748; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[A]] to i643749; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885763750; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr3751; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 163752; CHECK-NEXT: [[TMP13:%.*]] = call <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64> [[_MSLD1]], i32 1)3753; CHECK-NEXT: [[TMP14:%.*]] = or <2 x i32> [[TMP13]], zeroinitializer3754; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64> [[TMP1]], i32 1)3755; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i32> [[_MSLD]], <2 x i32> [[TMP14]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>3756; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[OUT]], <2 x i32> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>3757; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 83758; CHECK-NEXT: ret <4 x i32> [[TMP4]]3759;3760 %out = load <2 x i32>, ptr %ret3761 %tmp1 = load <2 x i64>, ptr %A3762 %tmp3 = call <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64> %tmp1, i32 1)3763 %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>3764 ret <4 x i32> %tmp43765}3766 3767declare <8 x i8> @llvm.aarch64.neon.rshrn.v8i8(<8 x i16>, i32) nounwind readnone3768declare <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32>, i32) nounwind readnone3769declare <2 x i32> @llvm.aarch64.neon.rshrn.v2i32(<2 x i64>, i32) nounwind readnone3770 3771define <8 x i8> @shrn8b(ptr %A) nounwind sanitize_memory {3772; CHECK-LABEL: define <8 x i8> @shrn8b(3773; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {3774; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83775; CHECK-NEXT: call void @llvm.donothing()3776; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03777; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]3778; CHECK: 2:3779; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3780; CHECK-NEXT: unreachable3781; CHECK: 3:3782; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 163783; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i643784; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885763785; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr3786; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP6]], align 163787; CHECK-NEXT: [[TMP7:%.*]] = lshr <8 x i16> [[_MSLD]], splat (i16 1)3788; CHECK-NEXT: [[TMP8:%.*]] = or <8 x i16> [[TMP7]], zeroinitializer3789; CHECK-NEXT: [[TMP2:%.*]] = lshr <8 x i16> [[TMP1]], splat (i16 1)3790; CHECK-NEXT: [[_MSPROP:%.*]] = trunc <8 x i16> [[TMP8]] to <8 x i8>3791; CHECK-NEXT: [[TMP3:%.*]] = trunc <8 x i16> [[TMP2]] to <8 x i8>3792; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 83793; CHECK-NEXT: ret <8 x i8> [[TMP3]]3794;3795 %tmp1 = load <8 x i16>, ptr %A3796 %tmp2 = lshr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>3797 %tmp3 = trunc <8 x i16> %tmp2 to <8 x i8>3798 ret <8 x i8> %tmp33799}3800 3801define <4 x i16> @shrn4h(ptr %A) nounwind sanitize_memory {3802; CHECK-LABEL: define <4 x i16> @shrn4h(3803; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {3804; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83805; CHECK-NEXT: call void @llvm.donothing()3806; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03807; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]3808; CHECK: 2:3809; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3810; CHECK-NEXT: unreachable3811; CHECK: 3:3812; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 163813; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i643814; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885763815; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr3816; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP6]], align 163817; CHECK-NEXT: [[TMP7:%.*]] = lshr <4 x i32> [[_MSLD]], splat (i32 1)3818; CHECK-NEXT: [[TMP8:%.*]] = or <4 x i32> [[TMP7]], zeroinitializer3819; CHECK-NEXT: [[TMP2:%.*]] = lshr <4 x i32> [[TMP1]], splat (i32 1)3820; CHECK-NEXT: [[_MSPROP:%.*]] = trunc <4 x i32> [[TMP8]] to <4 x i16>3821; CHECK-NEXT: [[TMP3:%.*]] = trunc <4 x i32> [[TMP2]] to <4 x i16>3822; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 83823; CHECK-NEXT: ret <4 x i16> [[TMP3]]3824;3825 %tmp1 = load <4 x i32>, ptr %A3826 %tmp2 = lshr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>3827 %tmp3 = trunc <4 x i32> %tmp2 to <4 x i16>3828 ret <4 x i16> %tmp33829}3830 3831define <2 x i32> @shrn2s(ptr %A) nounwind sanitize_memory {3832; CHECK-LABEL: define <2 x i32> @shrn2s(3833; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {3834; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83835; CHECK-NEXT: call void @llvm.donothing()3836; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03837; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]3838; CHECK: 2:3839; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3840; CHECK-NEXT: unreachable3841; CHECK: 3:3842; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 163843; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i643844; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885763845; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr3846; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP6]], align 163847; CHECK-NEXT: [[TMP7:%.*]] = lshr <2 x i64> [[_MSLD]], splat (i64 1)3848; CHECK-NEXT: [[TMP8:%.*]] = or <2 x i64> [[TMP7]], zeroinitializer3849; CHECK-NEXT: [[TMP2:%.*]] = lshr <2 x i64> [[TMP1]], splat (i64 1)3850; CHECK-NEXT: [[_MSPROP:%.*]] = trunc <2 x i64> [[TMP8]] to <2 x i32>3851; CHECK-NEXT: [[TMP3:%.*]] = trunc <2 x i64> [[TMP2]] to <2 x i32>3852; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 83853; CHECK-NEXT: ret <2 x i32> [[TMP3]]3854;3855 %tmp1 = load <2 x i64>, ptr %A3856 %tmp2 = lshr <2 x i64> %tmp1, <i64 1, i64 1>3857 %tmp3 = trunc <2 x i64> %tmp2 to <2 x i32>3858 ret <2 x i32> %tmp33859}3860 3861define <16 x i8> @shrn16b(ptr %ret, ptr %A) nounwind sanitize_memory {3862; CHECK-LABEL: define <16 x i8> @shrn16b(3863; CHECK-SAME: ptr [[RET:%.*]], ptr [[A:%.*]]) #[[ATTR0]] {3864; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83865; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83866; CHECK-NEXT: call void @llvm.donothing()3867; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03868; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]3869; CHECK: 3:3870; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3871; CHECK-NEXT: unreachable3872; CHECK: 4:3873; CHECK-NEXT: [[OUT:%.*]] = load <8 x i8>, ptr [[RET]], align 83874; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[RET]] to i643875; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885763876; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr3877; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 83878; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 03879; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]3880; CHECK: 8:3881; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3882; CHECK-NEXT: unreachable3883; CHECK: 9:3884; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 163885; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[A]] to i643886; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885763887; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr3888; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 163889; CHECK-NEXT: [[TMP13:%.*]] = lshr <8 x i16> [[_MSLD1]], splat (i16 1)3890; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i16> [[TMP13]], zeroinitializer3891; CHECK-NEXT: [[TMP2:%.*]] = lshr <8 x i16> [[TMP1]], splat (i16 1)3892; CHECK-NEXT: [[_MSPROP:%.*]] = trunc <8 x i16> [[TMP14]] to <8 x i8>3893; CHECK-NEXT: [[TMP3:%.*]] = trunc <8 x i16> [[TMP2]] to <8 x i8>3894; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <8 x i8> [[_MSLD]], <8 x i8> [[_MSPROP]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>3895; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x i8> [[OUT]], <8 x i8> [[TMP3]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>3896; CHECK-NEXT: store <16 x i8> [[_MSPROP2]], ptr @__msan_retval_tls, align 83897; CHECK-NEXT: ret <16 x i8> [[TMP4]]3898;3899 %out = load <8 x i8>, ptr %ret3900 %tmp1 = load <8 x i16>, ptr %A3901 %tmp2 = lshr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>3902 %tmp3 = trunc <8 x i16> %tmp2 to <8 x i8>3903 %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>3904 ret <16 x i8> %tmp43905}3906 3907define <8 x i16> @shrn8h(ptr %ret, ptr %A) nounwind sanitize_memory {3908; CHECK-LABEL: define <8 x i16> @shrn8h(3909; CHECK-SAME: ptr [[RET:%.*]], ptr [[A:%.*]]) #[[ATTR0]] {3910; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83911; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83912; CHECK-NEXT: call void @llvm.donothing()3913; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03914; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]3915; CHECK: 3:3916; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3917; CHECK-NEXT: unreachable3918; CHECK: 4:3919; CHECK-NEXT: [[OUT:%.*]] = load <4 x i16>, ptr [[RET]], align 83920; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[RET]] to i643921; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885763922; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr3923; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 83924; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 03925; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]3926; CHECK: 8:3927; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3928; CHECK-NEXT: unreachable3929; CHECK: 9:3930; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 163931; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[A]] to i643932; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885763933; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr3934; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 163935; CHECK-NEXT: [[TMP13:%.*]] = lshr <4 x i32> [[_MSLD1]], splat (i32 1)3936; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i32> [[TMP13]], zeroinitializer3937; CHECK-NEXT: [[TMP2:%.*]] = lshr <4 x i32> [[TMP1]], splat (i32 1)3938; CHECK-NEXT: [[_MSPROP:%.*]] = trunc <4 x i32> [[TMP14]] to <4 x i16>3939; CHECK-NEXT: [[TMP3:%.*]] = trunc <4 x i32> [[TMP2]] to <4 x i16>3940; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <4 x i16> [[_MSLD]], <4 x i16> [[_MSPROP]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>3941; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i16> [[OUT]], <4 x i16> [[TMP3]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>3942; CHECK-NEXT: store <8 x i16> [[_MSPROP2]], ptr @__msan_retval_tls, align 83943; CHECK-NEXT: ret <8 x i16> [[TMP4]]3944;3945 %out = load <4 x i16>, ptr %ret3946 %tmp1 = load <4 x i32>, ptr %A3947 %tmp2 = lshr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>3948 %tmp3 = trunc <4 x i32> %tmp2 to <4 x i16>3949 %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>3950 ret <8 x i16> %tmp43951}3952 3953define <4 x i32> @shrn4s(ptr %ret, ptr %A) nounwind sanitize_memory {3954; CHECK-LABEL: define <4 x i32> @shrn4s(3955; CHECK-SAME: ptr [[RET:%.*]], ptr [[A:%.*]]) #[[ATTR0]] {3956; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 83957; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 83958; CHECK-NEXT: call void @llvm.donothing()3959; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 03960; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]3961; CHECK: 3:3962; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3963; CHECK-NEXT: unreachable3964; CHECK: 4:3965; CHECK-NEXT: [[OUT:%.*]] = load <2 x i32>, ptr [[RET]], align 83966; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[RET]] to i643967; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885763968; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr3969; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 83970; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 03971; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]3972; CHECK: 8:3973; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]3974; CHECK-NEXT: unreachable3975; CHECK: 9:3976; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 163977; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[A]] to i643978; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885763979; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr3980; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 163981; CHECK-NEXT: [[TMP13:%.*]] = lshr <2 x i64> [[_MSLD1]], splat (i64 1)3982; CHECK-NEXT: [[TMP14:%.*]] = or <2 x i64> [[TMP13]], zeroinitializer3983; CHECK-NEXT: [[TMP2:%.*]] = lshr <2 x i64> [[TMP1]], splat (i64 1)3984; CHECK-NEXT: [[_MSPROP:%.*]] = trunc <2 x i64> [[TMP14]] to <2 x i32>3985; CHECK-NEXT: [[TMP3:%.*]] = trunc <2 x i64> [[TMP2]] to <2 x i32>3986; CHECK-NEXT: [[_MSPROP2:%.*]] = shufflevector <2 x i32> [[_MSLD]], <2 x i32> [[_MSPROP]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>3987; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[OUT]], <2 x i32> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>3988; CHECK-NEXT: store <4 x i32> [[_MSPROP2]], ptr @__msan_retval_tls, align 83989; CHECK-NEXT: ret <4 x i32> [[TMP4]]3990;3991 %out = load <2 x i32>, ptr %ret3992 %tmp1 = load <2 x i64>, ptr %A3993 %tmp2 = lshr <2 x i64> %tmp1, <i64 1, i64 1>3994 %tmp3 = trunc <2 x i64> %tmp2 to <2 x i32>3995 %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>3996 ret <4 x i32> %tmp43997}3998 3999declare <8 x i8> @llvm.aarch64.neon.shrn.v8i8(<8 x i16>, i32) nounwind readnone4000declare <4 x i16> @llvm.aarch64.neon.shrn.v4i16(<4 x i32>, i32) nounwind readnone4001declare <2 x i32> @llvm.aarch64.neon.shrn.v2i32(<2 x i64>, i32) nounwind readnone4002 4003define i32 @sqshrn1s(i64 %A) nounwind sanitize_memory {4004; CHECK-LABEL: define i32 @sqshrn1s(4005; CHECK-SAME: i64 [[A:%.*]]) #[[ATTR0]] {4006; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84007; CHECK-NEXT: call void @llvm.donothing()4008; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.aarch64.neon.sqshrn.i32(i64 [[TMP1]], i32 1)4009; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP2]], 04010; CHECK-NEXT: [[TMP:%.*]] = call i32 @llvm.aarch64.neon.sqshrn.i32(i64 [[A]], i32 1)4011; CHECK-NEXT: store i32 [[TMP3]], ptr @__msan_retval_tls, align 84012; CHECK-NEXT: ret i32 [[TMP]]4013;4014 %tmp = call i32 @llvm.aarch64.neon.sqshrn.i32(i64 %A, i32 1)4015 ret i32 %tmp4016}4017 4018define <8 x i8> @sqshrn8b(ptr %A) nounwind sanitize_memory {4019; CHECK-LABEL: define <8 x i8> @sqshrn8b(4020; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {4021; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84022; CHECK-NEXT: call void @llvm.donothing()4023; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04024; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]4025; CHECK: 2:4026; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4027; CHECK-NEXT: unreachable4028; CHECK: 3:4029; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 164030; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i644031; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885764032; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr4033; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP6]], align 164034; CHECK-NEXT: [[TMP7:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshrn.v8i8(<8 x i16> [[_MSLD]], i32 1)4035; CHECK-NEXT: [[TMP8:%.*]] = or <8 x i8> [[TMP7]], zeroinitializer4036; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshrn.v8i8(<8 x i16> [[TMP1]], i32 1)4037; CHECK-NEXT: store <8 x i8> [[TMP8]], ptr @__msan_retval_tls, align 84038; CHECK-NEXT: ret <8 x i8> [[TMP3]]4039;4040 %tmp1 = load <8 x i16>, ptr %A4041 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshrn.v8i8(<8 x i16> %tmp1, i32 1)4042 ret <8 x i8> %tmp34043}4044 4045define <4 x i16> @sqshrn4h(ptr %A) nounwind sanitize_memory {4046; CHECK-LABEL: define <4 x i16> @sqshrn4h(4047; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {4048; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84049; CHECK-NEXT: call void @llvm.donothing()4050; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04051; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]4052; CHECK: 2:4053; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4054; CHECK-NEXT: unreachable4055; CHECK: 3:4056; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 164057; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i644058; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885764059; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr4060; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP6]], align 164061; CHECK-NEXT: [[TMP7:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> [[_MSLD]], i32 1)4062; CHECK-NEXT: [[TMP8:%.*]] = or <4 x i16> [[TMP7]], zeroinitializer4063; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> [[TMP1]], i32 1)4064; CHECK-NEXT: store <4 x i16> [[TMP8]], ptr @__msan_retval_tls, align 84065; CHECK-NEXT: ret <4 x i16> [[TMP3]]4066;4067 %tmp1 = load <4 x i32>, ptr %A4068 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> %tmp1, i32 1)4069 ret <4 x i16> %tmp34070}4071 4072define <2 x i32> @sqshrn2s(ptr %A) nounwind sanitize_memory {4073; CHECK-LABEL: define <2 x i32> @sqshrn2s(4074; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {4075; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84076; CHECK-NEXT: call void @llvm.donothing()4077; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04078; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]4079; CHECK: 2:4080; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4081; CHECK-NEXT: unreachable4082; CHECK: 3:4083; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 164084; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i644085; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885764086; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr4087; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP6]], align 164088; CHECK-NEXT: [[TMP7:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshrn.v2i32(<2 x i64> [[_MSLD]], i32 1)4089; CHECK-NEXT: [[TMP8:%.*]] = or <2 x i32> [[TMP7]], zeroinitializer4090; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshrn.v2i32(<2 x i64> [[TMP1]], i32 1)4091; CHECK-NEXT: store <2 x i32> [[TMP8]], ptr @__msan_retval_tls, align 84092; CHECK-NEXT: ret <2 x i32> [[TMP3]]4093;4094 %tmp1 = load <2 x i64>, ptr %A4095 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshrn.v2i32(<2 x i64> %tmp1, i32 1)4096 ret <2 x i32> %tmp34097}4098 4099 4100define <16 x i8> @sqshrn16b(ptr %ret, ptr %A) nounwind sanitize_memory {4101; CHECK-LABEL: define <16 x i8> @sqshrn16b(4102; CHECK-SAME: ptr [[RET:%.*]], ptr [[A:%.*]]) #[[ATTR0]] {4103; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84104; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 84105; CHECK-NEXT: call void @llvm.donothing()4106; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04107; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]4108; CHECK: 3:4109; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4110; CHECK-NEXT: unreachable4111; CHECK: 4:4112; CHECK-NEXT: [[OUT:%.*]] = load <8 x i8>, ptr [[RET]], align 84113; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[RET]] to i644114; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885764115; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr4116; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 84117; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 04118; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]4119; CHECK: 8:4120; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4121; CHECK-NEXT: unreachable4122; CHECK: 9:4123; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 164124; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[A]] to i644125; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885764126; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr4127; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 164128; CHECK-NEXT: [[TMP13:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshrn.v8i8(<8 x i16> [[_MSLD1]], i32 1)4129; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i8> [[TMP13]], zeroinitializer4130; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshrn.v8i8(<8 x i16> [[TMP1]], i32 1)4131; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i8> [[_MSLD]], <8 x i8> [[TMP14]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>4132; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x i8> [[OUT]], <8 x i8> [[TMP3]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>4133; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 84134; CHECK-NEXT: ret <16 x i8> [[TMP4]]4135;4136 %out = load <8 x i8>, ptr %ret4137 %tmp1 = load <8 x i16>, ptr %A4138 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshrn.v8i8(<8 x i16> %tmp1, i32 1)4139 %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>4140 ret <16 x i8> %tmp44141}4142 4143define <8 x i16> @sqshrn8h(ptr %ret, ptr %A) nounwind sanitize_memory {4144; CHECK-LABEL: define <8 x i16> @sqshrn8h(4145; CHECK-SAME: ptr [[RET:%.*]], ptr [[A:%.*]]) #[[ATTR0]] {4146; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84147; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 84148; CHECK-NEXT: call void @llvm.donothing()4149; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04150; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]4151; CHECK: 3:4152; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4153; CHECK-NEXT: unreachable4154; CHECK: 4:4155; CHECK-NEXT: [[OUT:%.*]] = load <4 x i16>, ptr [[RET]], align 84156; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[RET]] to i644157; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885764158; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr4159; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 84160; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 04161; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]4162; CHECK: 8:4163; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4164; CHECK-NEXT: unreachable4165; CHECK: 9:4166; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 164167; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[A]] to i644168; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885764169; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr4170; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 164171; CHECK-NEXT: [[TMP13:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> [[_MSLD1]], i32 1)4172; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i16> [[TMP13]], zeroinitializer4173; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> [[TMP1]], i32 1)4174; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i16> [[_MSLD]], <4 x i16> [[TMP14]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>4175; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i16> [[OUT]], <4 x i16> [[TMP3]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>4176; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 84177; CHECK-NEXT: ret <8 x i16> [[TMP4]]4178;4179 %out = load <4 x i16>, ptr %ret4180 %tmp1 = load <4 x i32>, ptr %A4181 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32> %tmp1, i32 1)4182 %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>4183 ret <8 x i16> %tmp44184}4185 4186define <4 x i32> @sqshrn4s(ptr %ret, ptr %A) nounwind sanitize_memory {4187; CHECK-LABEL: define <4 x i32> @sqshrn4s(4188; CHECK-SAME: ptr [[RET:%.*]], ptr [[A:%.*]]) #[[ATTR0]] {4189; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84190; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 84191; CHECK-NEXT: call void @llvm.donothing()4192; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04193; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]4194; CHECK: 3:4195; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4196; CHECK-NEXT: unreachable4197; CHECK: 4:4198; CHECK-NEXT: [[OUT:%.*]] = load <2 x i32>, ptr [[RET]], align 84199; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[RET]] to i644200; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885764201; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr4202; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 84203; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 04204; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]4205; CHECK: 8:4206; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4207; CHECK-NEXT: unreachable4208; CHECK: 9:4209; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 164210; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[A]] to i644211; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885764212; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr4213; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 164214; CHECK-NEXT: [[TMP13:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshrn.v2i32(<2 x i64> [[_MSLD1]], i32 1)4215; CHECK-NEXT: [[TMP14:%.*]] = or <2 x i32> [[TMP13]], zeroinitializer4216; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshrn.v2i32(<2 x i64> [[TMP1]], i32 1)4217; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i32> [[_MSLD]], <2 x i32> [[TMP14]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>4218; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[OUT]], <2 x i32> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>4219; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 84220; CHECK-NEXT: ret <4 x i32> [[TMP4]]4221;4222 %out = load <2 x i32>, ptr %ret4223 %tmp1 = load <2 x i64>, ptr %A4224 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshrn.v2i32(<2 x i64> %tmp1, i32 1)4225 %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>4226 ret <4 x i32> %tmp44227}4228 4229declare i32 @llvm.aarch64.neon.sqshrn.i32(i64, i32) nounwind readnone4230declare <8 x i8> @llvm.aarch64.neon.sqshrn.v8i8(<8 x i16>, i32) nounwind readnone4231declare <4 x i16> @llvm.aarch64.neon.sqshrn.v4i16(<4 x i32>, i32) nounwind readnone4232declare <2 x i32> @llvm.aarch64.neon.sqshrn.v2i32(<2 x i64>, i32) nounwind readnone4233 4234define i32 @sqshrun1s(i64 %A) nounwind sanitize_memory {4235; CHECK-LABEL: define i32 @sqshrun1s(4236; CHECK-SAME: i64 [[A:%.*]]) #[[ATTR0]] {4237; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84238; CHECK-NEXT: call void @llvm.donothing()4239; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.aarch64.neon.sqshrun.i32(i64 [[TMP1]], i32 1)4240; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP2]], 04241; CHECK-NEXT: [[TMP:%.*]] = call i32 @llvm.aarch64.neon.sqshrun.i32(i64 [[A]], i32 1)4242; CHECK-NEXT: store i32 [[TMP3]], ptr @__msan_retval_tls, align 84243; CHECK-NEXT: ret i32 [[TMP]]4244;4245 %tmp = call i32 @llvm.aarch64.neon.sqshrun.i32(i64 %A, i32 1)4246 ret i32 %tmp4247}4248 4249define <8 x i8> @sqshrun8b(ptr %A) nounwind sanitize_memory {4250; CHECK-LABEL: define <8 x i8> @sqshrun8b(4251; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {4252; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84253; CHECK-NEXT: call void @llvm.donothing()4254; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04255; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]4256; CHECK: 2:4257; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4258; CHECK-NEXT: unreachable4259; CHECK: 3:4260; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 164261; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i644262; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885764263; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr4264; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP6]], align 164265; CHECK-NEXT: [[TMP7:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshrun.v8i8(<8 x i16> [[_MSLD]], i32 1)4266; CHECK-NEXT: [[TMP8:%.*]] = or <8 x i8> [[TMP7]], zeroinitializer4267; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshrun.v8i8(<8 x i16> [[TMP1]], i32 1)4268; CHECK-NEXT: store <8 x i8> [[TMP8]], ptr @__msan_retval_tls, align 84269; CHECK-NEXT: ret <8 x i8> [[TMP3]]4270;4271 %tmp1 = load <8 x i16>, ptr %A4272 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshrun.v8i8(<8 x i16> %tmp1, i32 1)4273 ret <8 x i8> %tmp34274}4275 4276define <4 x i16> @sqshrun4h(ptr %A) nounwind sanitize_memory {4277; CHECK-LABEL: define <4 x i16> @sqshrun4h(4278; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {4279; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84280; CHECK-NEXT: call void @llvm.donothing()4281; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04282; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]4283; CHECK: 2:4284; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4285; CHECK-NEXT: unreachable4286; CHECK: 3:4287; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 164288; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i644289; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885764290; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr4291; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP6]], align 164292; CHECK-NEXT: [[TMP7:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16(<4 x i32> [[_MSLD]], i32 1)4293; CHECK-NEXT: [[TMP8:%.*]] = or <4 x i16> [[TMP7]], zeroinitializer4294; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16(<4 x i32> [[TMP1]], i32 1)4295; CHECK-NEXT: store <4 x i16> [[TMP8]], ptr @__msan_retval_tls, align 84296; CHECK-NEXT: ret <4 x i16> [[TMP3]]4297;4298 %tmp1 = load <4 x i32>, ptr %A4299 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16(<4 x i32> %tmp1, i32 1)4300 ret <4 x i16> %tmp34301}4302 4303define <2 x i32> @sqshrun2s(ptr %A) nounwind sanitize_memory {4304; CHECK-LABEL: define <2 x i32> @sqshrun2s(4305; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {4306; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84307; CHECK-NEXT: call void @llvm.donothing()4308; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04309; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]4310; CHECK: 2:4311; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4312; CHECK-NEXT: unreachable4313; CHECK: 3:4314; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 164315; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i644316; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885764317; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr4318; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP6]], align 164319; CHECK-NEXT: [[TMP7:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshrun.v2i32(<2 x i64> [[_MSLD]], i32 1)4320; CHECK-NEXT: [[TMP8:%.*]] = or <2 x i32> [[TMP7]], zeroinitializer4321; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshrun.v2i32(<2 x i64> [[TMP1]], i32 1)4322; CHECK-NEXT: store <2 x i32> [[TMP8]], ptr @__msan_retval_tls, align 84323; CHECK-NEXT: ret <2 x i32> [[TMP3]]4324;4325 %tmp1 = load <2 x i64>, ptr %A4326 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshrun.v2i32(<2 x i64> %tmp1, i32 1)4327 ret <2 x i32> %tmp34328}4329 4330define <16 x i8> @sqshrun16b(ptr %ret, ptr %A) nounwind sanitize_memory {4331; CHECK-LABEL: define <16 x i8> @sqshrun16b(4332; CHECK-SAME: ptr [[RET:%.*]], ptr [[A:%.*]]) #[[ATTR0]] {4333; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84334; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 84335; CHECK-NEXT: call void @llvm.donothing()4336; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04337; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]4338; CHECK: 3:4339; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4340; CHECK-NEXT: unreachable4341; CHECK: 4:4342; CHECK-NEXT: [[OUT:%.*]] = load <8 x i8>, ptr [[RET]], align 84343; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[RET]] to i644344; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885764345; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr4346; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 84347; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 04348; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]4349; CHECK: 8:4350; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4351; CHECK-NEXT: unreachable4352; CHECK: 9:4353; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 164354; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[A]] to i644355; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885764356; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr4357; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 164358; CHECK-NEXT: [[TMP13:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshrun.v8i8(<8 x i16> [[_MSLD1]], i32 1)4359; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i8> [[TMP13]], zeroinitializer4360; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshrun.v8i8(<8 x i16> [[TMP1]], i32 1)4361; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i8> [[_MSLD]], <8 x i8> [[TMP14]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>4362; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x i8> [[OUT]], <8 x i8> [[TMP3]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>4363; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 84364; CHECK-NEXT: ret <16 x i8> [[TMP4]]4365;4366 %out = load <8 x i8>, ptr %ret4367 %tmp1 = load <8 x i16>, ptr %A4368 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshrun.v8i8(<8 x i16> %tmp1, i32 1)4369 %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>4370 ret <16 x i8> %tmp44371}4372 4373define <8 x i16> @sqshrun8h(ptr %ret, ptr %A) nounwind sanitize_memory {4374; CHECK-LABEL: define <8 x i16> @sqshrun8h(4375; CHECK-SAME: ptr [[RET:%.*]], ptr [[A:%.*]]) #[[ATTR0]] {4376; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84377; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 84378; CHECK-NEXT: call void @llvm.donothing()4379; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04380; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]4381; CHECK: 3:4382; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4383; CHECK-NEXT: unreachable4384; CHECK: 4:4385; CHECK-NEXT: [[OUT:%.*]] = load <4 x i16>, ptr [[RET]], align 84386; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[RET]] to i644387; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885764388; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr4389; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 84390; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 04391; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]4392; CHECK: 8:4393; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4394; CHECK-NEXT: unreachable4395; CHECK: 9:4396; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 164397; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[A]] to i644398; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885764399; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr4400; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 164401; CHECK-NEXT: [[TMP13:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16(<4 x i32> [[_MSLD1]], i32 1)4402; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i16> [[TMP13]], zeroinitializer4403; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16(<4 x i32> [[TMP1]], i32 1)4404; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i16> [[_MSLD]], <4 x i16> [[TMP14]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>4405; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i16> [[OUT]], <4 x i16> [[TMP3]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>4406; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 84407; CHECK-NEXT: ret <8 x i16> [[TMP4]]4408;4409 %out = load <4 x i16>, ptr %ret4410 %tmp1 = load <4 x i32>, ptr %A4411 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16(<4 x i32> %tmp1, i32 1)4412 %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>4413 ret <8 x i16> %tmp44414}4415 4416define <4 x i32> @sqshrun4s(ptr %ret, ptr %A) nounwind sanitize_memory {4417; CHECK-LABEL: define <4 x i32> @sqshrun4s(4418; CHECK-SAME: ptr [[RET:%.*]], ptr [[A:%.*]]) #[[ATTR0]] {4419; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84420; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 84421; CHECK-NEXT: call void @llvm.donothing()4422; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04423; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]4424; CHECK: 3:4425; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4426; CHECK-NEXT: unreachable4427; CHECK: 4:4428; CHECK-NEXT: [[OUT:%.*]] = load <2 x i32>, ptr [[RET]], align 84429; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[RET]] to i644430; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885764431; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr4432; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 84433; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 04434; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]4435; CHECK: 8:4436; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4437; CHECK-NEXT: unreachable4438; CHECK: 9:4439; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 164440; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[A]] to i644441; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885764442; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr4443; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 164444; CHECK-NEXT: [[TMP13:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshrun.v2i32(<2 x i64> [[_MSLD1]], i32 1)4445; CHECK-NEXT: [[TMP14:%.*]] = or <2 x i32> [[TMP13]], zeroinitializer4446; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshrun.v2i32(<2 x i64> [[TMP1]], i32 1)4447; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i32> [[_MSLD]], <2 x i32> [[TMP14]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>4448; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[OUT]], <2 x i32> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>4449; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 84450; CHECK-NEXT: ret <4 x i32> [[TMP4]]4451;4452 %out = load <2 x i32>, ptr %ret4453 %tmp1 = load <2 x i64>, ptr %A4454 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshrun.v2i32(<2 x i64> %tmp1, i32 1)4455 %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>4456 ret <4 x i32> %tmp44457}4458 4459declare i32 @llvm.aarch64.neon.sqshrun.i32(i64, i32) nounwind readnone4460declare <8 x i8> @llvm.aarch64.neon.sqshrun.v8i8(<8 x i16>, i32) nounwind readnone4461declare <4 x i16> @llvm.aarch64.neon.sqshrun.v4i16(<4 x i32>, i32) nounwind readnone4462declare <2 x i32> @llvm.aarch64.neon.sqshrun.v2i32(<2 x i64>, i32) nounwind readnone4463 4464define i32 @sqrshrn1s(i64 %A) nounwind sanitize_memory {4465; CHECK-LABEL: define i32 @sqrshrn1s(4466; CHECK-SAME: i64 [[A:%.*]]) #[[ATTR0]] {4467; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84468; CHECK-NEXT: call void @llvm.donothing()4469; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.aarch64.neon.sqrshrn.i32(i64 [[TMP1]], i32 1)4470; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP2]], 04471; CHECK-NEXT: [[TMP:%.*]] = call i32 @llvm.aarch64.neon.sqrshrn.i32(i64 [[A]], i32 1)4472; CHECK-NEXT: store i32 [[TMP3]], ptr @__msan_retval_tls, align 84473; CHECK-NEXT: ret i32 [[TMP]]4474;4475 %tmp = call i32 @llvm.aarch64.neon.sqrshrn.i32(i64 %A, i32 1)4476 ret i32 %tmp4477}4478 4479define <8 x i8> @sqrshrn8b(ptr %A) nounwind sanitize_memory {4480; CHECK-LABEL: define <8 x i8> @sqrshrn8b(4481; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {4482; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84483; CHECK-NEXT: call void @llvm.donothing()4484; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04485; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]4486; CHECK: 2:4487; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4488; CHECK-NEXT: unreachable4489; CHECK: 3:4490; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 164491; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i644492; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885764493; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr4494; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP6]], align 164495; CHECK-NEXT: [[TMP7:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16> [[_MSLD]], i32 1)4496; CHECK-NEXT: [[TMP8:%.*]] = or <8 x i8> [[TMP7]], zeroinitializer4497; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16> [[TMP1]], i32 1)4498; CHECK-NEXT: store <8 x i8> [[TMP8]], ptr @__msan_retval_tls, align 84499; CHECK-NEXT: ret <8 x i8> [[TMP3]]4500;4501 %tmp1 = load <8 x i16>, ptr %A4502 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16> %tmp1, i32 1)4503 ret <8 x i8> %tmp34504}4505 4506define <4 x i16> @sqrshrn4h(ptr %A) nounwind sanitize_memory {4507; CHECK-LABEL: define <4 x i16> @sqrshrn4h(4508; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {4509; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84510; CHECK-NEXT: call void @llvm.donothing()4511; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04512; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]4513; CHECK: 2:4514; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4515; CHECK-NEXT: unreachable4516; CHECK: 3:4517; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 164518; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i644519; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885764520; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr4521; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP6]], align 164522; CHECK-NEXT: [[TMP7:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32> [[_MSLD]], i32 1)4523; CHECK-NEXT: [[TMP8:%.*]] = or <4 x i16> [[TMP7]], zeroinitializer4524; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32> [[TMP1]], i32 1)4525; CHECK-NEXT: store <4 x i16> [[TMP8]], ptr @__msan_retval_tls, align 84526; CHECK-NEXT: ret <4 x i16> [[TMP3]]4527;4528 %tmp1 = load <4 x i32>, ptr %A4529 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32> %tmp1, i32 1)4530 ret <4 x i16> %tmp34531}4532 4533define <2 x i32> @sqrshrn2s(ptr %A) nounwind sanitize_memory {4534; CHECK-LABEL: define <2 x i32> @sqrshrn2s(4535; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {4536; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84537; CHECK-NEXT: call void @llvm.donothing()4538; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04539; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]4540; CHECK: 2:4541; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4542; CHECK-NEXT: unreachable4543; CHECK: 3:4544; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 164545; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i644546; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885764547; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr4548; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP6]], align 164549; CHECK-NEXT: [[TMP7:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqrshrn.v2i32(<2 x i64> [[_MSLD]], i32 1)4550; CHECK-NEXT: [[TMP8:%.*]] = or <2 x i32> [[TMP7]], zeroinitializer4551; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqrshrn.v2i32(<2 x i64> [[TMP1]], i32 1)4552; CHECK-NEXT: store <2 x i32> [[TMP8]], ptr @__msan_retval_tls, align 84553; CHECK-NEXT: ret <2 x i32> [[TMP3]]4554;4555 %tmp1 = load <2 x i64>, ptr %A4556 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqrshrn.v2i32(<2 x i64> %tmp1, i32 1)4557 ret <2 x i32> %tmp34558}4559 4560define <16 x i8> @sqrshrn16b(ptr %ret, ptr %A) nounwind sanitize_memory {4561; CHECK-LABEL: define <16 x i8> @sqrshrn16b(4562; CHECK-SAME: ptr [[RET:%.*]], ptr [[A:%.*]]) #[[ATTR0]] {4563; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84564; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 84565; CHECK-NEXT: call void @llvm.donothing()4566; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04567; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]4568; CHECK: 3:4569; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4570; CHECK-NEXT: unreachable4571; CHECK: 4:4572; CHECK-NEXT: [[OUT:%.*]] = load <8 x i8>, ptr [[RET]], align 84573; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[RET]] to i644574; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885764575; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr4576; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 84577; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 04578; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]4579; CHECK: 8:4580; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4581; CHECK-NEXT: unreachable4582; CHECK: 9:4583; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 164584; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[A]] to i644585; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885764586; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr4587; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 164588; CHECK-NEXT: [[TMP13:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16> [[_MSLD1]], i32 1)4589; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i8> [[TMP13]], zeroinitializer4590; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16> [[TMP1]], i32 1)4591; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i8> [[_MSLD]], <8 x i8> [[TMP14]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>4592; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x i8> [[OUT]], <8 x i8> [[TMP3]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>4593; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 84594; CHECK-NEXT: ret <16 x i8> [[TMP4]]4595;4596 %out = load <8 x i8>, ptr %ret4597 %tmp1 = load <8 x i16>, ptr %A4598 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16> %tmp1, i32 1)4599 %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>4600 ret <16 x i8> %tmp44601}4602 4603define <8 x i16> @sqrshrn8h(ptr %ret, ptr %A) nounwind sanitize_memory {4604; CHECK-LABEL: define <8 x i16> @sqrshrn8h(4605; CHECK-SAME: ptr [[RET:%.*]], ptr [[A:%.*]]) #[[ATTR0]] {4606; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84607; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 84608; CHECK-NEXT: call void @llvm.donothing()4609; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04610; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]4611; CHECK: 3:4612; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4613; CHECK-NEXT: unreachable4614; CHECK: 4:4615; CHECK-NEXT: [[OUT:%.*]] = load <4 x i16>, ptr [[RET]], align 84616; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[RET]] to i644617; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885764618; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr4619; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 84620; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 04621; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]4622; CHECK: 8:4623; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4624; CHECK-NEXT: unreachable4625; CHECK: 9:4626; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 164627; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[A]] to i644628; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885764629; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr4630; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 164631; CHECK-NEXT: [[TMP13:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32> [[_MSLD1]], i32 1)4632; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i16> [[TMP13]], zeroinitializer4633; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32> [[TMP1]], i32 1)4634; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i16> [[_MSLD]], <4 x i16> [[TMP14]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>4635; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i16> [[OUT]], <4 x i16> [[TMP3]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>4636; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 84637; CHECK-NEXT: ret <8 x i16> [[TMP4]]4638;4639 %out = load <4 x i16>, ptr %ret4640 %tmp1 = load <4 x i32>, ptr %A4641 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32> %tmp1, i32 1)4642 %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>4643 ret <8 x i16> %tmp44644}4645 4646define <4 x i32> @sqrshrn4s(ptr %ret, ptr %A) nounwind sanitize_memory {4647; CHECK-LABEL: define <4 x i32> @sqrshrn4s(4648; CHECK-SAME: ptr [[RET:%.*]], ptr [[A:%.*]]) #[[ATTR0]] {4649; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84650; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 84651; CHECK-NEXT: call void @llvm.donothing()4652; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04653; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]4654; CHECK: 3:4655; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4656; CHECK-NEXT: unreachable4657; CHECK: 4:4658; CHECK-NEXT: [[OUT:%.*]] = load <2 x i32>, ptr [[RET]], align 84659; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[RET]] to i644660; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885764661; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr4662; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 84663; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 04664; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]4665; CHECK: 8:4666; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4667; CHECK-NEXT: unreachable4668; CHECK: 9:4669; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 164670; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[A]] to i644671; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885764672; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr4673; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 164674; CHECK-NEXT: [[TMP13:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqrshrn.v2i32(<2 x i64> [[_MSLD1]], i32 1)4675; CHECK-NEXT: [[TMP14:%.*]] = or <2 x i32> [[TMP13]], zeroinitializer4676; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqrshrn.v2i32(<2 x i64> [[TMP1]], i32 1)4677; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i32> [[_MSLD]], <2 x i32> [[TMP14]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>4678; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[OUT]], <2 x i32> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>4679; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 84680; CHECK-NEXT: ret <4 x i32> [[TMP4]]4681;4682 %out = load <2 x i32>, ptr %ret4683 %tmp1 = load <2 x i64>, ptr %A4684 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqrshrn.v2i32(<2 x i64> %tmp1, i32 1)4685 %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>4686 ret <4 x i32> %tmp44687}4688 4689declare i32 @llvm.aarch64.neon.sqrshrn.i32(i64, i32) nounwind readnone4690declare <8 x i8> @llvm.aarch64.neon.sqrshrn.v8i8(<8 x i16>, i32) nounwind readnone4691declare <4 x i16> @llvm.aarch64.neon.sqrshrn.v4i16(<4 x i32>, i32) nounwind readnone4692declare <2 x i32> @llvm.aarch64.neon.sqrshrn.v2i32(<2 x i64>, i32) nounwind readnone4693 4694define i32 @sqrshrun1s(i64 %A) nounwind sanitize_memory {4695; CHECK-LABEL: define i32 @sqrshrun1s(4696; CHECK-SAME: i64 [[A:%.*]]) #[[ATTR0]] {4697; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84698; CHECK-NEXT: call void @llvm.donothing()4699; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.aarch64.neon.sqrshrun.i32(i64 [[TMP1]], i32 1)4700; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP2]], 04701; CHECK-NEXT: [[TMP:%.*]] = call i32 @llvm.aarch64.neon.sqrshrun.i32(i64 [[A]], i32 1)4702; CHECK-NEXT: store i32 [[TMP3]], ptr @__msan_retval_tls, align 84703; CHECK-NEXT: ret i32 [[TMP]]4704;4705 %tmp = call i32 @llvm.aarch64.neon.sqrshrun.i32(i64 %A, i32 1)4706 ret i32 %tmp4707}4708 4709define <8 x i8> @sqrshrun8b(ptr %A) nounwind sanitize_memory {4710; CHECK-LABEL: define <8 x i8> @sqrshrun8b(4711; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {4712; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84713; CHECK-NEXT: call void @llvm.donothing()4714; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04715; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]4716; CHECK: 2:4717; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4718; CHECK-NEXT: unreachable4719; CHECK: 3:4720; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 164721; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i644722; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885764723; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr4724; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP6]], align 164725; CHECK-NEXT: [[TMP7:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> [[_MSLD]], i32 1)4726; CHECK-NEXT: [[TMP8:%.*]] = or <8 x i8> [[TMP7]], zeroinitializer4727; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> [[TMP1]], i32 1)4728; CHECK-NEXT: store <8 x i8> [[TMP8]], ptr @__msan_retval_tls, align 84729; CHECK-NEXT: ret <8 x i8> [[TMP3]]4730;4731 %tmp1 = load <8 x i16>, ptr %A4732 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> %tmp1, i32 1)4733 ret <8 x i8> %tmp34734}4735 4736define <4 x i16> @sqrshrun4h(ptr %A) nounwind sanitize_memory {4737; CHECK-LABEL: define <4 x i16> @sqrshrun4h(4738; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {4739; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84740; CHECK-NEXT: call void @llvm.donothing()4741; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04742; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]4743; CHECK: 2:4744; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4745; CHECK-NEXT: unreachable4746; CHECK: 3:4747; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 164748; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i644749; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885764750; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr4751; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP6]], align 164752; CHECK-NEXT: [[TMP7:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> [[_MSLD]], i32 1)4753; CHECK-NEXT: [[TMP8:%.*]] = or <4 x i16> [[TMP7]], zeroinitializer4754; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> [[TMP1]], i32 1)4755; CHECK-NEXT: store <4 x i16> [[TMP8]], ptr @__msan_retval_tls, align 84756; CHECK-NEXT: ret <4 x i16> [[TMP3]]4757;4758 %tmp1 = load <4 x i32>, ptr %A4759 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %tmp1, i32 1)4760 ret <4 x i16> %tmp34761}4762 4763define <2 x i32> @sqrshrun2s(ptr %A) nounwind sanitize_memory {4764; CHECK-LABEL: define <2 x i32> @sqrshrun2s(4765; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {4766; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84767; CHECK-NEXT: call void @llvm.donothing()4768; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04769; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]4770; CHECK: 2:4771; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4772; CHECK-NEXT: unreachable4773; CHECK: 3:4774; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 164775; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i644776; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885764777; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr4778; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP6]], align 164779; CHECK-NEXT: [[TMP7:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqrshrun.v2i32(<2 x i64> [[_MSLD]], i32 1)4780; CHECK-NEXT: [[TMP8:%.*]] = or <2 x i32> [[TMP7]], zeroinitializer4781; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqrshrun.v2i32(<2 x i64> [[TMP1]], i32 1)4782; CHECK-NEXT: store <2 x i32> [[TMP8]], ptr @__msan_retval_tls, align 84783; CHECK-NEXT: ret <2 x i32> [[TMP3]]4784;4785 %tmp1 = load <2 x i64>, ptr %A4786 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqrshrun.v2i32(<2 x i64> %tmp1, i32 1)4787 ret <2 x i32> %tmp34788}4789 4790define <16 x i8> @sqrshrun16b(ptr %ret, ptr %A) nounwind sanitize_memory {4791; CHECK-LABEL: define <16 x i8> @sqrshrun16b(4792; CHECK-SAME: ptr [[RET:%.*]], ptr [[A:%.*]]) #[[ATTR0]] {4793; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84794; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 84795; CHECK-NEXT: call void @llvm.donothing()4796; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04797; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]4798; CHECK: 3:4799; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4800; CHECK-NEXT: unreachable4801; CHECK: 4:4802; CHECK-NEXT: [[OUT:%.*]] = load <8 x i8>, ptr [[RET]], align 84803; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[RET]] to i644804; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885764805; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr4806; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 84807; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 04808; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]4809; CHECK: 8:4810; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4811; CHECK-NEXT: unreachable4812; CHECK: 9:4813; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 164814; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[A]] to i644815; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885764816; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr4817; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 164818; CHECK-NEXT: [[TMP13:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> [[_MSLD1]], i32 1)4819; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i8> [[TMP13]], zeroinitializer4820; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> [[TMP1]], i32 1)4821; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i8> [[_MSLD]], <8 x i8> [[TMP14]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>4822; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x i8> [[OUT]], <8 x i8> [[TMP3]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>4823; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 84824; CHECK-NEXT: ret <16 x i8> [[TMP4]]4825;4826 %out = load <8 x i8>, ptr %ret4827 %tmp1 = load <8 x i16>, ptr %A4828 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> %tmp1, i32 1)4829 %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>4830 ret <16 x i8> %tmp44831}4832 4833define <8 x i16> @sqrshrun8h(ptr %ret, ptr %A) nounwind sanitize_memory {4834; CHECK-LABEL: define <8 x i16> @sqrshrun8h(4835; CHECK-SAME: ptr [[RET:%.*]], ptr [[A:%.*]]) #[[ATTR0]] {4836; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84837; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 84838; CHECK-NEXT: call void @llvm.donothing()4839; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04840; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]4841; CHECK: 3:4842; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4843; CHECK-NEXT: unreachable4844; CHECK: 4:4845; CHECK-NEXT: [[OUT:%.*]] = load <4 x i16>, ptr [[RET]], align 84846; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[RET]] to i644847; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885764848; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr4849; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 84850; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 04851; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]4852; CHECK: 8:4853; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4854; CHECK-NEXT: unreachable4855; CHECK: 9:4856; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 164857; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[A]] to i644858; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885764859; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr4860; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 164861; CHECK-NEXT: [[TMP13:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> [[_MSLD1]], i32 1)4862; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i16> [[TMP13]], zeroinitializer4863; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> [[TMP1]], i32 1)4864; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i16> [[_MSLD]], <4 x i16> [[TMP14]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>4865; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i16> [[OUT]], <4 x i16> [[TMP3]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>4866; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 84867; CHECK-NEXT: ret <8 x i16> [[TMP4]]4868;4869 %out = load <4 x i16>, ptr %ret4870 %tmp1 = load <4 x i32>, ptr %A4871 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> %tmp1, i32 1)4872 %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>4873 ret <8 x i16> %tmp44874}4875 4876define <4 x i32> @sqrshrun4s(ptr %ret, ptr %A) nounwind sanitize_memory {4877; CHECK-LABEL: define <4 x i32> @sqrshrun4s(4878; CHECK-SAME: ptr [[RET:%.*]], ptr [[A:%.*]]) #[[ATTR0]] {4879; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84880; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 84881; CHECK-NEXT: call void @llvm.donothing()4882; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04883; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]4884; CHECK: 3:4885; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4886; CHECK-NEXT: unreachable4887; CHECK: 4:4888; CHECK-NEXT: [[OUT:%.*]] = load <2 x i32>, ptr [[RET]], align 84889; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[RET]] to i644890; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885764891; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr4892; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 84893; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 04894; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]4895; CHECK: 8:4896; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4897; CHECK-NEXT: unreachable4898; CHECK: 9:4899; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 164900; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[A]] to i644901; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885764902; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr4903; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 164904; CHECK-NEXT: [[TMP13:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqrshrun.v2i32(<2 x i64> [[_MSLD1]], i32 1)4905; CHECK-NEXT: [[TMP14:%.*]] = or <2 x i32> [[TMP13]], zeroinitializer4906; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqrshrun.v2i32(<2 x i64> [[TMP1]], i32 1)4907; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i32> [[_MSLD]], <2 x i32> [[TMP14]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>4908; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[OUT]], <2 x i32> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>4909; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 84910; CHECK-NEXT: ret <4 x i32> [[TMP4]]4911;4912 %out = load <2 x i32>, ptr %ret4913 %tmp1 = load <2 x i64>, ptr %A4914 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqrshrun.v2i32(<2 x i64> %tmp1, i32 1)4915 %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>4916 ret <4 x i32> %tmp44917}4918 4919declare i32 @llvm.aarch64.neon.sqrshrun.i32(i64, i32) nounwind readnone4920declare <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16>, i32) nounwind readnone4921declare <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32>, i32) nounwind readnone4922declare <2 x i32> @llvm.aarch64.neon.sqrshrun.v2i32(<2 x i64>, i32) nounwind readnone4923 4924define i32 @uqrshrn1s(i64 %A) nounwind sanitize_memory {4925; CHECK-LABEL: define i32 @uqrshrn1s(4926; CHECK-SAME: i64 [[A:%.*]]) #[[ATTR0]] {4927; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84928; CHECK-NEXT: call void @llvm.donothing()4929; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.aarch64.neon.uqrshrn.i32(i64 [[TMP1]], i32 1)4930; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP2]], 04931; CHECK-NEXT: [[TMP:%.*]] = call i32 @llvm.aarch64.neon.uqrshrn.i32(i64 [[A]], i32 1)4932; CHECK-NEXT: store i32 [[TMP3]], ptr @__msan_retval_tls, align 84933; CHECK-NEXT: ret i32 [[TMP]]4934;4935 %tmp = call i32 @llvm.aarch64.neon.uqrshrn.i32(i64 %A, i32 1)4936 ret i32 %tmp4937}4938 4939define <8 x i8> @uqrshrn8b(ptr %A) nounwind sanitize_memory {4940; CHECK-LABEL: define <8 x i8> @uqrshrn8b(4941; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {4942; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84943; CHECK-NEXT: call void @llvm.donothing()4944; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04945; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]4946; CHECK: 2:4947; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4948; CHECK-NEXT: unreachable4949; CHECK: 3:4950; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 164951; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i644952; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885764953; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr4954; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP6]], align 164955; CHECK-NEXT: [[TMP7:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16> [[_MSLD]], i32 1)4956; CHECK-NEXT: [[TMP8:%.*]] = or <8 x i8> [[TMP7]], zeroinitializer4957; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16> [[TMP1]], i32 1)4958; CHECK-NEXT: store <8 x i8> [[TMP8]], ptr @__msan_retval_tls, align 84959; CHECK-NEXT: ret <8 x i8> [[TMP3]]4960;4961 %tmp1 = load <8 x i16>, ptr %A4962 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16> %tmp1, i32 1)4963 ret <8 x i8> %tmp34964}4965 4966define <4 x i16> @uqrshrn4h(ptr %A) nounwind sanitize_memory {4967; CHECK-LABEL: define <4 x i16> @uqrshrn4h(4968; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {4969; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84970; CHECK-NEXT: call void @llvm.donothing()4971; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04972; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]4973; CHECK: 2:4974; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]4975; CHECK-NEXT: unreachable4976; CHECK: 3:4977; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 164978; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i644979; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885764980; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr4981; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP6]], align 164982; CHECK-NEXT: [[TMP7:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> [[_MSLD]], i32 1)4983; CHECK-NEXT: [[TMP8:%.*]] = or <4 x i16> [[TMP7]], zeroinitializer4984; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> [[TMP1]], i32 1)4985; CHECK-NEXT: store <4 x i16> [[TMP8]], ptr @__msan_retval_tls, align 84986; CHECK-NEXT: ret <4 x i16> [[TMP3]]4987;4988 %tmp1 = load <4 x i32>, ptr %A4989 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> %tmp1, i32 1)4990 ret <4 x i16> %tmp34991}4992 4993define <2 x i32> @uqrshrn2s(ptr %A) nounwind sanitize_memory {4994; CHECK-LABEL: define <2 x i32> @uqrshrn2s(4995; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {4996; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 84997; CHECK-NEXT: call void @llvm.donothing()4998; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 04999; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]5000; CHECK: 2:5001; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5002; CHECK-NEXT: unreachable5003; CHECK: 3:5004; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 165005; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i645006; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885765007; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr5008; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP6]], align 165009; CHECK-NEXT: [[TMP7:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqrshrn.v2i32(<2 x i64> [[_MSLD]], i32 1)5010; CHECK-NEXT: [[TMP8:%.*]] = or <2 x i32> [[TMP7]], zeroinitializer5011; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqrshrn.v2i32(<2 x i64> [[TMP1]], i32 1)5012; CHECK-NEXT: store <2 x i32> [[TMP8]], ptr @__msan_retval_tls, align 85013; CHECK-NEXT: ret <2 x i32> [[TMP3]]5014;5015 %tmp1 = load <2 x i64>, ptr %A5016 %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqrshrn.v2i32(<2 x i64> %tmp1, i32 1)5017 ret <2 x i32> %tmp35018}5019 5020define <16 x i8> @uqrshrn16b(ptr %ret, ptr %A) nounwind sanitize_memory {5021; CHECK-LABEL: define <16 x i8> @uqrshrn16b(5022; CHECK-SAME: ptr [[RET:%.*]], ptr [[A:%.*]]) #[[ATTR0]] {5023; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85024; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 85025; CHECK-NEXT: call void @llvm.donothing()5026; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05027; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]5028; CHECK: 3:5029; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5030; CHECK-NEXT: unreachable5031; CHECK: 4:5032; CHECK-NEXT: [[OUT:%.*]] = load <8 x i8>, ptr [[RET]], align 85033; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[RET]] to i645034; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885765035; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr5036; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 85037; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 05038; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]5039; CHECK: 8:5040; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5041; CHECK-NEXT: unreachable5042; CHECK: 9:5043; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 165044; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[A]] to i645045; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885765046; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr5047; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 165048; CHECK-NEXT: [[TMP13:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16> [[_MSLD1]], i32 1)5049; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i8> [[TMP13]], zeroinitializer5050; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16> [[TMP1]], i32 1)5051; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i8> [[_MSLD]], <8 x i8> [[TMP14]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>5052; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x i8> [[OUT]], <8 x i8> [[TMP3]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>5053; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 85054; CHECK-NEXT: ret <16 x i8> [[TMP4]]5055;5056 %out = load <8 x i8>, ptr %ret5057 %tmp1 = load <8 x i16>, ptr %A5058 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16> %tmp1, i32 1)5059 %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>5060 ret <16 x i8> %tmp45061}5062 5063define <8 x i16> @uqrshrn8h(ptr %ret, ptr %A) nounwind sanitize_memory {5064; CHECK-LABEL: define <8 x i16> @uqrshrn8h(5065; CHECK-SAME: ptr [[RET:%.*]], ptr [[A:%.*]]) #[[ATTR0]] {5066; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85067; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 85068; CHECK-NEXT: call void @llvm.donothing()5069; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05070; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]5071; CHECK: 3:5072; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5073; CHECK-NEXT: unreachable5074; CHECK: 4:5075; CHECK-NEXT: [[OUT:%.*]] = load <4 x i16>, ptr [[RET]], align 85076; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[RET]] to i645077; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885765078; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr5079; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 85080; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 05081; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]5082; CHECK: 8:5083; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5084; CHECK-NEXT: unreachable5085; CHECK: 9:5086; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 165087; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[A]] to i645088; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885765089; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr5090; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 165091; CHECK-NEXT: [[TMP13:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> [[_MSLD1]], i32 1)5092; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i16> [[TMP13]], zeroinitializer5093; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> [[TMP1]], i32 1)5094; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i16> [[_MSLD]], <4 x i16> [[TMP14]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>5095; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i16> [[OUT]], <4 x i16> [[TMP3]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>5096; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 85097; CHECK-NEXT: ret <8 x i16> [[TMP4]]5098;5099 %out = load <4 x i16>, ptr %ret5100 %tmp1 = load <4 x i32>, ptr %A5101 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32> %tmp1, i32 1)5102 %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>5103 ret <8 x i16> %tmp45104}5105 5106define <4 x i32> @uqrshrn4s(ptr %ret, ptr %A) nounwind sanitize_memory {5107; CHECK-LABEL: define <4 x i32> @uqrshrn4s(5108; CHECK-SAME: ptr [[RET:%.*]], ptr [[A:%.*]]) #[[ATTR0]] {5109; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85110; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 85111; CHECK-NEXT: call void @llvm.donothing()5112; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05113; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]5114; CHECK: 3:5115; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5116; CHECK-NEXT: unreachable5117; CHECK: 4:5118; CHECK-NEXT: [[OUT:%.*]] = load <2 x i32>, ptr [[RET]], align 85119; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[RET]] to i645120; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885765121; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr5122; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 85123; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 05124; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]5125; CHECK: 8:5126; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5127; CHECK-NEXT: unreachable5128; CHECK: 9:5129; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 165130; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[A]] to i645131; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885765132; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr5133; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 165134; CHECK-NEXT: [[TMP13:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqrshrn.v2i32(<2 x i64> [[_MSLD1]], i32 1)5135; CHECK-NEXT: [[TMP14:%.*]] = or <2 x i32> [[TMP13]], zeroinitializer5136; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqrshrn.v2i32(<2 x i64> [[TMP1]], i32 1)5137; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i32> [[_MSLD]], <2 x i32> [[TMP14]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>5138; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[OUT]], <2 x i32> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>5139; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 85140; CHECK-NEXT: ret <4 x i32> [[TMP4]]5141;5142 %out = load <2 x i32>, ptr %ret5143 %tmp1 = load <2 x i64>, ptr %A5144 %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqrshrn.v2i32(<2 x i64> %tmp1, i32 1)5145 %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>5146 ret <4 x i32> %tmp45147}5148 5149declare i32 @llvm.aarch64.neon.uqrshrn.i32(i64, i32) nounwind readnone5150declare <8 x i8> @llvm.aarch64.neon.uqrshrn.v8i8(<8 x i16>, i32) nounwind readnone5151declare <4 x i16> @llvm.aarch64.neon.uqrshrn.v4i16(<4 x i32>, i32) nounwind readnone5152declare <2 x i32> @llvm.aarch64.neon.uqrshrn.v2i32(<2 x i64>, i32) nounwind readnone5153 5154define i32 @uqshrn1s(i64 %A) nounwind sanitize_memory {5155; CHECK-LABEL: define i32 @uqshrn1s(5156; CHECK-SAME: i64 [[A:%.*]]) #[[ATTR0]] {5157; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85158; CHECK-NEXT: call void @llvm.donothing()5159; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.aarch64.neon.uqshrn.i32(i64 [[TMP1]], i32 1)5160; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP2]], 05161; CHECK-NEXT: [[TMP:%.*]] = call i32 @llvm.aarch64.neon.uqshrn.i32(i64 [[A]], i32 1)5162; CHECK-NEXT: store i32 [[TMP3]], ptr @__msan_retval_tls, align 85163; CHECK-NEXT: ret i32 [[TMP]]5164;5165 %tmp = call i32 @llvm.aarch64.neon.uqshrn.i32(i64 %A, i32 1)5166 ret i32 %tmp5167}5168 5169define <8 x i8> @uqshrn8b(ptr %A) nounwind sanitize_memory {5170; CHECK-LABEL: define <8 x i8> @uqshrn8b(5171; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {5172; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85173; CHECK-NEXT: call void @llvm.donothing()5174; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05175; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]5176; CHECK: 2:5177; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5178; CHECK-NEXT: unreachable5179; CHECK: 3:5180; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 165181; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i645182; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885765183; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr5184; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP6]], align 165185; CHECK-NEXT: [[TMP7:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16> [[_MSLD]], i32 1)5186; CHECK-NEXT: [[TMP8:%.*]] = or <8 x i8> [[TMP7]], zeroinitializer5187; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16> [[TMP1]], i32 1)5188; CHECK-NEXT: store <8 x i8> [[TMP8]], ptr @__msan_retval_tls, align 85189; CHECK-NEXT: ret <8 x i8> [[TMP3]]5190;5191 %tmp1 = load <8 x i16>, ptr %A5192 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16> %tmp1, i32 1)5193 ret <8 x i8> %tmp35194}5195 5196define <4 x i16> @uqshrn4h(ptr %A) nounwind sanitize_memory {5197; CHECK-LABEL: define <4 x i16> @uqshrn4h(5198; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {5199; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85200; CHECK-NEXT: call void @llvm.donothing()5201; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05202; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]5203; CHECK: 2:5204; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5205; CHECK-NEXT: unreachable5206; CHECK: 3:5207; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 165208; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i645209; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885765210; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr5211; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP6]], align 165212; CHECK-NEXT: [[TMP7:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> [[_MSLD]], i32 1)5213; CHECK-NEXT: [[TMP8:%.*]] = or <4 x i16> [[TMP7]], zeroinitializer5214; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> [[TMP1]], i32 1)5215; CHECK-NEXT: store <4 x i16> [[TMP8]], ptr @__msan_retval_tls, align 85216; CHECK-NEXT: ret <4 x i16> [[TMP3]]5217;5218 %tmp1 = load <4 x i32>, ptr %A5219 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> %tmp1, i32 1)5220 ret <4 x i16> %tmp35221}5222 5223define <2 x i32> @uqshrn2s(ptr %A) nounwind sanitize_memory {5224; CHECK-LABEL: define <2 x i32> @uqshrn2s(5225; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {5226; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85227; CHECK-NEXT: call void @llvm.donothing()5228; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05229; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]5230; CHECK: 2:5231; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5232; CHECK-NEXT: unreachable5233; CHECK: 3:5234; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 165235; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i645236; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885765237; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr5238; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP6]], align 165239; CHECK-NEXT: [[TMP7:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64> [[_MSLD]], i32 1)5240; CHECK-NEXT: [[TMP8:%.*]] = or <2 x i32> [[TMP7]], zeroinitializer5241; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64> [[TMP1]], i32 1)5242; CHECK-NEXT: store <2 x i32> [[TMP8]], ptr @__msan_retval_tls, align 85243; CHECK-NEXT: ret <2 x i32> [[TMP3]]5244;5245 %tmp1 = load <2 x i64>, ptr %A5246 %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64> %tmp1, i32 1)5247 ret <2 x i32> %tmp35248}5249 5250define <16 x i8> @uqshrn16b(ptr %ret, ptr %A) nounwind sanitize_memory {5251; CHECK-LABEL: define <16 x i8> @uqshrn16b(5252; CHECK-SAME: ptr [[RET:%.*]], ptr [[A:%.*]]) #[[ATTR0]] {5253; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85254; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 85255; CHECK-NEXT: call void @llvm.donothing()5256; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05257; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]5258; CHECK: 3:5259; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5260; CHECK-NEXT: unreachable5261; CHECK: 4:5262; CHECK-NEXT: [[OUT:%.*]] = load <8 x i8>, ptr [[RET]], align 85263; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[RET]] to i645264; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885765265; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr5266; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 85267; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 05268; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]5269; CHECK: 8:5270; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5271; CHECK-NEXT: unreachable5272; CHECK: 9:5273; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 165274; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[A]] to i645275; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885765276; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr5277; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 165278; CHECK-NEXT: [[TMP13:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16> [[_MSLD1]], i32 1)5279; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i8> [[TMP13]], zeroinitializer5280; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16> [[TMP1]], i32 1)5281; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i8> [[_MSLD]], <8 x i8> [[TMP14]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>5282; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <8 x i8> [[OUT]], <8 x i8> [[TMP3]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>5283; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 85284; CHECK-NEXT: ret <16 x i8> [[TMP4]]5285;5286 %out = load <8 x i8>, ptr %ret5287 %tmp1 = load <8 x i16>, ptr %A5288 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16> %tmp1, i32 1)5289 %tmp4 = shufflevector <8 x i8> %out, <8 x i8> %tmp3, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>5290 ret <16 x i8> %tmp45291}5292 5293define <8 x i16> @uqshrn8h(ptr %ret, ptr %A) nounwind sanitize_memory {5294; CHECK-LABEL: define <8 x i16> @uqshrn8h(5295; CHECK-SAME: ptr [[RET:%.*]], ptr [[A:%.*]]) #[[ATTR0]] {5296; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85297; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 85298; CHECK-NEXT: call void @llvm.donothing()5299; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05300; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]5301; CHECK: 3:5302; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5303; CHECK-NEXT: unreachable5304; CHECK: 4:5305; CHECK-NEXT: [[OUT:%.*]] = load <4 x i16>, ptr [[RET]], align 85306; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[RET]] to i645307; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885765308; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr5309; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 85310; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 05311; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]5312; CHECK: 8:5313; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5314; CHECK-NEXT: unreachable5315; CHECK: 9:5316; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 165317; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[A]] to i645318; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885765319; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr5320; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 165321; CHECK-NEXT: [[TMP13:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> [[_MSLD1]], i32 1)5322; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i16> [[TMP13]], zeroinitializer5323; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> [[TMP1]], i32 1)5324; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i16> [[_MSLD]], <4 x i16> [[TMP14]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>5325; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i16> [[OUT]], <4 x i16> [[TMP3]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>5326; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 85327; CHECK-NEXT: ret <8 x i16> [[TMP4]]5328;5329 %out = load <4 x i16>, ptr %ret5330 %tmp1 = load <4 x i32>, ptr %A5331 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32> %tmp1, i32 1)5332 %tmp4 = shufflevector <4 x i16> %out, <4 x i16> %tmp3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>5333 ret <8 x i16> %tmp45334}5335 5336define <4 x i32> @uqshrn4s(ptr %ret, ptr %A) nounwind sanitize_memory {5337; CHECK-LABEL: define <4 x i32> @uqshrn4s(5338; CHECK-SAME: ptr [[RET:%.*]], ptr [[A:%.*]]) #[[ATTR0]] {5339; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85340; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 85341; CHECK-NEXT: call void @llvm.donothing()5342; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05343; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]5344; CHECK: 3:5345; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5346; CHECK-NEXT: unreachable5347; CHECK: 4:5348; CHECK-NEXT: [[OUT:%.*]] = load <2 x i32>, ptr [[RET]], align 85349; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[RET]] to i645350; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885765351; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr5352; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 85353; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 05354; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]5355; CHECK: 8:5356; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5357; CHECK-NEXT: unreachable5358; CHECK: 9:5359; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 165360; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[A]] to i645361; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885765362; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr5363; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 165364; CHECK-NEXT: [[TMP13:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64> [[_MSLD1]], i32 1)5365; CHECK-NEXT: [[TMP14:%.*]] = or <2 x i32> [[TMP13]], zeroinitializer5366; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64> [[TMP1]], i32 1)5367; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <2 x i32> [[_MSLD]], <2 x i32> [[TMP14]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>5368; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i32> [[OUT]], <2 x i32> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>5369; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 85370; CHECK-NEXT: ret <4 x i32> [[TMP4]]5371;5372 %out = load <2 x i32>, ptr %ret5373 %tmp1 = load <2 x i64>, ptr %A5374 %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64> %tmp1, i32 1)5375 %tmp4 = shufflevector <2 x i32> %out, <2 x i32> %tmp3, <4 x i32> <i32 0, i32 1, i32 2, i32 3>5376 ret <4 x i32> %tmp45377}5378 5379declare i32 @llvm.aarch64.neon.uqshrn.i32(i64, i32) nounwind readnone5380declare <8 x i8> @llvm.aarch64.neon.uqshrn.v8i8(<8 x i16>, i32) nounwind readnone5381declare <4 x i16> @llvm.aarch64.neon.uqshrn.v4i16(<4 x i32>, i32) nounwind readnone5382declare <2 x i32> @llvm.aarch64.neon.uqshrn.v2i32(<2 x i64>, i32) nounwind readnone5383 5384define <8 x i16> @ushll8h(ptr %A) nounwind sanitize_memory {5385; CHECK-LABEL: define <8 x i16> @ushll8h(5386; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {5387; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85388; CHECK-NEXT: call void @llvm.donothing()5389; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05390; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]5391; CHECK: 2:5392; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5393; CHECK-NEXT: unreachable5394; CHECK: 3:5395; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[A]], align 85396; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i645397; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885765398; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr5399; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP6]], align 85400; CHECK-NEXT: [[_MSPROP:%.*]] = zext <8 x i8> [[_MSLD]] to <8 x i16>5401; CHECK-NEXT: [[TMP2:%.*]] = zext <8 x i8> [[TMP1]] to <8 x i16>5402; CHECK-NEXT: [[TMP7:%.*]] = shl <8 x i16> [[_MSPROP]], splat (i16 1)5403; CHECK-NEXT: [[TMP8:%.*]] = or <8 x i16> [[TMP7]], zeroinitializer5404; CHECK-NEXT: [[TMP3:%.*]] = shl <8 x i16> [[TMP2]], splat (i16 1)5405; CHECK-NEXT: store <8 x i16> [[TMP8]], ptr @__msan_retval_tls, align 85406; CHECK-NEXT: ret <8 x i16> [[TMP3]]5407;5408 %tmp1 = load <8 x i8>, ptr %A5409 %tmp2 = zext <8 x i8> %tmp1 to <8 x i16>5410 %tmp3 = shl <8 x i16> %tmp2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>5411 ret <8 x i16> %tmp35412}5413 5414define <4 x i32> @ushll4s(ptr %A) nounwind sanitize_memory {5415; CHECK-LABEL: define <4 x i32> @ushll4s(5416; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {5417; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85418; CHECK-NEXT: call void @llvm.donothing()5419; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05420; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]5421; CHECK: 2:5422; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5423; CHECK-NEXT: unreachable5424; CHECK: 3:5425; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 85426; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i645427; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885765428; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr5429; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP6]], align 85430; CHECK-NEXT: [[_MSPROP:%.*]] = zext <4 x i16> [[_MSLD]] to <4 x i32>5431; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i16> [[TMP1]] to <4 x i32>5432; CHECK-NEXT: [[TMP7:%.*]] = shl <4 x i32> [[_MSPROP]], splat (i32 1)5433; CHECK-NEXT: [[TMP8:%.*]] = or <4 x i32> [[TMP7]], zeroinitializer5434; CHECK-NEXT: [[TMP3:%.*]] = shl <4 x i32> [[TMP2]], splat (i32 1)5435; CHECK-NEXT: store <4 x i32> [[TMP8]], ptr @__msan_retval_tls, align 85436; CHECK-NEXT: ret <4 x i32> [[TMP3]]5437;5438 %tmp1 = load <4 x i16>, ptr %A5439 %tmp2 = zext <4 x i16> %tmp1 to <4 x i32>5440 %tmp3 = shl <4 x i32> %tmp2, <i32 1, i32 1, i32 1, i32 1>5441 ret <4 x i32> %tmp35442}5443 5444define <2 x i64> @ushll2d(ptr %A) nounwind sanitize_memory {5445; CHECK-LABEL: define <2 x i64> @ushll2d(5446; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {5447; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85448; CHECK-NEXT: call void @llvm.donothing()5449; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05450; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]5451; CHECK: 2:5452; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5453; CHECK-NEXT: unreachable5454; CHECK: 3:5455; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 85456; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i645457; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885765458; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr5459; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP6]], align 85460; CHECK-NEXT: [[_MSPROP:%.*]] = zext <2 x i32> [[_MSLD]] to <2 x i64>5461; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>5462; CHECK-NEXT: [[TMP7:%.*]] = shl <2 x i64> [[_MSPROP]], splat (i64 1)5463; CHECK-NEXT: [[TMP8:%.*]] = or <2 x i64> [[TMP7]], zeroinitializer5464; CHECK-NEXT: [[TMP3:%.*]] = shl <2 x i64> [[TMP2]], splat (i64 1)5465; CHECK-NEXT: store <2 x i64> [[TMP8]], ptr @__msan_retval_tls, align 85466; CHECK-NEXT: ret <2 x i64> [[TMP3]]5467;5468 %tmp1 = load <2 x i32>, ptr %A5469 %tmp2 = zext <2 x i32> %tmp1 to <2 x i64>5470 %tmp3 = shl <2 x i64> %tmp2, <i64 1, i64 1>5471 ret <2 x i64> %tmp35472}5473 5474define <8 x i16> @ushll2_8h(ptr %A) nounwind sanitize_memory {5475; CHECK-LABEL: define <8 x i16> @ushll2_8h(5476; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {5477; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85478; CHECK-NEXT: call void @llvm.donothing()5479; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05480; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]5481; CHECK: 2:5482; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5483; CHECK-NEXT: unreachable5484; CHECK: 3:5485; CHECK-NEXT: [[LOAD1:%.*]] = load <16 x i8>, ptr [[A]], align 165486; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i645487; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885765488; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr5489; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP6]], align 165490; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <16 x i8> [[_MSLD]], <16 x i8> splat (i8 -1), <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>5491; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i8> [[LOAD1]], <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>5492; CHECK-NEXT: [[_MSPROP1:%.*]] = zext <8 x i8> [[_MSPROP]] to <8 x i16>5493; CHECK-NEXT: [[TMP2:%.*]] = zext <8 x i8> [[TMP1]] to <8 x i16>5494; CHECK-NEXT: [[TMP7:%.*]] = shl <8 x i16> [[_MSPROP1]], splat (i16 1)5495; CHECK-NEXT: [[TMP8:%.*]] = or <8 x i16> [[TMP7]], zeroinitializer5496; CHECK-NEXT: [[TMP3:%.*]] = shl <8 x i16> [[TMP2]], splat (i16 1)5497; CHECK-NEXT: store <8 x i16> [[TMP8]], ptr @__msan_retval_tls, align 85498; CHECK-NEXT: ret <8 x i16> [[TMP3]]5499;5500 %load1 = load <16 x i8>, ptr %A5501 %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>5502 %tmp2 = zext <8 x i8> %tmp1 to <8 x i16>5503 %tmp3 = shl <8 x i16> %tmp2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>5504 ret <8 x i16> %tmp35505}5506 5507define <4 x i32> @ushll2_4s(ptr %A) nounwind sanitize_memory {5508; CHECK-LABEL: define <4 x i32> @ushll2_4s(5509; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {5510; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85511; CHECK-NEXT: call void @llvm.donothing()5512; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05513; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]5514; CHECK: 2:5515; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5516; CHECK-NEXT: unreachable5517; CHECK: 3:5518; CHECK-NEXT: [[LOAD1:%.*]] = load <8 x i16>, ptr [[A]], align 165519; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i645520; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885765521; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr5522; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP6]], align 165523; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i16> [[_MSLD]], <8 x i16> splat (i16 -1), <4 x i32> <i32 4, i32 5, i32 6, i32 7>5524; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i16> [[LOAD1]], <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>5525; CHECK-NEXT: [[_MSPROP1:%.*]] = zext <4 x i16> [[_MSPROP]] to <4 x i32>5526; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i16> [[TMP1]] to <4 x i32>5527; CHECK-NEXT: [[TMP7:%.*]] = shl <4 x i32> [[_MSPROP1]], splat (i32 1)5528; CHECK-NEXT: [[TMP8:%.*]] = or <4 x i32> [[TMP7]], zeroinitializer5529; CHECK-NEXT: [[TMP3:%.*]] = shl <4 x i32> [[TMP2]], splat (i32 1)5530; CHECK-NEXT: store <4 x i32> [[TMP8]], ptr @__msan_retval_tls, align 85531; CHECK-NEXT: ret <4 x i32> [[TMP3]]5532;5533 %load1 = load <8 x i16>, ptr %A5534 %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>5535 %tmp2 = zext <4 x i16> %tmp1 to <4 x i32>5536 %tmp3 = shl <4 x i32> %tmp2, <i32 1, i32 1, i32 1, i32 1>5537 ret <4 x i32> %tmp35538}5539 5540define <2 x i64> @ushll2_2d(ptr %A) nounwind sanitize_memory {5541; CHECK-LABEL: define <2 x i64> @ushll2_2d(5542; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {5543; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85544; CHECK-NEXT: call void @llvm.donothing()5545; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05546; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]5547; CHECK: 2:5548; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5549; CHECK-NEXT: unreachable5550; CHECK: 3:5551; CHECK-NEXT: [[LOAD1:%.*]] = load <4 x i32>, ptr [[A]], align 165552; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i645553; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885765554; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr5555; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP6]], align 165556; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> splat (i32 -1), <2 x i32> <i32 2, i32 3>5557; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[LOAD1]], <4 x i32> undef, <2 x i32> <i32 2, i32 3>5558; CHECK-NEXT: [[_MSPROP1:%.*]] = zext <2 x i32> [[_MSPROP]] to <2 x i64>5559; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>5560; CHECK-NEXT: [[TMP7:%.*]] = shl <2 x i64> [[_MSPROP1]], splat (i64 1)5561; CHECK-NEXT: [[TMP8:%.*]] = or <2 x i64> [[TMP7]], zeroinitializer5562; CHECK-NEXT: [[TMP3:%.*]] = shl <2 x i64> [[TMP2]], splat (i64 1)5563; CHECK-NEXT: store <2 x i64> [[TMP8]], ptr @__msan_retval_tls, align 85564; CHECK-NEXT: ret <2 x i64> [[TMP3]]5565;5566 %load1 = load <4 x i32>, ptr %A5567 %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>5568 %tmp2 = zext <2 x i32> %tmp1 to <2 x i64>5569 %tmp3 = shl <2 x i64> %tmp2, <i64 1, i64 1>5570 ret <2 x i64> %tmp35571}5572 5573declare <16 x i8> @llvm.aarch64.neon.ushl.v16i8(<16 x i8>, <16 x i8>)5574declare <8 x i16> @llvm.aarch64.neon.ushl.v8i16(<8 x i16>, <8 x i16>)5575declare <4 x i32> @llvm.aarch64.neon.ushl.v4i32(<4 x i32>, <4 x i32>)5576declare <2 x i64> @llvm.aarch64.neon.ushl.v2i64(<2 x i64>, <2 x i64>)5577declare <1 x i64> @llvm.aarch64.neon.ushl.v1i64(<1 x i64>, <1 x i64>)5578declare i64 @llvm.aarch64.neon.ushl.i64(i64, i64)5579 5580define <8 x i16> @neon.ushll8h_constant_shift(ptr %A) nounwind sanitize_memory {5581; CHECK-LABEL: define <8 x i16> @neon.ushll8h_constant_shift(5582; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {5583; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85584; CHECK-NEXT: call void @llvm.donothing()5585; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05586; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]5587; CHECK: 2:5588; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5589; CHECK-NEXT: unreachable5590; CHECK: 3:5591; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[A]], align 85592; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i645593; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885765594; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr5595; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP6]], align 85596; CHECK-NEXT: [[_MSPROP:%.*]] = zext <8 x i8> [[_MSLD]] to <8 x i16>5597; CHECK-NEXT: [[TMP2:%.*]] = zext <8 x i8> [[TMP1]] to <8 x i16>5598; CHECK-NEXT: [[TMP7:%.*]] = call <8 x i16> @llvm.aarch64.neon.ushl.v8i16(<8 x i16> [[_MSPROP]], <8 x i16> splat (i16 1))5599; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i16> [[TMP7]], zeroinitializer5600; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i16> @llvm.aarch64.neon.ushl.v8i16(<8 x i16> [[TMP2]], <8 x i16> splat (i16 1))5601; CHECK-NEXT: store <8 x i16> [[_MSPROP1]], ptr @__msan_retval_tls, align 85602; CHECK-NEXT: ret <8 x i16> [[TMP3]]5603;5604 %tmp1 = load <8 x i8>, ptr %A5605 %tmp2 = zext <8 x i8> %tmp1 to <8 x i16>5606 %tmp3 = call <8 x i16> @llvm.aarch64.neon.ushl.v8i16(<8 x i16> %tmp2, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)5607 ret <8 x i16> %tmp35608}5609 5610define <8 x i16> @neon.ushl8h_no_constant_shift(ptr %A) nounwind sanitize_memory {5611; CHECK-LABEL: define <8 x i16> @neon.ushl8h_no_constant_shift(5612; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {5613; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85614; CHECK-NEXT: call void @llvm.donothing()5615; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05616; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]5617; CHECK: 2:5618; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5619; CHECK-NEXT: unreachable5620; CHECK: 3:5621; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[A]], align 85622; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i645623; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885765624; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr5625; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP6]], align 85626; CHECK-NEXT: [[_MSPROP:%.*]] = zext <8 x i8> [[_MSLD]] to <8 x i16>5627; CHECK-NEXT: [[TMP2:%.*]] = zext <8 x i8> [[TMP1]] to <8 x i16>5628; CHECK-NEXT: [[TMP7:%.*]] = bitcast <8 x i16> [[_MSPROP]] to i1285629; CHECK-NEXT: [[TMP8:%.*]] = trunc i128 [[TMP7]] to i645630; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i64 [[TMP8]], 05631; CHECK-NEXT: [[TMP10:%.*]] = sext i1 [[TMP9]] to i1285632; CHECK-NEXT: [[TMP11:%.*]] = bitcast i128 [[TMP10]] to <8 x i16>5633; CHECK-NEXT: [[TMP12:%.*]] = call <8 x i16> @llvm.aarch64.neon.ushl.v8i16(<8 x i16> [[_MSPROP]], <8 x i16> [[TMP2]])5634; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i16> [[TMP12]], [[TMP11]]5635; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i16> @llvm.aarch64.neon.ushl.v8i16(<8 x i16> [[TMP2]], <8 x i16> [[TMP2]])5636; CHECK-NEXT: store <8 x i16> [[_MSPROP1]], ptr @__msan_retval_tls, align 85637; CHECK-NEXT: ret <8 x i16> [[TMP3]]5638;5639 %tmp1 = load <8 x i8>, ptr %A5640 %tmp2 = zext <8 x i8> %tmp1 to <8 x i16>5641 %tmp3 = call <8 x i16> @llvm.aarch64.neon.ushl.v8i16(<8 x i16> %tmp2, <8 x i16> %tmp2)5642 ret <8 x i16> %tmp35643}5644 5645define <4 x i32> @neon.ushl8h_constant_shift_extend_not_2x(ptr %A) nounwind sanitize_memory {5646; CHECK-LABEL: define <4 x i32> @neon.ushl8h_constant_shift_extend_not_2x(5647; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {5648; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85649; CHECK-NEXT: call void @llvm.donothing()5650; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05651; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]5652; CHECK: 2:5653; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5654; CHECK-NEXT: unreachable5655; CHECK: 3:5656; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr [[A]], align 45657; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i645658; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885765659; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr5660; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i8>, ptr [[TMP6]], align 45661; CHECK-NEXT: [[_MSPROP:%.*]] = zext <4 x i8> [[_MSLD]] to <4 x i32>5662; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i8> [[TMP1]] to <4 x i32>5663; CHECK-NEXT: [[TMP7:%.*]] = call <4 x i32> @llvm.aarch64.neon.ushl.v4i32(<4 x i32> [[_MSPROP]], <4 x i32> splat (i32 1))5664; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[TMP7]], zeroinitializer5665; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.ushl.v4i32(<4 x i32> [[TMP2]], <4 x i32> splat (i32 1))5666; CHECK-NEXT: store <4 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 85667; CHECK-NEXT: ret <4 x i32> [[TMP3]]5668;5669 %tmp1 = load <4 x i8>, ptr %A5670 %tmp2 = zext <4 x i8> %tmp1 to <4 x i32>5671 %tmp3 = call <4 x i32> @llvm.aarch64.neon.ushl.v4i32(<4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)5672 ret <4 x i32> %tmp35673}5674 5675define <8 x i16> @neon.ushl8_noext_constant_shift(ptr %A) nounwind sanitize_memory {5676; CHECK-LABEL: define <8 x i16> @neon.ushl8_noext_constant_shift(5677; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {5678; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85679; CHECK-NEXT: call void @llvm.donothing()5680; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05681; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]5682; CHECK: 2:5683; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5684; CHECK-NEXT: unreachable5685; CHECK: 3:5686; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 165687; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i645688; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885765689; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr5690; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP6]], align 165691; CHECK-NEXT: [[TMP7:%.*]] = call <8 x i16> @llvm.aarch64.neon.ushl.v8i16(<8 x i16> [[_MSLD]], <8 x i16> splat (i16 1))5692; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP7]], zeroinitializer5693; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i16> @llvm.aarch64.neon.ushl.v8i16(<8 x i16> [[TMP1]], <8 x i16> splat (i16 1))5694; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 85695; CHECK-NEXT: ret <8 x i16> [[TMP3]]5696;5697 %tmp1 = load <8 x i16>, ptr %A5698 %tmp3 = call <8 x i16> @llvm.aarch64.neon.ushl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)5699 ret <8 x i16> %tmp35700}5701 5702define <4 x i32> @neon.ushll4s_constant_shift(ptr %A) nounwind sanitize_memory {5703; CHECK-LABEL: define <4 x i32> @neon.ushll4s_constant_shift(5704; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {5705; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85706; CHECK-NEXT: call void @llvm.donothing()5707; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05708; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]5709; CHECK: 2:5710; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5711; CHECK-NEXT: unreachable5712; CHECK: 3:5713; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 85714; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i645715; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885765716; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr5717; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP6]], align 85718; CHECK-NEXT: [[_MSPROP:%.*]] = zext <4 x i16> [[_MSLD]] to <4 x i32>5719; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i16> [[TMP1]] to <4 x i32>5720; CHECK-NEXT: [[TMP7:%.*]] = call <4 x i32> @llvm.aarch64.neon.ushl.v4i32(<4 x i32> [[_MSPROP]], <4 x i32> splat (i32 1))5721; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[TMP7]], zeroinitializer5722; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.ushl.v4i32(<4 x i32> [[TMP2]], <4 x i32> splat (i32 1))5723; CHECK-NEXT: store <4 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 85724; CHECK-NEXT: ret <4 x i32> [[TMP3]]5725;5726 %tmp1 = load <4 x i16>, ptr %A5727 %tmp2 = zext <4 x i16> %tmp1 to <4 x i32>5728 %tmp3 = call <4 x i32> @llvm.aarch64.neon.ushl.v4i32(<4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)5729 ret <4 x i32> %tmp35730}5731 5732; FIXME: unnecessary ushll.4s v0, v0, #0?5733define <4 x i32> @neon.ushll4s_neg_constant_shift(ptr %A) nounwind sanitize_memory {5734; CHECK-LABEL: define <4 x i32> @neon.ushll4s_neg_constant_shift(5735; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {5736; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85737; CHECK-NEXT: call void @llvm.donothing()5738; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05739; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]5740; CHECK: 2:5741; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5742; CHECK-NEXT: unreachable5743; CHECK: 3:5744; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 85745; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i645746; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885765747; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr5748; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP6]], align 85749; CHECK-NEXT: [[_MSPROP:%.*]] = zext <4 x i16> [[_MSLD]] to <4 x i32>5750; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i16> [[TMP1]] to <4 x i32>5751; CHECK-NEXT: [[TMP7:%.*]] = call <4 x i32> @llvm.aarch64.neon.ushl.v4i32(<4 x i32> [[_MSPROP]], <4 x i32> splat (i32 -1))5752; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[TMP7]], zeroinitializer5753; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.ushl.v4i32(<4 x i32> [[TMP2]], <4 x i32> splat (i32 -1))5754; CHECK-NEXT: store <4 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 85755; CHECK-NEXT: ret <4 x i32> [[TMP3]]5756;5757 %tmp1 = load <4 x i16>, ptr %A5758 %tmp2 = zext <4 x i16> %tmp1 to <4 x i32>5759 %tmp3 = call <4 x i32> @llvm.aarch64.neon.ushl.v4i32(<4 x i32> %tmp2, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)5760 ret <4 x i32> %tmp35761}5762 5763; FIXME: should be constant folded.5764define <4 x i32> @neon.ushll4s_constant_fold() nounwind sanitize_memory {5765; CHECK-LABEL: define <4 x i32> @neon.ushll4s_constant_fold(5766; CHECK-SAME: ) #[[ATTR0]] {5767; CHECK-NEXT: call void @llvm.donothing()5768; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.aarch64.neon.ushl.v4i32(<4 x i32> zeroinitializer, <4 x i32> splat (i32 1))5769; CHECK-NEXT: [[TMP2:%.*]] = or <4 x i32> [[TMP1]], zeroinitializer5770; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.ushl.v4i32(<4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32> splat (i32 1))5771; CHECK-NEXT: store <4 x i32> [[TMP2]], ptr @__msan_retval_tls, align 85772; CHECK-NEXT: ret <4 x i32> [[TMP3]]5773;5774 %tmp3 = call <4 x i32> @llvm.aarch64.neon.ushl.v4i32(<4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)5775 ret <4 x i32> %tmp35776}5777 5778define <2 x i64> @neon.ushll2d_constant_shift(ptr %A) nounwind sanitize_memory {5779; CHECK-LABEL: define <2 x i64> @neon.ushll2d_constant_shift(5780; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {5781; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85782; CHECK-NEXT: call void @llvm.donothing()5783; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05784; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]5785; CHECK: 2:5786; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5787; CHECK-NEXT: unreachable5788; CHECK: 3:5789; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 85790; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i645791; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885765792; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr5793; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP6]], align 85794; CHECK-NEXT: [[_MSPROP:%.*]] = zext <2 x i32> [[_MSLD]] to <2 x i64>5795; CHECK-NEXT: [[TMP2:%.*]] = zext <2 x i32> [[TMP1]] to <2 x i64>5796; CHECK-NEXT: [[TMP7:%.*]] = call <2 x i64> @llvm.aarch64.neon.ushl.v2i64(<2 x i64> [[_MSPROP]], <2 x i64> splat (i64 1))5797; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> [[TMP7]], zeroinitializer5798; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.ushl.v2i64(<2 x i64> [[TMP2]], <2 x i64> splat (i64 1))5799; CHECK-NEXT: store <2 x i64> [[_MSPROP1]], ptr @__msan_retval_tls, align 85800; CHECK-NEXT: ret <2 x i64> [[TMP3]]5801;5802 %tmp1 = load <2 x i32>, ptr %A5803 %tmp2 = zext <2 x i32> %tmp1 to <2 x i64>5804 %tmp3 = call <2 x i64> @llvm.aarch64.neon.ushl.v2i64(<2 x i64> %tmp2, <2 x i64> <i64 1, i64 1>)5805 ret <2 x i64> %tmp35806}5807 5808define <1 x i64> @neon.ushl_vscalar_constant_shift(ptr %A) nounwind sanitize_memory {5809; CHECK-LABEL: define <1 x i64> @neon.ushl_vscalar_constant_shift(5810; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {5811; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85812; CHECK-NEXT: call void @llvm.donothing()5813; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05814; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]5815; CHECK: 2:5816; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5817; CHECK-NEXT: unreachable5818; CHECK: 3:5819; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i32>, ptr [[A]], align 45820; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i645821; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885765822; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr5823; CHECK-NEXT: [[_MSLD:%.*]] = load <1 x i32>, ptr [[TMP6]], align 45824; CHECK-NEXT: [[_MSPROP:%.*]] = zext <1 x i32> [[_MSLD]] to <1 x i64>5825; CHECK-NEXT: [[TMP2:%.*]] = zext <1 x i32> [[TMP1]] to <1 x i64>5826; CHECK-NEXT: [[TMP7:%.*]] = call <1 x i64> @llvm.aarch64.neon.ushl.v1i64(<1 x i64> [[_MSPROP]], <1 x i64> splat (i64 1))5827; CHECK-NEXT: [[_MSPROP1:%.*]] = or <1 x i64> [[TMP7]], zeroinitializer5828; CHECK-NEXT: [[TMP3:%.*]] = call <1 x i64> @llvm.aarch64.neon.ushl.v1i64(<1 x i64> [[TMP2]], <1 x i64> splat (i64 1))5829; CHECK-NEXT: store <1 x i64> [[_MSPROP1]], ptr @__msan_retval_tls, align 85830; CHECK-NEXT: ret <1 x i64> [[TMP3]]5831;5832 %tmp1 = load <1 x i32>, ptr %A5833 %tmp2 = zext <1 x i32> %tmp1 to <1 x i64>5834 %tmp3 = call <1 x i64> @llvm.aarch64.neon.ushl.v1i64(<1 x i64> %tmp2, <1 x i64> <i64 1>)5835 ret <1 x i64> %tmp35836}5837 5838define i64 @neon.ushl_scalar_constant_shift(ptr %A) nounwind sanitize_memory {5839; CHECK-LABEL: define i64 @neon.ushl_scalar_constant_shift(5840; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {5841; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85842; CHECK-NEXT: call void @llvm.donothing()5843; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05844; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]5845; CHECK: 2:5846; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5847; CHECK-NEXT: unreachable5848; CHECK: 3:5849; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 45850; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i645851; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885765852; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr5853; CHECK-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP6]], align 45854; CHECK-NEXT: [[_MSPROP:%.*]] = zext i32 [[_MSLD]] to i645855; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i645856; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.aarch64.neon.ushl.i64(i64 [[_MSPROP]], i64 1)5857; CHECK-NEXT: [[_MSPROP1:%.*]] = or i64 [[TMP7]], 05858; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.ushl.i64(i64 [[TMP2]], i64 1)5859; CHECK-NEXT: store i64 [[_MSPROP1]], ptr @__msan_retval_tls, align 85860; CHECK-NEXT: ret i64 [[TMP3]]5861;5862 %tmp1 = load i32, ptr %A5863 %tmp2 = zext i32 %tmp1 to i645864 %tmp3 = call i64 @llvm.aarch64.neon.ushl.i64(i64 %tmp2, i64 1)5865 ret i64 %tmp35866}5867 5868define <8 x i16> @sshll8h(ptr %A) nounwind sanitize_memory {5869; CHECK-LABEL: define <8 x i16> @sshll8h(5870; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {5871; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85872; CHECK-NEXT: call void @llvm.donothing()5873; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05874; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]5875; CHECK: 2:5876; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5877; CHECK-NEXT: unreachable5878; CHECK: 3:5879; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[A]], align 85880; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i645881; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885765882; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr5883; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP6]], align 85884; CHECK-NEXT: [[_MSPROP:%.*]] = sext <8 x i8> [[_MSLD]] to <8 x i16>5885; CHECK-NEXT: [[TMP2:%.*]] = sext <8 x i8> [[TMP1]] to <8 x i16>5886; CHECK-NEXT: [[TMP7:%.*]] = shl <8 x i16> [[_MSPROP]], splat (i16 1)5887; CHECK-NEXT: [[TMP8:%.*]] = or <8 x i16> [[TMP7]], zeroinitializer5888; CHECK-NEXT: [[TMP3:%.*]] = shl <8 x i16> [[TMP2]], splat (i16 1)5889; CHECK-NEXT: store <8 x i16> [[TMP8]], ptr @__msan_retval_tls, align 85890; CHECK-NEXT: ret <8 x i16> [[TMP3]]5891;5892 %tmp1 = load <8 x i8>, ptr %A5893 %tmp2 = sext <8 x i8> %tmp1 to <8 x i16>5894 %tmp3 = shl <8 x i16> %tmp2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>5895 ret <8 x i16> %tmp35896}5897 5898define <2 x i64> @sshll2d(ptr %A) nounwind sanitize_memory {5899; CHECK-LABEL: define <2 x i64> @sshll2d(5900; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {5901; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85902; CHECK-NEXT: call void @llvm.donothing()5903; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05904; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]5905; CHECK: 2:5906; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5907; CHECK-NEXT: unreachable5908; CHECK: 3:5909; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 85910; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i645911; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885765912; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr5913; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP6]], align 85914; CHECK-NEXT: [[_MSPROP:%.*]] = sext <2 x i32> [[_MSLD]] to <2 x i64>5915; CHECK-NEXT: [[TMP2:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64>5916; CHECK-NEXT: [[TMP7:%.*]] = shl <2 x i64> [[_MSPROP]], splat (i64 1)5917; CHECK-NEXT: [[TMP8:%.*]] = or <2 x i64> [[TMP7]], zeroinitializer5918; CHECK-NEXT: [[TMP3:%.*]] = shl <2 x i64> [[TMP2]], splat (i64 1)5919; CHECK-NEXT: store <2 x i64> [[TMP8]], ptr @__msan_retval_tls, align 85920; CHECK-NEXT: ret <2 x i64> [[TMP3]]5921;5922 %tmp1 = load <2 x i32>, ptr %A5923 %tmp2 = sext <2 x i32> %tmp1 to <2 x i64>5924 %tmp3 = shl <2 x i64> %tmp2, <i64 1, i64 1>5925 ret <2 x i64> %tmp35926}5927 5928declare <16 x i8> @llvm.aarch64.neon.sshl.v16i8(<16 x i8>, <16 x i8>)5929declare <8 x i16> @llvm.aarch64.neon.sshl.v8i16(<8 x i16>, <8 x i16>)5930declare <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32>, <4 x i32>)5931declare <2 x i64> @llvm.aarch64.neon.sshl.v2i64(<2 x i64>, <2 x i64>)5932declare <1 x i64> @llvm.aarch64.neon.sshl.v1i64(<1 x i64>, <1 x i64>)5933declare i64 @llvm.aarch64.neon.sshl.i64(i64, i64)5934 5935define <16 x i8> @neon.sshl16b_constant_shift(ptr %A) nounwind sanitize_memory {5936; CHECK-LABEL: define <16 x i8> @neon.sshl16b_constant_shift(5937; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {5938; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85939; CHECK-NEXT: call void @llvm.donothing()5940; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05941; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]5942; CHECK: 2:5943; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5944; CHECK-NEXT: unreachable5945; CHECK: 3:5946; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[A]], align 165947; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i645948; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885765949; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr5950; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP6]], align 165951; CHECK-NEXT: [[TMP7:%.*]] = call <16 x i8> @llvm.aarch64.neon.sshl.v16i8(<16 x i8> [[_MSLD]], <16 x i8> splat (i8 1))5952; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP7]], zeroinitializer5953; CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.aarch64.neon.sshl.v16i8(<16 x i8> [[TMP1]], <16 x i8> splat (i8 1))5954; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 85955; CHECK-NEXT: ret <16 x i8> [[TMP2]]5956;5957 %tmp1 = load <16 x i8>, ptr %A5958 %tmp2 = call <16 x i8> @llvm.aarch64.neon.sshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)5959 ret <16 x i8> %tmp25960}5961 5962define <16 x i8> @neon.sshl16b_non_splat_constant_shift(ptr %A) nounwind sanitize_memory {5963; CHECK-LABEL: define <16 x i8> @neon.sshl16b_non_splat_constant_shift(5964; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {5965; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85966; CHECK-NEXT: call void @llvm.donothing()5967; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05968; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]5969; CHECK: 2:5970; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5971; CHECK-NEXT: unreachable5972; CHECK: 3:5973; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[A]], align 165974; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i645975; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885765976; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr5977; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP6]], align 165978; CHECK-NEXT: [[TMP7:%.*]] = call <16 x i8> @llvm.aarch64.neon.sshl.v16i8(<16 x i8> [[_MSLD]], <16 x i8> <i8 6, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)5979; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP7]], zeroinitializer5980; CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.aarch64.neon.sshl.v16i8(<16 x i8> [[TMP1]], <16 x i8> <i8 6, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)5981; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 85982; CHECK-NEXT: ret <16 x i8> [[TMP2]]5983;5984 %tmp1 = load <16 x i8>, ptr %A5985 %tmp2 = call <16 x i8> @llvm.aarch64.neon.sshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 6, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)5986 ret <16 x i8> %tmp25987}5988 5989define <16 x i8> @neon.sshl16b_neg_constant_shift(ptr %A) nounwind sanitize_memory {5990; CHECK-LABEL: define <16 x i8> @neon.sshl16b_neg_constant_shift(5991; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {5992; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 85993; CHECK-NEXT: call void @llvm.donothing()5994; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 05995; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]5996; CHECK: 2:5997; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]5998; CHECK-NEXT: unreachable5999; CHECK: 3:6000; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[A]], align 166001; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i646002; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885766003; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr6004; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP6]], align 166005; CHECK-NEXT: [[TMP7:%.*]] = call <16 x i8> @llvm.aarch64.neon.sshl.v16i8(<16 x i8> [[_MSLD]], <16 x i8> splat (i8 -2))6006; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP7]], zeroinitializer6007; CHECK-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.aarch64.neon.sshl.v16i8(<16 x i8> [[TMP1]], <16 x i8> splat (i8 -2))6008; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 86009; CHECK-NEXT: ret <16 x i8> [[TMP2]]6010;6011 %tmp1 = load <16 x i8>, ptr %A6012 %tmp2 = call <16 x i8> @llvm.aarch64.neon.sshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2, i8 -2>)6013 ret <16 x i8> %tmp26014}6015 6016define <8 x i16> @neon.sshll8h_constant_shift(ptr %A) nounwind sanitize_memory {6017; CHECK-LABEL: define <8 x i16> @neon.sshll8h_constant_shift(6018; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {6019; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86020; CHECK-NEXT: call void @llvm.donothing()6021; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06022; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]6023; CHECK: 2:6024; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6025; CHECK-NEXT: unreachable6026; CHECK: 3:6027; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[A]], align 86028; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i646029; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885766030; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr6031; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP6]], align 86032; CHECK-NEXT: [[_MSPROP:%.*]] = sext <8 x i8> [[_MSLD]] to <8 x i16>6033; CHECK-NEXT: [[TMP2:%.*]] = sext <8 x i8> [[TMP1]] to <8 x i16>6034; CHECK-NEXT: [[TMP7:%.*]] = call <8 x i16> @llvm.aarch64.neon.sshl.v8i16(<8 x i16> [[_MSPROP]], <8 x i16> splat (i16 1))6035; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i16> [[TMP7]], zeroinitializer6036; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i16> @llvm.aarch64.neon.sshl.v8i16(<8 x i16> [[TMP2]], <8 x i16> splat (i16 1))6037; CHECK-NEXT: store <8 x i16> [[_MSPROP1]], ptr @__msan_retval_tls, align 86038; CHECK-NEXT: ret <8 x i16> [[TMP3]]6039;6040 %tmp1 = load <8 x i8>, ptr %A6041 %tmp2 = sext <8 x i8> %tmp1 to <8 x i16>6042 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sshl.v8i16(<8 x i16> %tmp2, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)6043 ret <8 x i16> %tmp36044}6045 6046define <4 x i32> @neon.sshl4s_wrong_ext_constant_shift(ptr %A) nounwind sanitize_memory {6047; CHECK-LABEL: define <4 x i32> @neon.sshl4s_wrong_ext_constant_shift(6048; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {6049; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86050; CHECK-NEXT: call void @llvm.donothing()6051; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06052; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]6053; CHECK: 2:6054; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6055; CHECK-NEXT: unreachable6056; CHECK: 3:6057; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr [[A]], align 46058; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i646059; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885766060; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr6061; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i8>, ptr [[TMP6]], align 46062; CHECK-NEXT: [[_MSPROP:%.*]] = sext <4 x i8> [[_MSLD]] to <4 x i32>6063; CHECK-NEXT: [[TMP2:%.*]] = sext <4 x i8> [[TMP1]] to <4 x i32>6064; CHECK-NEXT: [[TMP7:%.*]] = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> [[_MSPROP]], <4 x i32> splat (i32 1))6065; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[TMP7]], zeroinitializer6066; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> [[TMP2]], <4 x i32> splat (i32 1))6067; CHECK-NEXT: store <4 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 86068; CHECK-NEXT: ret <4 x i32> [[TMP3]]6069;6070 %tmp1 = load <4 x i8>, ptr %A6071 %tmp2 = sext <4 x i8> %tmp1 to <4 x i32>6072 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)6073 ret <4 x i32> %tmp36074}6075 6076define <4 x i32> @neon.sshll4s_constant_shift(ptr %A) nounwind sanitize_memory {6077; CHECK-LABEL: define <4 x i32> @neon.sshll4s_constant_shift(6078; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {6079; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86080; CHECK-NEXT: call void @llvm.donothing()6081; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06082; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]6083; CHECK: 2:6084; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6085; CHECK-NEXT: unreachable6086; CHECK: 3:6087; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 86088; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i646089; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885766090; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr6091; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP6]], align 86092; CHECK-NEXT: [[_MSPROP:%.*]] = sext <4 x i16> [[_MSLD]] to <4 x i32>6093; CHECK-NEXT: [[TMP2:%.*]] = sext <4 x i16> [[TMP1]] to <4 x i32>6094; CHECK-NEXT: [[TMP7:%.*]] = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> [[_MSPROP]], <4 x i32> splat (i32 1))6095; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[TMP7]], zeroinitializer6096; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> [[TMP2]], <4 x i32> splat (i32 1))6097; CHECK-NEXT: store <4 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 86098; CHECK-NEXT: ret <4 x i32> [[TMP3]]6099;6100 %tmp1 = load <4 x i16>, ptr %A6101 %tmp2 = sext <4 x i16> %tmp1 to <4 x i32>6102 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> %tmp2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)6103 ret <4 x i32> %tmp36104}6105 6106define <4 x i32> @neon.sshll4s_neg_constant_shift(ptr %A) nounwind sanitize_memory {6107; CHECK-LABEL: define <4 x i32> @neon.sshll4s_neg_constant_shift(6108; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {6109; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86110; CHECK-NEXT: call void @llvm.donothing()6111; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06112; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]6113; CHECK: 2:6114; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6115; CHECK-NEXT: unreachable6116; CHECK: 3:6117; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 86118; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i646119; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885766120; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr6121; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP6]], align 86122; CHECK-NEXT: [[_MSPROP:%.*]] = sext <4 x i16> [[_MSLD]] to <4 x i32>6123; CHECK-NEXT: [[TMP2:%.*]] = sext <4 x i16> [[TMP1]] to <4 x i32>6124; CHECK-NEXT: [[TMP7:%.*]] = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> [[_MSPROP]], <4 x i32> splat (i32 -1))6125; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i32> [[TMP7]], zeroinitializer6126; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> [[TMP2]], <4 x i32> splat (i32 -1))6127; CHECK-NEXT: store <4 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 86128; CHECK-NEXT: ret <4 x i32> [[TMP3]]6129;6130 %tmp1 = load <4 x i16>, ptr %A6131 %tmp2 = sext <4 x i16> %tmp1 to <4 x i32>6132 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> %tmp2, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)6133 ret <4 x i32> %tmp36134}6135 6136; FIXME: should be constant folded.6137define <4 x i32> @neon.sshl4s_constant_fold() nounwind sanitize_memory {6138; CHECK-LABEL: define <4 x i32> @neon.sshl4s_constant_fold(6139; CHECK-SAME: ) #[[ATTR0]] {6140; CHECK-NEXT: call void @llvm.donothing()6141; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> zeroinitializer, <4 x i32> splat (i32 2))6142; CHECK-NEXT: [[TMP2:%.*]] = or <4 x i32> [[TMP1]], zeroinitializer6143; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32> splat (i32 2))6144; CHECK-NEXT: store <4 x i32> [[TMP2]], ptr @__msan_retval_tls, align 86145; CHECK-NEXT: ret <4 x i32> [[TMP3]]6146;6147 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32> <i32 2, i32 2, i32 2, i32 2>)6148 ret <4 x i32> %tmp36149}6150 6151define <4 x i32> @neon.sshl4s_no_fold(ptr %A) nounwind sanitize_memory {6152; CHECK-LABEL: define <4 x i32> @neon.sshl4s_no_fold(6153; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {6154; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86155; CHECK-NEXT: call void @llvm.donothing()6156; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06157; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]6158; CHECK: 2:6159; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6160; CHECK-NEXT: unreachable6161; CHECK: 3:6162; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 166163; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i646164; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885766165; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr6166; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP6]], align 166167; CHECK-NEXT: [[TMP7:%.*]] = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> [[_MSLD]], <4 x i32> splat (i32 1))6168; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP7]], zeroinitializer6169; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> [[TMP1]], <4 x i32> splat (i32 1))6170; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 86171; CHECK-NEXT: ret <4 x i32> [[TMP3]]6172;6173 %tmp1 = load <4 x i32>, ptr %A6174 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)6175 ret <4 x i32> %tmp36176}6177 6178define <2 x i64> @neon.sshll2d_constant_shift(ptr %A) nounwind sanitize_memory {6179; CHECK-LABEL: define <2 x i64> @neon.sshll2d_constant_shift(6180; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {6181; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86182; CHECK-NEXT: call void @llvm.donothing()6183; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06184; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]6185; CHECK: 2:6186; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6187; CHECK-NEXT: unreachable6188; CHECK: 3:6189; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 86190; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i646191; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885766192; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr6193; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP6]], align 86194; CHECK-NEXT: [[_MSPROP:%.*]] = sext <2 x i32> [[_MSLD]] to <2 x i64>6195; CHECK-NEXT: [[TMP2:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64>6196; CHECK-NEXT: [[TMP7:%.*]] = call <2 x i64> @llvm.aarch64.neon.sshl.v2i64(<2 x i64> [[_MSPROP]], <2 x i64> splat (i64 1))6197; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> [[TMP7]], zeroinitializer6198; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.sshl.v2i64(<2 x i64> [[TMP2]], <2 x i64> splat (i64 1))6199; CHECK-NEXT: store <2 x i64> [[_MSPROP1]], ptr @__msan_retval_tls, align 86200; CHECK-NEXT: ret <2 x i64> [[TMP3]]6201;6202 %tmp1 = load <2 x i32>, ptr %A6203 %tmp2 = sext <2 x i32> %tmp1 to <2 x i64>6204 %tmp3 = call <2 x i64> @llvm.aarch64.neon.sshl.v2i64(<2 x i64> %tmp2, <2 x i64> <i64 1, i64 1>)6205 ret <2 x i64> %tmp36206}6207 6208define <1 x i64> @neon.sshll_vscalar_constant_shift(ptr %A) nounwind sanitize_memory {6209; CHECK-LABEL: define <1 x i64> @neon.sshll_vscalar_constant_shift(6210; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {6211; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86212; CHECK-NEXT: call void @llvm.donothing()6213; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06214; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]6215; CHECK: 2:6216; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6217; CHECK-NEXT: unreachable6218; CHECK: 3:6219; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i32>, ptr [[A]], align 46220; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i646221; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885766222; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr6223; CHECK-NEXT: [[_MSLD:%.*]] = load <1 x i32>, ptr [[TMP6]], align 46224; CHECK-NEXT: [[_MSPROP:%.*]] = zext <1 x i32> [[_MSLD]] to <1 x i64>6225; CHECK-NEXT: [[TMP2:%.*]] = zext <1 x i32> [[TMP1]] to <1 x i64>6226; CHECK-NEXT: [[TMP7:%.*]] = call <1 x i64> @llvm.aarch64.neon.sshl.v1i64(<1 x i64> [[_MSPROP]], <1 x i64> splat (i64 1))6227; CHECK-NEXT: [[_MSPROP1:%.*]] = or <1 x i64> [[TMP7]], zeroinitializer6228; CHECK-NEXT: [[TMP3:%.*]] = call <1 x i64> @llvm.aarch64.neon.sshl.v1i64(<1 x i64> [[TMP2]], <1 x i64> splat (i64 1))6229; CHECK-NEXT: store <1 x i64> [[_MSPROP1]], ptr @__msan_retval_tls, align 86230; CHECK-NEXT: ret <1 x i64> [[TMP3]]6231;6232 %tmp1 = load <1 x i32>, ptr %A6233 %tmp2 = zext <1 x i32> %tmp1 to <1 x i64>6234 %tmp3 = call <1 x i64> @llvm.aarch64.neon.sshl.v1i64(<1 x i64> %tmp2, <1 x i64> <i64 1>)6235 ret <1 x i64> %tmp36236}6237 6238define i64 @neon.sshll_scalar_constant_shift(ptr %A) nounwind sanitize_memory {6239; CHECK-LABEL: define i64 @neon.sshll_scalar_constant_shift(6240; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {6241; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86242; CHECK-NEXT: call void @llvm.donothing()6243; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06244; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]6245; CHECK: 2:6246; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6247; CHECK-NEXT: unreachable6248; CHECK: 3:6249; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 46250; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i646251; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885766252; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr6253; CHECK-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP6]], align 46254; CHECK-NEXT: [[_MSPROP:%.*]] = zext i32 [[_MSLD]] to i646255; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i646256; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.aarch64.neon.sshl.i64(i64 [[_MSPROP]], i64 1)6257; CHECK-NEXT: [[_MSPROP1:%.*]] = or i64 [[TMP7]], 06258; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.sshl.i64(i64 [[TMP2]], i64 1)6259; CHECK-NEXT: store i64 [[_MSPROP1]], ptr @__msan_retval_tls, align 86260; CHECK-NEXT: ret i64 [[TMP3]]6261;6262 %tmp1 = load i32, ptr %A6263 %tmp2 = zext i32 %tmp1 to i646264 %tmp3 = call i64 @llvm.aarch64.neon.sshl.i64(i64 %tmp2, i64 1)6265 ret i64 %tmp36266}6267 6268define i64 @neon.sshll_scalar_constant_shift_m1(ptr %A) nounwind sanitize_memory {6269; CHECK-LABEL: define i64 @neon.sshll_scalar_constant_shift_m1(6270; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {6271; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86272; CHECK-NEXT: call void @llvm.donothing()6273; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06274; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]6275; CHECK: 2:6276; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6277; CHECK-NEXT: unreachable6278; CHECK: 3:6279; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[A]], align 46280; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i646281; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885766282; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr6283; CHECK-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP6]], align 46284; CHECK-NEXT: [[_MSPROP:%.*]] = zext i32 [[_MSLD]] to i646285; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i646286; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.aarch64.neon.sshl.i64(i64 [[_MSPROP]], i64 -1)6287; CHECK-NEXT: [[_MSPROP1:%.*]] = or i64 [[TMP7]], 06288; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.sshl.i64(i64 [[TMP2]], i64 -1)6289; CHECK-NEXT: store i64 [[_MSPROP1]], ptr @__msan_retval_tls, align 86290; CHECK-NEXT: ret i64 [[TMP3]]6291;6292 %tmp1 = load i32, ptr %A6293 %tmp2 = zext i32 %tmp1 to i646294 %tmp3 = call i64 @llvm.aarch64.neon.sshl.i64(i64 %tmp2, i64 -1)6295 ret i64 %tmp36296}6297 6298; FIXME: should be constant folded.6299define <2 x i64> @neon.sshl2d_constant_fold() nounwind sanitize_memory {6300; CHECK-LABEL: define <2 x i64> @neon.sshl2d_constant_fold(6301; CHECK-SAME: ) #[[ATTR0]] {6302; CHECK-NEXT: call void @llvm.donothing()6303; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i64> @llvm.aarch64.neon.sshl.v2i64(<2 x i64> zeroinitializer, <2 x i64> splat (i64 1))6304; CHECK-NEXT: [[TMP2:%.*]] = or <2 x i64> [[TMP1]], zeroinitializer6305; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.sshl.v2i64(<2 x i64> <i64 99, i64 1000>, <2 x i64> splat (i64 1))6306; CHECK-NEXT: store <2 x i64> [[TMP2]], ptr @__msan_retval_tls, align 86307; CHECK-NEXT: ret <2 x i64> [[TMP3]]6308;6309 %tmp3 = call <2 x i64> @llvm.aarch64.neon.sshl.v2i64(<2 x i64> <i64 99, i64 1000>, <2 x i64> <i64 1, i64 1>)6310 ret <2 x i64> %tmp36311}6312 6313define <2 x i64> @neon.sshl2d_no_fold(ptr %A) nounwind sanitize_memory {6314; CHECK-LABEL: define <2 x i64> @neon.sshl2d_no_fold(6315; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {6316; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86317; CHECK-NEXT: call void @llvm.donothing()6318; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06319; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]6320; CHECK: 2:6321; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6322; CHECK-NEXT: unreachable6323; CHECK: 3:6324; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr [[A]], align 166325; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i646326; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885766327; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr6328; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP6]], align 166329; CHECK-NEXT: [[TMP7:%.*]] = call <2 x i64> @llvm.aarch64.neon.sshl.v2i64(<2 x i64> [[_MSLD]], <2 x i64> splat (i64 2))6330; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP7]], zeroinitializer6331; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.sshl.v2i64(<2 x i64> [[TMP2]], <2 x i64> splat (i64 2))6332; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 86333; CHECK-NEXT: ret <2 x i64> [[TMP3]]6334;6335 %tmp2 = load <2 x i64>, ptr %A6336 %tmp3 = call <2 x i64> @llvm.aarch64.neon.sshl.v2i64(<2 x i64> %tmp2, <2 x i64> <i64 2, i64 2>)6337 ret <2 x i64> %tmp36338}6339 6340define <8 x i16> @sshll2_8h(ptr %A) nounwind sanitize_memory {6341; CHECK-LABEL: define <8 x i16> @sshll2_8h(6342; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {6343; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86344; CHECK-NEXT: call void @llvm.donothing()6345; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06346; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]6347; CHECK: 2:6348; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6349; CHECK-NEXT: unreachable6350; CHECK: 3:6351; CHECK-NEXT: [[LOAD1:%.*]] = load <16 x i8>, ptr [[A]], align 166352; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i646353; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885766354; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr6355; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP6]], align 166356; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <16 x i8> [[_MSLD]], <16 x i8> splat (i8 -1), <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>6357; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <16 x i8> [[LOAD1]], <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>6358; CHECK-NEXT: [[_MSPROP1:%.*]] = sext <8 x i8> [[_MSPROP]] to <8 x i16>6359; CHECK-NEXT: [[TMP2:%.*]] = sext <8 x i8> [[TMP1]] to <8 x i16>6360; CHECK-NEXT: [[TMP7:%.*]] = shl <8 x i16> [[_MSPROP1]], splat (i16 1)6361; CHECK-NEXT: [[TMP8:%.*]] = or <8 x i16> [[TMP7]], zeroinitializer6362; CHECK-NEXT: [[TMP3:%.*]] = shl <8 x i16> [[TMP2]], splat (i16 1)6363; CHECK-NEXT: store <8 x i16> [[TMP8]], ptr @__msan_retval_tls, align 86364; CHECK-NEXT: ret <8 x i16> [[TMP3]]6365;6366 %load1 = load <16 x i8>, ptr %A6367 %tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>6368 %tmp2 = sext <8 x i8> %tmp1 to <8 x i16>6369 %tmp3 = shl <8 x i16> %tmp2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>6370 ret <8 x i16> %tmp36371}6372 6373define <4 x i32> @sshll2_4s(ptr %A) nounwind sanitize_memory {6374; CHECK-LABEL: define <4 x i32> @sshll2_4s(6375; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {6376; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86377; CHECK-NEXT: call void @llvm.donothing()6378; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06379; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]6380; CHECK: 2:6381; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6382; CHECK-NEXT: unreachable6383; CHECK: 3:6384; CHECK-NEXT: [[LOAD1:%.*]] = load <8 x i16>, ptr [[A]], align 166385; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i646386; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885766387; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr6388; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP6]], align 166389; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i16> [[_MSLD]], <8 x i16> splat (i16 -1), <4 x i32> <i32 4, i32 5, i32 6, i32 7>6390; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <8 x i16> [[LOAD1]], <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>6391; CHECK-NEXT: [[_MSPROP1:%.*]] = sext <4 x i16> [[_MSPROP]] to <4 x i32>6392; CHECK-NEXT: [[TMP2:%.*]] = sext <4 x i16> [[TMP1]] to <4 x i32>6393; CHECK-NEXT: [[TMP7:%.*]] = shl <4 x i32> [[_MSPROP1]], splat (i32 1)6394; CHECK-NEXT: [[TMP8:%.*]] = or <4 x i32> [[TMP7]], zeroinitializer6395; CHECK-NEXT: [[TMP3:%.*]] = shl <4 x i32> [[TMP2]], splat (i32 1)6396; CHECK-NEXT: store <4 x i32> [[TMP8]], ptr @__msan_retval_tls, align 86397; CHECK-NEXT: ret <4 x i32> [[TMP3]]6398;6399 %load1 = load <8 x i16>, ptr %A6400 %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>6401 %tmp2 = sext <4 x i16> %tmp1 to <4 x i32>6402 %tmp3 = shl <4 x i32> %tmp2, <i32 1, i32 1, i32 1, i32 1>6403 ret <4 x i32> %tmp36404}6405 6406define <2 x i64> @sshll2_2d(ptr %A) nounwind sanitize_memory {6407; CHECK-LABEL: define <2 x i64> @sshll2_2d(6408; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {6409; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86410; CHECK-NEXT: call void @llvm.donothing()6411; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06412; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]6413; CHECK: 2:6414; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6415; CHECK-NEXT: unreachable6416; CHECK: 3:6417; CHECK-NEXT: [[LOAD1:%.*]] = load <4 x i32>, ptr [[A]], align 166418; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i646419; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885766420; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr6421; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP6]], align 166422; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i32> [[_MSLD]], <4 x i32> splat (i32 -1), <2 x i32> <i32 2, i32 3>6423; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[LOAD1]], <4 x i32> undef, <2 x i32> <i32 2, i32 3>6424; CHECK-NEXT: [[_MSPROP1:%.*]] = sext <2 x i32> [[_MSPROP]] to <2 x i64>6425; CHECK-NEXT: [[TMP2:%.*]] = sext <2 x i32> [[TMP1]] to <2 x i64>6426; CHECK-NEXT: [[TMP7:%.*]] = shl <2 x i64> [[_MSPROP1]], splat (i64 1)6427; CHECK-NEXT: [[TMP8:%.*]] = or <2 x i64> [[TMP7]], zeroinitializer6428; CHECK-NEXT: [[TMP3:%.*]] = shl <2 x i64> [[TMP2]], splat (i64 1)6429; CHECK-NEXT: store <2 x i64> [[TMP8]], ptr @__msan_retval_tls, align 86430; CHECK-NEXT: ret <2 x i64> [[TMP3]]6431;6432 %load1 = load <4 x i32>, ptr %A6433 %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>6434 %tmp2 = sext <2 x i32> %tmp1 to <2 x i64>6435 %tmp3 = shl <2 x i64> %tmp2, <i64 1, i64 1>6436 ret <2 x i64> %tmp36437}6438 6439define <8 x i8> @sqshli8b(ptr %A) nounwind sanitize_memory {6440; CHECK-LABEL: define <8 x i8> @sqshli8b(6441; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {6442; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86443; CHECK-NEXT: call void @llvm.donothing()6444; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06445; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]6446; CHECK: 2:6447; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6448; CHECK-NEXT: unreachable6449; CHECK: 3:6450; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[A]], align 86451; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i646452; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885766453; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr6454; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP6]], align 86455; CHECK-NEXT: [[TMP7:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8> [[_MSLD]], <8 x i8> splat (i8 1))6456; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i8> [[TMP7]], zeroinitializer6457; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8> [[TMP1]], <8 x i8> splat (i8 1))6458; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 86459; CHECK-NEXT: ret <8 x i8> [[TMP3]]6460;6461 %tmp1 = load <8 x i8>, ptr %A6462 %tmp3 = call <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)6463 ret <8 x i8> %tmp36464}6465 6466define <4 x i16> @sqshli4h(ptr %A) nounwind sanitize_memory {6467; CHECK-LABEL: define <4 x i16> @sqshli4h(6468; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {6469; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86470; CHECK-NEXT: call void @llvm.donothing()6471; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06472; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]6473; CHECK: 2:6474; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6475; CHECK-NEXT: unreachable6476; CHECK: 3:6477; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 86478; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i646479; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885766480; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr6481; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP6]], align 86482; CHECK-NEXT: [[TMP7:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> [[_MSLD]], <4 x i16> splat (i16 1))6483; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[TMP7]], zeroinitializer6484; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> [[TMP1]], <4 x i16> splat (i16 1))6485; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 86486; CHECK-NEXT: ret <4 x i16> [[TMP3]]6487;6488 %tmp1 = load <4 x i16>, ptr %A6489 %tmp3 = call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 1, i16 1, i16 1, i16 1>)6490 ret <4 x i16> %tmp36491}6492 6493define <2 x i32> @sqshli2s(ptr %A) nounwind sanitize_memory {6494; CHECK-LABEL: define <2 x i32> @sqshli2s(6495; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {6496; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86497; CHECK-NEXT: call void @llvm.donothing()6498; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06499; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]6500; CHECK: 2:6501; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6502; CHECK-NEXT: unreachable6503; CHECK: 3:6504; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 86505; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i646506; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885766507; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr6508; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP6]], align 86509; CHECK-NEXT: [[TMP7:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshl.v2i32(<2 x i32> [[_MSLD]], <2 x i32> splat (i32 1))6510; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[TMP7]], zeroinitializer6511; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshl.v2i32(<2 x i32> [[TMP1]], <2 x i32> splat (i32 1))6512; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 86513; CHECK-NEXT: ret <2 x i32> [[TMP3]]6514;6515 %tmp1 = load <2 x i32>, ptr %A6516 %tmp3 = call <2 x i32> @llvm.aarch64.neon.sqshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 1, i32 1>)6517 ret <2 x i32> %tmp36518}6519 6520define <16 x i8> @sqshli16b(ptr %A) nounwind sanitize_memory {6521; CHECK-LABEL: define <16 x i8> @sqshli16b(6522; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {6523; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86524; CHECK-NEXT: call void @llvm.donothing()6525; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06526; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]6527; CHECK: 2:6528; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6529; CHECK-NEXT: unreachable6530; CHECK: 3:6531; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[A]], align 166532; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i646533; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885766534; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr6535; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP6]], align 166536; CHECK-NEXT: [[TMP7:%.*]] = call <16 x i8> @llvm.aarch64.neon.sqshl.v16i8(<16 x i8> [[_MSLD]], <16 x i8> splat (i8 1))6537; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP7]], zeroinitializer6538; CHECK-NEXT: [[TMP3:%.*]] = call <16 x i8> @llvm.aarch64.neon.sqshl.v16i8(<16 x i8> [[TMP1]], <16 x i8> splat (i8 1))6539; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 86540; CHECK-NEXT: ret <16 x i8> [[TMP3]]6541;6542 %tmp1 = load <16 x i8>, ptr %A6543 %tmp3 = call <16 x i8> @llvm.aarch64.neon.sqshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)6544 ret <16 x i8> %tmp36545}6546 6547define <8 x i16> @sqshli8h(ptr %A) nounwind sanitize_memory {6548; CHECK-LABEL: define <8 x i16> @sqshli8h(6549; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {6550; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86551; CHECK-NEXT: call void @llvm.donothing()6552; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06553; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]6554; CHECK: 2:6555; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6556; CHECK-NEXT: unreachable6557; CHECK: 3:6558; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 166559; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i646560; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885766561; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr6562; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP6]], align 166563; CHECK-NEXT: [[TMP7:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqshl.v8i16(<8 x i16> [[_MSLD]], <8 x i16> splat (i16 1))6564; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP7]], zeroinitializer6565; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqshl.v8i16(<8 x i16> [[TMP1]], <8 x i16> splat (i16 1))6566; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 86567; CHECK-NEXT: ret <8 x i16> [[TMP3]]6568;6569 %tmp1 = load <8 x i16>, ptr %A6570 %tmp3 = call <8 x i16> @llvm.aarch64.neon.sqshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)6571 ret <8 x i16> %tmp36572}6573 6574define <4 x i32> @sqshli4s(ptr %A) nounwind sanitize_memory {6575; CHECK-LABEL: define <4 x i32> @sqshli4s(6576; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {6577; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86578; CHECK-NEXT: call void @llvm.donothing()6579; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06580; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]6581; CHECK: 2:6582; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6583; CHECK-NEXT: unreachable6584; CHECK: 3:6585; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 166586; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i646587; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885766588; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr6589; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP6]], align 166590; CHECK-NEXT: [[TMP7:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqshl.v4i32(<4 x i32> [[_MSLD]], <4 x i32> splat (i32 1))6591; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP7]], zeroinitializer6592; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqshl.v4i32(<4 x i32> [[TMP1]], <4 x i32> splat (i32 1))6593; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 86594; CHECK-NEXT: ret <4 x i32> [[TMP3]]6595;6596 %tmp1 = load <4 x i32>, ptr %A6597 %tmp3 = call <4 x i32> @llvm.aarch64.neon.sqshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)6598 ret <4 x i32> %tmp36599}6600 6601define <2 x i64> @sqshli2d(ptr %A) nounwind sanitize_memory {6602; CHECK-LABEL: define <2 x i64> @sqshli2d(6603; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {6604; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86605; CHECK-NEXT: call void @llvm.donothing()6606; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06607; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]6608; CHECK: 2:6609; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6610; CHECK-NEXT: unreachable6611; CHECK: 3:6612; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 166613; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i646614; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885766615; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr6616; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP6]], align 166617; CHECK-NEXT: [[TMP7:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqshl.v2i64(<2 x i64> [[_MSLD]], <2 x i64> splat (i64 1))6618; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP7]], zeroinitializer6619; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqshl.v2i64(<2 x i64> [[TMP1]], <2 x i64> splat (i64 1))6620; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 86621; CHECK-NEXT: ret <2 x i64> [[TMP3]]6622;6623 %tmp1 = load <2 x i64>, ptr %A6624 %tmp3 = call <2 x i64> @llvm.aarch64.neon.sqshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 1, i64 1>)6625 ret <2 x i64> %tmp36626}6627 6628define <8 x i8> @uqshli8b(ptr %A) nounwind sanitize_memory {6629; CHECK-LABEL: define <8 x i8> @uqshli8b(6630; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {6631; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86632; CHECK-NEXT: call void @llvm.donothing()6633; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06634; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]6635; CHECK: 2:6636; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6637; CHECK-NEXT: unreachable6638; CHECK: 3:6639; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[A]], align 86640; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i646641; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885766642; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr6643; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP6]], align 86644; CHECK-NEXT: [[TMP7:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> [[_MSLD]], <8 x i8> splat (i8 1))6645; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i8> [[TMP7]], zeroinitializer6646; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> [[TMP1]], <8 x i8> splat (i8 1))6647; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 86648; CHECK-NEXT: ret <8 x i8> [[TMP3]]6649;6650 %tmp1 = load <8 x i8>, ptr %A6651 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)6652 ret <8 x i8> %tmp36653}6654 6655define <8 x i8> @uqshli8b_1(ptr %A) nounwind sanitize_memory {6656; CHECK-LABEL: define <8 x i8> @uqshli8b_1(6657; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {6658; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86659; CHECK-NEXT: call void @llvm.donothing()6660; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06661; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]6662; CHECK: 2:6663; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6664; CHECK-NEXT: unreachable6665; CHECK: 3:6666; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[A]], align 86667; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i646668; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885766669; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr6670; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP6]], align 86671; CHECK-NEXT: [[TMP7:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> [[_MSLD]], <8 x i8> splat (i8 8))6672; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i8> [[TMP7]], zeroinitializer6673; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> [[TMP1]], <8 x i8> splat (i8 8))6674; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 86675; CHECK-NEXT: ret <8 x i8> [[TMP3]]6676;6677 %tmp1 = load <8 x i8>, ptr %A6678 %tmp3 = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>)6679 ret <8 x i8> %tmp36680}6681 6682define <4 x i16> @uqshli4h(ptr %A) nounwind sanitize_memory {6683; CHECK-LABEL: define <4 x i16> @uqshli4h(6684; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {6685; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86686; CHECK-NEXT: call void @llvm.donothing()6687; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06688; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]6689; CHECK: 2:6690; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6691; CHECK-NEXT: unreachable6692; CHECK: 3:6693; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 86694; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i646695; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885766696; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr6697; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP6]], align 86698; CHECK-NEXT: [[TMP7:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16> [[_MSLD]], <4 x i16> splat (i16 1))6699; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[TMP7]], zeroinitializer6700; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16> [[TMP1]], <4 x i16> splat (i16 1))6701; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 86702; CHECK-NEXT: ret <4 x i16> [[TMP3]]6703;6704 %tmp1 = load <4 x i16>, ptr %A6705 %tmp3 = call <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 1, i16 1, i16 1, i16 1>)6706 ret <4 x i16> %tmp36707}6708 6709define <2 x i32> @uqshli2s(ptr %A) nounwind sanitize_memory {6710; CHECK-LABEL: define <2 x i32> @uqshli2s(6711; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {6712; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86713; CHECK-NEXT: call void @llvm.donothing()6714; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06715; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]6716; CHECK: 2:6717; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6718; CHECK-NEXT: unreachable6719; CHECK: 3:6720; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 86721; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i646722; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885766723; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr6724; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP6]], align 86725; CHECK-NEXT: [[TMP7:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqshl.v2i32(<2 x i32> [[_MSLD]], <2 x i32> splat (i32 1))6726; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[TMP7]], zeroinitializer6727; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqshl.v2i32(<2 x i32> [[TMP1]], <2 x i32> splat (i32 1))6728; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 86729; CHECK-NEXT: ret <2 x i32> [[TMP3]]6730;6731 %tmp1 = load <2 x i32>, ptr %A6732 %tmp3 = call <2 x i32> @llvm.aarch64.neon.uqshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 1, i32 1>)6733 ret <2 x i32> %tmp36734}6735 6736define <16 x i8> @uqshli16b(ptr %A) nounwind sanitize_memory {6737; CHECK-LABEL: define <16 x i8> @uqshli16b(6738; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {6739; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86740; CHECK-NEXT: call void @llvm.donothing()6741; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06742; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]6743; CHECK: 2:6744; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6745; CHECK-NEXT: unreachable6746; CHECK: 3:6747; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[A]], align 166748; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i646749; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885766750; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr6751; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP6]], align 166752; CHECK-NEXT: [[TMP7:%.*]] = call <16 x i8> @llvm.aarch64.neon.uqshl.v16i8(<16 x i8> [[_MSLD]], <16 x i8> splat (i8 1))6753; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP7]], zeroinitializer6754; CHECK-NEXT: [[TMP3:%.*]] = call <16 x i8> @llvm.aarch64.neon.uqshl.v16i8(<16 x i8> [[TMP1]], <16 x i8> splat (i8 1))6755; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 86756; CHECK-NEXT: ret <16 x i8> [[TMP3]]6757;6758 %tmp1 = load <16 x i8>, ptr %A6759 %tmp3 = call <16 x i8> @llvm.aarch64.neon.uqshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>)6760 ret <16 x i8> %tmp36761}6762 6763define <8 x i16> @uqshli8h(ptr %A) nounwind sanitize_memory {6764; CHECK-LABEL: define <8 x i16> @uqshli8h(6765; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {6766; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86767; CHECK-NEXT: call void @llvm.donothing()6768; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06769; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]6770; CHECK: 2:6771; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6772; CHECK-NEXT: unreachable6773; CHECK: 3:6774; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 166775; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i646776; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885766777; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr6778; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP6]], align 166779; CHECK-NEXT: [[TMP7:%.*]] = call <8 x i16> @llvm.aarch64.neon.uqshl.v8i16(<8 x i16> [[_MSLD]], <8 x i16> splat (i16 1))6780; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP7]], zeroinitializer6781; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i16> @llvm.aarch64.neon.uqshl.v8i16(<8 x i16> [[TMP1]], <8 x i16> splat (i16 1))6782; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 86783; CHECK-NEXT: ret <8 x i16> [[TMP3]]6784;6785 %tmp1 = load <8 x i16>, ptr %A6786 %tmp3 = call <8 x i16> @llvm.aarch64.neon.uqshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)6787 ret <8 x i16> %tmp36788}6789 6790define <4 x i32> @uqshli4s(ptr %A) nounwind sanitize_memory {6791; CHECK-LABEL: define <4 x i32> @uqshli4s(6792; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {6793; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86794; CHECK-NEXT: call void @llvm.donothing()6795; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06796; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]6797; CHECK: 2:6798; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6799; CHECK-NEXT: unreachable6800; CHECK: 3:6801; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 166802; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i646803; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885766804; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr6805; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP6]], align 166806; CHECK-NEXT: [[TMP7:%.*]] = call <4 x i32> @llvm.aarch64.neon.uqshl.v4i32(<4 x i32> [[_MSLD]], <4 x i32> splat (i32 1))6807; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP7]], zeroinitializer6808; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.uqshl.v4i32(<4 x i32> [[TMP1]], <4 x i32> splat (i32 1))6809; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 86810; CHECK-NEXT: ret <4 x i32> [[TMP3]]6811;6812 %tmp1 = load <4 x i32>, ptr %A6813 %tmp3 = call <4 x i32> @llvm.aarch64.neon.uqshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 1, i32 1, i32 1, i32 1>)6814 ret <4 x i32> %tmp36815}6816 6817define <2 x i64> @uqshli2d(ptr %A) nounwind sanitize_memory {6818; CHECK-LABEL: define <2 x i64> @uqshli2d(6819; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] {6820; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86821; CHECK-NEXT: call void @llvm.donothing()6822; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06823; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP2:%.*]], label [[TMP3:%.*]], !prof [[PROF1]]6824; CHECK: 2:6825; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6826; CHECK-NEXT: unreachable6827; CHECK: 3:6828; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 166829; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[A]] to i646830; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 1935140464885766831; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr6832; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP6]], align 166833; CHECK-NEXT: [[TMP7:%.*]] = call <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64> [[_MSLD]], <2 x i64> splat (i64 1))6834; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP7]], zeroinitializer6835; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64> [[TMP1]], <2 x i64> splat (i64 1))6836; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 86837; CHECK-NEXT: ret <2 x i64> [[TMP3]]6838;6839 %tmp1 = load <2 x i64>, ptr %A6840 %tmp3 = call <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 1, i64 1>)6841 ret <2 x i64> %tmp36842}6843 6844define <8 x i8> @ursra8b(ptr %A, ptr %B) nounwind sanitize_memory {6845; CHECK-LABEL: define <8 x i8> @ursra8b(6846; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {6847; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86848; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 86849; CHECK-NEXT: call void @llvm.donothing()6850; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06851; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]6852; CHECK: 3:6853; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6854; CHECK-NEXT: unreachable6855; CHECK: 4:6856; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[A]], align 86857; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i646858; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885766859; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr6860; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 86861; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i8> @llvm.aarch64.neon.urshl.v8i8(<8 x i8> [[_MSLD]], <8 x i8> splat (i8 -1))6862; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i8> [[TMP8]], zeroinitializer6863; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.urshl.v8i8(<8 x i8> [[TMP1]], <8 x i8> splat (i8 -1))6864; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 06865; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP13:%.*]], label [[TMP14:%.*]], !prof [[PROF1]]6866; CHECK: 10:6867; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6868; CHECK-NEXT: unreachable6869; CHECK: 11:6870; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i8>, ptr [[B]], align 86871; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i646872; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885766873; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr6874; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP12]], align 86875; CHECK-NEXT: [[_MSPROP2:%.*]] = or <8 x i8> [[_MSPROP]], [[_MSLD1]]6876; CHECK-NEXT: [[TMP5:%.*]] = add <8 x i8> [[TMP3]], [[TMP4]]6877; CHECK-NEXT: store <8 x i8> [[_MSPROP2]], ptr @__msan_retval_tls, align 86878; CHECK-NEXT: ret <8 x i8> [[TMP5]]6879;6880 %tmp1 = load <8 x i8>, ptr %A6881 %tmp3 = call <8 x i8> @llvm.aarch64.neon.urshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)6882 %tmp4 = load <8 x i8>, ptr %B6883 %tmp5 = add <8 x i8> %tmp3, %tmp46884 ret <8 x i8> %tmp56885}6886 6887define <4 x i16> @ursra4h(ptr %A, ptr %B) nounwind sanitize_memory {6888; CHECK-LABEL: define <4 x i16> @ursra4h(6889; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {6890; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86891; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 86892; CHECK-NEXT: call void @llvm.donothing()6893; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06894; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]6895; CHECK: 3:6896; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6897; CHECK-NEXT: unreachable6898; CHECK: 4:6899; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 86900; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i646901; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885766902; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr6903; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 86904; CHECK-NEXT: [[TMP8:%.*]] = call <4 x i16> @llvm.aarch64.neon.urshl.v4i16(<4 x i16> [[_MSLD]], <4 x i16> splat (i16 -1))6905; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[TMP8]], zeroinitializer6906; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.urshl.v4i16(<4 x i16> [[TMP1]], <4 x i16> splat (i16 -1))6907; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 06908; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP13:%.*]], label [[TMP14:%.*]], !prof [[PROF1]]6909; CHECK: 10:6910; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6911; CHECK-NEXT: unreachable6912; CHECK: 11:6913; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i16>, ptr [[B]], align 86914; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i646915; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885766916; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr6917; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 86918; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i16> [[_MSPROP]], [[_MSLD1]]6919; CHECK-NEXT: [[TMP5:%.*]] = add <4 x i16> [[TMP3]], [[TMP4]]6920; CHECK-NEXT: store <4 x i16> [[_MSPROP2]], ptr @__msan_retval_tls, align 86921; CHECK-NEXT: ret <4 x i16> [[TMP5]]6922;6923 %tmp1 = load <4 x i16>, ptr %A6924 %tmp3 = call <4 x i16> @llvm.aarch64.neon.urshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>)6925 %tmp4 = load <4 x i16>, ptr %B6926 %tmp5 = add <4 x i16> %tmp3, %tmp46927 ret <4 x i16> %tmp56928}6929 6930define <2 x i32> @ursra2s(ptr %A, ptr %B) nounwind sanitize_memory {6931; CHECK-LABEL: define <2 x i32> @ursra2s(6932; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {6933; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86934; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 86935; CHECK-NEXT: call void @llvm.donothing()6936; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06937; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]6938; CHECK: 3:6939; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6940; CHECK-NEXT: unreachable6941; CHECK: 4:6942; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 86943; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i646944; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885766945; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr6946; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 86947; CHECK-NEXT: [[TMP8:%.*]] = call <2 x i32> @llvm.aarch64.neon.urshl.v2i32(<2 x i32> [[_MSLD]], <2 x i32> splat (i32 -1))6948; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[TMP8]], zeroinitializer6949; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.urshl.v2i32(<2 x i32> [[TMP1]], <2 x i32> splat (i32 -1))6950; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 06951; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP13:%.*]], label [[TMP14:%.*]], !prof [[PROF1]]6952; CHECK: 10:6953; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6954; CHECK-NEXT: unreachable6955; CHECK: 11:6956; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i32>, ptr [[B]], align 86957; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i646958; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885766959; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr6960; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 86961; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i32> [[_MSPROP]], [[_MSLD1]]6962; CHECK-NEXT: [[TMP5:%.*]] = add <2 x i32> [[TMP3]], [[TMP4]]6963; CHECK-NEXT: store <2 x i32> [[_MSPROP2]], ptr @__msan_retval_tls, align 86964; CHECK-NEXT: ret <2 x i32> [[TMP5]]6965;6966 %tmp1 = load <2 x i32>, ptr %A6967 %tmp3 = call <2 x i32> @llvm.aarch64.neon.urshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 -1, i32 -1>)6968 %tmp4 = load <2 x i32>, ptr %B6969 %tmp5 = add <2 x i32> %tmp3, %tmp46970 ret <2 x i32> %tmp56971}6972 6973define <16 x i8> @ursra16b(ptr %A, ptr %B) nounwind sanitize_memory {6974; CHECK-LABEL: define <16 x i8> @ursra16b(6975; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {6976; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 86977; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 86978; CHECK-NEXT: call void @llvm.donothing()6979; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 06980; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]6981; CHECK: 3:6982; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6983; CHECK-NEXT: unreachable6984; CHECK: 4:6985; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[A]], align 166986; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i646987; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885766988; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr6989; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP7]], align 166990; CHECK-NEXT: [[TMP8:%.*]] = call <16 x i8> @llvm.aarch64.neon.urshl.v16i8(<16 x i8> [[_MSLD]], <16 x i8> splat (i8 -1))6991; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP8]], zeroinitializer6992; CHECK-NEXT: [[TMP3:%.*]] = call <16 x i8> @llvm.aarch64.neon.urshl.v16i8(<16 x i8> [[TMP1]], <16 x i8> splat (i8 -1))6993; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 06994; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP13:%.*]], label [[TMP14:%.*]], !prof [[PROF1]]6995; CHECK: 10:6996; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]6997; CHECK-NEXT: unreachable6998; CHECK: 11:6999; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i8>, ptr [[B]], align 167000; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i647001; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885767002; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr7003; CHECK-NEXT: [[_MSLD1:%.*]] = load <16 x i8>, ptr [[TMP12]], align 167004; CHECK-NEXT: [[_MSPROP2:%.*]] = or <16 x i8> [[_MSPROP]], [[_MSLD1]]7005; CHECK-NEXT: [[TMP5:%.*]] = add <16 x i8> [[TMP3]], [[TMP4]]7006; CHECK-NEXT: store <16 x i8> [[_MSPROP2]], ptr @__msan_retval_tls, align 87007; CHECK-NEXT: ret <16 x i8> [[TMP5]]7008;7009 %tmp1 = load <16 x i8>, ptr %A7010 %tmp3 = call <16 x i8> @llvm.aarch64.neon.urshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)7011 %tmp4 = load <16 x i8>, ptr %B7012 %tmp5 = add <16 x i8> %tmp3, %tmp47013 ret <16 x i8> %tmp57014}7015 7016define <8 x i16> @ursra8h(ptr %A, ptr %B) nounwind sanitize_memory {7017; CHECK-LABEL: define <8 x i16> @ursra8h(7018; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {7019; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 87020; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 87021; CHECK-NEXT: call void @llvm.donothing()7022; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 07023; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]7024; CHECK: 3:7025; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7026; CHECK-NEXT: unreachable7027; CHECK: 4:7028; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 167029; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i647030; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885767031; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr7032; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 167033; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16> [[_MSLD]], <8 x i16> splat (i16 -1))7034; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP8]], zeroinitializer7035; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16> [[TMP1]], <8 x i16> splat (i16 -1))7036; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 07037; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP13:%.*]], label [[TMP14:%.*]], !prof [[PROF1]]7038; CHECK: 10:7039; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7040; CHECK-NEXT: unreachable7041; CHECK: 11:7042; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i16>, ptr [[B]], align 167043; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i647044; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885767045; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr7046; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 167047; CHECK-NEXT: [[_MSPROP2:%.*]] = or <8 x i16> [[_MSPROP]], [[_MSLD1]]7048; CHECK-NEXT: [[TMP5:%.*]] = add <8 x i16> [[TMP3]], [[TMP4]]7049; CHECK-NEXT: store <8 x i16> [[_MSPROP2]], ptr @__msan_retval_tls, align 87050; CHECK-NEXT: ret <8 x i16> [[TMP5]]7051;7052 %tmp1 = load <8 x i16>, ptr %A7053 %tmp3 = call <8 x i16> @llvm.aarch64.neon.urshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>)7054 %tmp4 = load <8 x i16>, ptr %B7055 %tmp5 = add <8 x i16> %tmp3, %tmp47056 ret <8 x i16> %tmp57057}7058 7059define <4 x i32> @ursra4s(ptr %A, ptr %B) nounwind sanitize_memory {7060; CHECK-LABEL: define <4 x i32> @ursra4s(7061; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {7062; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 87063; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 87064; CHECK-NEXT: call void @llvm.donothing()7065; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 07066; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]7067; CHECK: 3:7068; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7069; CHECK-NEXT: unreachable7070; CHECK: 4:7071; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 167072; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i647073; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885767074; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr7075; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 167076; CHECK-NEXT: [[TMP8:%.*]] = call <4 x i32> @llvm.aarch64.neon.urshl.v4i32(<4 x i32> [[_MSLD]], <4 x i32> splat (i32 -1))7077; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP8]], zeroinitializer7078; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.urshl.v4i32(<4 x i32> [[TMP1]], <4 x i32> splat (i32 -1))7079; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 07080; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP13:%.*]], label [[TMP14:%.*]], !prof [[PROF1]]7081; CHECK: 10:7082; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7083; CHECK-NEXT: unreachable7084; CHECK: 11:7085; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr [[B]], align 167086; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i647087; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885767088; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr7089; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 167090; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i32> [[_MSPROP]], [[_MSLD1]]7091; CHECK-NEXT: [[TMP5:%.*]] = add <4 x i32> [[TMP3]], [[TMP4]]7092; CHECK-NEXT: store <4 x i32> [[_MSPROP2]], ptr @__msan_retval_tls, align 87093; CHECK-NEXT: ret <4 x i32> [[TMP5]]7094;7095 %tmp1 = load <4 x i32>, ptr %A7096 %tmp3 = call <4 x i32> @llvm.aarch64.neon.urshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)7097 %tmp4 = load <4 x i32>, ptr %B7098 %tmp5 = add <4 x i32> %tmp3, %tmp47099 ret <4 x i32> %tmp57100}7101 7102define <2 x i64> @ursra2d(ptr %A, ptr %B) nounwind sanitize_memory {7103; CHECK-LABEL: define <2 x i64> @ursra2d(7104; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {7105; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 87106; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 87107; CHECK-NEXT: call void @llvm.donothing()7108; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 07109; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]7110; CHECK: 3:7111; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7112; CHECK-NEXT: unreachable7113; CHECK: 4:7114; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 167115; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i647116; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885767117; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr7118; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 167119; CHECK-NEXT: [[TMP8:%.*]] = call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> [[_MSLD]], <2 x i64> splat (i64 -1))7120; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP8]], zeroinitializer7121; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> [[TMP1]], <2 x i64> splat (i64 -1))7122; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 07123; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP13:%.*]], label [[TMP14:%.*]], !prof [[PROF1]]7124; CHECK: 10:7125; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7126; CHECK-NEXT: unreachable7127; CHECK: 11:7128; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr [[B]], align 167129; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i647130; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885767131; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr7132; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 167133; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i64> [[_MSPROP]], [[_MSLD1]]7134; CHECK-NEXT: [[TMP5:%.*]] = add <2 x i64> [[TMP3]], [[TMP4]]7135; CHECK-NEXT: store <2 x i64> [[_MSPROP2]], ptr @__msan_retval_tls, align 87136; CHECK-NEXT: ret <2 x i64> [[TMP5]]7137;7138 %tmp1 = load <2 x i64>, ptr %A7139 %tmp3 = call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 -1, i64 -1>)7140 %tmp4 = load <2 x i64>, ptr %B7141 %tmp5 = add <2 x i64> %tmp3, %tmp47142 ret <2 x i64> %tmp57143}7144 7145define <1 x i64> @ursra1d(ptr %A, ptr %B) nounwind sanitize_memory {7146; CHECK-LABEL: define <1 x i64> @ursra1d(7147; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {7148; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 87149; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 87150; CHECK-NEXT: call void @llvm.donothing()7151; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 07152; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]7153; CHECK: 3:7154; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7155; CHECK-NEXT: unreachable7156; CHECK: 4:7157; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr [[A]], align 87158; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i647159; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885767160; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr7161; CHECK-NEXT: [[_MSLD:%.*]] = load <1 x i64>, ptr [[TMP7]], align 87162; CHECK-NEXT: [[TMP8:%.*]] = call <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64> [[_MSLD]], <1 x i64> splat (i64 -1))7163; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP8]], zeroinitializer7164; CHECK-NEXT: [[TMP3:%.*]] = call <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64> [[TMP1]], <1 x i64> splat (i64 -1))7165; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 07166; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP13:%.*]], label [[TMP14:%.*]], !prof [[PROF1]]7167; CHECK: 10:7168; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7169; CHECK-NEXT: unreachable7170; CHECK: 11:7171; CHECK-NEXT: [[TMP4:%.*]] = load <1 x i64>, ptr [[B]], align 87172; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i647173; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885767174; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr7175; CHECK-NEXT: [[_MSLD1:%.*]] = load <1 x i64>, ptr [[TMP12]], align 87176; CHECK-NEXT: [[_MSPROP2:%.*]] = or <1 x i64> [[_MSPROP]], [[_MSLD1]]7177; CHECK-NEXT: [[TMP5:%.*]] = add <1 x i64> [[TMP3]], [[TMP4]]7178; CHECK-NEXT: store <1 x i64> [[_MSPROP2]], ptr @__msan_retval_tls, align 87179; CHECK-NEXT: ret <1 x i64> [[TMP5]]7180;7181 %tmp1 = load <1 x i64>, ptr %A7182 %tmp3 = call <1 x i64> @llvm.aarch64.neon.urshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 -1>)7183 %tmp4 = load <1 x i64>, ptr %B7184 %tmp5 = add <1 x i64> %tmp3, %tmp47185 ret <1 x i64> %tmp57186}7187 7188define i64 @ursra_scalar(ptr %A, ptr %B) nounwind sanitize_memory {7189; CHECK-LABEL: define i64 @ursra_scalar(7190; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {7191; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 87192; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 87193; CHECK-NEXT: call void @llvm.donothing()7194; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 07195; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]7196; CHECK: 3:7197; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7198; CHECK-NEXT: unreachable7199; CHECK: 4:7200; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[A]], align 87201; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i647202; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885767203; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr7204; CHECK-NEXT: [[_MSLD:%.*]] = load i64, ptr [[TMP7]], align 87205; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.aarch64.neon.urshl.i64(i64 [[_MSLD]], i64 -1)7206; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP8]], 07207; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.urshl.i64(i64 [[TMP1]], i64 -1)7208; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 07209; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP13:%.*]], label [[TMP14:%.*]], !prof [[PROF1]]7210; CHECK: 10:7211; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7212; CHECK-NEXT: unreachable7213; CHECK: 11:7214; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr [[B]], align 87215; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i647216; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885767217; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr7218; CHECK-NEXT: [[_MSLD1:%.*]] = load i64, ptr [[TMP12]], align 87219; CHECK-NEXT: [[_MSPROP2:%.*]] = or i64 [[_MSPROP]], [[_MSLD1]]7220; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[TMP3]], [[TMP4]]7221; CHECK-NEXT: store i64 [[_MSPROP2]], ptr @__msan_retval_tls, align 87222; CHECK-NEXT: ret i64 [[TMP5]]7223;7224 %tmp1 = load i64, ptr %A7225 %tmp3 = call i64 @llvm.aarch64.neon.urshl.i64(i64 %tmp1, i64 -1)7226 %tmp4 = load i64, ptr %B7227 %tmp5 = add i64 %tmp3, %tmp47228 ret i64 %tmp57229}7230 7231define <8 x i8> @srsra8b(ptr %A, ptr %B) nounwind sanitize_memory {7232; CHECK-LABEL: define <8 x i8> @srsra8b(7233; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {7234; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 87235; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 87236; CHECK-NEXT: call void @llvm.donothing()7237; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 07238; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]7239; CHECK: 3:7240; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7241; CHECK-NEXT: unreachable7242; CHECK: 4:7243; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[A]], align 87244; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i647245; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885767246; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr7247; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 87248; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i8> @llvm.aarch64.neon.srshl.v8i8(<8 x i8> [[_MSLD]], <8 x i8> splat (i8 -1))7249; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i8> [[TMP8]], zeroinitializer7250; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.srshl.v8i8(<8 x i8> [[TMP1]], <8 x i8> splat (i8 -1))7251; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 07252; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP13:%.*]], label [[TMP14:%.*]], !prof [[PROF1]]7253; CHECK: 10:7254; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7255; CHECK-NEXT: unreachable7256; CHECK: 11:7257; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i8>, ptr [[B]], align 87258; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i647259; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885767260; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr7261; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP12]], align 87262; CHECK-NEXT: [[_MSPROP2:%.*]] = or <8 x i8> [[_MSPROP]], [[_MSLD1]]7263; CHECK-NEXT: [[TMP5:%.*]] = add <8 x i8> [[TMP3]], [[TMP4]]7264; CHECK-NEXT: store <8 x i8> [[_MSPROP2]], ptr @__msan_retval_tls, align 87265; CHECK-NEXT: ret <8 x i8> [[TMP5]]7266;7267 %tmp1 = load <8 x i8>, ptr %A7268 %tmp3 = call <8 x i8> @llvm.aarch64.neon.srshl.v8i8(<8 x i8> %tmp1, <8 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)7269 %tmp4 = load <8 x i8>, ptr %B7270 %tmp5 = add <8 x i8> %tmp3, %tmp47271 ret <8 x i8> %tmp57272}7273 7274define <4 x i16> @srsra4h(ptr %A, ptr %B) nounwind sanitize_memory {7275; CHECK-LABEL: define <4 x i16> @srsra4h(7276; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {7277; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 87278; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 87279; CHECK-NEXT: call void @llvm.donothing()7280; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 07281; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]7282; CHECK: 3:7283; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7284; CHECK-NEXT: unreachable7285; CHECK: 4:7286; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 87287; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i647288; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885767289; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr7290; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 87291; CHECK-NEXT: [[TMP8:%.*]] = call <4 x i16> @llvm.aarch64.neon.srshl.v4i16(<4 x i16> [[_MSLD]], <4 x i16> splat (i16 -1))7292; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[TMP8]], zeroinitializer7293; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.srshl.v4i16(<4 x i16> [[TMP1]], <4 x i16> splat (i16 -1))7294; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 07295; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP13:%.*]], label [[TMP14:%.*]], !prof [[PROF1]]7296; CHECK: 10:7297; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7298; CHECK-NEXT: unreachable7299; CHECK: 11:7300; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i16>, ptr [[B]], align 87301; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i647302; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885767303; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr7304; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 87305; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i16> [[_MSPROP]], [[_MSLD1]]7306; CHECK-NEXT: [[TMP5:%.*]] = add <4 x i16> [[TMP3]], [[TMP4]]7307; CHECK-NEXT: store <4 x i16> [[_MSPROP2]], ptr @__msan_retval_tls, align 87308; CHECK-NEXT: ret <4 x i16> [[TMP5]]7309;7310 %tmp1 = load <4 x i16>, ptr %A7311 %tmp3 = call <4 x i16> @llvm.aarch64.neon.srshl.v4i16(<4 x i16> %tmp1, <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>)7312 %tmp4 = load <4 x i16>, ptr %B7313 %tmp5 = add <4 x i16> %tmp3, %tmp47314 ret <4 x i16> %tmp57315}7316 7317define <2 x i32> @srsra2s(ptr %A, ptr %B) nounwind sanitize_memory {7318; CHECK-LABEL: define <2 x i32> @srsra2s(7319; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {7320; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 87321; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 87322; CHECK-NEXT: call void @llvm.donothing()7323; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 07324; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]7325; CHECK: 3:7326; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7327; CHECK-NEXT: unreachable7328; CHECK: 4:7329; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 87330; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i647331; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885767332; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr7333; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 87334; CHECK-NEXT: [[TMP8:%.*]] = call <2 x i32> @llvm.aarch64.neon.srshl.v2i32(<2 x i32> [[_MSLD]], <2 x i32> splat (i32 -1))7335; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[TMP8]], zeroinitializer7336; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.srshl.v2i32(<2 x i32> [[TMP1]], <2 x i32> splat (i32 -1))7337; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 07338; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP13:%.*]], label [[TMP14:%.*]], !prof [[PROF1]]7339; CHECK: 10:7340; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7341; CHECK-NEXT: unreachable7342; CHECK: 11:7343; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i32>, ptr [[B]], align 87344; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i647345; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885767346; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr7347; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 87348; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i32> [[_MSPROP]], [[_MSLD1]]7349; CHECK-NEXT: [[TMP5:%.*]] = add <2 x i32> [[TMP3]], [[TMP4]]7350; CHECK-NEXT: store <2 x i32> [[_MSPROP2]], ptr @__msan_retval_tls, align 87351; CHECK-NEXT: ret <2 x i32> [[TMP5]]7352;7353 %tmp1 = load <2 x i32>, ptr %A7354 %tmp3 = call <2 x i32> @llvm.aarch64.neon.srshl.v2i32(<2 x i32> %tmp1, <2 x i32> <i32 -1, i32 -1>)7355 %tmp4 = load <2 x i32>, ptr %B7356 %tmp5 = add <2 x i32> %tmp3, %tmp47357 ret <2 x i32> %tmp57358}7359 7360define <16 x i8> @srsra16b(ptr %A, ptr %B) nounwind sanitize_memory {7361; CHECK-LABEL: define <16 x i8> @srsra16b(7362; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {7363; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 87364; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 87365; CHECK-NEXT: call void @llvm.donothing()7366; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 07367; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]7368; CHECK: 3:7369; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7370; CHECK-NEXT: unreachable7371; CHECK: 4:7372; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[A]], align 167373; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i647374; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885767375; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr7376; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP7]], align 167377; CHECK-NEXT: [[TMP8:%.*]] = call <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8> [[_MSLD]], <16 x i8> splat (i8 -1))7378; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP8]], zeroinitializer7379; CHECK-NEXT: [[TMP3:%.*]] = call <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8> [[TMP1]], <16 x i8> splat (i8 -1))7380; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 07381; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP13:%.*]], label [[TMP14:%.*]], !prof [[PROF1]]7382; CHECK: 10:7383; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7384; CHECK-NEXT: unreachable7385; CHECK: 11:7386; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i8>, ptr [[B]], align 167387; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i647388; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885767389; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr7390; CHECK-NEXT: [[_MSLD1:%.*]] = load <16 x i8>, ptr [[TMP12]], align 167391; CHECK-NEXT: [[_MSPROP2:%.*]] = or <16 x i8> [[_MSPROP]], [[_MSLD1]]7392; CHECK-NEXT: [[TMP5:%.*]] = add <16 x i8> [[TMP3]], [[TMP4]]7393; CHECK-NEXT: store <16 x i8> [[_MSPROP2]], ptr @__msan_retval_tls, align 87394; CHECK-NEXT: ret <16 x i8> [[TMP5]]7395;7396 %tmp1 = load <16 x i8>, ptr %A7397 %tmp3 = call <16 x i8> @llvm.aarch64.neon.srshl.v16i8(<16 x i8> %tmp1, <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>)7398 %tmp4 = load <16 x i8>, ptr %B7399 %tmp5 = add <16 x i8> %tmp3, %tmp47400 ret <16 x i8> %tmp57401}7402 7403define <8 x i16> @srsra8h(ptr %A, ptr %B) nounwind sanitize_memory {7404; CHECK-LABEL: define <8 x i16> @srsra8h(7405; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {7406; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 87407; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 87408; CHECK-NEXT: call void @llvm.donothing()7409; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 07410; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]7411; CHECK: 3:7412; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7413; CHECK-NEXT: unreachable7414; CHECK: 4:7415; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 167416; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i647417; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885767418; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr7419; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 167420; CHECK-NEXT: [[TMP8:%.*]] = call <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16> [[_MSLD]], <8 x i16> splat (i16 -1))7421; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP8]], zeroinitializer7422; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16> [[TMP1]], <8 x i16> splat (i16 -1))7423; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 07424; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP13:%.*]], label [[TMP14:%.*]], !prof [[PROF1]]7425; CHECK: 10:7426; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7427; CHECK-NEXT: unreachable7428; CHECK: 11:7429; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i16>, ptr [[B]], align 167430; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i647431; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885767432; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr7433; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 167434; CHECK-NEXT: [[_MSPROP2:%.*]] = or <8 x i16> [[_MSPROP]], [[_MSLD1]]7435; CHECK-NEXT: [[TMP5:%.*]] = add <8 x i16> [[TMP3]], [[TMP4]]7436; CHECK-NEXT: store <8 x i16> [[_MSPROP2]], ptr @__msan_retval_tls, align 87437; CHECK-NEXT: ret <8 x i16> [[TMP5]]7438;7439 %tmp1 = load <8 x i16>, ptr %A7440 %tmp3 = call <8 x i16> @llvm.aarch64.neon.srshl.v8i16(<8 x i16> %tmp1, <8 x i16> <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>)7441 %tmp4 = load <8 x i16>, ptr %B7442 %tmp5 = add <8 x i16> %tmp3, %tmp47443 ret <8 x i16> %tmp57444}7445 7446define <4 x i32> @srsra4s(ptr %A, ptr %B) nounwind sanitize_memory {7447; CHECK-LABEL: define <4 x i32> @srsra4s(7448; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {7449; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 87450; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 87451; CHECK-NEXT: call void @llvm.donothing()7452; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 07453; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]7454; CHECK: 3:7455; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7456; CHECK-NEXT: unreachable7457; CHECK: 4:7458; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 167459; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i647460; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885767461; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr7462; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 167463; CHECK-NEXT: [[TMP8:%.*]] = call <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32> [[_MSLD]], <4 x i32> splat (i32 -1))7464; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP8]], zeroinitializer7465; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32> [[TMP1]], <4 x i32> splat (i32 -1))7466; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 07467; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP13:%.*]], label [[TMP14:%.*]], !prof [[PROF1]]7468; CHECK: 10:7469; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7470; CHECK-NEXT: unreachable7471; CHECK: 11:7472; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr [[B]], align 167473; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i647474; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885767475; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr7476; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 167477; CHECK-NEXT: [[_MSPROP2:%.*]] = or <4 x i32> [[_MSPROP]], [[_MSLD1]]7478; CHECK-NEXT: [[TMP5:%.*]] = add <4 x i32> [[TMP3]], [[TMP4]]7479; CHECK-NEXT: store <4 x i32> [[_MSPROP2]], ptr @__msan_retval_tls, align 87480; CHECK-NEXT: ret <4 x i32> [[TMP5]]7481;7482 %tmp1 = load <4 x i32>, ptr %A7483 %tmp3 = call <4 x i32> @llvm.aarch64.neon.srshl.v4i32(<4 x i32> %tmp1, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>)7484 %tmp4 = load <4 x i32>, ptr %B7485 %tmp5 = add <4 x i32> %tmp3, %tmp47486 ret <4 x i32> %tmp57487}7488 7489define <2 x i64> @srsra2d(ptr %A, ptr %B) nounwind sanitize_memory {7490; CHECK-LABEL: define <2 x i64> @srsra2d(7491; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {7492; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 87493; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 87494; CHECK-NEXT: call void @llvm.donothing()7495; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 07496; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]7497; CHECK: 3:7498; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7499; CHECK-NEXT: unreachable7500; CHECK: 4:7501; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 167502; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i647503; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885767504; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr7505; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 167506; CHECK-NEXT: [[TMP8:%.*]] = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> [[_MSLD]], <2 x i64> splat (i64 -1))7507; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP8]], zeroinitializer7508; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> [[TMP1]], <2 x i64> splat (i64 -1))7509; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 07510; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP13:%.*]], label [[TMP14:%.*]], !prof [[PROF1]]7511; CHECK: 10:7512; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7513; CHECK-NEXT: unreachable7514; CHECK: 11:7515; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr [[B]], align 167516; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i647517; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885767518; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr7519; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 167520; CHECK-NEXT: [[_MSPROP2:%.*]] = or <2 x i64> [[_MSPROP]], [[_MSLD1]]7521; CHECK-NEXT: [[TMP5:%.*]] = add <2 x i64> [[TMP3]], [[TMP4]]7522; CHECK-NEXT: store <2 x i64> [[_MSPROP2]], ptr @__msan_retval_tls, align 87523; CHECK-NEXT: ret <2 x i64> [[TMP5]]7524;7525 %tmp1 = load <2 x i64>, ptr %A7526 %tmp3 = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> %tmp1, <2 x i64> <i64 -1, i64 -1>)7527 %tmp4 = load <2 x i64>, ptr %B7528 %tmp5 = add <2 x i64> %tmp3, %tmp47529 ret <2 x i64> %tmp57530}7531 7532define <1 x i64> @srsra1d(ptr %A, ptr %B) nounwind sanitize_memory {7533; CHECK-LABEL: define <1 x i64> @srsra1d(7534; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {7535; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 87536; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 87537; CHECK-NEXT: call void @llvm.donothing()7538; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 07539; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]7540; CHECK: 3:7541; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7542; CHECK-NEXT: unreachable7543; CHECK: 4:7544; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr [[A]], align 87545; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i647546; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885767547; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr7548; CHECK-NEXT: [[_MSLD:%.*]] = load <1 x i64>, ptr [[TMP7]], align 87549; CHECK-NEXT: [[TMP8:%.*]] = call <1 x i64> @llvm.aarch64.neon.srshl.v1i64(<1 x i64> [[_MSLD]], <1 x i64> splat (i64 -1))7550; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP8]], zeroinitializer7551; CHECK-NEXT: [[TMP3:%.*]] = call <1 x i64> @llvm.aarch64.neon.srshl.v1i64(<1 x i64> [[TMP1]], <1 x i64> splat (i64 -1))7552; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 07553; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP13:%.*]], label [[TMP14:%.*]], !prof [[PROF1]]7554; CHECK: 10:7555; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7556; CHECK-NEXT: unreachable7557; CHECK: 11:7558; CHECK-NEXT: [[TMP4:%.*]] = load <1 x i64>, ptr [[B]], align 87559; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i647560; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885767561; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr7562; CHECK-NEXT: [[_MSLD1:%.*]] = load <1 x i64>, ptr [[TMP12]], align 87563; CHECK-NEXT: [[_MSPROP2:%.*]] = or <1 x i64> [[_MSPROP]], [[_MSLD1]]7564; CHECK-NEXT: [[TMP5:%.*]] = add <1 x i64> [[TMP3]], [[TMP4]]7565; CHECK-NEXT: store <1 x i64> [[_MSPROP2]], ptr @__msan_retval_tls, align 87566; CHECK-NEXT: ret <1 x i64> [[TMP5]]7567;7568 %tmp1 = load <1 x i64>, ptr %A7569 %tmp3 = call <1 x i64> @llvm.aarch64.neon.srshl.v1i64(<1 x i64> %tmp1, <1 x i64> <i64 -1>)7570 %tmp4 = load <1 x i64>, ptr %B7571 %tmp5 = add <1 x i64> %tmp3, %tmp47572 ret <1 x i64> %tmp57573}7574 7575define i64 @srsra_scalar(ptr %A, ptr %B) nounwind sanitize_memory {7576; CHECK-LABEL: define i64 @srsra_scalar(7577; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {7578; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 87579; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 87580; CHECK-NEXT: call void @llvm.donothing()7581; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 07582; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]7583; CHECK: 3:7584; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7585; CHECK-NEXT: unreachable7586; CHECK: 4:7587; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[A]], align 87588; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i647589; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885767590; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr7591; CHECK-NEXT: [[_MSLD:%.*]] = load i64, ptr [[TMP7]], align 87592; CHECK-NEXT: [[TMP8:%.*]] = call i64 @llvm.aarch64.neon.srshl.i64(i64 [[_MSLD]], i64 -1)7593; CHECK-NEXT: [[_MSPROP:%.*]] = or i64 [[TMP8]], 07594; CHECK-NEXT: [[TMP3:%.*]] = call i64 @llvm.aarch64.neon.srshl.i64(i64 [[TMP1]], i64 -1)7595; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP2]], 07596; CHECK-NEXT: br i1 [[_MSCMP3]], label [[TMP13:%.*]], label [[TMP14:%.*]], !prof [[PROF1]]7597; CHECK: 10:7598; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7599; CHECK-NEXT: unreachable7600; CHECK: 11:7601; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr [[B]], align 87602; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i647603; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885767604; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr7605; CHECK-NEXT: [[_MSLD1:%.*]] = load i64, ptr [[TMP12]], align 87606; CHECK-NEXT: [[_MSPROP2:%.*]] = or i64 [[_MSPROP]], [[_MSLD1]]7607; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[TMP3]], [[TMP4]]7608; CHECK-NEXT: store i64 [[_MSPROP2]], ptr @__msan_retval_tls, align 87609; CHECK-NEXT: ret i64 [[TMP5]]7610;7611 %tmp1 = load i64, ptr %A7612 %tmp3 = call i64 @llvm.aarch64.neon.srshl.i64(i64 %tmp1, i64 -1)7613 %tmp4 = load i64, ptr %B7614 %tmp5 = add i64 %tmp3, %tmp47615 ret i64 %tmp57616}7617 7618define <8 x i8> @usra8b(ptr %A, ptr %B) nounwind sanitize_memory {7619; CHECK-LABEL: define <8 x i8> @usra8b(7620; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {7621; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 87622; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 87623; CHECK-NEXT: call void @llvm.donothing()7624; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 07625; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]7626; CHECK: 3:7627; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7628; CHECK-NEXT: unreachable7629; CHECK: 4:7630; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[A]], align 87631; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i647632; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885767633; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr7634; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 87635; CHECK-NEXT: [[TMP8:%.*]] = lshr <8 x i8> [[_MSLD]], splat (i8 1)7636; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i8> [[TMP8]], zeroinitializer7637; CHECK-NEXT: [[TMP3:%.*]] = lshr <8 x i8> [[TMP1]], splat (i8 1)7638; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 07639; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]7640; CHECK: 10:7641; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7642; CHECK-NEXT: unreachable7643; CHECK: 11:7644; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i8>, ptr [[B]], align 87645; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[B]] to i647646; CHECK-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], 1935140464885767647; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr7648; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP14]], align 87649; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i8> [[TMP9]], [[_MSLD1]]7650; CHECK-NEXT: [[TMP5:%.*]] = add <8 x i8> [[TMP3]], [[TMP4]]7651; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 87652; CHECK-NEXT: ret <8 x i8> [[TMP5]]7653;7654 %tmp1 = load <8 x i8>, ptr %A7655 %tmp3 = lshr <8 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>7656 %tmp4 = load <8 x i8>, ptr %B7657 %tmp5 = add <8 x i8> %tmp3, %tmp47658 ret <8 x i8> %tmp57659}7660 7661define <4 x i16> @usra4h(ptr %A, ptr %B) nounwind sanitize_memory {7662; CHECK-LABEL: define <4 x i16> @usra4h(7663; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {7664; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 87665; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 87666; CHECK-NEXT: call void @llvm.donothing()7667; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 07668; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]7669; CHECK: 3:7670; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7671; CHECK-NEXT: unreachable7672; CHECK: 4:7673; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 87674; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i647675; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885767676; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr7677; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 87678; CHECK-NEXT: [[TMP8:%.*]] = lshr <4 x i16> [[_MSLD]], splat (i16 1)7679; CHECK-NEXT: [[TMP9:%.*]] = or <4 x i16> [[TMP8]], zeroinitializer7680; CHECK-NEXT: [[TMP3:%.*]] = lshr <4 x i16> [[TMP1]], splat (i16 1)7681; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 07682; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]7683; CHECK: 10:7684; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7685; CHECK-NEXT: unreachable7686; CHECK: 11:7687; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i16>, ptr [[B]], align 87688; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[B]] to i647689; CHECK-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], 1935140464885767690; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr7691; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP14]], align 87692; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[TMP9]], [[_MSLD1]]7693; CHECK-NEXT: [[TMP5:%.*]] = add <4 x i16> [[TMP3]], [[TMP4]]7694; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 87695; CHECK-NEXT: ret <4 x i16> [[TMP5]]7696;7697 %tmp1 = load <4 x i16>, ptr %A7698 %tmp3 = lshr <4 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1>7699 %tmp4 = load <4 x i16>, ptr %B7700 %tmp5 = add <4 x i16> %tmp3, %tmp47701 ret <4 x i16> %tmp57702}7703 7704define <2 x i32> @usra2s(ptr %A, ptr %B) nounwind sanitize_memory {7705; CHECK-LABEL: define <2 x i32> @usra2s(7706; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {7707; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 87708; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 87709; CHECK-NEXT: call void @llvm.donothing()7710; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 07711; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]7712; CHECK: 3:7713; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7714; CHECK-NEXT: unreachable7715; CHECK: 4:7716; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 87717; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i647718; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885767719; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr7720; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 87721; CHECK-NEXT: [[TMP8:%.*]] = lshr <2 x i32> [[_MSLD]], splat (i32 1)7722; CHECK-NEXT: [[TMP9:%.*]] = or <2 x i32> [[TMP8]], zeroinitializer7723; CHECK-NEXT: [[TMP3:%.*]] = lshr <2 x i32> [[TMP1]], splat (i32 1)7724; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 07725; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]7726; CHECK: 10:7727; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7728; CHECK-NEXT: unreachable7729; CHECK: 11:7730; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i32>, ptr [[B]], align 87731; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[B]] to i647732; CHECK-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], 1935140464885767733; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr7734; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP14]], align 87735; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[TMP9]], [[_MSLD1]]7736; CHECK-NEXT: [[TMP5:%.*]] = add <2 x i32> [[TMP3]], [[TMP4]]7737; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 87738; CHECK-NEXT: ret <2 x i32> [[TMP5]]7739;7740 %tmp1 = load <2 x i32>, ptr %A7741 %tmp3 = lshr <2 x i32> %tmp1, <i32 1, i32 1>7742 %tmp4 = load <2 x i32>, ptr %B7743 %tmp5 = add <2 x i32> %tmp3, %tmp47744 ret <2 x i32> %tmp57745}7746 7747define <16 x i8> @usra16b(ptr %A, ptr %B) nounwind sanitize_memory {7748; CHECK-LABEL: define <16 x i8> @usra16b(7749; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {7750; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 87751; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 87752; CHECK-NEXT: call void @llvm.donothing()7753; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 07754; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]7755; CHECK: 3:7756; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7757; CHECK-NEXT: unreachable7758; CHECK: 4:7759; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[A]], align 167760; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i647761; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885767762; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr7763; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP7]], align 167764; CHECK-NEXT: [[TMP8:%.*]] = lshr <16 x i8> [[_MSLD]], splat (i8 1)7765; CHECK-NEXT: [[TMP9:%.*]] = or <16 x i8> [[TMP8]], zeroinitializer7766; CHECK-NEXT: [[TMP3:%.*]] = lshr <16 x i8> [[TMP1]], splat (i8 1)7767; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 07768; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]7769; CHECK: 10:7770; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7771; CHECK-NEXT: unreachable7772; CHECK: 11:7773; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i8>, ptr [[B]], align 167774; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[B]] to i647775; CHECK-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], 1935140464885767776; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr7777; CHECK-NEXT: [[_MSLD1:%.*]] = load <16 x i8>, ptr [[TMP14]], align 167778; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP9]], [[_MSLD1]]7779; CHECK-NEXT: [[TMP5:%.*]] = add <16 x i8> [[TMP3]], [[TMP4]]7780; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 87781; CHECK-NEXT: ret <16 x i8> [[TMP5]]7782;7783 %tmp1 = load <16 x i8>, ptr %A7784 %tmp3 = lshr <16 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>7785 %tmp4 = load <16 x i8>, ptr %B7786 %tmp5 = add <16 x i8> %tmp3, %tmp47787 ret <16 x i8> %tmp57788}7789 7790define <8 x i16> @usra8h(ptr %A, ptr %B) nounwind sanitize_memory {7791; CHECK-LABEL: define <8 x i16> @usra8h(7792; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {7793; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 87794; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 87795; CHECK-NEXT: call void @llvm.donothing()7796; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 07797; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]7798; CHECK: 3:7799; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7800; CHECK-NEXT: unreachable7801; CHECK: 4:7802; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 167803; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i647804; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885767805; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr7806; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 167807; CHECK-NEXT: [[TMP8:%.*]] = lshr <8 x i16> [[_MSLD]], splat (i16 1)7808; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i16> [[TMP8]], zeroinitializer7809; CHECK-NEXT: [[TMP3:%.*]] = lshr <8 x i16> [[TMP1]], splat (i16 1)7810; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 07811; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]7812; CHECK: 10:7813; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7814; CHECK-NEXT: unreachable7815; CHECK: 11:7816; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i16>, ptr [[B]], align 167817; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[B]] to i647818; CHECK-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], 1935140464885767819; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr7820; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP14]], align 167821; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP9]], [[_MSLD1]]7822; CHECK-NEXT: [[TMP5:%.*]] = add <8 x i16> [[TMP3]], [[TMP4]]7823; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 87824; CHECK-NEXT: ret <8 x i16> [[TMP5]]7825;7826 %tmp1 = load <8 x i16>, ptr %A7827 %tmp3 = lshr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>7828 %tmp4 = load <8 x i16>, ptr %B7829 %tmp5 = add <8 x i16> %tmp3, %tmp47830 ret <8 x i16> %tmp57831}7832 7833define <4 x i32> @usra4s(ptr %A, ptr %B) nounwind sanitize_memory {7834; CHECK-LABEL: define <4 x i32> @usra4s(7835; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {7836; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 87837; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 87838; CHECK-NEXT: call void @llvm.donothing()7839; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 07840; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]7841; CHECK: 3:7842; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7843; CHECK-NEXT: unreachable7844; CHECK: 4:7845; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 167846; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i647847; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885767848; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr7849; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 167850; CHECK-NEXT: [[TMP8:%.*]] = lshr <4 x i32> [[_MSLD]], splat (i32 1)7851; CHECK-NEXT: [[TMP9:%.*]] = or <4 x i32> [[TMP8]], zeroinitializer7852; CHECK-NEXT: [[TMP3:%.*]] = lshr <4 x i32> [[TMP1]], splat (i32 1)7853; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 07854; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]7855; CHECK: 10:7856; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7857; CHECK-NEXT: unreachable7858; CHECK: 11:7859; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr [[B]], align 167860; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[B]] to i647861; CHECK-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], 1935140464885767862; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr7863; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP14]], align 167864; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP9]], [[_MSLD1]]7865; CHECK-NEXT: [[TMP5:%.*]] = add <4 x i32> [[TMP3]], [[TMP4]]7866; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 87867; CHECK-NEXT: ret <4 x i32> [[TMP5]]7868;7869 %tmp1 = load <4 x i32>, ptr %A7870 %tmp3 = lshr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>7871 %tmp4 = load <4 x i32>, ptr %B7872 %tmp5 = add <4 x i32> %tmp3, %tmp47873 ret <4 x i32> %tmp57874}7875 7876define <2 x i64> @usra2d(ptr %A, ptr %B) nounwind sanitize_memory {7877; CHECK-LABEL: define <2 x i64> @usra2d(7878; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {7879; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 87880; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 87881; CHECK-NEXT: call void @llvm.donothing()7882; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 07883; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]7884; CHECK: 3:7885; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7886; CHECK-NEXT: unreachable7887; CHECK: 4:7888; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 167889; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i647890; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885767891; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr7892; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 167893; CHECK-NEXT: [[TMP8:%.*]] = lshr <2 x i64> [[_MSLD]], splat (i64 1)7894; CHECK-NEXT: [[TMP9:%.*]] = or <2 x i64> [[TMP8]], zeroinitializer7895; CHECK-NEXT: [[TMP3:%.*]] = lshr <2 x i64> [[TMP1]], splat (i64 1)7896; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 07897; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]7898; CHECK: 10:7899; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7900; CHECK-NEXT: unreachable7901; CHECK: 11:7902; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr [[B]], align 167903; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[B]] to i647904; CHECK-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], 1935140464885767905; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr7906; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP14]], align 167907; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP9]], [[_MSLD1]]7908; CHECK-NEXT: [[TMP5:%.*]] = add <2 x i64> [[TMP3]], [[TMP4]]7909; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 87910; CHECK-NEXT: ret <2 x i64> [[TMP5]]7911;7912 %tmp1 = load <2 x i64>, ptr %A7913 %tmp3 = lshr <2 x i64> %tmp1, <i64 1, i64 1>7914 %tmp4 = load <2 x i64>, ptr %B7915 %tmp5 = add <2 x i64> %tmp3, %tmp47916 ret <2 x i64> %tmp57917}7918 7919define <1 x i64> @usra1d(ptr %A, ptr %B) nounwind sanitize_memory {7920; CHECK-LABEL: define <1 x i64> @usra1d(7921; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {7922; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 87923; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 87924; CHECK-NEXT: call void @llvm.donothing()7925; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 07926; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]7927; CHECK: 3:7928; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7929; CHECK-NEXT: unreachable7930; CHECK: 4:7931; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr [[A]], align 87932; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i647933; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885767934; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr7935; CHECK-NEXT: [[_MSLD:%.*]] = load <1 x i64>, ptr [[TMP7]], align 87936; CHECK-NEXT: [[TMP8:%.*]] = lshr <1 x i64> [[_MSLD]], splat (i64 1)7937; CHECK-NEXT: [[TMP9:%.*]] = or <1 x i64> [[TMP8]], zeroinitializer7938; CHECK-NEXT: [[TMP3:%.*]] = lshr <1 x i64> [[TMP1]], splat (i64 1)7939; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 07940; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]7941; CHECK: 10:7942; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7943; CHECK-NEXT: unreachable7944; CHECK: 11:7945; CHECK-NEXT: [[TMP4:%.*]] = load <1 x i64>, ptr [[B]], align 87946; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[B]] to i647947; CHECK-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], 1935140464885767948; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr7949; CHECK-NEXT: [[_MSLD1:%.*]] = load <1 x i64>, ptr [[TMP14]], align 87950; CHECK-NEXT: [[_MSPROP:%.*]] = or <1 x i64> [[TMP9]], [[_MSLD1]]7951; CHECK-NEXT: [[TMP5:%.*]] = add <1 x i64> [[TMP3]], [[TMP4]]7952; CHECK-NEXT: store <1 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 87953; CHECK-NEXT: ret <1 x i64> [[TMP5]]7954;7955 %tmp1 = load <1 x i64>, ptr %A7956 %tmp3 = lshr <1 x i64> %tmp1, <i64 1>7957 %tmp4 = load <1 x i64>, ptr %B7958 %tmp5 = add <1 x i64> %tmp3, %tmp47959 ret <1 x i64> %tmp57960}7961 7962define <8 x i8> @ssra8b(ptr %A, ptr %B) nounwind sanitize_memory {7963; CHECK-LABEL: define <8 x i8> @ssra8b(7964; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {7965; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 87966; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 87967; CHECK-NEXT: call void @llvm.donothing()7968; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 07969; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]7970; CHECK: 3:7971; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7972; CHECK-NEXT: unreachable7973; CHECK: 4:7974; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[A]], align 87975; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i647976; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885767977; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr7978; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 87979; CHECK-NEXT: [[TMP8:%.*]] = ashr <8 x i8> [[_MSLD]], splat (i8 1)7980; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i8> [[TMP8]], zeroinitializer7981; CHECK-NEXT: [[TMP3:%.*]] = ashr <8 x i8> [[TMP1]], splat (i8 1)7982; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 07983; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]7984; CHECK: 10:7985; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]7986; CHECK-NEXT: unreachable7987; CHECK: 11:7988; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i8>, ptr [[B]], align 87989; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[B]] to i647990; CHECK-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], 1935140464885767991; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr7992; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP14]], align 87993; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i8> [[TMP9]], [[_MSLD1]]7994; CHECK-NEXT: [[TMP5:%.*]] = add <8 x i8> [[TMP3]], [[TMP4]]7995; CHECK-NEXT: store <8 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 87996; CHECK-NEXT: ret <8 x i8> [[TMP5]]7997;7998 %tmp1 = load <8 x i8>, ptr %A7999 %tmp3 = ashr <8 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>8000 %tmp4 = load <8 x i8>, ptr %B8001 %tmp5 = add <8 x i8> %tmp3, %tmp48002 ret <8 x i8> %tmp58003}8004 8005define <4 x i16> @ssra4h(ptr %A, ptr %B) nounwind sanitize_memory {8006; CHECK-LABEL: define <4 x i16> @ssra4h(8007; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {8008; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 88009; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 88010; CHECK-NEXT: call void @llvm.donothing()8011; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 08012; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]8013; CHECK: 3:8014; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8015; CHECK-NEXT: unreachable8016; CHECK: 4:8017; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 88018; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i648019; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885768020; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr8021; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 88022; CHECK-NEXT: [[TMP8:%.*]] = ashr <4 x i16> [[_MSLD]], splat (i16 1)8023; CHECK-NEXT: [[TMP9:%.*]] = or <4 x i16> [[TMP8]], zeroinitializer8024; CHECK-NEXT: [[TMP3:%.*]] = ashr <4 x i16> [[TMP1]], splat (i16 1)8025; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 08026; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]8027; CHECK: 10:8028; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8029; CHECK-NEXT: unreachable8030; CHECK: 11:8031; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i16>, ptr [[B]], align 88032; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[B]] to i648033; CHECK-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], 1935140464885768034; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr8035; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP14]], align 88036; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i16> [[TMP9]], [[_MSLD1]]8037; CHECK-NEXT: [[TMP5:%.*]] = add <4 x i16> [[TMP3]], [[TMP4]]8038; CHECK-NEXT: store <4 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 88039; CHECK-NEXT: ret <4 x i16> [[TMP5]]8040;8041 %tmp1 = load <4 x i16>, ptr %A8042 %tmp3 = ashr <4 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1>8043 %tmp4 = load <4 x i16>, ptr %B8044 %tmp5 = add <4 x i16> %tmp3, %tmp48045 ret <4 x i16> %tmp58046}8047 8048define <2 x i32> @ssra2s(ptr %A, ptr %B) nounwind sanitize_memory {8049; CHECK-LABEL: define <2 x i32> @ssra2s(8050; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {8051; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 88052; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 88053; CHECK-NEXT: call void @llvm.donothing()8054; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 08055; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]8056; CHECK: 3:8057; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8058; CHECK-NEXT: unreachable8059; CHECK: 4:8060; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 88061; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i648062; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885768063; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr8064; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 88065; CHECK-NEXT: [[TMP8:%.*]] = ashr <2 x i32> [[_MSLD]], splat (i32 1)8066; CHECK-NEXT: [[TMP9:%.*]] = or <2 x i32> [[TMP8]], zeroinitializer8067; CHECK-NEXT: [[TMP3:%.*]] = ashr <2 x i32> [[TMP1]], splat (i32 1)8068; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 08069; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]8070; CHECK: 10:8071; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8072; CHECK-NEXT: unreachable8073; CHECK: 11:8074; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i32>, ptr [[B]], align 88075; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[B]] to i648076; CHECK-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], 1935140464885768077; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr8078; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP14]], align 88079; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i32> [[TMP9]], [[_MSLD1]]8080; CHECK-NEXT: [[TMP5:%.*]] = add <2 x i32> [[TMP3]], [[TMP4]]8081; CHECK-NEXT: store <2 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 88082; CHECK-NEXT: ret <2 x i32> [[TMP5]]8083;8084 %tmp1 = load <2 x i32>, ptr %A8085 %tmp3 = ashr <2 x i32> %tmp1, <i32 1, i32 1>8086 %tmp4 = load <2 x i32>, ptr %B8087 %tmp5 = add <2 x i32> %tmp3, %tmp48088 ret <2 x i32> %tmp58089}8090 8091define <16 x i8> @ssra16b(ptr %A, ptr %B) nounwind sanitize_memory {8092; CHECK-LABEL: define <16 x i8> @ssra16b(8093; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {8094; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 88095; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 88096; CHECK-NEXT: call void @llvm.donothing()8097; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 08098; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]8099; CHECK: 3:8100; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8101; CHECK-NEXT: unreachable8102; CHECK: 4:8103; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[A]], align 168104; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i648105; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885768106; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr8107; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP7]], align 168108; CHECK-NEXT: [[TMP8:%.*]] = ashr <16 x i8> [[_MSLD]], splat (i8 1)8109; CHECK-NEXT: [[TMP9:%.*]] = or <16 x i8> [[TMP8]], zeroinitializer8110; CHECK-NEXT: [[TMP3:%.*]] = ashr <16 x i8> [[TMP1]], splat (i8 1)8111; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 08112; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]8113; CHECK: 10:8114; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8115; CHECK-NEXT: unreachable8116; CHECK: 11:8117; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i8>, ptr [[B]], align 168118; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[B]] to i648119; CHECK-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], 1935140464885768120; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr8121; CHECK-NEXT: [[_MSLD1:%.*]] = load <16 x i8>, ptr [[TMP14]], align 168122; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i8> [[TMP9]], [[_MSLD1]]8123; CHECK-NEXT: [[TMP5:%.*]] = add <16 x i8> [[TMP3]], [[TMP4]]8124; CHECK-NEXT: store <16 x i8> [[_MSPROP]], ptr @__msan_retval_tls, align 88125; CHECK-NEXT: ret <16 x i8> [[TMP5]]8126;8127 %tmp1 = load <16 x i8>, ptr %A8128 %tmp3 = ashr <16 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>8129 %tmp4 = load <16 x i8>, ptr %B8130 %tmp5 = add <16 x i8> %tmp3, %tmp48131 ret <16 x i8> %tmp58132}8133 8134define <8 x i16> @ssra8h(ptr %A, ptr %B) nounwind sanitize_memory {8135; CHECK-LABEL: define <8 x i16> @ssra8h(8136; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {8137; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 88138; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 88139; CHECK-NEXT: call void @llvm.donothing()8140; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 08141; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]8142; CHECK: 3:8143; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8144; CHECK-NEXT: unreachable8145; CHECK: 4:8146; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 168147; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i648148; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885768149; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr8150; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 168151; CHECK-NEXT: [[TMP8:%.*]] = ashr <8 x i16> [[_MSLD]], splat (i16 1)8152; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i16> [[TMP8]], zeroinitializer8153; CHECK-NEXT: [[TMP3:%.*]] = ashr <8 x i16> [[TMP1]], splat (i16 1)8154; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 08155; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]8156; CHECK: 10:8157; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8158; CHECK-NEXT: unreachable8159; CHECK: 11:8160; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i16>, ptr [[B]], align 168161; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[B]] to i648162; CHECK-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], 1935140464885768163; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr8164; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP14]], align 168165; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP9]], [[_MSLD1]]8166; CHECK-NEXT: [[TMP5:%.*]] = add <8 x i16> [[TMP3]], [[TMP4]]8167; CHECK-NEXT: store <8 x i16> [[_MSPROP]], ptr @__msan_retval_tls, align 88168; CHECK-NEXT: ret <8 x i16> [[TMP5]]8169;8170 %tmp1 = load <8 x i16>, ptr %A8171 %tmp3 = ashr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>8172 %tmp4 = load <8 x i16>, ptr %B8173 %tmp5 = add <8 x i16> %tmp3, %tmp48174 ret <8 x i16> %tmp58175}8176 8177define <4 x i32> @ssra4s(ptr %A, ptr %B) nounwind sanitize_memory {8178; CHECK-LABEL: define <4 x i32> @ssra4s(8179; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {8180; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 88181; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 88182; CHECK-NEXT: call void @llvm.donothing()8183; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 08184; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]8185; CHECK: 3:8186; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8187; CHECK-NEXT: unreachable8188; CHECK: 4:8189; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 168190; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i648191; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885768192; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr8193; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 168194; CHECK-NEXT: [[TMP8:%.*]] = ashr <4 x i32> [[_MSLD]], splat (i32 1)8195; CHECK-NEXT: [[TMP9:%.*]] = or <4 x i32> [[TMP8]], zeroinitializer8196; CHECK-NEXT: [[TMP3:%.*]] = ashr <4 x i32> [[TMP1]], splat (i32 1)8197; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 08198; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]8199; CHECK: 10:8200; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8201; CHECK-NEXT: unreachable8202; CHECK: 11:8203; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr [[B]], align 168204; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[B]] to i648205; CHECK-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], 1935140464885768206; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr8207; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP14]], align 168208; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP9]], [[_MSLD1]]8209; CHECK-NEXT: [[TMP5:%.*]] = add <4 x i32> [[TMP3]], [[TMP4]]8210; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 88211; CHECK-NEXT: ret <4 x i32> [[TMP5]]8212;8213 %tmp1 = load <4 x i32>, ptr %A8214 %tmp3 = ashr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>8215 %tmp4 = load <4 x i32>, ptr %B8216 %tmp5 = add <4 x i32> %tmp3, %tmp48217 ret <4 x i32> %tmp58218}8219 8220define <2 x i64> @ssra2d(ptr %A, ptr %B) nounwind sanitize_memory {8221; CHECK-LABEL: define <2 x i64> @ssra2d(8222; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {8223; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 88224; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 88225; CHECK-NEXT: call void @llvm.donothing()8226; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 08227; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]8228; CHECK: 3:8229; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8230; CHECK-NEXT: unreachable8231; CHECK: 4:8232; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 168233; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i648234; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885768235; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr8236; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 168237; CHECK-NEXT: [[TMP8:%.*]] = ashr <2 x i64> [[_MSLD]], splat (i64 1)8238; CHECK-NEXT: [[TMP9:%.*]] = or <2 x i64> [[TMP8]], zeroinitializer8239; CHECK-NEXT: [[TMP3:%.*]] = ashr <2 x i64> [[TMP1]], splat (i64 1)8240; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 08241; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP10:%.*]], label [[TMP11:%.*]], !prof [[PROF1]]8242; CHECK: 10:8243; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8244; CHECK-NEXT: unreachable8245; CHECK: 11:8246; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr [[B]], align 168247; CHECK-NEXT: [[TMP12:%.*]] = ptrtoint ptr [[B]] to i648248; CHECK-NEXT: [[TMP13:%.*]] = xor i64 [[TMP12]], 1935140464885768249; CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP13]] to ptr8250; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP14]], align 168251; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP9]], [[_MSLD1]]8252; CHECK-NEXT: [[TMP5:%.*]] = add <2 x i64> [[TMP3]], [[TMP4]]8253; CHECK-NEXT: store <2 x i64> [[_MSPROP]], ptr @__msan_retval_tls, align 88254; CHECK-NEXT: ret <2 x i64> [[TMP5]]8255;8256 %tmp1 = load <2 x i64>, ptr %A8257 %tmp3 = ashr <2 x i64> %tmp1, <i64 1, i64 1>8258 %tmp4 = load <2 x i64>, ptr %B8259 %tmp5 = add <2 x i64> %tmp3, %tmp48260 ret <2 x i64> %tmp58261}8262 8263define <8 x i8> @shr_orr8b(ptr %A, ptr %B) nounwind sanitize_memory {8264; CHECK-LABEL: define <8 x i8> @shr_orr8b(8265; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {8266; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 88267; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 88268; CHECK-NEXT: call void @llvm.donothing()8269; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 08270; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]8271; CHECK: 3:8272; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8273; CHECK-NEXT: unreachable8274; CHECK: 4:8275; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[A]], align 88276; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i648277; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885768278; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr8279; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 88280; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 08281; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]8282; CHECK: 8:8283; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8284; CHECK-NEXT: unreachable8285; CHECK: 9:8286; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i8>, ptr [[B]], align 88287; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i648288; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885768289; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr8290; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP12]], align 88291; CHECK-NEXT: [[TMP13:%.*]] = lshr <8 x i8> [[_MSLD]], splat (i8 1)8292; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i8> [[TMP13]], zeroinitializer8293; CHECK-NEXT: [[TMP3:%.*]] = lshr <8 x i8> [[TMP1]], splat (i8 1)8294; CHECK-NEXT: [[TMP15:%.*]] = xor <8 x i8> [[TMP3]], splat (i8 -1)8295; CHECK-NEXT: [[TMP16:%.*]] = xor <8 x i8> [[TMP4]], splat (i8 -1)8296; CHECK-NEXT: [[TMP17:%.*]] = and <8 x i8> [[TMP14]], [[_MSLD1]]8297; CHECK-NEXT: [[TMP18:%.*]] = and <8 x i8> [[TMP15]], [[_MSLD1]]8298; CHECK-NEXT: [[TMP19:%.*]] = and <8 x i8> [[TMP14]], [[TMP16]]8299; CHECK-NEXT: [[TMP20:%.*]] = or <8 x i8> [[TMP17]], [[TMP18]]8300; CHECK-NEXT: [[TMP21:%.*]] = or <8 x i8> [[TMP20]], [[TMP19]]8301; CHECK-NEXT: [[TMP5:%.*]] = or <8 x i8> [[TMP3]], [[TMP4]]8302; CHECK-NEXT: store <8 x i8> [[TMP21]], ptr @__msan_retval_tls, align 88303; CHECK-NEXT: ret <8 x i8> [[TMP5]]8304;8305 %tmp1 = load <8 x i8>, ptr %A8306 %tmp4 = load <8 x i8>, ptr %B8307 %tmp3 = lshr <8 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>8308 %tmp5 = or <8 x i8> %tmp3, %tmp48309 ret <8 x i8> %tmp58310}8311 8312define <4 x i16> @shr_orr4h(ptr %A, ptr %B) nounwind sanitize_memory {8313; CHECK-LABEL: define <4 x i16> @shr_orr4h(8314; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {8315; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 88316; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 88317; CHECK-NEXT: call void @llvm.donothing()8318; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 08319; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]8320; CHECK: 3:8321; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8322; CHECK-NEXT: unreachable8323; CHECK: 4:8324; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 88325; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i648326; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885768327; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr8328; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 88329; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 08330; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]8331; CHECK: 8:8332; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8333; CHECK-NEXT: unreachable8334; CHECK: 9:8335; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i16>, ptr [[B]], align 88336; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i648337; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885768338; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr8339; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 88340; CHECK-NEXT: [[TMP13:%.*]] = lshr <4 x i16> [[_MSLD]], splat (i16 1)8341; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i16> [[TMP13]], zeroinitializer8342; CHECK-NEXT: [[TMP3:%.*]] = lshr <4 x i16> [[TMP1]], splat (i16 1)8343; CHECK-NEXT: [[TMP15:%.*]] = xor <4 x i16> [[TMP3]], splat (i16 -1)8344; CHECK-NEXT: [[TMP16:%.*]] = xor <4 x i16> [[TMP4]], splat (i16 -1)8345; CHECK-NEXT: [[TMP17:%.*]] = and <4 x i16> [[TMP14]], [[_MSLD1]]8346; CHECK-NEXT: [[TMP18:%.*]] = and <4 x i16> [[TMP15]], [[_MSLD1]]8347; CHECK-NEXT: [[TMP19:%.*]] = and <4 x i16> [[TMP14]], [[TMP16]]8348; CHECK-NEXT: [[TMP20:%.*]] = or <4 x i16> [[TMP17]], [[TMP18]]8349; CHECK-NEXT: [[TMP21:%.*]] = or <4 x i16> [[TMP20]], [[TMP19]]8350; CHECK-NEXT: [[TMP5:%.*]] = or <4 x i16> [[TMP3]], [[TMP4]]8351; CHECK-NEXT: store <4 x i16> [[TMP21]], ptr @__msan_retval_tls, align 88352; CHECK-NEXT: ret <4 x i16> [[TMP5]]8353;8354 %tmp1 = load <4 x i16>, ptr %A8355 %tmp4 = load <4 x i16>, ptr %B8356 %tmp3 = lshr <4 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1>8357 %tmp5 = or <4 x i16> %tmp3, %tmp48358 ret <4 x i16> %tmp58359}8360 8361define <2 x i32> @shr_orr2s(ptr %A, ptr %B) nounwind sanitize_memory {8362; CHECK-LABEL: define <2 x i32> @shr_orr2s(8363; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {8364; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 88365; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 88366; CHECK-NEXT: call void @llvm.donothing()8367; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 08368; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]8369; CHECK: 3:8370; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8371; CHECK-NEXT: unreachable8372; CHECK: 4:8373; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 88374; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i648375; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885768376; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr8377; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 88378; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 08379; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]8380; CHECK: 8:8381; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8382; CHECK-NEXT: unreachable8383; CHECK: 9:8384; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i32>, ptr [[B]], align 88385; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i648386; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885768387; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr8388; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 88389; CHECK-NEXT: [[TMP13:%.*]] = lshr <2 x i32> [[_MSLD]], splat (i32 1)8390; CHECK-NEXT: [[TMP14:%.*]] = or <2 x i32> [[TMP13]], zeroinitializer8391; CHECK-NEXT: [[TMP3:%.*]] = lshr <2 x i32> [[TMP1]], splat (i32 1)8392; CHECK-NEXT: [[TMP15:%.*]] = xor <2 x i32> [[TMP3]], splat (i32 -1)8393; CHECK-NEXT: [[TMP16:%.*]] = xor <2 x i32> [[TMP4]], splat (i32 -1)8394; CHECK-NEXT: [[TMP17:%.*]] = and <2 x i32> [[TMP14]], [[_MSLD1]]8395; CHECK-NEXT: [[TMP18:%.*]] = and <2 x i32> [[TMP15]], [[_MSLD1]]8396; CHECK-NEXT: [[TMP19:%.*]] = and <2 x i32> [[TMP14]], [[TMP16]]8397; CHECK-NEXT: [[TMP20:%.*]] = or <2 x i32> [[TMP17]], [[TMP18]]8398; CHECK-NEXT: [[TMP21:%.*]] = or <2 x i32> [[TMP20]], [[TMP19]]8399; CHECK-NEXT: [[TMP5:%.*]] = or <2 x i32> [[TMP3]], [[TMP4]]8400; CHECK-NEXT: store <2 x i32> [[TMP21]], ptr @__msan_retval_tls, align 88401; CHECK-NEXT: ret <2 x i32> [[TMP5]]8402;8403 %tmp1 = load <2 x i32>, ptr %A8404 %tmp4 = load <2 x i32>, ptr %B8405 %tmp3 = lshr <2 x i32> %tmp1, <i32 1, i32 1>8406 %tmp5 = or <2 x i32> %tmp3, %tmp48407 ret <2 x i32> %tmp58408}8409 8410define <16 x i8> @shr_orr16b(ptr %A, ptr %B) nounwind sanitize_memory {8411; CHECK-LABEL: define <16 x i8> @shr_orr16b(8412; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {8413; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 88414; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 88415; CHECK-NEXT: call void @llvm.donothing()8416; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 08417; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]8418; CHECK: 3:8419; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8420; CHECK-NEXT: unreachable8421; CHECK: 4:8422; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[A]], align 168423; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i648424; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885768425; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr8426; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP7]], align 168427; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 08428; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]8429; CHECK: 8:8430; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8431; CHECK-NEXT: unreachable8432; CHECK: 9:8433; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i8>, ptr [[B]], align 168434; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i648435; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885768436; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr8437; CHECK-NEXT: [[_MSLD1:%.*]] = load <16 x i8>, ptr [[TMP12]], align 168438; CHECK-NEXT: [[TMP13:%.*]] = lshr <16 x i8> [[_MSLD]], splat (i8 1)8439; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i8> [[TMP13]], zeroinitializer8440; CHECK-NEXT: [[TMP3:%.*]] = lshr <16 x i8> [[TMP1]], splat (i8 1)8441; CHECK-NEXT: [[TMP15:%.*]] = xor <16 x i8> [[TMP3]], splat (i8 -1)8442; CHECK-NEXT: [[TMP16:%.*]] = xor <16 x i8> [[TMP4]], splat (i8 -1)8443; CHECK-NEXT: [[TMP17:%.*]] = and <16 x i8> [[TMP14]], [[_MSLD1]]8444; CHECK-NEXT: [[TMP18:%.*]] = and <16 x i8> [[TMP15]], [[_MSLD1]]8445; CHECK-NEXT: [[TMP19:%.*]] = and <16 x i8> [[TMP14]], [[TMP16]]8446; CHECK-NEXT: [[TMP20:%.*]] = or <16 x i8> [[TMP17]], [[TMP18]]8447; CHECK-NEXT: [[TMP21:%.*]] = or <16 x i8> [[TMP20]], [[TMP19]]8448; CHECK-NEXT: [[TMP5:%.*]] = or <16 x i8> [[TMP3]], [[TMP4]]8449; CHECK-NEXT: store <16 x i8> [[TMP21]], ptr @__msan_retval_tls, align 88450; CHECK-NEXT: ret <16 x i8> [[TMP5]]8451;8452 %tmp1 = load <16 x i8>, ptr %A8453 %tmp4 = load <16 x i8>, ptr %B8454 %tmp3 = lshr <16 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>8455 %tmp5 = or <16 x i8> %tmp3, %tmp48456 ret <16 x i8> %tmp58457}8458 8459define <8 x i16> @shr_orr8h(ptr %A, ptr %B) nounwind sanitize_memory {8460; CHECK-LABEL: define <8 x i16> @shr_orr8h(8461; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {8462; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 88463; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 88464; CHECK-NEXT: call void @llvm.donothing()8465; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 08466; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]8467; CHECK: 3:8468; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8469; CHECK-NEXT: unreachable8470; CHECK: 4:8471; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 168472; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i648473; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885768474; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr8475; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 168476; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 08477; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]8478; CHECK: 8:8479; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8480; CHECK-NEXT: unreachable8481; CHECK: 9:8482; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i16>, ptr [[B]], align 168483; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i648484; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885768485; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr8486; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 168487; CHECK-NEXT: [[TMP13:%.*]] = lshr <8 x i16> [[_MSLD]], splat (i16 1)8488; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i16> [[TMP13]], zeroinitializer8489; CHECK-NEXT: [[TMP3:%.*]] = lshr <8 x i16> [[TMP1]], splat (i16 1)8490; CHECK-NEXT: [[TMP15:%.*]] = xor <8 x i16> [[TMP3]], splat (i16 -1)8491; CHECK-NEXT: [[TMP16:%.*]] = xor <8 x i16> [[TMP4]], splat (i16 -1)8492; CHECK-NEXT: [[TMP17:%.*]] = and <8 x i16> [[TMP14]], [[_MSLD1]]8493; CHECK-NEXT: [[TMP18:%.*]] = and <8 x i16> [[TMP15]], [[_MSLD1]]8494; CHECK-NEXT: [[TMP19:%.*]] = and <8 x i16> [[TMP14]], [[TMP16]]8495; CHECK-NEXT: [[TMP20:%.*]] = or <8 x i16> [[TMP17]], [[TMP18]]8496; CHECK-NEXT: [[TMP21:%.*]] = or <8 x i16> [[TMP20]], [[TMP19]]8497; CHECK-NEXT: [[TMP5:%.*]] = or <8 x i16> [[TMP3]], [[TMP4]]8498; CHECK-NEXT: store <8 x i16> [[TMP21]], ptr @__msan_retval_tls, align 88499; CHECK-NEXT: ret <8 x i16> [[TMP5]]8500;8501 %tmp1 = load <8 x i16>, ptr %A8502 %tmp4 = load <8 x i16>, ptr %B8503 %tmp3 = lshr <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>8504 %tmp5 = or <8 x i16> %tmp3, %tmp48505 ret <8 x i16> %tmp58506}8507 8508define <4 x i32> @shr_orr4s(ptr %A, ptr %B) nounwind sanitize_memory {8509; CHECK-LABEL: define <4 x i32> @shr_orr4s(8510; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {8511; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 88512; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 88513; CHECK-NEXT: call void @llvm.donothing()8514; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 08515; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]8516; CHECK: 3:8517; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8518; CHECK-NEXT: unreachable8519; CHECK: 4:8520; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 168521; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i648522; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885768523; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr8524; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 168525; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 08526; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]8527; CHECK: 8:8528; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8529; CHECK-NEXT: unreachable8530; CHECK: 9:8531; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr [[B]], align 168532; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i648533; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885768534; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr8535; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 168536; CHECK-NEXT: [[TMP13:%.*]] = lshr <4 x i32> [[_MSLD]], splat (i32 1)8537; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i32> [[TMP13]], zeroinitializer8538; CHECK-NEXT: [[TMP3:%.*]] = lshr <4 x i32> [[TMP1]], splat (i32 1)8539; CHECK-NEXT: [[TMP15:%.*]] = xor <4 x i32> [[TMP3]], splat (i32 -1)8540; CHECK-NEXT: [[TMP16:%.*]] = xor <4 x i32> [[TMP4]], splat (i32 -1)8541; CHECK-NEXT: [[TMP17:%.*]] = and <4 x i32> [[TMP14]], [[_MSLD1]]8542; CHECK-NEXT: [[TMP18:%.*]] = and <4 x i32> [[TMP15]], [[_MSLD1]]8543; CHECK-NEXT: [[TMP19:%.*]] = and <4 x i32> [[TMP14]], [[TMP16]]8544; CHECK-NEXT: [[TMP20:%.*]] = or <4 x i32> [[TMP17]], [[TMP18]]8545; CHECK-NEXT: [[TMP21:%.*]] = or <4 x i32> [[TMP20]], [[TMP19]]8546; CHECK-NEXT: [[TMP5:%.*]] = or <4 x i32> [[TMP3]], [[TMP4]]8547; CHECK-NEXT: store <4 x i32> [[TMP21]], ptr @__msan_retval_tls, align 88548; CHECK-NEXT: ret <4 x i32> [[TMP5]]8549;8550 %tmp1 = load <4 x i32>, ptr %A8551 %tmp4 = load <4 x i32>, ptr %B8552 %tmp3 = lshr <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>8553 %tmp5 = or <4 x i32> %tmp3, %tmp48554 ret <4 x i32> %tmp58555}8556 8557define <2 x i64> @shr_orr2d(ptr %A, ptr %B) nounwind sanitize_memory {8558; CHECK-LABEL: define <2 x i64> @shr_orr2d(8559; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {8560; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 88561; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 88562; CHECK-NEXT: call void @llvm.donothing()8563; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 08564; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]8565; CHECK: 3:8566; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8567; CHECK-NEXT: unreachable8568; CHECK: 4:8569; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 168570; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i648571; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885768572; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr8573; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 168574; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 08575; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]8576; CHECK: 8:8577; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8578; CHECK-NEXT: unreachable8579; CHECK: 9:8580; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr [[B]], align 168581; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i648582; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885768583; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr8584; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 168585; CHECK-NEXT: [[TMP13:%.*]] = lshr <2 x i64> [[_MSLD]], splat (i64 1)8586; CHECK-NEXT: [[TMP14:%.*]] = or <2 x i64> [[TMP13]], zeroinitializer8587; CHECK-NEXT: [[TMP3:%.*]] = lshr <2 x i64> [[TMP1]], splat (i64 1)8588; CHECK-NEXT: [[TMP15:%.*]] = xor <2 x i64> [[TMP3]], splat (i64 -1)8589; CHECK-NEXT: [[TMP16:%.*]] = xor <2 x i64> [[TMP4]], splat (i64 -1)8590; CHECK-NEXT: [[TMP17:%.*]] = and <2 x i64> [[TMP14]], [[_MSLD1]]8591; CHECK-NEXT: [[TMP18:%.*]] = and <2 x i64> [[TMP15]], [[_MSLD1]]8592; CHECK-NEXT: [[TMP19:%.*]] = and <2 x i64> [[TMP14]], [[TMP16]]8593; CHECK-NEXT: [[TMP20:%.*]] = or <2 x i64> [[TMP17]], [[TMP18]]8594; CHECK-NEXT: [[TMP21:%.*]] = or <2 x i64> [[TMP20]], [[TMP19]]8595; CHECK-NEXT: [[TMP5:%.*]] = or <2 x i64> [[TMP3]], [[TMP4]]8596; CHECK-NEXT: store <2 x i64> [[TMP21]], ptr @__msan_retval_tls, align 88597; CHECK-NEXT: ret <2 x i64> [[TMP5]]8598;8599 %tmp1 = load <2 x i64>, ptr %A8600 %tmp4 = load <2 x i64>, ptr %B8601 %tmp3 = lshr <2 x i64> %tmp1, <i64 1, i64 1>8602 %tmp5 = or <2 x i64> %tmp3, %tmp48603 ret <2 x i64> %tmp58604}8605 8606define <8 x i8> @shl_orr8b(ptr %A, ptr %B) nounwind sanitize_memory {8607; CHECK-LABEL: define <8 x i8> @shl_orr8b(8608; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {8609; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 88610; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 88611; CHECK-NEXT: call void @llvm.donothing()8612; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 08613; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]8614; CHECK: 3:8615; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8616; CHECK-NEXT: unreachable8617; CHECK: 4:8618; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[A]], align 88619; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i648620; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885768621; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr8622; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 88623; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 08624; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]8625; CHECK: 8:8626; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8627; CHECK-NEXT: unreachable8628; CHECK: 9:8629; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i8>, ptr [[B]], align 88630; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i648631; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885768632; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr8633; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP12]], align 88634; CHECK-NEXT: [[TMP13:%.*]] = shl <8 x i8> [[_MSLD]], splat (i8 1)8635; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i8> [[TMP13]], zeroinitializer8636; CHECK-NEXT: [[TMP3:%.*]] = shl <8 x i8> [[TMP1]], splat (i8 1)8637; CHECK-NEXT: [[TMP15:%.*]] = xor <8 x i8> [[TMP3]], splat (i8 -1)8638; CHECK-NEXT: [[TMP16:%.*]] = xor <8 x i8> [[TMP4]], splat (i8 -1)8639; CHECK-NEXT: [[TMP17:%.*]] = and <8 x i8> [[TMP14]], [[_MSLD1]]8640; CHECK-NEXT: [[TMP18:%.*]] = and <8 x i8> [[TMP15]], [[_MSLD1]]8641; CHECK-NEXT: [[TMP19:%.*]] = and <8 x i8> [[TMP14]], [[TMP16]]8642; CHECK-NEXT: [[TMP20:%.*]] = or <8 x i8> [[TMP17]], [[TMP18]]8643; CHECK-NEXT: [[TMP21:%.*]] = or <8 x i8> [[TMP20]], [[TMP19]]8644; CHECK-NEXT: [[TMP5:%.*]] = or <8 x i8> [[TMP3]], [[TMP4]]8645; CHECK-NEXT: store <8 x i8> [[TMP21]], ptr @__msan_retval_tls, align 88646; CHECK-NEXT: ret <8 x i8> [[TMP5]]8647;8648 %tmp1 = load <8 x i8>, ptr %A8649 %tmp4 = load <8 x i8>, ptr %B8650 %tmp3 = shl <8 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>8651 %tmp5 = or <8 x i8> %tmp3, %tmp48652 ret <8 x i8> %tmp58653}8654 8655define <4 x i16> @shl_orr4h(ptr %A, ptr %B) nounwind sanitize_memory {8656; CHECK-LABEL: define <4 x i16> @shl_orr4h(8657; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {8658; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 88659; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 88660; CHECK-NEXT: call void @llvm.donothing()8661; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 08662; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]8663; CHECK: 3:8664; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8665; CHECK-NEXT: unreachable8666; CHECK: 4:8667; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 88668; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i648669; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885768670; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr8671; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 88672; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 08673; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]8674; CHECK: 8:8675; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8676; CHECK-NEXT: unreachable8677; CHECK: 9:8678; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i16>, ptr [[B]], align 88679; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i648680; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885768681; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr8682; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 88683; CHECK-NEXT: [[TMP13:%.*]] = shl <4 x i16> [[_MSLD]], splat (i16 1)8684; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i16> [[TMP13]], zeroinitializer8685; CHECK-NEXT: [[TMP3:%.*]] = shl <4 x i16> [[TMP1]], splat (i16 1)8686; CHECK-NEXT: [[TMP15:%.*]] = xor <4 x i16> [[TMP3]], splat (i16 -1)8687; CHECK-NEXT: [[TMP16:%.*]] = xor <4 x i16> [[TMP4]], splat (i16 -1)8688; CHECK-NEXT: [[TMP17:%.*]] = and <4 x i16> [[TMP14]], [[_MSLD1]]8689; CHECK-NEXT: [[TMP18:%.*]] = and <4 x i16> [[TMP15]], [[_MSLD1]]8690; CHECK-NEXT: [[TMP19:%.*]] = and <4 x i16> [[TMP14]], [[TMP16]]8691; CHECK-NEXT: [[TMP20:%.*]] = or <4 x i16> [[TMP17]], [[TMP18]]8692; CHECK-NEXT: [[TMP21:%.*]] = or <4 x i16> [[TMP20]], [[TMP19]]8693; CHECK-NEXT: [[TMP5:%.*]] = or <4 x i16> [[TMP3]], [[TMP4]]8694; CHECK-NEXT: store <4 x i16> [[TMP21]], ptr @__msan_retval_tls, align 88695; CHECK-NEXT: ret <4 x i16> [[TMP5]]8696;8697 %tmp1 = load <4 x i16>, ptr %A8698 %tmp4 = load <4 x i16>, ptr %B8699 %tmp3 = shl <4 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1>8700 %tmp5 = or <4 x i16> %tmp3, %tmp48701 ret <4 x i16> %tmp58702}8703 8704define <2 x i32> @shl_orr2s(ptr %A, ptr %B) nounwind sanitize_memory {8705; CHECK-LABEL: define <2 x i32> @shl_orr2s(8706; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {8707; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 88708; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 88709; CHECK-NEXT: call void @llvm.donothing()8710; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 08711; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]8712; CHECK: 3:8713; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8714; CHECK-NEXT: unreachable8715; CHECK: 4:8716; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 88717; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i648718; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885768719; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr8720; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 88721; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 08722; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]8723; CHECK: 8:8724; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8725; CHECK-NEXT: unreachable8726; CHECK: 9:8727; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i32>, ptr [[B]], align 88728; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i648729; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885768730; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr8731; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 88732; CHECK-NEXT: [[TMP13:%.*]] = shl <2 x i32> [[_MSLD]], splat (i32 1)8733; CHECK-NEXT: [[TMP14:%.*]] = or <2 x i32> [[TMP13]], zeroinitializer8734; CHECK-NEXT: [[TMP3:%.*]] = shl <2 x i32> [[TMP1]], splat (i32 1)8735; CHECK-NEXT: [[TMP15:%.*]] = xor <2 x i32> [[TMP3]], splat (i32 -1)8736; CHECK-NEXT: [[TMP16:%.*]] = xor <2 x i32> [[TMP4]], splat (i32 -1)8737; CHECK-NEXT: [[TMP17:%.*]] = and <2 x i32> [[TMP14]], [[_MSLD1]]8738; CHECK-NEXT: [[TMP18:%.*]] = and <2 x i32> [[TMP15]], [[_MSLD1]]8739; CHECK-NEXT: [[TMP19:%.*]] = and <2 x i32> [[TMP14]], [[TMP16]]8740; CHECK-NEXT: [[TMP20:%.*]] = or <2 x i32> [[TMP17]], [[TMP18]]8741; CHECK-NEXT: [[TMP21:%.*]] = or <2 x i32> [[TMP20]], [[TMP19]]8742; CHECK-NEXT: [[TMP5:%.*]] = or <2 x i32> [[TMP3]], [[TMP4]]8743; CHECK-NEXT: store <2 x i32> [[TMP21]], ptr @__msan_retval_tls, align 88744; CHECK-NEXT: ret <2 x i32> [[TMP5]]8745;8746 %tmp1 = load <2 x i32>, ptr %A8747 %tmp4 = load <2 x i32>, ptr %B8748 %tmp3 = shl <2 x i32> %tmp1, <i32 1, i32 1>8749 %tmp5 = or <2 x i32> %tmp3, %tmp48750 ret <2 x i32> %tmp58751}8752 8753define <16 x i8> @shl_orr16b(ptr %A, ptr %B) nounwind sanitize_memory {8754; CHECK-LABEL: define <16 x i8> @shl_orr16b(8755; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {8756; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 88757; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 88758; CHECK-NEXT: call void @llvm.donothing()8759; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 08760; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]8761; CHECK: 3:8762; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8763; CHECK-NEXT: unreachable8764; CHECK: 4:8765; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[A]], align 168766; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i648767; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885768768; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr8769; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP7]], align 168770; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 08771; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]8772; CHECK: 8:8773; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8774; CHECK-NEXT: unreachable8775; CHECK: 9:8776; CHECK-NEXT: [[TMP4:%.*]] = load <16 x i8>, ptr [[B]], align 168777; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i648778; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885768779; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr8780; CHECK-NEXT: [[_MSLD1:%.*]] = load <16 x i8>, ptr [[TMP12]], align 168781; CHECK-NEXT: [[TMP13:%.*]] = shl <16 x i8> [[_MSLD]], splat (i8 1)8782; CHECK-NEXT: [[TMP14:%.*]] = or <16 x i8> [[TMP13]], zeroinitializer8783; CHECK-NEXT: [[TMP3:%.*]] = shl <16 x i8> [[TMP1]], splat (i8 1)8784; CHECK-NEXT: [[TMP15:%.*]] = xor <16 x i8> [[TMP3]], splat (i8 -1)8785; CHECK-NEXT: [[TMP16:%.*]] = xor <16 x i8> [[TMP4]], splat (i8 -1)8786; CHECK-NEXT: [[TMP17:%.*]] = and <16 x i8> [[TMP14]], [[_MSLD1]]8787; CHECK-NEXT: [[TMP18:%.*]] = and <16 x i8> [[TMP15]], [[_MSLD1]]8788; CHECK-NEXT: [[TMP19:%.*]] = and <16 x i8> [[TMP14]], [[TMP16]]8789; CHECK-NEXT: [[TMP20:%.*]] = or <16 x i8> [[TMP17]], [[TMP18]]8790; CHECK-NEXT: [[TMP21:%.*]] = or <16 x i8> [[TMP20]], [[TMP19]]8791; CHECK-NEXT: [[TMP5:%.*]] = or <16 x i8> [[TMP3]], [[TMP4]]8792; CHECK-NEXT: store <16 x i8> [[TMP21]], ptr @__msan_retval_tls, align 88793; CHECK-NEXT: ret <16 x i8> [[TMP5]]8794;8795 %tmp1 = load <16 x i8>, ptr %A8796 %tmp4 = load <16 x i8>, ptr %B8797 %tmp3 = shl <16 x i8> %tmp1, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>8798 %tmp5 = or <16 x i8> %tmp3, %tmp48799 ret <16 x i8> %tmp58800}8801 8802define <8 x i16> @shl_orr8h(ptr %A, ptr %B) nounwind sanitize_memory {8803; CHECK-LABEL: define <8 x i16> @shl_orr8h(8804; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {8805; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 88806; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 88807; CHECK-NEXT: call void @llvm.donothing()8808; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 08809; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]8810; CHECK: 3:8811; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8812; CHECK-NEXT: unreachable8813; CHECK: 4:8814; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 168815; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i648816; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885768817; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr8818; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 168819; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 08820; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]8821; CHECK: 8:8822; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8823; CHECK-NEXT: unreachable8824; CHECK: 9:8825; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i16>, ptr [[B]], align 168826; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i648827; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885768828; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr8829; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 168830; CHECK-NEXT: [[TMP13:%.*]] = shl <8 x i16> [[_MSLD]], splat (i16 1)8831; CHECK-NEXT: [[TMP14:%.*]] = or <8 x i16> [[TMP13]], zeroinitializer8832; CHECK-NEXT: [[TMP3:%.*]] = shl <8 x i16> [[TMP1]], splat (i16 1)8833; CHECK-NEXT: [[TMP15:%.*]] = xor <8 x i16> [[TMP3]], splat (i16 -1)8834; CHECK-NEXT: [[TMP16:%.*]] = xor <8 x i16> [[TMP4]], splat (i16 -1)8835; CHECK-NEXT: [[TMP17:%.*]] = and <8 x i16> [[TMP14]], [[_MSLD1]]8836; CHECK-NEXT: [[TMP18:%.*]] = and <8 x i16> [[TMP15]], [[_MSLD1]]8837; CHECK-NEXT: [[TMP19:%.*]] = and <8 x i16> [[TMP14]], [[TMP16]]8838; CHECK-NEXT: [[TMP20:%.*]] = or <8 x i16> [[TMP17]], [[TMP18]]8839; CHECK-NEXT: [[TMP21:%.*]] = or <8 x i16> [[TMP20]], [[TMP19]]8840; CHECK-NEXT: [[TMP5:%.*]] = or <8 x i16> [[TMP3]], [[TMP4]]8841; CHECK-NEXT: store <8 x i16> [[TMP21]], ptr @__msan_retval_tls, align 88842; CHECK-NEXT: ret <8 x i16> [[TMP5]]8843;8844 %tmp1 = load <8 x i16>, ptr %A8845 %tmp4 = load <8 x i16>, ptr %B8846 %tmp3 = shl <8 x i16> %tmp1, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>8847 %tmp5 = or <8 x i16> %tmp3, %tmp48848 ret <8 x i16> %tmp58849}8850 8851define <4 x i32> @shl_orr4s(ptr %A, ptr %B) nounwind sanitize_memory {8852; CHECK-LABEL: define <4 x i32> @shl_orr4s(8853; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {8854; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 88855; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 88856; CHECK-NEXT: call void @llvm.donothing()8857; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 08858; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]8859; CHECK: 3:8860; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8861; CHECK-NEXT: unreachable8862; CHECK: 4:8863; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 168864; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i648865; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885768866; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr8867; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 168868; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 08869; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]8870; CHECK: 8:8871; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8872; CHECK-NEXT: unreachable8873; CHECK: 9:8874; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr [[B]], align 168875; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i648876; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885768877; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr8878; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 168879; CHECK-NEXT: [[TMP13:%.*]] = shl <4 x i32> [[_MSLD]], splat (i32 1)8880; CHECK-NEXT: [[TMP14:%.*]] = or <4 x i32> [[TMP13]], zeroinitializer8881; CHECK-NEXT: [[TMP3:%.*]] = shl <4 x i32> [[TMP1]], splat (i32 1)8882; CHECK-NEXT: [[TMP15:%.*]] = xor <4 x i32> [[TMP3]], splat (i32 -1)8883; CHECK-NEXT: [[TMP16:%.*]] = xor <4 x i32> [[TMP4]], splat (i32 -1)8884; CHECK-NEXT: [[TMP17:%.*]] = and <4 x i32> [[TMP14]], [[_MSLD1]]8885; CHECK-NEXT: [[TMP18:%.*]] = and <4 x i32> [[TMP15]], [[_MSLD1]]8886; CHECK-NEXT: [[TMP19:%.*]] = and <4 x i32> [[TMP14]], [[TMP16]]8887; CHECK-NEXT: [[TMP20:%.*]] = or <4 x i32> [[TMP17]], [[TMP18]]8888; CHECK-NEXT: [[TMP21:%.*]] = or <4 x i32> [[TMP20]], [[TMP19]]8889; CHECK-NEXT: [[TMP5:%.*]] = or <4 x i32> [[TMP3]], [[TMP4]]8890; CHECK-NEXT: store <4 x i32> [[TMP21]], ptr @__msan_retval_tls, align 88891; CHECK-NEXT: ret <4 x i32> [[TMP5]]8892;8893 %tmp1 = load <4 x i32>, ptr %A8894 %tmp4 = load <4 x i32>, ptr %B8895 %tmp3 = shl <4 x i32> %tmp1, <i32 1, i32 1, i32 1, i32 1>8896 %tmp5 = or <4 x i32> %tmp3, %tmp48897 ret <4 x i32> %tmp58898}8899 8900define <2 x i64> @shl_orr2d(ptr %A, ptr %B) nounwind sanitize_memory {8901; CHECK-LABEL: define <2 x i64> @shl_orr2d(8902; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {8903; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 88904; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 88905; CHECK-NEXT: call void @llvm.donothing()8906; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 08907; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]8908; CHECK: 3:8909; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8910; CHECK-NEXT: unreachable8911; CHECK: 4:8912; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 168913; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i648914; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885768915; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr8916; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 168917; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 08918; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]8919; CHECK: 8:8920; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8921; CHECK-NEXT: unreachable8922; CHECK: 9:8923; CHECK-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr [[B]], align 168924; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i648925; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885768926; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr8927; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 168928; CHECK-NEXT: [[TMP13:%.*]] = shl <2 x i64> [[_MSLD]], splat (i64 1)8929; CHECK-NEXT: [[TMP14:%.*]] = or <2 x i64> [[TMP13]], zeroinitializer8930; CHECK-NEXT: [[TMP3:%.*]] = shl <2 x i64> [[TMP1]], splat (i64 1)8931; CHECK-NEXT: [[TMP15:%.*]] = xor <2 x i64> [[TMP3]], splat (i64 -1)8932; CHECK-NEXT: [[TMP16:%.*]] = xor <2 x i64> [[TMP4]], splat (i64 -1)8933; CHECK-NEXT: [[TMP17:%.*]] = and <2 x i64> [[TMP14]], [[_MSLD1]]8934; CHECK-NEXT: [[TMP18:%.*]] = and <2 x i64> [[TMP15]], [[_MSLD1]]8935; CHECK-NEXT: [[TMP19:%.*]] = and <2 x i64> [[TMP14]], [[TMP16]]8936; CHECK-NEXT: [[TMP20:%.*]] = or <2 x i64> [[TMP17]], [[TMP18]]8937; CHECK-NEXT: [[TMP21:%.*]] = or <2 x i64> [[TMP20]], [[TMP19]]8938; CHECK-NEXT: [[TMP5:%.*]] = or <2 x i64> [[TMP3]], [[TMP4]]8939; CHECK-NEXT: store <2 x i64> [[TMP21]], ptr @__msan_retval_tls, align 88940; CHECK-NEXT: ret <2 x i64> [[TMP5]]8941;8942 %tmp1 = load <2 x i64>, ptr %A8943 %tmp4 = load <2 x i64>, ptr %B8944 %tmp3 = shl <2 x i64> %tmp1, <i64 1, i64 1>8945 %tmp5 = or <2 x i64> %tmp3, %tmp48946 ret <2 x i64> %tmp58947}8948 8949define <8 x i16> @shll(<8 x i8> %in) sanitize_memory {8950; CHECK-LABEL: define <8 x i16> @shll(8951; CHECK-SAME: <8 x i8> [[IN:%.*]]) #[[ATTR3:[0-9]+]] {8952; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr @__msan_param_tls, align 88953; CHECK-NEXT: call void @llvm.donothing()8954; CHECK-NEXT: [[_MSPROP:%.*]] = zext <8 x i8> [[TMP1]] to <8 x i16>8955; CHECK-NEXT: [[EXT:%.*]] = zext <8 x i8> [[IN]] to <8 x i16>8956; CHECK-NEXT: [[TMP2:%.*]] = shl <8 x i16> [[_MSPROP]], splat (i16 8)8957; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i16> [[TMP2]], zeroinitializer8958; CHECK-NEXT: [[RES:%.*]] = shl <8 x i16> [[EXT]], splat (i16 8)8959; CHECK-NEXT: store <8 x i16> [[TMP3]], ptr @__msan_retval_tls, align 88960; CHECK-NEXT: ret <8 x i16> [[RES]]8961;8962 %ext = zext <8 x i8> %in to <8 x i16>8963 %res = shl <8 x i16> %ext, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>8964 ret <8 x i16> %res8965}8966 8967define <4 x i32> @shll_high(<8 x i16> %in) sanitize_memory {8968; CHECK-LABEL: define <4 x i32> @shll_high(8969; CHECK-SAME: <8 x i16> [[IN:%.*]]) #[[ATTR3]] {8970; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 88971; CHECK-NEXT: call void @llvm.donothing()8972; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <8 x i16> [[TMP1]], <8 x i16> splat (i16 -1), <4 x i32> <i32 4, i32 5, i32 6, i32 7>8973; CHECK-NEXT: [[EXTRACT:%.*]] = shufflevector <8 x i16> [[IN]], <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>8974; CHECK-NEXT: [[_MSPROP1:%.*]] = zext <4 x i16> [[_MSPROP]] to <4 x i32>8975; CHECK-NEXT: [[EXT:%.*]] = zext <4 x i16> [[EXTRACT]] to <4 x i32>8976; CHECK-NEXT: [[TMP2:%.*]] = shl <4 x i32> [[_MSPROP1]], splat (i32 16)8977; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP2]], zeroinitializer8978; CHECK-NEXT: [[RES:%.*]] = shl <4 x i32> [[EXT]], splat (i32 16)8979; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr @__msan_retval_tls, align 88980; CHECK-NEXT: ret <4 x i32> [[RES]]8981;8982 %extract = shufflevector <8 x i16> %in, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>8983 %ext = zext <4 x i16> %extract to <4 x i32>8984 %res = shl <4 x i32> %ext, <i32 16, i32 16, i32 16, i32 16>8985 ret <4 x i32> %res8986}8987 8988define <8 x i8> @sli8b(ptr %A, ptr %B) nounwind sanitize_memory {8989; CHECK-LABEL: define <8 x i8> @sli8b(8990; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {8991; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 88992; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 88993; CHECK-NEXT: call void @llvm.donothing()8994; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 08995; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]8996; CHECK: 3:8997; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]8998; CHECK-NEXT: unreachable8999; CHECK: 4:9000; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr [[A]], align 89001; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i649002; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885769003; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr9004; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i8>, ptr [[TMP7]], align 89005; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 09006; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]9007; CHECK: 8:9008; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]9009; CHECK-NEXT: unreachable9010; CHECK: 9:9011; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i8>, ptr [[B]], align 89012; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i649013; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885769014; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr9015; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i8>, ptr [[TMP12]], align 89016; CHECK-NEXT: [[TMP13:%.*]] = bitcast <8 x i8> [[_MSLD]] to i649017; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP13]], 09018; CHECK-NEXT: [[TMP14:%.*]] = bitcast <8 x i8> [[_MSLD1]] to i649019; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP14]], 09020; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP3]], [[_MSCMP4]]9021; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP15:%.*]], label [[TMP16:%.*]], !prof [[PROF1]]9022; CHECK: 15:9023; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]9024; CHECK-NEXT: unreachable9025; CHECK: 16:9026; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i8> @llvm.aarch64.neon.vsli.v8i8(<8 x i8> [[TMP1]], <8 x i8> [[TMP2]], i32 1)9027; CHECK-NEXT: store <8 x i8> zeroinitializer, ptr @__msan_retval_tls, align 89028; CHECK-NEXT: ret <8 x i8> [[TMP3]]9029;9030 %tmp1 = load <8 x i8>, ptr %A9031 %tmp2 = load <8 x i8>, ptr %B9032 %tmp3 = call <8 x i8> @llvm.aarch64.neon.vsli.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2, i32 1)9033 ret <8 x i8> %tmp39034}9035 9036define <4 x i16> @sli4h(ptr %A, ptr %B) nounwind sanitize_memory {9037; CHECK-LABEL: define <4 x i16> @sli4h(9038; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {9039; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 89040; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 89041; CHECK-NEXT: call void @llvm.donothing()9042; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 09043; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]9044; CHECK: 3:9045; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]9046; CHECK-NEXT: unreachable9047; CHECK: 4:9048; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr [[A]], align 89049; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i649050; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885769051; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr9052; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i16>, ptr [[TMP7]], align 89053; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 09054; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]9055; CHECK: 8:9056; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]9057; CHECK-NEXT: unreachable9058; CHECK: 9:9059; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i16>, ptr [[B]], align 89060; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i649061; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885769062; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr9063; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i16>, ptr [[TMP12]], align 89064; CHECK-NEXT: [[TMP13:%.*]] = bitcast <4 x i16> [[_MSLD]] to i649065; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP13]], 09066; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i16> [[_MSLD1]] to i649067; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP14]], 09068; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP3]], [[_MSCMP4]]9069; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP15:%.*]], label [[TMP16:%.*]], !prof [[PROF1]]9070; CHECK: 15:9071; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]9072; CHECK-NEXT: unreachable9073; CHECK: 16:9074; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i16> @llvm.aarch64.neon.vsli.v4i16(<4 x i16> [[TMP1]], <4 x i16> [[TMP2]], i32 1)9075; CHECK-NEXT: store <4 x i16> zeroinitializer, ptr @__msan_retval_tls, align 89076; CHECK-NEXT: ret <4 x i16> [[TMP3]]9077;9078 %tmp1 = load <4 x i16>, ptr %A9079 %tmp2 = load <4 x i16>, ptr %B9080 %tmp3 = call <4 x i16> @llvm.aarch64.neon.vsli.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2, i32 1)9081 ret <4 x i16> %tmp39082}9083 9084define <2 x i32> @sli2s(ptr %A, ptr %B) nounwind sanitize_memory {9085; CHECK-LABEL: define <2 x i32> @sli2s(9086; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {9087; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 89088; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 89089; CHECK-NEXT: call void @llvm.donothing()9090; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 09091; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]9092; CHECK: 3:9093; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]9094; CHECK-NEXT: unreachable9095; CHECK: 4:9096; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr [[A]], align 89097; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i649098; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885769099; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr9100; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i32>, ptr [[TMP7]], align 89101; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 09102; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]9103; CHECK: 8:9104; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]9105; CHECK-NEXT: unreachable9106; CHECK: 9:9107; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i32>, ptr [[B]], align 89108; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i649109; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885769110; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr9111; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i32>, ptr [[TMP12]], align 89112; CHECK-NEXT: [[TMP13:%.*]] = bitcast <2 x i32> [[_MSLD]] to i649113; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP13]], 09114; CHECK-NEXT: [[TMP14:%.*]] = bitcast <2 x i32> [[_MSLD1]] to i649115; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP14]], 09116; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP3]], [[_MSCMP4]]9117; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP15:%.*]], label [[TMP16:%.*]], !prof [[PROF1]]9118; CHECK: 15:9119; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]9120; CHECK-NEXT: unreachable9121; CHECK: 16:9122; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i32> @llvm.aarch64.neon.vsli.v2i32(<2 x i32> [[TMP1]], <2 x i32> [[TMP2]], i32 1)9123; CHECK-NEXT: store <2 x i32> zeroinitializer, ptr @__msan_retval_tls, align 89124; CHECK-NEXT: ret <2 x i32> [[TMP3]]9125;9126 %tmp1 = load <2 x i32>, ptr %A9127 %tmp2 = load <2 x i32>, ptr %B9128 %tmp3 = call <2 x i32> @llvm.aarch64.neon.vsli.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2, i32 1)9129 ret <2 x i32> %tmp39130}9131 9132define <1 x i64> @sli1d(ptr %A, ptr %B) nounwind sanitize_memory {9133; CHECK-LABEL: define <1 x i64> @sli1d(9134; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {9135; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 89136; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 89137; CHECK-NEXT: call void @llvm.donothing()9138; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 09139; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]9140; CHECK: 3:9141; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]9142; CHECK-NEXT: unreachable9143; CHECK: 4:9144; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr [[A]], align 89145; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i649146; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885769147; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr9148; CHECK-NEXT: [[_MSLD:%.*]] = load <1 x i64>, ptr [[TMP7]], align 89149; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 09150; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]9151; CHECK: 8:9152; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]9153; CHECK-NEXT: unreachable9154; CHECK: 9:9155; CHECK-NEXT: [[TMP2:%.*]] = load <1 x i64>, ptr [[B]], align 89156; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i649157; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885769158; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr9159; CHECK-NEXT: [[_MSLD1:%.*]] = load <1 x i64>, ptr [[TMP12]], align 89160; CHECK-NEXT: [[TMP13:%.*]] = bitcast <1 x i64> [[_MSLD]] to i649161; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i64 [[TMP13]], 09162; CHECK-NEXT: [[TMP14:%.*]] = bitcast <1 x i64> [[_MSLD1]] to i649163; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i64 [[TMP14]], 09164; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP3]], [[_MSCMP4]]9165; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP15:%.*]], label [[TMP16:%.*]], !prof [[PROF1]]9166; CHECK: 15:9167; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]9168; CHECK-NEXT: unreachable9169; CHECK: 16:9170; CHECK-NEXT: [[TMP3:%.*]] = call <1 x i64> @llvm.aarch64.neon.vsli.v1i64(<1 x i64> [[TMP1]], <1 x i64> [[TMP2]], i32 1)9171; CHECK-NEXT: store <1 x i64> zeroinitializer, ptr @__msan_retval_tls, align 89172; CHECK-NEXT: ret <1 x i64> [[TMP3]]9173;9174 %tmp1 = load <1 x i64>, ptr %A9175 %tmp2 = load <1 x i64>, ptr %B9176 %tmp3 = call <1 x i64> @llvm.aarch64.neon.vsli.v1i64(<1 x i64> %tmp1, <1 x i64> %tmp2, i32 1)9177 ret <1 x i64> %tmp39178}9179 9180define <16 x i8> @sli16b(ptr %A, ptr %B) nounwind sanitize_memory {9181; CHECK-LABEL: define <16 x i8> @sli16b(9182; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {9183; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 89184; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 89185; CHECK-NEXT: call void @llvm.donothing()9186; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 09187; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]9188; CHECK: 3:9189; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]9190; CHECK-NEXT: unreachable9191; CHECK: 4:9192; CHECK-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr [[A]], align 169193; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i649194; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885769195; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr9196; CHECK-NEXT: [[_MSLD:%.*]] = load <16 x i8>, ptr [[TMP7]], align 169197; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 09198; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]9199; CHECK: 8:9200; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]9201; CHECK-NEXT: unreachable9202; CHECK: 9:9203; CHECK-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr [[B]], align 169204; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i649205; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885769206; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr9207; CHECK-NEXT: [[_MSLD1:%.*]] = load <16 x i8>, ptr [[TMP12]], align 169208; CHECK-NEXT: [[TMP13:%.*]] = bitcast <16 x i8> [[_MSLD]] to i1289209; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP13]], 09210; CHECK-NEXT: [[TMP14:%.*]] = bitcast <16 x i8> [[_MSLD1]] to i1289211; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP14]], 09212; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP3]], [[_MSCMP4]]9213; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP15:%.*]], label [[TMP16:%.*]], !prof [[PROF1]]9214; CHECK: 15:9215; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]9216; CHECK-NEXT: unreachable9217; CHECK: 16:9218; CHECK-NEXT: [[TMP3:%.*]] = call <16 x i8> @llvm.aarch64.neon.vsli.v16i8(<16 x i8> [[TMP1]], <16 x i8> [[TMP2]], i32 1)9219; CHECK-NEXT: store <16 x i8> zeroinitializer, ptr @__msan_retval_tls, align 89220; CHECK-NEXT: ret <16 x i8> [[TMP3]]9221;9222 %tmp1 = load <16 x i8>, ptr %A9223 %tmp2 = load <16 x i8>, ptr %B9224 %tmp3 = call <16 x i8> @llvm.aarch64.neon.vsli.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2, i32 1)9225 ret <16 x i8> %tmp39226}9227 9228define <8 x i16> @sli8h(ptr %A, ptr %B) nounwind sanitize_memory {9229; CHECK-LABEL: define <8 x i16> @sli8h(9230; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {9231; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 89232; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 89233; CHECK-NEXT: call void @llvm.donothing()9234; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 09235; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]9236; CHECK: 3:9237; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]9238; CHECK-NEXT: unreachable9239; CHECK: 4:9240; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr [[A]], align 169241; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i649242; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885769243; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr9244; CHECK-NEXT: [[_MSLD:%.*]] = load <8 x i16>, ptr [[TMP7]], align 169245; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 09246; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]9247; CHECK: 8:9248; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]9249; CHECK-NEXT: unreachable9250; CHECK: 9:9251; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr [[B]], align 169252; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i649253; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885769254; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr9255; CHECK-NEXT: [[_MSLD1:%.*]] = load <8 x i16>, ptr [[TMP12]], align 169256; CHECK-NEXT: [[TMP13:%.*]] = bitcast <8 x i16> [[_MSLD]] to i1289257; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP13]], 09258; CHECK-NEXT: [[TMP14:%.*]] = bitcast <8 x i16> [[_MSLD1]] to i1289259; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP14]], 09260; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP3]], [[_MSCMP4]]9261; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP15:%.*]], label [[TMP16:%.*]], !prof [[PROF1]]9262; CHECK: 15:9263; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]9264; CHECK-NEXT: unreachable9265; CHECK: 16:9266; CHECK-NEXT: [[TMP3:%.*]] = call <8 x i16> @llvm.aarch64.neon.vsli.v8i16(<8 x i16> [[TMP1]], <8 x i16> [[TMP2]], i32 1)9267; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr @__msan_retval_tls, align 89268; CHECK-NEXT: ret <8 x i16> [[TMP3]]9269;9270 %tmp1 = load <8 x i16>, ptr %A9271 %tmp2 = load <8 x i16>, ptr %B9272 %tmp3 = call <8 x i16> @llvm.aarch64.neon.vsli.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2, i32 1)9273 ret <8 x i16> %tmp39274}9275 9276define <4 x i32> @sli4s(ptr %A, ptr %B) nounwind sanitize_memory {9277; CHECK-LABEL: define <4 x i32> @sli4s(9278; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {9279; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 89280; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 89281; CHECK-NEXT: call void @llvm.donothing()9282; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 09283; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]9284; CHECK: 3:9285; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]9286; CHECK-NEXT: unreachable9287; CHECK: 4:9288; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr [[A]], align 169289; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i649290; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885769291; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr9292; CHECK-NEXT: [[_MSLD:%.*]] = load <4 x i32>, ptr [[TMP7]], align 169293; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 09294; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]9295; CHECK: 8:9296; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]9297; CHECK-NEXT: unreachable9298; CHECK: 9:9299; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr [[B]], align 169300; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i649301; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885769302; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr9303; CHECK-NEXT: [[_MSLD1:%.*]] = load <4 x i32>, ptr [[TMP12]], align 169304; CHECK-NEXT: [[TMP13:%.*]] = bitcast <4 x i32> [[_MSLD]] to i1289305; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP13]], 09306; CHECK-NEXT: [[TMP14:%.*]] = bitcast <4 x i32> [[_MSLD1]] to i1289307; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP14]], 09308; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP3]], [[_MSCMP4]]9309; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP15:%.*]], label [[TMP16:%.*]], !prof [[PROF1]]9310; CHECK: 15:9311; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]9312; CHECK-NEXT: unreachable9313; CHECK: 16:9314; CHECK-NEXT: [[TMP3:%.*]] = call <4 x i32> @llvm.aarch64.neon.vsli.v4i32(<4 x i32> [[TMP1]], <4 x i32> [[TMP2]], i32 1)9315; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr @__msan_retval_tls, align 89316; CHECK-NEXT: ret <4 x i32> [[TMP3]]9317;9318 %tmp1 = load <4 x i32>, ptr %A9319 %tmp2 = load <4 x i32>, ptr %B9320 %tmp3 = call <4 x i32> @llvm.aarch64.neon.vsli.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2, i32 1)9321 ret <4 x i32> %tmp39322}9323 9324define <2 x i64> @sli2d(ptr %A, ptr %B) nounwind sanitize_memory {9325; CHECK-LABEL: define <2 x i64> @sli2d(9326; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] {9327; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 89328; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 89329; CHECK-NEXT: call void @llvm.donothing()9330; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP1]], 09331; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP3:%.*]], label [[TMP4:%.*]], !prof [[PROF1]]9332; CHECK: 3:9333; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]9334; CHECK-NEXT: unreachable9335; CHECK: 4:9336; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[A]], align 169337; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[A]] to i649338; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885769339; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr9340; CHECK-NEXT: [[_MSLD:%.*]] = load <2 x i64>, ptr [[TMP7]], align 169341; CHECK-NEXT: [[_MSCMP2:%.*]] = icmp ne i64 [[TMP2]], 09342; CHECK-NEXT: br i1 [[_MSCMP2]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]9343; CHECK: 8:9344; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]9345; CHECK-NEXT: unreachable9346; CHECK: 9:9347; CHECK-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr [[B]], align 169348; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i649349; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 1935140464885769350; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr9351; CHECK-NEXT: [[_MSLD1:%.*]] = load <2 x i64>, ptr [[TMP12]], align 169352; CHECK-NEXT: [[TMP13:%.*]] = bitcast <2 x i64> [[_MSLD]] to i1289353; CHECK-NEXT: [[_MSCMP3:%.*]] = icmp ne i128 [[TMP13]], 09354; CHECK-NEXT: [[TMP14:%.*]] = bitcast <2 x i64> [[_MSLD1]] to i1289355; CHECK-NEXT: [[_MSCMP4:%.*]] = icmp ne i128 [[TMP14]], 09356; CHECK-NEXT: [[_MSOR:%.*]] = or i1 [[_MSCMP3]], [[_MSCMP4]]9357; CHECK-NEXT: br i1 [[_MSOR]], label [[TMP15:%.*]], label [[TMP16:%.*]], !prof [[PROF1]]9358; CHECK: 15:9359; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]9360; CHECK-NEXT: unreachable9361; CHECK: 16:9362; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.vsli.v2i64(<2 x i64> [[TMP1]], <2 x i64> [[TMP2]], i32 1)9363; CHECK-NEXT: store <2 x i64> zeroinitializer, ptr @__msan_retval_tls, align 89364; CHECK-NEXT: ret <2 x i64> [[TMP3]]9365;9366 %tmp1 = load <2 x i64>, ptr %A9367 %tmp2 = load <2 x i64>, ptr %B9368 %tmp3 = call <2 x i64> @llvm.aarch64.neon.vsli.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, i32 1)9369 ret <2 x i64> %tmp39370}9371 9372declare <8 x i8> @llvm.aarch64.neon.vsli.v8i8(<8 x i8>, <8 x i8>, i32) nounwind readnone9373declare <4 x i16> @llvm.aarch64.neon.vsli.v4i16(<4 x i16>, <4 x i16>, i32) nounwind readnone9374declare <2 x i32> @llvm.aarch64.neon.vsli.v2i32(<2 x i32>, <2 x i32>, i32) nounwind readnone9375declare <1 x i64> @llvm.aarch64.neon.vsli.v1i64(<1 x i64>, <1 x i64>, i32) nounwind readnone9376 9377declare <16 x i8> @llvm.aarch64.neon.vsli.v16i8(<16 x i8>, <16 x i8>, i32) nounwind readnone9378declare <8 x i16> @llvm.aarch64.neon.vsli.v8i16(<8 x i16>, <8 x i16>, i32) nounwind readnone9379declare <4 x i32> @llvm.aarch64.neon.vsli.v4i32(<4 x i32>, <4 x i32>, i32) nounwind readnone9380declare <2 x i64> @llvm.aarch64.neon.vsli.v2i64(<2 x i64>, <2 x i64>, i32) nounwind readnone9381 9382define <1 x i64> @ashr_v1i64(<1 x i64> %a, <1 x i64> %b) sanitize_memory {9383; CHECK-LABEL: define <1 x i64> @ashr_v1i64(9384; CHECK-SAME: <1 x i64> [[A:%.*]], <1 x i64> [[B:%.*]]) #[[ATTR3]] {9385; CHECK-NEXT: [[TMP1:%.*]] = load <1 x i64>, ptr @__msan_param_tls, align 89386; CHECK-NEXT: [[TMP2:%.*]] = load <1 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 8), align 89387; CHECK-NEXT: call void @llvm.donothing()9388; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <1 x i64> [[TMP2]], zeroinitializer9389; CHECK-NEXT: [[TMP4:%.*]] = sext <1 x i1> [[TMP3]] to <1 x i64>9390; CHECK-NEXT: [[TMP5:%.*]] = ashr <1 x i64> [[TMP1]], [[B]]9391; CHECK-NEXT: [[TMP6:%.*]] = or <1 x i64> [[TMP5]], [[TMP4]]9392; CHECK-NEXT: [[C:%.*]] = ashr <1 x i64> [[A]], [[B]]9393; CHECK-NEXT: store <1 x i64> [[TMP6]], ptr @__msan_retval_tls, align 89394; CHECK-NEXT: ret <1 x i64> [[C]]9395;9396 %c = ashr <1 x i64> %a, %b9397 ret <1 x i64> %c9398}9399 9400define void @sqshl_zero_shift_amount(<2 x i64> %a, <2 x i64> %b, ptr %dst) sanitize_memory {9401; CHECK-LABEL: define void @sqshl_zero_shift_amount(9402; CHECK-SAME: <2 x i64> [[A:%.*]], <2 x i64> [[B:%.*]], ptr [[DST:%.*]]) #[[ATTR3]] {9403; CHECK-NEXT: entry:9404; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 89405; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 89406; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 89407; CHECK-NEXT: call void @llvm.donothing()9408; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> [[TMP1]], <2 x i32> <i32 0, i32 2>9409; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> [[TMP1]], <2 x i32> <i32 1, i32 3>9410; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP10]], [[TMP4]]9411; CHECK-NEXT: [[VPADDQ_V2_I_I:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> [[A]], <2 x i64> [[B]])9412; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqshl.v2i64(<2 x i64> [[_MSPROP]], <2 x i64> zeroinitializer)9413; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> [[TMP3]], zeroinitializer9414; CHECK-NEXT: [[VSHLQ_V2_I_I:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.sqshl.v2i64(<2 x i64> [[VPADDQ_V2_I_I]], <2 x i64> zeroinitializer)9415; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 09416; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]9417; CHECK: 8:9418; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]9419; CHECK-NEXT: unreachable9420; CHECK: 9:9421; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[DST]] to i649422; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885769423; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr9424; CHECK-NEXT: store <2 x i64> [[_MSPROP1]], ptr [[TMP7]], align 89425; CHECK-NEXT: store <2 x i64> [[VSHLQ_V2_I_I]], ptr [[DST]], align 89426; CHECK-NEXT: ret void9427;9428entry:9429 %vpaddq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> %a, <2 x i64> %b)9430 %vshlq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.sqshl.v2i64(<2 x i64> %vpaddq_v2.i.i, <2 x i64> zeroinitializer)9431 store <2 x i64> %vshlq_v2.i.i, ptr %dst, align 89432 ret void9433}9434 9435define void @uqshl_zero_shift_amount(<2 x i64> %a, <2 x i64> %b, ptr %dst) sanitize_memory {9436; CHECK-LABEL: define void @uqshl_zero_shift_amount(9437; CHECK-SAME: <2 x i64> [[A:%.*]], <2 x i64> [[B:%.*]], ptr [[DST:%.*]]) #[[ATTR3]] {9438; CHECK-NEXT: entry:9439; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 89440; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 89441; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 89442; CHECK-NEXT: call void @llvm.donothing()9443; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> [[TMP1]], <2 x i32> <i32 0, i32 2>9444; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> [[TMP1]], <2 x i32> <i32 1, i32 3>9445; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP10]], [[TMP4]]9446; CHECK-NEXT: [[VPADDQ_V2_I_I:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> [[A]], <2 x i64> [[B]])9447; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64> [[_MSPROP]], <2 x i64> zeroinitializer)9448; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> [[TMP3]], zeroinitializer9449; CHECK-NEXT: [[VSHLQ_V2_I_I:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64> [[VPADDQ_V2_I_I]], <2 x i64> zeroinitializer)9450; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 09451; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]9452; CHECK: 8:9453; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]9454; CHECK-NEXT: unreachable9455; CHECK: 9:9456; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[DST]] to i649457; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885769458; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr9459; CHECK-NEXT: store <2 x i64> [[_MSPROP1]], ptr [[TMP7]], align 89460; CHECK-NEXT: store <2 x i64> [[VSHLQ_V2_I_I]], ptr [[DST]], align 89461; CHECK-NEXT: ret void9462;9463entry:9464 %vpaddq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> %a, <2 x i64> %b)9465 %vshlq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64> %vpaddq_v2.i.i, <2 x i64> zeroinitializer)9466 store <2 x i64> %vshlq_v2.i.i, ptr %dst, align 89467 ret void9468}9469 9470define void @srshl_zero_shift_amount(<2 x i64> %a, <2 x i64> %b, ptr %dst) sanitize_memory {9471; CHECK-LABEL: define void @srshl_zero_shift_amount(9472; CHECK-SAME: <2 x i64> [[A:%.*]], <2 x i64> [[B:%.*]], ptr [[DST:%.*]]) #[[ATTR3]] {9473; CHECK-NEXT: entry:9474; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 89475; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 89476; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 89477; CHECK-NEXT: call void @llvm.donothing()9478; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> [[TMP1]], <2 x i32> <i32 0, i32 2>9479; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> [[TMP1]], <2 x i32> <i32 1, i32 3>9480; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP10]], [[TMP4]]9481; CHECK-NEXT: [[VPADDQ_V2_I_I:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> [[A]], <2 x i64> [[B]])9482; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> [[_MSPROP]], <2 x i64> zeroinitializer)9483; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> [[TMP3]], zeroinitializer9484; CHECK-NEXT: [[VSHLQ_V2_I_I:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> [[VPADDQ_V2_I_I]], <2 x i64> zeroinitializer)9485; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 09486; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]9487; CHECK: 8:9488; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]9489; CHECK-NEXT: unreachable9490; CHECK: 9:9491; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[DST]] to i649492; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885769493; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr9494; CHECK-NEXT: store <2 x i64> [[_MSPROP1]], ptr [[TMP7]], align 89495; CHECK-NEXT: store <2 x i64> [[VSHLQ_V2_I_I]], ptr [[DST]], align 89496; CHECK-NEXT: ret void9497;9498entry:9499 %vpaddq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> %a, <2 x i64> %b)9500 %vshlq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.srshl.v2i64(<2 x i64> %vpaddq_v2.i.i, <2 x i64> zeroinitializer)9501 store <2 x i64> %vshlq_v2.i.i, ptr %dst, align 89502 ret void9503}9504 9505define void @urshl_zero_shift_amount(<2 x i64> %a, <2 x i64> %b, ptr %dst) sanitize_memory {9506; CHECK-LABEL: define void @urshl_zero_shift_amount(9507; CHECK-SAME: <2 x i64> [[A:%.*]], <2 x i64> [[B:%.*]], ptr [[DST:%.*]]) #[[ATTR3]] {9508; CHECK-NEXT: entry:9509; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 89510; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 89511; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 89512; CHECK-NEXT: call void @llvm.donothing()9513; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> [[TMP1]], <2 x i32> <i32 0, i32 2>9514; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> [[TMP1]], <2 x i32> <i32 1, i32 3>9515; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP10]], [[TMP4]]9516; CHECK-NEXT: [[VPADDQ_V2_I_I:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> [[A]], <2 x i64> [[B]])9517; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> [[_MSPROP]], <2 x i64> zeroinitializer)9518; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> [[TMP3]], zeroinitializer9519; CHECK-NEXT: [[VSHLQ_V2_I_I:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> [[VPADDQ_V2_I_I]], <2 x i64> zeroinitializer)9520; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 09521; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]9522; CHECK: 8:9523; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]9524; CHECK-NEXT: unreachable9525; CHECK: 9:9526; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[DST]] to i649527; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885769528; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr9529; CHECK-NEXT: store <2 x i64> [[_MSPROP1]], ptr [[TMP7]], align 89530; CHECK-NEXT: store <2 x i64> [[VSHLQ_V2_I_I]], ptr [[DST]], align 89531; CHECK-NEXT: ret void9532;9533entry:9534 %vpaddq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> %a, <2 x i64> %b)9535 %vshlq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.urshl.v2i64(<2 x i64> %vpaddq_v2.i.i, <2 x i64> zeroinitializer)9536 store <2 x i64> %vshlq_v2.i.i, ptr %dst, align 89537 ret void9538}9539 9540define void @sqshlu_zero_shift_amount(<2 x i64> %a, <2 x i64> %b, ptr %dst) sanitize_memory {9541; CHECK-LABEL: define void @sqshlu_zero_shift_amount(9542; CHECK-SAME: <2 x i64> [[A:%.*]], <2 x i64> [[B:%.*]], ptr [[DST:%.*]]) #[[ATTR3]] {9543; CHECK-NEXT: entry:9544; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 89545; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 89546; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 89547; CHECK-NEXT: call void @llvm.donothing()9548; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> [[TMP1]], <2 x i32> <i32 0, i32 2>9549; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> [[TMP1]], <2 x i32> <i32 1, i32 3>9550; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP10]], [[TMP4]]9551; CHECK-NEXT: [[VPADDQ_V2_I_I:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> [[A]], <2 x i64> [[B]])9552; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqshlu.v2i64(<2 x i64> [[_MSPROP]], <2 x i64> zeroinitializer)9553; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> [[TMP3]], zeroinitializer9554; CHECK-NEXT: [[VSHLQ_V2_I_I:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.sqshlu.v2i64(<2 x i64> [[VPADDQ_V2_I_I]], <2 x i64> zeroinitializer)9555; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 09556; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]9557; CHECK: 8:9558; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]9559; CHECK-NEXT: unreachable9560; CHECK: 9:9561; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[DST]] to i649562; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885769563; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr9564; CHECK-NEXT: store <2 x i64> [[_MSPROP1]], ptr [[TMP7]], align 89565; CHECK-NEXT: store <2 x i64> [[VSHLQ_V2_I_I]], ptr [[DST]], align 89566; CHECK-NEXT: ret void9567;9568entry:9569 %vpaddq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> %a, <2 x i64> %b)9570 %vshlq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.sqshlu.v2i64(<2 x i64> %vpaddq_v2.i.i, <2 x i64> zeroinitializer)9571 store <2 x i64> %vshlq_v2.i.i, ptr %dst, align 89572 ret void9573}9574 9575define void @sshl_zero_shift_amount(<2 x i64> %a, <2 x i64> %b, ptr %dst) sanitize_memory {9576; CHECK-LABEL: define void @sshl_zero_shift_amount(9577; CHECK-SAME: <2 x i64> [[A:%.*]], <2 x i64> [[B:%.*]], ptr [[DST:%.*]]) #[[ATTR3]] {9578; CHECK-NEXT: entry:9579; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 89580; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 89581; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 89582; CHECK-NEXT: call void @llvm.donothing()9583; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> [[TMP1]], <2 x i32> <i32 0, i32 2>9584; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> [[TMP1]], <2 x i32> <i32 1, i32 3>9585; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP10]], [[TMP4]]9586; CHECK-NEXT: [[VPADDQ_V2_I_I:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> [[A]], <2 x i64> [[B]])9587; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.sshl.v2i64(<2 x i64> [[_MSPROP]], <2 x i64> zeroinitializer)9588; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> [[TMP3]], zeroinitializer9589; CHECK-NEXT: [[VSHLQ_V2_I_I:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.sshl.v2i64(<2 x i64> [[VPADDQ_V2_I_I]], <2 x i64> zeroinitializer)9590; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 09591; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]9592; CHECK: 8:9593; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]9594; CHECK-NEXT: unreachable9595; CHECK: 9:9596; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[DST]] to i649597; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885769598; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr9599; CHECK-NEXT: store <2 x i64> [[_MSPROP1]], ptr [[TMP7]], align 89600; CHECK-NEXT: store <2 x i64> [[VSHLQ_V2_I_I]], ptr [[DST]], align 89601; CHECK-NEXT: ret void9602;9603entry:9604 %vpaddq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> %a, <2 x i64> %b)9605 %vshlq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.sshl.v2i64(<2 x i64> %vpaddq_v2.i.i, <2 x i64> zeroinitializer)9606 store <2 x i64> %vshlq_v2.i.i, ptr %dst, align 89607 ret void9608}9609 9610define void @ushl_zero_shift_amount(<2 x i64> %a, <2 x i64> %b, ptr %dst) sanitize_memory {9611; CHECK-LABEL: define void @ushl_zero_shift_amount(9612; CHECK-SAME: <2 x i64> [[A:%.*]], <2 x i64> [[B:%.*]], ptr [[DST:%.*]]) #[[ATTR3]] {9613; CHECK-NEXT: entry:9614; CHECK-NEXT: [[TMP0:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 89615; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr getelementptr (i8, ptr @__msan_param_tls, i64 16), align 89616; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr getelementptr (i8, ptr @__msan_param_tls, i64 32), align 89617; CHECK-NEXT: call void @llvm.donothing()9618; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> [[TMP1]], <2 x i32> <i32 0, i32 2>9619; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <2 x i64> [[TMP0]], <2 x i64> [[TMP1]], <2 x i32> <i32 1, i32 3>9620; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP10]], [[TMP4]]9621; CHECK-NEXT: [[VPADDQ_V2_I_I:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> [[A]], <2 x i64> [[B]])9622; CHECK-NEXT: [[TMP3:%.*]] = call <2 x i64> @llvm.aarch64.neon.ushl.v2i64(<2 x i64> [[_MSPROP]], <2 x i64> zeroinitializer)9623; CHECK-NEXT: [[_MSPROP1:%.*]] = or <2 x i64> [[TMP3]], zeroinitializer9624; CHECK-NEXT: [[VSHLQ_V2_I_I:%.*]] = tail call <2 x i64> @llvm.aarch64.neon.ushl.v2i64(<2 x i64> [[VPADDQ_V2_I_I]], <2 x i64> zeroinitializer)9625; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i64 [[TMP2]], 09626; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP8:%.*]], label [[TMP9:%.*]], !prof [[PROF1]]9627; CHECK: 8:9628; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR5]]9629; CHECK-NEXT: unreachable9630; CHECK: 9:9631; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[DST]] to i649632; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 1935140464885769633; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr9634; CHECK-NEXT: store <2 x i64> [[_MSPROP1]], ptr [[TMP7]], align 89635; CHECK-NEXT: store <2 x i64> [[VSHLQ_V2_I_I]], ptr [[DST]], align 89636; CHECK-NEXT: ret void9637;9638entry:9639 %vpaddq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64> %a, <2 x i64> %b)9640 %vshlq_v2.i.i = tail call <2 x i64> @llvm.aarch64.neon.ushl.v2i64(<2 x i64> %vpaddq_v2.i.i, <2 x i64> zeroinitializer)9641 store <2 x i64> %vshlq_v2.i.i, ptr %dst, align 89642 ret void9643}9644 9645define <4 x i32> @sext_rshrn(<4 x i32> noundef %a) sanitize_memory {9646; CHECK-LABEL: define <4 x i32> @sext_rshrn(9647; CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR3]] {9648; CHECK-NEXT: entry:9649; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 89650; CHECK-NEXT: call void @llvm.donothing()9651; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> [[TMP0]], i32 13)9652; CHECK-NEXT: [[TMP2:%.*]] = or <4 x i16> [[TMP1]], zeroinitializer9653; CHECK-NEXT: [[VRSHRN_N1:%.*]] = tail call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> [[A]], i32 13)9654; CHECK-NEXT: [[_MSPROP:%.*]] = sext <4 x i16> [[TMP2]] to <4 x i32>9655; CHECK-NEXT: [[VMOVL_I:%.*]] = sext <4 x i16> [[VRSHRN_N1]] to <4 x i32>9656; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 89657; CHECK-NEXT: ret <4 x i32> [[VMOVL_I]]9658;9659entry:9660 %vrshrn_n1 = tail call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> %a, i32 13)9661 %vmovl.i = sext <4 x i16> %vrshrn_n1 to <4 x i32>9662 ret <4 x i32> %vmovl.i9663}9664 9665define <4 x i32> @zext_rshrn(<4 x i32> noundef %a) sanitize_memory {9666; CHECK-LABEL: define <4 x i32> @zext_rshrn(9667; CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR3]] {9668; CHECK-NEXT: entry:9669; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 89670; CHECK-NEXT: call void @llvm.donothing()9671; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> [[TMP0]], i32 13)9672; CHECK-NEXT: [[TMP2:%.*]] = or <4 x i16> [[TMP1]], zeroinitializer9673; CHECK-NEXT: [[VRSHRN_N1:%.*]] = tail call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> [[A]], i32 13)9674; CHECK-NEXT: [[_MSPROP:%.*]] = zext <4 x i16> [[TMP2]] to <4 x i32>9675; CHECK-NEXT: [[VMOVL_I:%.*]] = zext <4 x i16> [[VRSHRN_N1]] to <4 x i32>9676; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 89677; CHECK-NEXT: ret <4 x i32> [[VMOVL_I]]9678;9679entry:9680 %vrshrn_n1 = tail call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> %a, i32 13)9681 %vmovl.i = zext <4 x i16> %vrshrn_n1 to <4 x i32>9682 ret <4 x i32> %vmovl.i9683}9684 9685define <4 x i16> @mul_rshrn(<4 x i32> noundef %a) sanitize_memory {9686; CHECK-LABEL: define <4 x i16> @mul_rshrn(9687; CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR3]] {9688; CHECK-NEXT: entry:9689; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 89690; CHECK-NEXT: call void @llvm.donothing()9691; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP0]], zeroinitializer9692; CHECK-NEXT: [[B:%.*]] = add <4 x i32> [[A]], splat (i32 3)9693; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> [[_MSPROP]], i32 13)9694; CHECK-NEXT: [[TMP2:%.*]] = or <4 x i16> [[TMP1]], zeroinitializer9695; CHECK-NEXT: [[VRSHRN_N1:%.*]] = tail call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> [[B]], i32 13)9696; CHECK-NEXT: store <4 x i16> [[TMP2]], ptr @__msan_retval_tls, align 89697; CHECK-NEXT: ret <4 x i16> [[VRSHRN_N1]]9698;9699entry:9700 %b = add <4 x i32> %a, <i32 3, i32 3, i32 3, i32 3>9701 %vrshrn_n1 = tail call <4 x i16> @llvm.aarch64.neon.rshrn.v4i16(<4 x i32> %b, i32 13)9702 ret <4 x i16> %vrshrn_n19703}9704 9705declare <2 x i64> @llvm.aarch64.neon.addp.v2i64(<2 x i64>, <2 x i64>)9706;.9707; CHECK: [[PROF1]] = !{!"branch_weights", i32 1, i32 1048575}9708;.9709