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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 42; RUN: opt < %s -passes=msan -S | FileCheck %s3;4; Forked from llvm/test/CodeGen/AArch64/qshrn.ll5;6; Heuristically (but correctly) handled: llvm.smax, llvm.smin, llvm.umin7 8target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"9target triple = "aarch64--linux-android9001"10 11define <4 x i16> @NarrowAShrI32By5(<4 x i32> %x) #0 {12; CHECK-LABEL: define <4 x i16> @NarrowAShrI32By5(13; CHECK-SAME: <4 x i32> [[X:%.*]]) #[[ATTR0:[0-9]+]] {14; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 815; CHECK-NEXT: call void @llvm.donothing()16; CHECK-NEXT: [[TMP2:%.*]] = ashr <4 x i32> [[TMP1]], splat (i32 5)17; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP2]], zeroinitializer18; CHECK-NEXT: [[S:%.*]] = ashr <4 x i32> [[X]], splat (i32 5)19; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP3]], zeroinitializer20; CHECK-NEXT: [[TMP6:%.*]] = trunc <4 x i32> [[_MSPROP]] to <4 x i16>21; CHECK-NEXT: [[R:%.*]] = tail call <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32> [[S]])22; CHECK-NEXT: store <4 x i16> [[TMP6]], ptr @__msan_retval_tls, align 823; CHECK-NEXT: ret <4 x i16> [[R]]24;25 %s = ashr <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>26 %r = tail call <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32> %s)27 ret <4 x i16> %r28}29 30define <4 x i16> @NarrowAShrU32By5(<4 x i32> %x) #0 {31; CHECK-LABEL: define <4 x i16> @NarrowAShrU32By5(32; CHECK-SAME: <4 x i32> [[X:%.*]]) #[[ATTR0]] {33; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 834; CHECK-NEXT: call void @llvm.donothing()35; CHECK-NEXT: [[TMP2:%.*]] = ashr <4 x i32> [[TMP1]], splat (i32 5)36; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP2]], zeroinitializer37; CHECK-NEXT: [[S:%.*]] = ashr <4 x i32> [[X]], splat (i32 5)38; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP3]], zeroinitializer39; CHECK-NEXT: [[TMP6:%.*]] = trunc <4 x i32> [[_MSPROP]] to <4 x i16>40; CHECK-NEXT: [[R:%.*]] = tail call <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32> [[S]])41; CHECK-NEXT: store <4 x i16> [[TMP6]], ptr @__msan_retval_tls, align 842; CHECK-NEXT: ret <4 x i16> [[R]]43;44 %s = ashr <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>45 %r = tail call <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32> %s)46 ret <4 x i16> %r47}48 49define <4 x i16> @NarrowAShrI32By5ToU16(<4 x i32> %x) #0 {50; CHECK-LABEL: define <4 x i16> @NarrowAShrI32By5ToU16(51; CHECK-SAME: <4 x i32> [[X:%.*]]) #[[ATTR0]] {52; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 853; CHECK-NEXT: call void @llvm.donothing()54; CHECK-NEXT: [[TMP2:%.*]] = ashr <4 x i32> [[TMP1]], splat (i32 5)55; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP2]], zeroinitializer56; CHECK-NEXT: [[S:%.*]] = ashr <4 x i32> [[X]], splat (i32 5)57; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP3]], zeroinitializer58; CHECK-NEXT: [[TMP6:%.*]] = trunc <4 x i32> [[_MSPROP]] to <4 x i16>59; CHECK-NEXT: [[R:%.*]] = tail call <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32> [[S]])60; CHECK-NEXT: store <4 x i16> [[TMP6]], ptr @__msan_retval_tls, align 861; CHECK-NEXT: ret <4 x i16> [[R]]62;63 %s = ashr <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>64 %r = tail call <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32> %s)65 ret <4 x i16> %r66}67 68define <4 x i16> @NarrowLShrI32By5(<4 x i32> %x) #0 {69; CHECK-LABEL: define <4 x i16> @NarrowLShrI32By5(70; CHECK-SAME: <4 x i32> [[X:%.*]]) #[[ATTR0]] {71; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 872; CHECK-NEXT: call void @llvm.donothing()73; CHECK-NEXT: [[TMP2:%.*]] = lshr <4 x i32> [[TMP1]], splat (i32 5)74; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP2]], zeroinitializer75; CHECK-NEXT: [[S:%.*]] = lshr <4 x i32> [[X]], splat (i32 5)76; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP3]], zeroinitializer77; CHECK-NEXT: [[TMP6:%.*]] = trunc <4 x i32> [[_MSPROP]] to <4 x i16>78; CHECK-NEXT: [[R:%.*]] = tail call <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32> [[S]])79; CHECK-NEXT: store <4 x i16> [[TMP6]], ptr @__msan_retval_tls, align 880; CHECK-NEXT: ret <4 x i16> [[R]]81;82 %s = lshr <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>83 %r = tail call <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32> %s)84 ret <4 x i16> %r85}86 87define <4 x i16> @NarrowLShrU32By5(<4 x i32> %x) #0 {88; CHECK-LABEL: define <4 x i16> @NarrowLShrU32By5(89; CHECK-SAME: <4 x i32> [[X:%.*]]) #[[ATTR0]] {90; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 891; CHECK-NEXT: call void @llvm.donothing()92; CHECK-NEXT: [[TMP2:%.*]] = lshr <4 x i32> [[TMP1]], splat (i32 5)93; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP2]], zeroinitializer94; CHECK-NEXT: [[S:%.*]] = lshr <4 x i32> [[X]], splat (i32 5)95; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP3]], zeroinitializer96; CHECK-NEXT: [[TMP6:%.*]] = trunc <4 x i32> [[_MSPROP]] to <4 x i16>97; CHECK-NEXT: [[R:%.*]] = tail call <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32> [[S]])98; CHECK-NEXT: store <4 x i16> [[TMP6]], ptr @__msan_retval_tls, align 899; CHECK-NEXT: ret <4 x i16> [[R]]100;101 %s = lshr <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>102 %r = tail call <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32> %s)103 ret <4 x i16> %r104}105 106define <4 x i16> @NarrowLShrI32By5ToU16(<4 x i32> %x) #0 {107; CHECK-LABEL: define <4 x i16> @NarrowLShrI32By5ToU16(108; CHECK-SAME: <4 x i32> [[X:%.*]]) #[[ATTR0]] {109; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8110; CHECK-NEXT: call void @llvm.donothing()111; CHECK-NEXT: [[TMP2:%.*]] = lshr <4 x i32> [[TMP1]], splat (i32 5)112; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP2]], zeroinitializer113; CHECK-NEXT: [[S:%.*]] = lshr <4 x i32> [[X]], splat (i32 5)114; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP3]], zeroinitializer115; CHECK-NEXT: [[TMP6:%.*]] = trunc <4 x i32> [[_MSPROP]] to <4 x i16>116; CHECK-NEXT: [[R:%.*]] = tail call <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32> [[S]])117; CHECK-NEXT: store <4 x i16> [[TMP6]], ptr @__msan_retval_tls, align 8118; CHECK-NEXT: ret <4 x i16> [[R]]119;120 %s = lshr <4 x i32> %x, <i32 5, i32 5, i32 5, i32 5>121 %r = tail call <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32> %s)122 ret <4 x i16> %r123}124 125 126define <2 x i32> @NarrowAShri64By5(<2 x i64> %x) #0 {127; CHECK-LABEL: define <2 x i32> @NarrowAShri64By5(128; CHECK-SAME: <2 x i64> [[X:%.*]]) #[[ATTR0]] {129; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8130; CHECK-NEXT: call void @llvm.donothing()131; CHECK-NEXT: [[TMP2:%.*]] = ashr <2 x i64> [[TMP1]], splat (i64 5)132; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP2]], zeroinitializer133; CHECK-NEXT: [[S:%.*]] = ashr <2 x i64> [[X]], splat (i64 5)134; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP3]], zeroinitializer135; CHECK-NEXT: [[TMP5:%.*]] = trunc <2 x i64> [[_MSPROP]] to <2 x i32>136; CHECK-NEXT: [[R:%.*]] = tail call <2 x i32> @llvm.aarch64.neon.sqxtn.v2i32(<2 x i64> [[S]])137; CHECK-NEXT: store <2 x i32> [[TMP5]], ptr @__msan_retval_tls, align 8138; CHECK-NEXT: ret <2 x i32> [[R]]139;140 %s = ashr <2 x i64> %x, <i64 5, i64 5>141 %r = tail call <2 x i32> @llvm.aarch64.neon.sqxtn.v2i32(<2 x i64> %s)142 ret <2 x i32> %r143}144 145define <2 x i32> @NarrowAShrU64By5(<2 x i64> %x) #0 {146; CHECK-LABEL: define <2 x i32> @NarrowAShrU64By5(147; CHECK-SAME: <2 x i64> [[X:%.*]]) #[[ATTR0]] {148; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8149; CHECK-NEXT: call void @llvm.donothing()150; CHECK-NEXT: [[TMP2:%.*]] = ashr <2 x i64> [[TMP1]], splat (i64 5)151; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP2]], zeroinitializer152; CHECK-NEXT: [[S:%.*]] = ashr <2 x i64> [[X]], splat (i64 5)153; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP3]], zeroinitializer154; CHECK-NEXT: [[TMP5:%.*]] = trunc <2 x i64> [[_MSPROP]] to <2 x i32>155; CHECK-NEXT: [[R:%.*]] = tail call <2 x i32> @llvm.aarch64.neon.uqxtn.v2i32(<2 x i64> [[S]])156; CHECK-NEXT: store <2 x i32> [[TMP5]], ptr @__msan_retval_tls, align 8157; CHECK-NEXT: ret <2 x i32> [[R]]158;159 %s = ashr <2 x i64> %x, <i64 5, i64 5>160 %r = tail call <2 x i32> @llvm.aarch64.neon.uqxtn.v2i32(<2 x i64> %s)161 ret <2 x i32> %r162}163 164define <2 x i32> @NarrowAShri64By5ToU32(<2 x i64> %x) #0 {165; CHECK-LABEL: define <2 x i32> @NarrowAShri64By5ToU32(166; CHECK-SAME: <2 x i64> [[X:%.*]]) #[[ATTR0]] {167; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8168; CHECK-NEXT: call void @llvm.donothing()169; CHECK-NEXT: [[TMP2:%.*]] = ashr <2 x i64> [[TMP1]], splat (i64 5)170; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP2]], zeroinitializer171; CHECK-NEXT: [[S:%.*]] = ashr <2 x i64> [[X]], splat (i64 5)172; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP3]], zeroinitializer173; CHECK-NEXT: [[TMP5:%.*]] = trunc <2 x i64> [[_MSPROP]] to <2 x i32>174; CHECK-NEXT: [[R:%.*]] = tail call <2 x i32> @llvm.aarch64.neon.sqxtun.v2i32(<2 x i64> [[S]])175; CHECK-NEXT: store <2 x i32> [[TMP5]], ptr @__msan_retval_tls, align 8176; CHECK-NEXT: ret <2 x i32> [[R]]177;178 %s = ashr <2 x i64> %x, <i64 5, i64 5>179 %r = tail call <2 x i32> @llvm.aarch64.neon.sqxtun.v2i32(<2 x i64> %s)180 ret <2 x i32> %r181}182 183define <2 x i32> @NarrowLShri64By5(<2 x i64> %x) #0 {184; CHECK-LABEL: define <2 x i32> @NarrowLShri64By5(185; CHECK-SAME: <2 x i64> [[X:%.*]]) #[[ATTR0]] {186; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8187; CHECK-NEXT: call void @llvm.donothing()188; CHECK-NEXT: [[TMP2:%.*]] = lshr <2 x i64> [[TMP1]], splat (i64 5)189; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP2]], zeroinitializer190; CHECK-NEXT: [[S:%.*]] = lshr <2 x i64> [[X]], splat (i64 5)191; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP3]], zeroinitializer192; CHECK-NEXT: [[TMP5:%.*]] = trunc <2 x i64> [[_MSPROP]] to <2 x i32>193; CHECK-NEXT: [[R:%.*]] = tail call <2 x i32> @llvm.aarch64.neon.sqxtn.v2i32(<2 x i64> [[S]])194; CHECK-NEXT: store <2 x i32> [[TMP5]], ptr @__msan_retval_tls, align 8195; CHECK-NEXT: ret <2 x i32> [[R]]196;197 %s = lshr <2 x i64> %x, <i64 5, i64 5>198 %r = tail call <2 x i32> @llvm.aarch64.neon.sqxtn.v2i32(<2 x i64> %s)199 ret <2 x i32> %r200}201 202define <2 x i32> @NarrowLShrU64By5(<2 x i64> %x) #0 {203; CHECK-LABEL: define <2 x i32> @NarrowLShrU64By5(204; CHECK-SAME: <2 x i64> [[X:%.*]]) #[[ATTR0]] {205; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8206; CHECK-NEXT: call void @llvm.donothing()207; CHECK-NEXT: [[TMP2:%.*]] = lshr <2 x i64> [[TMP1]], splat (i64 5)208; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP2]], zeroinitializer209; CHECK-NEXT: [[S:%.*]] = lshr <2 x i64> [[X]], splat (i64 5)210; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP3]], zeroinitializer211; CHECK-NEXT: [[TMP5:%.*]] = trunc <2 x i64> [[_MSPROP]] to <2 x i32>212; CHECK-NEXT: [[R:%.*]] = tail call <2 x i32> @llvm.aarch64.neon.uqxtn.v2i32(<2 x i64> [[S]])213; CHECK-NEXT: store <2 x i32> [[TMP5]], ptr @__msan_retval_tls, align 8214; CHECK-NEXT: ret <2 x i32> [[R]]215;216 %s = lshr <2 x i64> %x, <i64 5, i64 5>217 %r = tail call <2 x i32> @llvm.aarch64.neon.uqxtn.v2i32(<2 x i64> %s)218 ret <2 x i32> %r219}220 221define <2 x i32> @NarrowLShri64By5ToU32(<2 x i64> %x) #0 {222; CHECK-LABEL: define <2 x i32> @NarrowLShri64By5ToU32(223; CHECK-SAME: <2 x i64> [[X:%.*]]) #[[ATTR0]] {224; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8225; CHECK-NEXT: call void @llvm.donothing()226; CHECK-NEXT: [[TMP2:%.*]] = lshr <2 x i64> [[TMP1]], splat (i64 5)227; CHECK-NEXT: [[TMP3:%.*]] = or <2 x i64> [[TMP2]], zeroinitializer228; CHECK-NEXT: [[S:%.*]] = lshr <2 x i64> [[X]], splat (i64 5)229; CHECK-NEXT: [[_MSPROP:%.*]] = or <2 x i64> [[TMP3]], zeroinitializer230; CHECK-NEXT: [[TMP5:%.*]] = trunc <2 x i64> [[_MSPROP]] to <2 x i32>231; CHECK-NEXT: [[R:%.*]] = tail call <2 x i32> @llvm.aarch64.neon.sqxtun.v2i32(<2 x i64> [[S]])232; CHECK-NEXT: store <2 x i32> [[TMP5]], ptr @__msan_retval_tls, align 8233; CHECK-NEXT: ret <2 x i32> [[R]]234;235 %s = lshr <2 x i64> %x, <i64 5, i64 5>236 %r = tail call <2 x i32> @llvm.aarch64.neon.sqxtun.v2i32(<2 x i64> %s)237 ret <2 x i32> %r238}239 240 241define <8 x i8> @NarrowAShri16By5(<8 x i16> %x) #0 {242; CHECK-LABEL: define <8 x i8> @NarrowAShri16By5(243; CHECK-SAME: <8 x i16> [[X:%.*]]) #[[ATTR0]] {244; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8245; CHECK-NEXT: call void @llvm.donothing()246; CHECK-NEXT: [[TMP2:%.*]] = ashr <8 x i16> [[TMP1]], splat (i16 5)247; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i16> [[TMP2]], zeroinitializer248; CHECK-NEXT: [[S:%.*]] = ashr <8 x i16> [[X]], splat (i16 5)249; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP3]], zeroinitializer250; CHECK-NEXT: [[TMP6:%.*]] = trunc <8 x i16> [[_MSPROP]] to <8 x i8>251; CHECK-NEXT: [[R:%.*]] = tail call <8 x i8> @llvm.aarch64.neon.sqxtn.v8i8(<8 x i16> [[S]])252; CHECK-NEXT: store <8 x i8> [[TMP6]], ptr @__msan_retval_tls, align 8253; CHECK-NEXT: ret <8 x i8> [[R]]254;255 %s = ashr <8 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>256 %r = tail call <8 x i8> @llvm.aarch64.neon.sqxtn.v8i8(<8 x i16> %s)257 ret <8 x i8> %r258}259 260define <8 x i8> @NarrowAShrU16By5(<8 x i16> %x) #0 {261; CHECK-LABEL: define <8 x i8> @NarrowAShrU16By5(262; CHECK-SAME: <8 x i16> [[X:%.*]]) #[[ATTR0]] {263; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8264; CHECK-NEXT: call void @llvm.donothing()265; CHECK-NEXT: [[TMP2:%.*]] = ashr <8 x i16> [[TMP1]], splat (i16 5)266; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i16> [[TMP2]], zeroinitializer267; CHECK-NEXT: [[S:%.*]] = ashr <8 x i16> [[X]], splat (i16 5)268; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP3]], zeroinitializer269; CHECK-NEXT: [[TMP6:%.*]] = trunc <8 x i16> [[_MSPROP]] to <8 x i8>270; CHECK-NEXT: [[R:%.*]] = tail call <8 x i8> @llvm.aarch64.neon.uqxtn.v8i8(<8 x i16> [[S]])271; CHECK-NEXT: store <8 x i8> [[TMP6]], ptr @__msan_retval_tls, align 8272; CHECK-NEXT: ret <8 x i8> [[R]]273;274 %s = ashr <8 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>275 %r = tail call <8 x i8> @llvm.aarch64.neon.uqxtn.v8i8(<8 x i16> %s)276 ret <8 x i8> %r277}278 279define <8 x i8> @NarrowAShri16By5ToU8(<8 x i16> %x) #0 {280; CHECK-LABEL: define <8 x i8> @NarrowAShri16By5ToU8(281; CHECK-SAME: <8 x i16> [[X:%.*]]) #[[ATTR0]] {282; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8283; CHECK-NEXT: call void @llvm.donothing()284; CHECK-NEXT: [[TMP2:%.*]] = ashr <8 x i16> [[TMP1]], splat (i16 5)285; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i16> [[TMP2]], zeroinitializer286; CHECK-NEXT: [[S:%.*]] = ashr <8 x i16> [[X]], splat (i16 5)287; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP3]], zeroinitializer288; CHECK-NEXT: [[TMP6:%.*]] = trunc <8 x i16> [[_MSPROP]] to <8 x i8>289; CHECK-NEXT: [[R:%.*]] = tail call <8 x i8> @llvm.aarch64.neon.sqxtun.v8i8(<8 x i16> [[S]])290; CHECK-NEXT: store <8 x i8> [[TMP6]], ptr @__msan_retval_tls, align 8291; CHECK-NEXT: ret <8 x i8> [[R]]292;293 %s = ashr <8 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>294 %r = tail call <8 x i8> @llvm.aarch64.neon.sqxtun.v8i8(<8 x i16> %s)295 ret <8 x i8> %r296}297 298define <8 x i8> @NarrowLShri16By5(<8 x i16> %x) #0 {299; CHECK-LABEL: define <8 x i8> @NarrowLShri16By5(300; CHECK-SAME: <8 x i16> [[X:%.*]]) #[[ATTR0]] {301; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8302; CHECK-NEXT: call void @llvm.donothing()303; CHECK-NEXT: [[TMP2:%.*]] = lshr <8 x i16> [[TMP1]], splat (i16 5)304; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i16> [[TMP2]], zeroinitializer305; CHECK-NEXT: [[S:%.*]] = lshr <8 x i16> [[X]], splat (i16 5)306; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP3]], zeroinitializer307; CHECK-NEXT: [[TMP6:%.*]] = trunc <8 x i16> [[_MSPROP]] to <8 x i8>308; CHECK-NEXT: [[R:%.*]] = tail call <8 x i8> @llvm.aarch64.neon.sqxtn.v8i8(<8 x i16> [[S]])309; CHECK-NEXT: store <8 x i8> [[TMP6]], ptr @__msan_retval_tls, align 8310; CHECK-NEXT: ret <8 x i8> [[R]]311;312 %s = lshr <8 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>313 %r = tail call <8 x i8> @llvm.aarch64.neon.sqxtn.v8i8(<8 x i16> %s)314 ret <8 x i8> %r315}316 317define <8 x i8> @NarrowLShrU16By5(<8 x i16> %x) #0 {318; CHECK-LABEL: define <8 x i8> @NarrowLShrU16By5(319; CHECK-SAME: <8 x i16> [[X:%.*]]) #[[ATTR0]] {320; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8321; CHECK-NEXT: call void @llvm.donothing()322; CHECK-NEXT: [[TMP2:%.*]] = lshr <8 x i16> [[TMP1]], splat (i16 5)323; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i16> [[TMP2]], zeroinitializer324; CHECK-NEXT: [[S:%.*]] = lshr <8 x i16> [[X]], splat (i16 5)325; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP3]], zeroinitializer326; CHECK-NEXT: [[TMP6:%.*]] = trunc <8 x i16> [[_MSPROP]] to <8 x i8>327; CHECK-NEXT: [[R:%.*]] = tail call <8 x i8> @llvm.aarch64.neon.uqxtn.v8i8(<8 x i16> [[S]])328; CHECK-NEXT: store <8 x i8> [[TMP6]], ptr @__msan_retval_tls, align 8329; CHECK-NEXT: ret <8 x i8> [[R]]330;331 %s = lshr <8 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>332 %r = tail call <8 x i8> @llvm.aarch64.neon.uqxtn.v8i8(<8 x i16> %s)333 ret <8 x i8> %r334}335 336define <8 x i8> @NarrowLShri16By5ToU8(<8 x i16> %x) #0 {337; CHECK-LABEL: define <8 x i8> @NarrowLShri16By5ToU8(338; CHECK-SAME: <8 x i16> [[X:%.*]]) #[[ATTR0]] {339; CHECK-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8340; CHECK-NEXT: call void @llvm.donothing()341; CHECK-NEXT: [[TMP2:%.*]] = lshr <8 x i16> [[TMP1]], splat (i16 5)342; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i16> [[TMP2]], zeroinitializer343; CHECK-NEXT: [[S:%.*]] = lshr <8 x i16> [[X]], splat (i16 5)344; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i16> [[TMP3]], zeroinitializer345; CHECK-NEXT: [[TMP6:%.*]] = trunc <8 x i16> [[_MSPROP]] to <8 x i8>346; CHECK-NEXT: [[R:%.*]] = tail call <8 x i8> @llvm.aarch64.neon.sqxtun.v8i8(<8 x i16> [[S]])347; CHECK-NEXT: store <8 x i8> [[TMP6]], ptr @__msan_retval_tls, align 8348; CHECK-NEXT: ret <8 x i8> [[R]]349;350 %s = lshr <8 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>351 %r = tail call <8 x i8> @llvm.aarch64.neon.sqxtun.v8i8(<8 x i16> %s)352 ret <8 x i8> %r353}354 355 356 357 358 359define <4 x i16> @NarrowAShrI32By31(<4 x i32> %x) #0 {360; CHECK-LABEL: define <4 x i16> @NarrowAShrI32By31(361; CHECK-SAME: <4 x i32> [[X:%.*]]) #[[ATTR0]] {362; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8363; CHECK-NEXT: call void @llvm.donothing()364; CHECK-NEXT: [[TMP2:%.*]] = ashr <4 x i32> [[TMP1]], splat (i32 16)365; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP2]], zeroinitializer366; CHECK-NEXT: [[S:%.*]] = ashr <4 x i32> [[X]], splat (i32 16)367; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP3]], zeroinitializer368; CHECK-NEXT: [[TMP6:%.*]] = trunc <4 x i32> [[_MSPROP]] to <4 x i16>369; CHECK-NEXT: [[R:%.*]] = tail call <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32> [[S]])370; CHECK-NEXT: store <4 x i16> [[TMP6]], ptr @__msan_retval_tls, align 8371; CHECK-NEXT: ret <4 x i16> [[R]]372;373 %s = ashr <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16>374 %r = tail call <4 x i16> @llvm.aarch64.neon.sqxtn.v4i16(<4 x i32> %s)375 ret <4 x i16> %r376}377 378define <4 x i16> @NarrowAShrI32By31ToU16(<4 x i32> %x) #0 {379; CHECK-LABEL: define <4 x i16> @NarrowAShrI32By31ToU16(380; CHECK-SAME: <4 x i32> [[X:%.*]]) #[[ATTR0]] {381; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8382; CHECK-NEXT: call void @llvm.donothing()383; CHECK-NEXT: [[TMP2:%.*]] = ashr <4 x i32> [[TMP1]], splat (i32 16)384; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP2]], zeroinitializer385; CHECK-NEXT: [[S:%.*]] = ashr <4 x i32> [[X]], splat (i32 16)386; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP3]], zeroinitializer387; CHECK-NEXT: [[TMP6:%.*]] = trunc <4 x i32> [[_MSPROP]] to <4 x i16>388; CHECK-NEXT: [[R:%.*]] = tail call <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32> [[S]])389; CHECK-NEXT: store <4 x i16> [[TMP6]], ptr @__msan_retval_tls, align 8390; CHECK-NEXT: ret <4 x i16> [[R]]391;392 %s = ashr <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16>393 %r = tail call <4 x i16> @llvm.aarch64.neon.sqxtun.v4i16(<4 x i32> %s)394 ret <4 x i16> %r395}396 397define <4 x i16> @NarrowLShrU32By31(<4 x i32> %x) #0 {398; CHECK-LABEL: define <4 x i16> @NarrowLShrU32By31(399; CHECK-SAME: <4 x i32> [[X:%.*]]) #[[ATTR0]] {400; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8401; CHECK-NEXT: call void @llvm.donothing()402; CHECK-NEXT: [[TMP2:%.*]] = lshr <4 x i32> [[TMP1]], splat (i32 16)403; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[TMP2]], zeroinitializer404; CHECK-NEXT: [[S:%.*]] = lshr <4 x i32> [[X]], splat (i32 16)405; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i32> [[TMP3]], zeroinitializer406; CHECK-NEXT: [[TMP6:%.*]] = trunc <4 x i32> [[_MSPROP]] to <4 x i16>407; CHECK-NEXT: [[R:%.*]] = tail call <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32> [[S]])408; CHECK-NEXT: store <4 x i16> [[TMP6]], ptr @__msan_retval_tls, align 8409; CHECK-NEXT: ret <4 x i16> [[R]]410;411 %s = lshr <4 x i32> %x, <i32 16, i32 16, i32 16, i32 16>412 %r = tail call <4 x i16> @llvm.aarch64.neon.uqxtn.v4i16(<4 x i32> %s)413 ret <4 x i16> %r414}415 416 417define <16 x i8> @signed_minmax_v8i16_to_v16i8(<16 x i16> %x) #0 {418; CHECK-LABEL: define <16 x i8> @signed_minmax_v8i16_to_v16i8(419; CHECK-SAME: <16 x i16> [[X:%.*]]) #[[ATTR0]] {420; CHECK-NEXT: entry:421; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8422; CHECK-NEXT: call void @llvm.donothing()423; CHECK-NEXT: [[TMP1:%.*]] = ashr <16 x i16> [[TMP0]], splat (i16 5)424; CHECK-NEXT: [[TMP2:%.*]] = or <16 x i16> [[TMP1]], zeroinitializer425; CHECK-NEXT: [[S:%.*]] = ashr <16 x i16> [[X]], splat (i16 5)426; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP2]], zeroinitializer427; CHECK-NEXT: [[MIN:%.*]] = call <16 x i16> @llvm.smin.v16i16(<16 x i16> [[S]], <16 x i16> splat (i16 127))428; CHECK-NEXT: [[_MSPROP1:%.*]] = or <16 x i16> [[_MSPROP]], zeroinitializer429; CHECK-NEXT: [[MAX:%.*]] = call <16 x i16> @llvm.smax.v16i16(<16 x i16> [[MIN]], <16 x i16> splat (i16 -128))430; CHECK-NEXT: [[_MSPROP2:%.*]] = trunc <16 x i16> [[_MSPROP1]] to <16 x i8>431; CHECK-NEXT: [[TRUNC:%.*]] = trunc <16 x i16> [[MAX]] to <16 x i8>432; CHECK-NEXT: store <16 x i8> [[_MSPROP2]], ptr @__msan_retval_tls, align 8433; CHECK-NEXT: ret <16 x i8> [[TRUNC]]434;435entry:436 %s = ashr <16 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>437 %min = call <16 x i16> @llvm.smin.v8i16(<16 x i16> %s, <16 x i16> <i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127, i16 127>)438 %max = call <16 x i16> @llvm.smax.v8i16(<16 x i16> %min, <16 x i16> <i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128, i16 -128>)439 %trunc = trunc <16 x i16> %max to <16 x i8>440 ret <16 x i8> %trunc441}442 443define <16 x i8> @unsigned_minmax_v8i16_to_v16i8(<16 x i16> %x) #0 {444; CHECK-LABEL: define <16 x i8> @unsigned_minmax_v8i16_to_v16i8(445; CHECK-SAME: <16 x i16> [[X:%.*]]) #[[ATTR0]] {446; CHECK-NEXT: entry:447; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8448; CHECK-NEXT: call void @llvm.donothing()449; CHECK-NEXT: [[TMP1:%.*]] = lshr <16 x i16> [[TMP0]], splat (i16 5)450; CHECK-NEXT: [[TMP2:%.*]] = or <16 x i16> [[TMP1]], zeroinitializer451; CHECK-NEXT: [[S:%.*]] = lshr <16 x i16> [[X]], splat (i16 5)452; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP2]], zeroinitializer453; CHECK-NEXT: [[MIN:%.*]] = call <16 x i16> @llvm.umin.v16i16(<16 x i16> [[S]], <16 x i16> splat (i16 255))454; CHECK-NEXT: [[_MSPROP1:%.*]] = trunc <16 x i16> [[_MSPROP]] to <16 x i8>455; CHECK-NEXT: [[TRUNC:%.*]] = trunc <16 x i16> [[MIN]] to <16 x i8>456; CHECK-NEXT: store <16 x i8> [[_MSPROP1]], ptr @__msan_retval_tls, align 8457; CHECK-NEXT: ret <16 x i8> [[TRUNC]]458;459entry:460 %s = lshr <16 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>461 %min = call <16 x i16> @llvm.umin.v8i16(<16 x i16> %s, <16 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>)462 %trunc = trunc <16 x i16> %min to <16 x i8>463 ret <16 x i8> %trunc464}465 466define <16 x i8> @unsigned_signed_minmax_v8i16_to_v16i8(<16 x i16> %x) #0 {467; CHECK-LABEL: define <16 x i8> @unsigned_signed_minmax_v8i16_to_v16i8(468; CHECK-SAME: <16 x i16> [[X:%.*]]) #[[ATTR0]] {469; CHECK-NEXT: entry:470; CHECK-NEXT: [[TMP0:%.*]] = load <16 x i16>, ptr @__msan_param_tls, align 8471; CHECK-NEXT: call void @llvm.donothing()472; CHECK-NEXT: [[TMP1:%.*]] = ashr <16 x i16> [[TMP0]], splat (i16 5)473; CHECK-NEXT: [[TMP2:%.*]] = or <16 x i16> [[TMP1]], zeroinitializer474; CHECK-NEXT: [[S:%.*]] = ashr <16 x i16> [[X]], splat (i16 5)475; CHECK-NEXT: [[_MSPROP:%.*]] = or <16 x i16> [[TMP2]], zeroinitializer476; CHECK-NEXT: [[MAX:%.*]] = call <16 x i16> @llvm.smax.v16i16(<16 x i16> [[S]], <16 x i16> zeroinitializer)477; CHECK-NEXT: [[_MSPROP1:%.*]] = or <16 x i16> [[_MSPROP]], zeroinitializer478; CHECK-NEXT: [[MIN:%.*]] = call <16 x i16> @llvm.umin.v16i16(<16 x i16> [[MAX]], <16 x i16> splat (i16 255))479; CHECK-NEXT: [[_MSPROP2:%.*]] = trunc <16 x i16> [[_MSPROP1]] to <16 x i8>480; CHECK-NEXT: [[TRUNC:%.*]] = trunc <16 x i16> [[MIN]] to <16 x i8>481; CHECK-NEXT: store <16 x i8> [[_MSPROP2]], ptr @__msan_retval_tls, align 8482; CHECK-NEXT: ret <16 x i8> [[TRUNC]]483;484entry:485 %s = ashr <16 x i16> %x, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>486 %max = call <16 x i16> @llvm.smax.v8i16(<16 x i16> %s, <16 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>)487 %min = call <16 x i16> @llvm.umin.v8i16(<16 x i16> %max, <16 x i16> <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>)488 %trunc = trunc <16 x i16> %min to <16 x i8>489 ret <16 x i8> %trunc490}491 492 493define <8 x i16> @signed_minmax_v4i32_to_v8i16(<8 x i32> %x) #0 {494; CHECK-LABEL: define <8 x i16> @signed_minmax_v4i32_to_v8i16(495; CHECK-SAME: <8 x i32> [[X:%.*]]) #[[ATTR0]] {496; CHECK-NEXT: entry:497; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8498; CHECK-NEXT: call void @llvm.donothing()499; CHECK-NEXT: [[TMP1:%.*]] = ashr <8 x i32> [[TMP0]], splat (i32 5)500; CHECK-NEXT: [[TMP2:%.*]] = or <8 x i32> [[TMP1]], zeroinitializer501; CHECK-NEXT: [[S:%.*]] = ashr <8 x i32> [[X]], splat (i32 5)502; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP2]], zeroinitializer503; CHECK-NEXT: [[MIN:%.*]] = call <8 x i32> @llvm.smin.v8i32(<8 x i32> [[S]], <8 x i32> splat (i32 32767))504; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i32> [[_MSPROP]], zeroinitializer505; CHECK-NEXT: [[MAX:%.*]] = call <8 x i32> @llvm.smax.v8i32(<8 x i32> [[MIN]], <8 x i32> splat (i32 -32768))506; CHECK-NEXT: [[_MSPROP2:%.*]] = trunc <8 x i32> [[_MSPROP1]] to <8 x i16>507; CHECK-NEXT: [[TRUNC:%.*]] = trunc <8 x i32> [[MAX]] to <8 x i16>508; CHECK-NEXT: store <8 x i16> [[_MSPROP2]], ptr @__msan_retval_tls, align 8509; CHECK-NEXT: ret <8 x i16> [[TRUNC]]510;511entry:512 %s = ashr <8 x i32> %x, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>513 %min = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %s, <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>)514 %max = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %min, <8 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768, i32 -32768>)515 %trunc = trunc <8 x i32> %max to <8 x i16>516 ret <8 x i16> %trunc517}518 519define <8 x i16> @unsigned_minmax_v4i32_to_v8i16(<8 x i32> %x) #0 {520; CHECK-LABEL: define <8 x i16> @unsigned_minmax_v4i32_to_v8i16(521; CHECK-SAME: <8 x i32> [[X:%.*]]) #[[ATTR0]] {522; CHECK-NEXT: entry:523; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8524; CHECK-NEXT: call void @llvm.donothing()525; CHECK-NEXT: [[TMP1:%.*]] = lshr <8 x i32> [[TMP0]], splat (i32 5)526; CHECK-NEXT: [[TMP2:%.*]] = or <8 x i32> [[TMP1]], zeroinitializer527; CHECK-NEXT: [[S:%.*]] = lshr <8 x i32> [[X]], splat (i32 5)528; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP2]], zeroinitializer529; CHECK-NEXT: [[MIN:%.*]] = call <8 x i32> @llvm.umin.v8i32(<8 x i32> [[S]], <8 x i32> splat (i32 65535))530; CHECK-NEXT: [[_MSPROP1:%.*]] = trunc <8 x i32> [[_MSPROP]] to <8 x i16>531; CHECK-NEXT: [[TRUNC:%.*]] = trunc <8 x i32> [[MIN]] to <8 x i16>532; CHECK-NEXT: store <8 x i16> [[_MSPROP1]], ptr @__msan_retval_tls, align 8533; CHECK-NEXT: ret <8 x i16> [[TRUNC]]534;535entry:536 %s = lshr <8 x i32> %x, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>537 %min = call <8 x i32> @llvm.umin.v8i32(<8 x i32> %s, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>)538 %trunc = trunc <8 x i32> %min to <8 x i16>539 ret <8 x i16> %trunc540}541 542define <8 x i16> @unsigned_signed_minmax_v4i32_to_v8i16(<8 x i32> %x) #0 {543; CHECK-LABEL: define <8 x i16> @unsigned_signed_minmax_v4i32_to_v8i16(544; CHECK-SAME: <8 x i32> [[X:%.*]]) #[[ATTR0]] {545; CHECK-NEXT: entry:546; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i32>, ptr @__msan_param_tls, align 8547; CHECK-NEXT: call void @llvm.donothing()548; CHECK-NEXT: [[TMP1:%.*]] = ashr <8 x i32> [[TMP0]], splat (i32 5)549; CHECK-NEXT: [[TMP2:%.*]] = or <8 x i32> [[TMP1]], zeroinitializer550; CHECK-NEXT: [[S:%.*]] = ashr <8 x i32> [[X]], splat (i32 5)551; CHECK-NEXT: [[_MSPROP:%.*]] = or <8 x i32> [[TMP2]], zeroinitializer552; CHECK-NEXT: [[MAX:%.*]] = call <8 x i32> @llvm.smax.v8i32(<8 x i32> [[S]], <8 x i32> zeroinitializer)553; CHECK-NEXT: [[_MSPROP1:%.*]] = or <8 x i32> [[_MSPROP]], zeroinitializer554; CHECK-NEXT: [[MIN:%.*]] = call <8 x i32> @llvm.umin.v8i32(<8 x i32> [[MAX]], <8 x i32> splat (i32 65535))555; CHECK-NEXT: [[_MSPROP2:%.*]] = trunc <8 x i32> [[_MSPROP1]] to <8 x i16>556; CHECK-NEXT: [[TRUNC:%.*]] = trunc <8 x i32> [[MIN]] to <8 x i16>557; CHECK-NEXT: store <8 x i16> [[_MSPROP2]], ptr @__msan_retval_tls, align 8558; CHECK-NEXT: ret <8 x i16> [[TRUNC]]559;560entry:561 %s = ashr <8 x i32> %x, <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>562 %max = call <8 x i32> @llvm.smax.v8i32(<8 x i32> %s, <8 x i32> <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>)563 %min = call <8 x i32> @llvm.umin.v8i32(<8 x i32> %max, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>)564 %trunc = trunc <8 x i32> %min to <8 x i16>565 ret <8 x i16> %trunc566}567 568 569define <4 x i32> @signed_minmax_v4i64_to_v8i32(<4 x i64> %x) #0 {570; CHECK-LABEL: define <4 x i32> @signed_minmax_v4i64_to_v8i32(571; CHECK-SAME: <4 x i64> [[X:%.*]]) #[[ATTR0]] {572; CHECK-NEXT: entry:573; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8574; CHECK-NEXT: call void @llvm.donothing()575; CHECK-NEXT: [[TMP1:%.*]] = ashr <4 x i64> [[TMP0]], splat (i64 5)576; CHECK-NEXT: [[TMP2:%.*]] = or <4 x i64> [[TMP1]], zeroinitializer577; CHECK-NEXT: [[S:%.*]] = ashr <4 x i64> [[X]], splat (i64 5)578; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> [[TMP2]], zeroinitializer579; CHECK-NEXT: [[MIN:%.*]] = call <4 x i64> @llvm.smin.v4i64(<4 x i64> [[S]], <4 x i64> splat (i64 2147483647))580; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i64> [[_MSPROP]], zeroinitializer581; CHECK-NEXT: [[MAX:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[MIN]], <4 x i64> splat (i64 -2147483648))582; CHECK-NEXT: [[_MSPROP2:%.*]] = trunc <4 x i64> [[_MSPROP1]] to <4 x i32>583; CHECK-NEXT: [[TRUNC:%.*]] = trunc <4 x i64> [[MAX]] to <4 x i32>584; CHECK-NEXT: store <4 x i32> [[_MSPROP2]], ptr @__msan_retval_tls, align 8585; CHECK-NEXT: ret <4 x i32> [[TRUNC]]586;587entry:588 %s = ashr <4 x i64> %x, <i64 5, i64 5, i64 5, i64 5>589 %min = call <4 x i64> @llvm.smin.v8i64(<4 x i64> %s, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>)590 %max = call <4 x i64> @llvm.smax.v8i64(<4 x i64> %min, <4 x i64> <i64 -2147483648, i64 -2147483648, i64 -2147483648, i64 -2147483648>)591 %trunc = trunc <4 x i64> %max to <4 x i32>592 ret <4 x i32> %trunc593}594 595define <4 x i32> @unsigned_minmax_v4i64_to_v8i32(<4 x i64> %x) #0 {596; CHECK-LABEL: define <4 x i32> @unsigned_minmax_v4i64_to_v8i32(597; CHECK-SAME: <4 x i64> [[X:%.*]]) #[[ATTR0]] {598; CHECK-NEXT: entry:599; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8600; CHECK-NEXT: call void @llvm.donothing()601; CHECK-NEXT: [[TMP1:%.*]] = lshr <4 x i64> [[TMP0]], splat (i64 5)602; CHECK-NEXT: [[TMP2:%.*]] = or <4 x i64> [[TMP1]], zeroinitializer603; CHECK-NEXT: [[S:%.*]] = lshr <4 x i64> [[X]], splat (i64 5)604; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> [[TMP2]], zeroinitializer605; CHECK-NEXT: [[MIN:%.*]] = call <4 x i64> @llvm.umin.v4i64(<4 x i64> [[S]], <4 x i64> splat (i64 4294967295))606; CHECK-NEXT: [[_MSPROP1:%.*]] = trunc <4 x i64> [[_MSPROP]] to <4 x i32>607; CHECK-NEXT: [[TRUNC:%.*]] = trunc <4 x i64> [[MIN]] to <4 x i32>608; CHECK-NEXT: store <4 x i32> [[_MSPROP1]], ptr @__msan_retval_tls, align 8609; CHECK-NEXT: ret <4 x i32> [[TRUNC]]610;611entry:612 %s = lshr <4 x i64> %x, <i64 5, i64 5, i64 5, i64 5>613 %min = call <4 x i64> @llvm.umin.v8i64(<4 x i64> %s, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)614 %trunc = trunc <4 x i64> %min to <4 x i32>615 ret <4 x i32> %trunc616}617 618define <4 x i32> @unsigned_signed_minmax_v4i64_to_v8i32(<4 x i64> %x) #0 {619; CHECK-LABEL: define <4 x i32> @unsigned_signed_minmax_v4i64_to_v8i32(620; CHECK-SAME: <4 x i64> [[X:%.*]]) #[[ATTR0]] {621; CHECK-NEXT: entry:622; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i64>, ptr @__msan_param_tls, align 8623; CHECK-NEXT: call void @llvm.donothing()624; CHECK-NEXT: [[TMP1:%.*]] = ashr <4 x i64> [[TMP0]], splat (i64 5)625; CHECK-NEXT: [[TMP2:%.*]] = or <4 x i64> [[TMP1]], zeroinitializer626; CHECK-NEXT: [[S:%.*]] = ashr <4 x i64> [[X]], splat (i64 5)627; CHECK-NEXT: [[_MSPROP:%.*]] = or <4 x i64> [[TMP2]], zeroinitializer628; CHECK-NEXT: [[MAX:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[S]], <4 x i64> zeroinitializer)629; CHECK-NEXT: [[_MSPROP1:%.*]] = or <4 x i64> [[_MSPROP]], zeroinitializer630; CHECK-NEXT: [[MIN:%.*]] = call <4 x i64> @llvm.umin.v4i64(<4 x i64> [[MAX]], <4 x i64> splat (i64 4294967295))631; CHECK-NEXT: [[_MSPROP2:%.*]] = trunc <4 x i64> [[_MSPROP1]] to <4 x i32>632; CHECK-NEXT: [[TRUNC:%.*]] = trunc <4 x i64> [[MIN]] to <4 x i32>633; CHECK-NEXT: store <4 x i32> [[_MSPROP2]], ptr @__msan_retval_tls, align 8634; CHECK-NEXT: ret <4 x i32> [[TRUNC]]635;636entry:637 %s = ashr <4 x i64> %x, <i64 5, i64 5, i64 5, i64 5>638 %max = call <4 x i64> @llvm.smax.v8i64(<4 x i64> %s, <4 x i64> <i64 0, i64 0, i64 0, i64 0>)639 %min = call <4 x i64> @llvm.umin.v8i64(<4 x i64> %max, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)640 %trunc = trunc <4 x i64> %min to <4 x i32>641 ret <4 x i32> %trunc642}643 644attributes #0 = { sanitize_memory }645